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  1. /*
  2.  * $Header: c:\\cygwin\\cvsroot/Vert03/vertlib/print_vhdl.h,v 1.1.1.1 2003/11/04 23:34:57
  3.  * mjames Exp $
  4.  *
  5.  * $Log: print_vhdl.h,v $
  6.  * Revision 1.1.1.1  2003/11/04 23:34:57  mjames
  7.  * Imported into local repositrory
  8.  *
  9.  * Revision 1.5  2002/08/23 14:18:24  mjames
  10.  * Removed some constants to the header file
  11.  *
  12.  * Revision 1.4  2001/10/31 22:20:13  mjames
  13.  * Tidying up problematical comments caused by CVS
  14.  * 'intelligent' comment guessing
  15.  *
  16.  * Revision 1.3  2001/06/06 12:10:19  mjames
  17.  * Move from HPUX
  18.  *
  19.  * Revision 1.2  2000/11/29 23:25:39  mjames
  20.  * Corrected a failure to cope with integer type ports on entities
  21.  * in acf_yacc.y
  22.  *
  23.  * Altered the elaborate command to call up the template command aw well
  24.  *
  25.  * Altered equivalent pins handler to cope with the absence of any templates
  26.  *
  27.  * Altered printout routines to use correct datatype for expansion of
  28.  * VHDL constants
  29.  *
  30.  * Revision 1.1.1.1  2000/10/19 21:58:39  mjames
  31.  * Mike put it here
  32.  *
  33.  *
  34.  * Revision 1.13  2000/10/04  10:37:15  10:37:15  mjames (Mike James)
  35.  * Modified for Vertical2 : support COMPONENTS and SIGNALS
  36.  *
  37.  * Revision 1.13  2000/10/04  10:37:15  10:37:15  mjames (Mike James)
  38.  * Part of Release PSAVAT01
  39.  *
  40.  * Revision 1.12  2000/10/02  11:04:18  11:04:18  mjames (Mike James)
  41.  * new_vhdl
  42.  *
  43.  * Revision 1.11  2000/09/27  14:42:31  14:42:31  mjames (Mike James)
  44.  * Part of Release Sep_27_ST_2000
  45.  *
  46.  * Revision 1.10  2000/09/21  10:16:00  10:16:00  mjames (Mike James)
  47.  * Part of Release Sep21Alpha
  48.  *
  49.  * Revision 1.9  2000/08/25  09:57:24  09:57:24  mjames (Mike James)
  50.  * Part of Release Aug25_alpha
  51.  *
  52.  * Revision 1.8  2000/08/16  08:57:40  08:57:40  mjames (Mike James)
  53.  * Part of Release CD01_Aug2000
  54.  *
  55.  * Revision 1.7  2000/08/14  14:45:19  14:45:19  mjames (Mike James)
  56.  * Part of Release Aug_14_2000
  57.  *
  58.  * Revision 1.6  2000/08/11  08:30:40  08:30:40  mjames (Mike James)
  59.  * Part of Release Aug_11_2000
  60.  *
  61.  * Revision 1.5  2000/08/09  10:31:57  10:31:57  mjames (Mike James)
  62.  * Part of Release Aug__9_2000
  63.  *
  64.  * Revision 1.4  2000/05/31  11:43:11  11:43:11  mjames (Mike James)
  65.  * Part of Release May_31_2000
  66.  *
  67.  * Revision 1.3  2000/05/08  17:01:47  17:01:47  mjames (Mike James)
  68.  * Part of Release May__8_2000
  69.  *
  70.  * Revision 1.2  2000/05/08  16:59:40  16:59:40  mjames (Mike James)
  71.  * Part of Release May__8_2000
  72.  *
  73.  * Revision 1.1  99/11/23  13:52:31  13:52:31  mjames (Mike James)
  74.  * Initial revision
  75.  *
  76.  * Revision 1.1  1999/11/02 10:04:23  Mike_on_acorn
  77.  * Initial revision
  78.  */
  79.  
  80. /* listing width */
  81. #define MAXWIDTH 60
  82.  
  83. /* lessthan this pin count, connector pins are seen as wires not busses
  84.  in both VHDL and verilog bundles */
  85.  
  86. #define MINBUNDLE 5
  87.  
  88. extern char *make_vhdl_name (char *buffer, char *str);
  89.  
  90. /* prints out the used subrange */
  91. extern void decode_vhdl_bus (FILE *f, vhdl_t *vhdl, generic_print_style recurse_generics);
  92.  
  93. /* prints out the bus type and range if needed */
  94. extern void decode_vhdl_type (FILE *f, vhdl_t *vhdl, generic_print_style recurse_generics);
  95.  
  96. extern void print_VHDL_component (FILE *f, socket_t *dev, int All);
  97.  
  98. extern void print_VHDL_instance (FILE *f, socket_t *dev, int All);
  99.  
  100. extern void produce_VHDL (FILE *f, char *entityname, char *template);
  101.