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  1. /* $Header: c:\\cygwin\\cvsroot/Vert03/versionlib/version.h,v 1.1.1.1 2003/11/04 23:34:56
  2.  * mjames Exp $ */
  3. /*
  4.  * $Log: version.h,v $
  5.  * Revision 1.1.1.1  2003/11/04 23:34:56  mjames
  6.  * Imported into local repositrory
  7.  *
  8.  * Revision 1.32  2003/01/02 21:37:18  mjames
  9.  * Experiment on creating NOT_ROUTABLE_H and NOT_ROUTABLE_L
  10.  * properties on the nets so that pin jumpers can be made without a problem.
  11.  *
  12.  * Still need to sort out pin assignments made to these not_routable nets
  13.  * which will become legal in some cases so that pullups and pulldown
  14.  * pins can be used on the FPGA.
  15.  *
  16.  * Revision 1.31  2002/12/09 10:31:50  mjames
  17.  * Corrected 2 warnings about #ident
  18.  * Added warning about "chip X1" which gets confused with component called "X1"
  19.  *
  20.  * Revision 1.30  2002/10/02 19:37:27  MJAMES
  21.  * Moved dummy functions to a separate support file.
  22.  *
  23.  * Used correct number of arguments to define_pin
  24.  *
  25.  * Revision 1.29  2002/09/18 08:52:29  mjames
  26.  * New minor version to reflect new pin renaming
  27.  *
  28.  * Revision 1.28  2002/09/09 09:50:11  mjames
  29.  * Upgraded minor version to represent pin renaming enhancements
  30.  *
  31.  * Revision 1.27  2002/08/23 14:03:16  mjames
  32.  * Version string split up so that require command is possible
  33.  *
  34.  * Revision 1.26  2002/08/06 12:52:21  mjames
  35.  * Merge in from latest version
  36.  *
  37.  * Revision 1.31  2002/08/06 08:54:25  mjames
  38.  * Udated major version number
  39.  *
  40.  * Revision 1.30  2002/04/10 14:29:09  mjames
  41.  * Moved setting debug level to cmdutil.c
  42.  *
  43.  * Amended print external command to list all net names on socket pins
  44.  * whether routed or not.
  45.  *
  46.  * Revision 1.29  2002/03/22 16:16:28  mjames
  47.  * Modifications to undo over-zealous checking of
  48.  * current chip even in incorrect scenarios.
  49.  *
  50.  * Revision 1.28  2002/03/21 17:18:15  mjames
  51.  * Added search path to vertical file opening for read
  52.  *
  53.  * Revision 1.27  2002/03/19 11:59:34  mjames
  54.  * Applying paranoid programming to the use of current_chip pointer
  55.  * as there were some address exceptions created in cases of missing
  56.  * components being instantiated in VHDL
  57.  *
  58.  * Revision 1.26  2002/03/08 14:58:57  mjames
  59.  * Edited all of the commands in the cmdexec1.c and cmdexec2.c files
  60.  * so that they can be read by doc2.pl
  61.  *
  62.  * Revision 1.25  2002/01/16 11:22:50  mjames
  63.  * database.h header file is read in first as it undefined DLL stuff irrelevant
  64.  * to HPUX
  65.  *
  66.  * Revision 1.24  2002/01/16 10:09:34  mjames
  67.  * Moved up to release 15.2a
  68.  *
  69.  * Revision 1.23  2002/01/03 16:36:09  mjames
  70.  * Method of accessing Vertical version changed to avoid
  71.  * global variable
  72.  *
  73.  * Revision 1.22  2001/12/20 13:53:51  mjames
  74.  * Update version number to 15.1
  75.  *
  76.  * Revision 1.21  2001/12/13 22:03:30  mjames
  77.  * Version upgraded to 15 in recognition of include files being
  78.  * allowed in several different Vertical  database formats.
  79.  *
  80.  * Revision 1.20  2001/11/19 10:42:25  mjames
  81.  * Merged back DTC release
  82.  *
  83.  * Revision 1.19  2001/11/09 22:16:19  mjames
  84.  * Incremented version from last released version to indicate work being
  85.  * undertaken
  86.  *
  87.  * Revision 1.18.2.3  2001/11/19 10:26:28  mjames
  88.  * Merge
  89.  *
  90.  * Revision 1.18.2.2  2001/11/19 10:25:29  mjames
  91.  * Merge
  92.  *
  93.  * Revision 1.19  2001/11/09 22:16:19  mjames
  94.  * Incremented version from last released version to indicate work being
  95.  * undertaken
  96.  *
  97.  * Revision 1.18  2001/10/31 19:53:19  mjames
  98.  * Made it version 14.5a
  99.  *
  100.  * Revision 1.17  2001/10/18 21:59:15  mjames
  101.  * Updated minor number: reflects tidying Verilog generation code
  102.  *
  103.  * Revision 1.16  2001/10/11 16:11:25  mjames
  104.  * Update version to reflect working with SWAP and Certify
  105.  *
  106.  * Revision 1.15  2001/10/10 09:54:30  mjames
  107.  * Modified command line handler to correctly recognise
  108.  * comment leaders anywhere on line, not just as first character.
  109.  *
  110.  * Revision 1.14  2001/09/25 23:16:51  mjames
  111.  * Update because  wildcard behaviour amended
  112.  *
  113.  * Revision 1.13  2001/09/21 14:25:29  mjames
  114.  * Changed to version 14 to reflect enhancements
  115.  * Skipped version 13 for some reason
  116.  *
  117.  * Revision 1.12  2001/09/13 21:05:29  mjames
  118.  * Changed version code to reflect major differences in the features of the
  119.  * code
  120.  *
  121.  * Revision 1.11  2001/08/23 21:38:39  mjames
  122.  * Added version command to list out all of the tags
  123.  *
  124.  * Revision 1.10  2001/08/23 20:45:35  mjames
  125.  * Updated minor version code to reflect changes made recently
  126.  *
  127.  * Revision 1.9  2001/07/09 10:04:34  mjames
  128.  * Placed the version string in an independent file to save time on building
  129.  * all of the variants of Vertical
  130.  *
  131.  * Revision 1.8  2001/06/22 11:09:11  mjames
  132.  * Changed minor version to .04 to reflect new extract templates comand
  133.  *
  134.  * Revision 1.7  2001/04/30 13:31:45  Administrator
  135.  * Started to add in Verilog parsing
  136.  *
  137.  * Revision 1.6  2001/03/29 22:11:21  mjames
  138.  * Version modified to 12.01 to indicate a major change in functionality
  139.  * with Verilog output . Problems now exist with the Vertical pragmas as
  140.  * they are interpreted differently or not at all....
  141.  *
  142.  * Revision 1.5  2001/03/29 22:08:56  mjames
  143.  * Modified to define the scope of set generic commands : now can be global
  144.  * or defined for a socket or a simple wildcarded list of sockets.
  145.  *
  146.  * In addition the is_FPGA property has been activated so that FPGA components
  147.  * are not listed out when used in a Verilog (.vb) file.
  148.  *
  149.  * Version raised to 11.02
  150.  *
  151.  * Revision 1.4  2001/02/21 16:37:33  mjames
  152.  * Provided a new method of defining port maps with VHDL which allows for short
  153.  * cut definitions.
  154.  *
  155.  * Cleaned up TCL/Tk interfacing issues
  156.  *
  157.  * Revision 1.3  2001/01/02 07:53:53  mjames
  158.  * Made changes to allow for interface with TCL/Tk
  159.  *
  160.  * Revision 1.2  2000/10/19 22:17:32  mjames
  161.  * Changed to PSAVAT release 10.1
  162.  *
  163.  * Revision 1.1  2000/10/12  14:27:56  14:27:56  mjames (Mike James)
  164.  * Initial revision
  165.  *
  166.  */
  167. #pragma once
  168.  
  169. #include <stdio.h>
  170.  
  171.  /* Version file for VERTICAL */
  172.  
  173. /* single binary */
  174. extern char const Vertical_Version[];
  175. extern char const Vertical_Time[];
  176. extern char const Vertical_Release[];
  177.  
  178. #define TOOL_NAME "ACF_READ"
  179.  
  180. extern void InitialiseVersionStrings (void);
  181.  
  182. /* The entry point for a routine that lists out all of the
  183.    module versions in use in vertical */
  184.  
  185. extern void list_versions (FILE *f);
  186.