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  1. /*
  2.  * hardware.c
  3.  *
  4.  *  Created on: 19 Aug 2017
  5.  *      Author: Mike
  6.  */
  7. #include "ch.h"
  8. #include "hal.h"
  9. #include "hardware.h"
  10.  
  11. void TIM1_UP_IRQHandler(void) {
  12. // we have an interrupt here .
  13.  
  14.  
  15.  
  16. }
  17.  
  18. void initTimer(void) {
  19.         rccEnableTIM1(FALSE);
  20.         rccResetTIM1();
  21.         nvicEnableVector(TIM1_UP_IRQn,
  22.                         CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY));
  23.         //gptp->clock = STM32_TIMCLK2;
  24.  
  25.         TIM1->CR1 = 0; /* Initially stopped.           */
  26.         TIM1->CR2 = TIM_CR2_CCDS; /* DMA on UE (if any).          */
  27.         TIM1->PSC = 72; /* Prescaler value.             */
  28.         TIM1->DIER = 0;
  29.  
  30. }
  31.  
  32. void stopTimer(void) {
  33.         nvicDisableVector(TIM1_UP_IRQn);
  34.         rccDisableTIM1(FALSE);
  35. }
  36.  
  37. void startTimer(void) {
  38.           TIM1->ARR  = 12405;           /* Time constant.               */
  39.           TIM1->EGR  = TIM_EGR_UG;             /* Update event.                */
  40.           TIM1->CNT  = 0;                      /* Reset counter.               */
  41.           /* NOTE: After generating the UG event it takes several clock cycles before
  42.              SR bit 0 goes to 1. This is because the clearing of CNT has been inserted
  43.              before the clearing of SR, to give it some time.*/
  44.           TIM1->SR   = 0;                      /* Clear pending IRQs (if any). */
  45.           TIM1->DIER = TIM_DIER_UIE;           /* Update Event IRQ enabled.    */
  46.           TIM1->CR1  = TIM_CR1_URS | TIM_CR1_CEN;
  47. }
  48.