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  1. -- vertical vhdl
  2. --       FPGA / EPLD / PCB / VHDL tools        --
  3. -- NFL Technologies 1995-2003 --
  4.  
  5. -- by: Mike James
  6.  
  7. -- package version:  ²B  compiled: %²B--
  8.  
  9. -- Produced by WRITE VHDL (HPUX)
  10. -- at 14:05:20  on 01/04/2019
  11.  
  12. LIBRARY IEEE,WORK;
  13. USE IEEE.std_logic_1164.ALL;
  14.  
  15.  
  16. -- vertical read_off
  17. ENTITY fred IS
  18.   PORT (
  19.  
  20.      );
  21. END fred;
  22.  
  23.  
  24. -- vertical read_on
  25. LIBRARY IEEE,WORK;
  26. USE IEEE.std_logic_1164.ALL;
  27.  
  28.  
  29.  
  30. ARCHITECTURE top_arch OF  fred IS
  31.  
  32.  
  33.  
  34.  
  35.  
  36. BEGIN
  37.  
  38. -- Bundled signals
  39.  
  40. -- Buffered signals
  41.  
  42. --
  43.  
  44. END top_arch;
  45.  
  46.  
  47. -- vertical end;
  48.