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Terminals which are not used:
PROCESS
State 1 contains 10 shift/reduce conflicts.
State 9 contains 2 shift/reduce conflicts.
State 10 contains 1 shift/reduce conflict.
State 12 contains 5 shift/reduce conflicts.
State 13 contains 10 shift/reduce conflicts and 1 reduce/reduce conflict.
State 42 contains 4 shift/reduce conflicts.
State 43 contains 2 shift/reduce conflicts.
State 44 contains 2 shift/reduce conflicts.
State 45 contains 2 shift/reduce conflicts.
State 46 contains 2 shift/reduce conflicts.
State 47 contains 1 shift/reduce conflict.
State 48 contains 1 shift/reduce conflict.
State 49 contains 1 shift/reduce conflict.
State 50 contains 1 shift/reduce conflict.
State 51 contains 2 shift/reduce conflicts.
State 58 contains 3 shift/reduce conflicts.
State 60 contains 4 shift/reduce conflicts and 5 reduce/reduce conflicts.
State 67 contains 2 shift/reduce conflicts and 1 reduce/reduce conflict.
State 71 contains 2 shift/reduce conflicts.
State 73 contains 1 shift/reduce conflict.
State 82 contains 6 shift/reduce conflicts.
State 90 contains 4 shift/reduce conflicts.
State 93 contains 2 shift/reduce conflicts.
State 123 contains 4 shift/reduce conflicts.
State 137 contains 1 shift/reduce conflict.
State 153 contains 3 shift/reduce conflicts.
State 154 contains 4 reduce/reduce conflicts.
State 178 contains 5 shift/reduce conflicts.
State 189 contains 7 shift/reduce conflicts and 7 reduce/reduce conflicts.
State 198 contains 4 shift/reduce conflicts.
State 199 contains 4 shift/reduce conflicts.
State 200 contains 2 shift/reduce conflicts.
State 201 contains 2 shift/reduce conflicts.
State 202 contains 2 shift/reduce conflicts.
State 203 contains 2 shift/reduce conflicts.
State 204 contains 2 shift/reduce conflicts.
State 205 contains 2 shift/reduce conflicts.
State 206 contains 2 shift/reduce conflicts.
State 207 contains 1 shift/reduce conflict.
State 208 contains 1 shift/reduce conflict.
State 209 contains 1 shift/reduce conflict.
State 210 contains 1 shift/reduce conflict.
State 222 contains 5 shift/reduce conflicts.
State 227 contains 1 shift/reduce conflict.
State 247 contains 1 shift/reduce conflict.
State 269 contains 4 shift/reduce conflicts.
State 305 contains 3 shift/reduce conflicts.
State 352 contains 1 reduce/reduce conflict.
State 374 contains 4 shift/reduce conflicts.
State 393 contains 4 shift/reduce conflicts.
State 487 contains 3 shift/reduce conflicts.
State 495 contains 1 shift/reduce conflict.
State 513 contains 3 shift/reduce conflicts.
State 537 contains 1 shift/reduce conflict.
State 562 contains 1 shift/reduce conflict.
State 563 contains 1 shift/reduce conflict.
State 564 contains 1 shift/reduce conflict.
State 565 contains 1 shift/reduce conflict.
State 630 contains 1 shift/reduce conflict.
State 632 contains 1 shift/reduce conflict.
State 649 contains 1 shift/reduce conflict.
State 668 contains 1 shift/reduce conflict.
Grammar
Number, Line, Rule
1 282 file -> FILEMODE objects
2 283 file -> CMDMODE cmd_objects
3 289 cmd_objects -> cmd_objects cmd_object
4 290 cmd_objects -> cmd_object
5 293 cmd_object -> bus_range
6 302 objects -> objects object
7 303 objects -> object
8 306 object -> chip_decl
9 307 object -> components_decl
10 308 object -> template_decl
11 309 object -> joined_decl
12 310 object -> nets_decl
13 311 object -> rename_pins_block
14 312 object -> global_generic_decl
15 313 object -> vhdl_region
16 314 object -> verilog_region
17 315 object -> ahdl_region
18 316 object -> /* empty */
19 322 astring -> QUOTED_STRING
20 323 astring -> TXT_STRING
21 324 astring -> NUM_STRING
22 329 chip_decl -> chip_id_decl chip_body
23 331 chip_body -> BEGIN_TOK flex_chip_body
24 332 chip_body -> ASSIGNED apex_chip_body
25 338 flex_chip_body -> chip_info_lines pin_declarations pin_equivalences END end_item
26 347 chip_id_decl -> CHIP astring
27 372 chip_info_lines -> chip_info_lines chip_info_line
28 373 chip_info_lines -> chip_info_line
29 374 chip_info_lines -> /* empty */
30 377 chip_info_line -> device_declaration
31 378 chip_info_line -> route_flags_info
32 379 chip_info_line -> routing_status
33 380 chip_info_line -> chip_generic_decl
34 382 device_declaration -> DEVICE '=' astring end_item
35 387 pin_equivalences -> pin_equivalence pin_equivalences
36 388 pin_equivalences -> pin_equivalence
37 389 pin_equivalences -> /* empty */
38 398 end_item -> ';'
39 400 routing_status -> UNROUTED end_item
40 404 route_flags_info -> ROUTE_FLAGS '=' route_flag_value end_item
41 407 route_flag_value -> NUM_STRING
42 415 pin_declarations -> pin_declarations pin_declaration
43 416 pin_declarations -> pin_declaration
44 417 pin_declarations -> /* empty */
45 420 pin_declaration -> name_part ':' pin_rest end_item
46 426 name_part -> netname
47 437 pin_rest -> pin_dir pin_group '=' pin_ident vhdl_type_opt
48 438 pin_rest -> UNROUTED
49 439 pin_rest -> LOCATION '=' astring
50 442 pin_dir -> PINDIR
51 445 pin_group -> '(' NUM_STRING ')'
52 446 pin_group -> /* empty */
53 448 pin_ident -> netname
54 452 apex_chip_body -> apex_device_declaration apex_info_lines
55 455 apex_device_declaration -> TO AN astring apex_speed_grade
56 460 apex_speed_grade -> '-' NUM_STRING
57 471 apex_speed_grade -> /* empty */
58 474 apex_info_lines -> apex_info_lines apex_info_line
59 475 apex_info_lines -> apex_info_line
60 477 apex_info_line -> GND ':' astring more_colons
61 478 apex_info_line -> GND_RES_IO ':' astring more_colons
62 479 apex_info_line -> GND_RES_IN ':' astring more_colons
63 480 apex_info_line -> VCC ':' astring ':' NUM_STRING
64 481 apex_info_line -> VCC ':' astring more_colons
65 482 apex_info_line -> TXT_STRING ':' astring more_colons
66 483 apex_info_line -> TXT_STRING ':' astring ':' PINDIR ':' astring ':'
67 492 apex_info_line -> TXT_STRING '[' expr ']' ':' astring ':' PINDIR ':' astring ':'
68 505 more_colons -> ':' more_colons
69 506 more_colons -> ':'
70 514 vhdl_type_opt -> ':' vhdl_type
71 515 vhdl_type_opt -> /* empty */
72 522 vhdl_type -> astring vhdl_type_default_value_opt
73 533 vhdl_type -> astring '(' bus_range ')' vhdl_type_default_value_opt
74 548 vhdl_type -> INTEGER vhdl_type_default_value_opt
75 559 vhdl_type -> INTEGER RANGE simple_range_expr vhdl_type_default_value_opt
76 571 vhdl_type -> NATURAL vhdl_type_default_value_opt
77 582 vhdl_type -> NATURAL RANGE simple_range_expr vhdl_type_default_value_opt
78 594 vhdl_type -> BOOLEAN vhdl_type_default_value_opt
79 606 vhdl_type_default_value_opt -> ASSIGN bus_range
80 607 vhdl_type_default_value_opt -> /* empty */
81 613 bus_range -> expr1
82 614 bus_range -> expr
83 618 expr1 -> simple_range_expr
84 621 expr1 -> QUOTED_STRING
85 625 expr1 -> QUOTE astring QUOTE
86 630 simple_range_expr -> expr TO expr
87 634 simple_range_expr -> expr DOWNTO expr
88 642 primary_expr -> '(' expr ')'
89 646 primary_expr -> '~' expr
90 650 primary_expr -> '-' expr
91 655 primary_expr -> NUM_STRING
92 659 primary_expr -> TXT_STRING
93 663 primary_expr -> TRUE
94 666 primary_expr -> FALSE
95 671 mult_expr -> primary_expr
96 675 mult_expr -> mult_expr '*' primary_expr
97 679 mult_expr -> mult_expr '/' primary_expr
98 683 mult_expr -> mult_expr '%' primary_expr
99 687 mult_expr -> mult_expr TO_POW primary_expr
100 694 add_expr -> mult_expr
101 698 add_expr -> add_expr '+' mult_expr
102 702 add_expr -> add_expr '-' mult_expr
103 708 shift_expr -> add_expr
104 712 shift_expr -> shift_expr SHL add_expr
105 716 shift_expr -> shift_expr SHR add_expr
106 723 relational_expr -> shift_expr
107 727 relational_expr -> relational_expr '>' shift_expr
108 731 relational_expr -> relational_expr '<' shift_expr
109 738 equality_expr -> relational_expr
110 742 equality_expr -> equality_expr EQ_EQ relational_expr
111 746 equality_expr -> equality_expr N_EQ relational_expr
112 753 and_expr -> equality_expr
113 757 and_expr -> and_expr '&' equality_expr
114 764 exor_expr -> and_expr
115 768 exor_expr -> exor_expr '^' and_expr
116 775 or_expr -> exor_expr
117 779 or_expr -> or_expr '|' or_expr
118 786 logand_expr -> or_expr
119 790 logand_expr -> logand_expr LOG_AND or_expr
120 796 logor_expr -> logand_expr
121 800 logor_expr -> logor_expr LOG_OR logand_expr
122 807 cond_expr -> logor_expr '?' colon_expr
123 814 colon_expr -> expr ':' expr
124 819 expr -> cond_expr
125 823 expr -> logor_expr
126 834 @1 -> /* empty */
127 834 pin_equivalence -> EQUIVALENT @1 '(' equivalent_pins ')' end_item
128 840 equivalent_pins -> equivalent_pin end_item equivalent_pins
129 841 equivalent_pins -> equivalent_pin
130 842 equivalent_pins -> /* empty */
131 845 equivalent_pin -> astring
132 855 vhdl_region -> VHDL vhdl_blocks END end_item
133 860 vhdl_blocks -> vhdl_blocks vhdl_block
134 861 vhdl_blocks -> vhdl_block
135 865 vhdl_block -> vhdl_chip_decl
136 866 vhdl_block -> vhdl_architecture
137 867 vhdl_block -> vhdl_package_decl
138 868 vhdl_block -> vhdl_library_decl
139 869 vhdl_block -> vhdl_use_decl
140 870 vhdl_block -> /* empty */
141 876 @2 -> /* empty */
142 876 vhdl_chip_decl -> ENTITY hdl_entityname_decl IS @2 vhdl_generic_decl_opt vhdl_port_decl_opt END TXT_STRING end_item
143 887 hdl_entityname_decl -> TXT_STRING
144 906 vhdl_generic_decl_opt -> vhdl_generic_decl
145 907 vhdl_generic_decl_opt -> /* empty */
146 911 @3 -> /* empty */
147 911 vhdl_generic_decl -> GENERIC '(' @3 generic_defn_lines ')' end_item
148 922 vhdl_port_decl_opt -> vhdl_port_decl
149 923 vhdl_port_decl_opt -> /* empty */
150 926 vhdl_port_decl -> PORT '(' vhdl_port_list ')' end_item
151 928 vhdl_port_list -> vhdl_port_list end_item vhdl_port_item
152 929 vhdl_port_list -> vhdl_port_item
153 930 vhdl_port_list -> /* empty */
154 937 vhdl_port_item -> vhdl_name_list ':' pin_dir vhdl_type vhdl_assign_opt
155 942 vhdl_name_list -> vhdl_name_list ',' hdl_name_part
156 943 vhdl_name_list -> hdl_name_part
157 948 hdl_name_part -> netname
158 964 vhdl_assign_opt -> ASSIGN expr
159 965 vhdl_assign_opt -> /* empty */
160 973 vhdl_architecture -> ARCHITECTURE astring OF astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring end_item
161 979 vhdl_architecture_declarations -> vhdl_architecture_declarations vhdl_architecture_decl
162 980 vhdl_architecture_declarations -> vhdl_architecture_decl
163 981 vhdl_architecture_declarations -> /* empty */
164 984 vhdl_architecture_decl -> vhdl_component_decl
165 985 vhdl_architecture_decl -> vhdl_constant_decl
166 986 vhdl_architecture_decl -> vhdl_signal_decl
167 987 vhdl_architecture_decl -> vhdl_configuration_decl
168 993 vhdl_package_decl -> PACKAGE package_name IS vhdl_package_declarations END astring end_item
169 997 package_name -> astring
170 1000 vhdl_package_declarations -> vhdl_package_declarations vhdl_package_decl_item
171 1001 vhdl_package_declarations -> vhdl_package_decl_item
172 1002 vhdl_package_declarations -> /* empty */
173 1005 vhdl_package_decl_item -> vhdl_component_decl
174 1006 vhdl_package_decl_item -> vhdl_constant_decl
175 1007 vhdl_package_decl_item -> vhdl_signal_decl
176 1008 vhdl_package_decl_item -> vhdl_configuration_decl
177 1014 vhdl_component_decl -> COMPONENT hdl_compname_decl vhdl_generic_decl_opt vhdl_port_decl_opt END COMPONENT end_item
178 1022 hdl_compname_decl -> TXT_STRING
179 1041 @4 -> /* empty */
180 1041 vhdl_constant_decl -> CONSTANT @4 generic_defn_text end_item
181 1049 @5 -> /* empty */
182 1049 vhdl_signal_decl -> SIGNAL @5 hdl_signal_names ':' vhdl_type end_item
183 1061 hdl_signal_names -> hdl_signal_names ',' hdl_signal_name
184 1062 hdl_signal_names -> hdl_signal_name
185 1065 hdl_signal_name -> astring
186 1082 vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring '.' astring '(' astring ')' ';'
187 1092 vhdl_architecture_body_items -> vhdl_architecture_body_items vhdl_architecture_body_item
188 1093 vhdl_architecture_body_items -> vhdl_architecture_body_item
189 1094 vhdl_architecture_body_items -> /* empty */
190 1097 vhdl_architecture_body_item -> vhdl_concurrent_assignment
191 1098 vhdl_architecture_body_item -> vhdl_component_instance
192 1111 vhdl_component_instance -> vhdl_inst_comp_binding vhdl_inst_generic_map vhdl_inst_port_map end_item
193 1135 vhdl_inst_comp_binding -> TXT_STRING ':' TXT_STRING
194 1165 @6 -> /* empty */
195 1165 vhdl_inst_generic_map -> GENERIC MAP @6 '(' vhdl_gen_map_list ')'
196 1175 vhdl_inst_generic_map -> /* empty */
197 1178 vhdl_inst_port_map -> PORT MAP '(' vhdl_port_map_list ')'
198 1179 vhdl_inst_port_map -> /* empty */
199 1183 vhdl_gen_map_list -> vhdl_gen_map_list ',' vhdl_gen_map
200 1184 vhdl_gen_map_list -> vhdl_gen_map
201 1187 vhdl_gen_map -> astring CONNECTED bus_range
202 1200 vhdl_port_map_list -> vhdl_port_map_list ',' vhdl_port_map
203 1201 vhdl_port_map_list -> vhdl_port_map
204 1206 vhdl_port_map -> astring vhdl_port_map_slice_opt CONNECTED rename_new_name
205 1243 vhdl_port_map -> astring vhdl_port_map_slice_opt CONNECTED OPEN
206 1272 vhdl_port_map -> rename_new_name vhdl_port_map_slice_opt
207 1308 vhdl_port_map -> OPEN
208 1335 vhdl_port_map_slice_opt -> '(' bus_range ')'
209 1340 vhdl_port_map_slice_opt -> /* empty */
210 1348 vhdl_concurrent_assignment -> astring SIG_ASSIGN astring end_item
211 1392 vhdl_library_decl -> LIBRARY vhdl_library_list ';'
212 1394 vhdl_library_list -> vhdl_library_name ',' vhdl_library_list
213 1395 vhdl_library_list -> vhdl_library_name
214 1398 vhdl_library_name -> astring
215 1404 vhdl_use_decl -> USE vhdl_lib_members ';'
216 1406 vhdl_lib_members -> vhdl_lib_member ',' vhdl_lib_members
217 1407 vhdl_lib_members -> vhdl_lib_member
218 1410 vhdl_lib_member -> astring '.' astring '.' vhdl_lib_member_select
219 1411 vhdl_lib_member -> astring '.' vhdl_lib_member_select
220 1415 vhdl_lib_member_select -> ALL
221 1416 vhdl_lib_member_select -> astring
222 1424 verilog_region -> VERILOG verilog_blocks END end_item
223 1429 verilog_blocks -> verilog_blocks verilog_block
224 1430 verilog_blocks -> verilog_block
225 1434 verilog_block -> verilog_module_decl
226 1435 verilog_block -> verilog_toplevel_decl
227 1436 verilog_block -> /* empty */
228 1452 verilog_module_header -> MODULE hdl_compname_decl verilog_port_list verilog_pindir_block
229 1456 verilog_toplevel_decl -> verilog_module_header verilog_module_body ENDMODULE
230 1458 verilog_module_decl -> verilog_module_header ENDMODULE
231 1462 @7 -> /* empty */
232 1462 verilog_port_list -> '(' verilog_ports ')' ';' @7 verilog_pindir_block
233 1465 verilog_port_list -> /* empty */
234 1467 verilog_ports -> verilog_ports ',' verilog_port
235 1468 verilog_ports -> verilog_port
236 1469 verilog_ports -> /* empty */
237 1472 verilog_port -> hdl_name_part
238 1474 verilog_bus_expr -> '[' expr ']'
239 1477 verilog_bus_expr -> '[' expr ':' expr ']'
240 1480 verilog_bus_expr -> /* empty */
241 1486 verilog_module_body -> verilog_wires_block verilog_module_instance_block
242 1491 verilog_pindir_block -> verilog_pindir_block verilog_pindir_decl
243 1492 verilog_pindir_block -> verilog_pindir_decl
244 1493 verilog_pindir_block -> /* empty */
245 1497 @8 -> /* empty */
246 1497 verilog_pindir_decl -> pin_dir @8 verilog_bus_expr hdl_signal_names ';'
247 1505 verilog_wires_block -> verilog_wires_decl verilog_wires_block
248 1506 verilog_wires_block -> verilog_wires_decl
249 1507 verilog_wires_block -> /* empty */
250 1511 verilog_wires_decl -> verilog_wire_start verilog_bus_expr hdl_signal_names verilog_wire_end
251 1516 verilog_wire_start -> WIRE
252 1519 verilog_wire_end -> ';'
253 1525 verilog_module_instance_block -> verilog_module_instances
254 1527 verilog_module_instances -> verilog_module_instances verilog_module_instance
255 1528 verilog_module_instances -> verilog_module_instance
256 1529 verilog_module_instances -> /* empty */
257 1532 verilog_module_instance -> astring astring '(' verilog_port_map_list ')' ';'
258 1566 verilog_port_map_list -> verilog_port_maps
259 1566 verilog_port_map_list -> /* empty */
260 1569 verilog_port_maps -> verilog_port_maps ',' verilog_port_map
261 1570 verilog_port_maps -> verilog_port_map
262 1573 verilog_port_map -> '.' astring '(' astring verilog_bus_expr ')'
263 1616 verilog_port_map -> '.' astring '(' ')'
264 1649 @9 -> /* empty */
265 1649 global_generic_decl -> GENERIC @9 generic_defn_lines END end_item
266 1655 @10 -> /* empty */
267 1655 chip_generic_decl -> GENERIC @10 generic_defn_lines END end_item
268 1663 generic_defn_lines -> generic_defn_lines end_item generic_defn_text
269 1664 generic_defn_lines -> generic_defn_text
270 1665 generic_defn_lines -> /* empty */
271 1669 generic_const_opt -> CONSTANT
272 1670 generic_const_opt -> /* empty */
273 1673 generic_pindir_opt -> PINDIR
274 1674 generic_pindir_opt -> /* empty */
275 1678 generic_defn_text -> generic_const_opt generic_defn_name_list ':' generic_pindir_opt generic_defn_type
276 1680 generic_defn_name_list -> generic_defn_name_list ',' generic_defn_name
277 1681 generic_defn_name_list -> generic_defn_name
278 1683 generic_defn_name -> astring
279 1687 generic_defn_type -> INTEGER opt_integer
280 1702 generic_defn_type -> BOOLEAN opt_integer
281 1717 generic_defn_type -> INTEGER RANGE opt_bus_range
282 1732 @11 -> /* empty */
283 1732 generic_defn_type -> DECLARATION @11 assign_words
284 1748 @12 -> /* empty */
285 1748 generic_defn_type -> INSTANCE @12 assign_words
286 1762 @13 -> /* empty */
287 1762 generic_defn_type -> STRING @13 assign_words
288 1776 @14 -> /* empty */
289 1776 generic_defn_type -> ENV_STRING @14 assign_words
290 1793 generic_defn_type -> ATTRIBUTE opt_integer
291 1810 opt_integer -> ASSIGN expr
292 1811 opt_integer -> /* empty */
293 1814 opt_bus_range -> ASSIGN bus_range
294 1815 opt_bus_range -> /* empty */
295 1822 assign_words -> ASSIGN several_words
296 1823 assign_words -> /* empty */
297 1827 several_words -> word several_words
298 1828 several_words -> word
299 1832 word -> astring
300 1837 components_decl -> COMPONENTS BEGIN_TOK comp_defn_lines END end_item
301 1844 comp_defn_lines -> comp_defn_lines comp_defn_line
302 1845 comp_defn_lines -> comp_defn_line
303 1846 comp_defn_lines -> /* empty */
304 1849 comp_defn_line -> chip_ident ':' chip_name chip_type chip_value end_item
305 1852 chip_ident -> astring
306 1855 chip_name -> astring
307 1858 chip_type -> astring
308 1861 chip_value -> astring
309 1868 joined_decl -> JOINED_NETS BEGIN_TOK join_decls END end_item
310 1874 join_decls -> join_decls join_decl
311 1875 join_decls -> join_decl
312 1876 join_decls -> /* empty */
313 1883 join_decl -> alias_part root_net '=' '(' joined_nets ')' end_item
314 1884 @15 -> /* empty */
315 1884 join_decl -> CONN astring astring @15 end_item
316 1889 join_decl -> VHDL_CONN vhdl_concurrent_assignment
317 1894 alias_part -> ALIAS
318 1897 alias_part -> JUMPER
319 1898 alias_part -> /* empty */
320 1901 root_net -> netname
321 1935 joined_nets -> joined_nets joined_net
322 1936 joined_nets -> joined_net
323 1939 joined_net -> single_net end_item
324 1940 joined_net -> jumper_node end_item
325 1943 single_net -> netname
326 1963 jumper_node -> netname '(' astring ')'
327 2008 rename_pins_block -> RENAME_PINS BEGIN_TOK rename_pin_decls END end_item
328 2015 rename_pin_decls -> rename_pin_decls rename_pin_decl
329 2016 rename_pin_decls -> rename_pin_decl
330 2021 rename_pin_decl -> rename_new_name '=' '(' rename_pin_items ')' end_item
331 2023 rename_new_name -> netname
332 2025 rename_new_name -> netname '(' bus_range ')'
333 2034 rename_pin_items -> rename_pin_items rename_pin_item
334 2035 rename_pin_items -> rename_pin_item
335 2038 rename_pin_item -> astring '.' astring end_item
336 2041 rename_pin_item -> /* empty */
337 2051 @16 -> /* empty */
338 2051 nets_decl -> WIRED_NETS @16 BEGIN_TOK connection_block END end_item
339 2059 connection_block -> connection_block connection_block_item
340 2060 connection_block -> connection_block_item
341 2063 connection_block_item -> routed_decl
342 2064 connection_block_item -> unrouted_decl
343 2065 connection_block_item -> named_decl
344 2066 connection_block_item -> conn_decls
345 2067 connection_block_item -> /* empty */
346 2071 routed_decl -> ROUTED
347 2074 unrouted_decl -> UNROUTED
348 2077 named_decl -> NAMED
349 2082 conn_decls -> conn_decls conn_decl
350 2083 conn_decls -> conn_decl
351 2087 @17 -> /* empty */
352 2087 conn_decl -> CONN conn_ident conn_name last_route_status end_item nodelist END_CONN @17 end_item
353 2092 conn_ident -> netname
354 2098 conn_name -> astring
355 2102 last_route_status -> astring
356 2105 nodelist -> nodelist net_node
357 2106 nodelist -> net_node
358 2107 nodelist -> /* empty */
359 2110 net_node -> skt_id '(' node_id ')' fix_loc_part force_pin_dir node_group end_item
360 2119 force_pin_dir -> PINDIR
361 2128 force_pin_dir -> /* empty */
362 2137 skt_id -> astring
363 2141 node_id -> netname
364 2148 fix_loc_part -> FIX_LOCATION
365 2150 fix_loc_part -> /* empty */
366 2154 node_group -> '(' NUM_STRING ')'
367 2155 node_group -> /* empty */
368 2163 netname -> VCC
369 2164 netname -> GND
370 2165 netname -> astring
371 2180 template_decl -> template_id_decl BEGIN_TOK template_info_lines pin_declarations pin_equivalences END end_item
372 2201 template_id_decl -> TEMPLATE template_name
373 2203 template_name -> astring
374 2209 template_info_lines -> template_info_lines template_info_line
375 2210 template_info_lines -> template_info_line
376 2213 template_info_line -> chip_generic_decl
377 2214 template_info_line -> alias_to_another_template
378 2215 template_info_line -> /* empty */
379 2219 alias_to_another_template -> ALIAS astring end_item
380 2250 ahdl_region -> AHDL ahdl_chip_decls END end_item
381 2255 ahdl_chip_decls -> ahdl_chip_decl ahdl_chip_decls
382 2256 ahdl_chip_decls -> ahdl_chip_decl
383 2259 ahdl_chip_decl -> ahdl_entityname_decl
384 2260 ahdl_chip_decl -> ahdl_port_decl
385 2261 ahdl_chip_decl -> /* empty */
386 2264 ahdl_entityname_decl -> SUBDESIGN TXT_STRING
387 2281 ahdl_port_decl -> '(' ahdl_port_list ')'
388 2283 ahdl_port_list -> ahdl_port_list end_item ahdl_port_item
389 2284 ahdl_port_list -> ahdl_port_item
390 2285 ahdl_port_list -> /* empty */
391 2292 ahdl_port_item -> ahdl_name_list ':' pin_dir
392 2301 ahdl_name_list -> ahdl_name_list ',' ahdl_name_part
393 2302 ahdl_name_list -> ahdl_name_part
394 2305 ahdl_name_part -> astring
Terminals, with rules where they appear
$ (-1)
'%' (37) 98
'&' (38) 113
'(' (40) 51 73 88 127 147 150 186 195 197 208 232 257 262 263 313 326
330 332 359 366 387
')' (41) 51 73 88 127 147 150 186 195 197 208 232 257 262 263 313 326
330 332 359 366 387
'*' (42) 96
'+' (43) 101
',' (44) 155 183 199 202 212 216 234 260 276 392
'-' (45) 56 90 102
'.' (46) 186 218 219 262 263 335
'/' (47) 97
':' (58) 45 60 61 62 63 64 65 66 67 68 69 70 123 154 182 186 193 239
275 304 391
';' (59) 38 186 211 215 232 246 252 257
'<' (60) 108
'=' (61) 34 40 47 49 313 330
'>' (62) 107
'?' (63) 122
'[' (91) 67 238 239
']' (93) 67 238 239
'^' (94) 115
'|' (124) 117
'~' (126) 89
error (256)
FILEMODE (257) 1
CMDMODE (258) 2
CHIP (259) 26
BEGIN_TOK (260) 23 160 300 309 327 338 371
END (261) 25 132 142 160 168 177 222 265 267 300 309 327 338 371 380
DEVICE (262) 34
COMPONENTS (263) 300
WIRED_NETS (264) 338
CONN (265) 315 352
END_CONN (266) 352
JOINED_NETS (267) 309
ALIAS (268) 317 379
JUMPER (269) 318
RENAME_PINS (270) 327
TEMPLATE (271) 372
FIX_LOCATION (272) 364
LOCATION (273) 49
UNROUTED (274) 39 48 347
ROUTED (275) 346
NAMED (276) 348
ASSIGN (277) 79 158 291 293 295
SIG_ASSIGN (278) 210
CONNECTED (279) 201 204 205
ROUTE_FLAGS (280) 40
DECLARATION (281) 283
INSTANCE (282) 285
AHDL (283) 380
VERILOG (284) 222
SUBDESIGN (285) 386
OPEN (286) 205 207
BOOLEAN (287) 78 280
TRUE (288) 93
FALSE (289) 94
TO (290) 55 86
DOWNTO (291) 87
GENERIC (292) 147 195 265 267
RANGE (293) 75 77 281
INTEGER (294) 74 75 279 281
NATURAL (295) 76 77
SIGNAL (296) 182
CONSTANT (297) 180 271
VHDL (298) 132
PORT (299) 150 197
ENTITY (300) 142 186
IS (301) 142 160 168
COMPONENT (302) 177
MAP (303) 195 197
ARCHITECTURE (304) 160
OF (305) 160
EQUIVALENT (306) 127
TO_POW (307) 99
MODULE (308) 228
ENDMODULE (309) 229 230
LIBRARY (310) 211
USE (311) 186 215
ALL (312) 220
PACKAGE (313) 168
FOR (314) 186
PROCESS (315)
ASSIGNED (316) 24
AN (317) 55
WIRE (318) 251
GND (319) 60 369
GND_RES_IO (320) 61
GND_RES_IN (321) 62
VCC (322) 63 64 368
ATTRIBUTE (323) 290
ENV_STRING (324) 289
STRING (325) 287
SHL (326) 104
SHR (327) 105
EQ_EQ (328) 110
N_EQ (329) 111
LOG_AND (330) 119
LOG_OR (331) 121
QUOTE (332) 85
VHDL_CONN (333) 316
QUOTED_STRING (334) 19 84
TXT_STRING (335) 20 65 66 67 92 142 143 178 193 386
NUM_STRING (336) 21 41 51 56 63 91 366
PINDIR (337) 50 66 67 273 360
UMINUS (338)
Nonterminals, with rules where they appear
file (106)
on left: 1 2
cmd_objects (107)
on left: 3 4, on right: 2 3
cmd_object (108)
on left: 5, on right: 3 4
objects (109)
on left: 6 7, on right: 1 6
object (110)
on left: 8 9 10 11 12 13 14 15 16 17 18, on right: 6 7
astring (111)
on left: 19 20 21, on right: 26 34 49 55 60 61 62 63 64 65 66 67
72 73 85 131 160 168 169 185 186 201 204 205 210 214 218 219 221
257 262 263 278 299 305 306 307 308 315 326 335 354 355 362 370
373 379 394
chip_decl (112)
on left: 22, on right: 8
chip_body (113)
on left: 23 24, on right: 22
flex_chip_body (114)
on left: 25, on right: 23
chip_id_decl (115)
on left: 26, on right: 22
chip_info_lines (116)
on left: 27 28 29, on right: 25 27
chip_info_line (117)
on left: 30 31 32 33, on right: 27 28
device_declaration (118)
on left: 34, on right: 30
pin_equivalences (119)
on left: 35 36 37, on right: 25 35 371
end_item (120)
on left: 38, on right: 25 34 39 40 45 127 128 132 142 147 150 151
160 168 177 180 182 192 210 222 265 267 268 300 304 309 313 315
323 324 327 330 335 338 352 359 371 379 380 388
routing_status (121)
on left: 39, on right: 32
route_flags_info (122)
on left: 40, on right: 31
route_flag_value (123)
on left: 41, on right: 40
pin_declarations (124)
on left: 42 43 44, on right: 25 42 371
pin_declaration (125)
on left: 45, on right: 42 43
name_part (126)
on left: 46, on right: 45
pin_rest (127)
on left: 47 48 49, on right: 45
pin_dir (128)
on left: 50, on right: 47 154 246 391
pin_group (129)
on left: 51 52, on right: 47
pin_ident (130)
on left: 53, on right: 47
apex_chip_body (131)
on left: 54, on right: 24
apex_device_declaration (132)
on left: 55, on right: 54
apex_speed_grade (133)
on left: 56 57, on right: 55
apex_info_lines (134)
on left: 58 59, on right: 54 58
apex_info_line (135)
on left: 60 61 62 63 64 65 66 67, on right: 58 59
more_colons (136)
on left: 68 69, on right: 60 61 62 64 65 68
vhdl_type_opt (137)
on left: 70 71, on right: 47
vhdl_type (138)
on left: 72 73 74 75 76 77 78, on right: 70 154 182
vhdl_type_default_value_opt (139)
on left: 79 80, on right: 72 73 74 75 76 77 78
bus_range (140)
on left: 81 82, on right: 5 73 79 201 208 293 332
expr1 (141)
on left: 83 84 85, on right: 81
simple_range_expr (142)
on left: 86 87, on right: 75 77 83
primary_expr (143)
on left: 88 89 90 91 92 93 94, on right: 95 96 97 98 99
mult_expr (144)
on left: 95 96 97 98 99, on right: 96 97 98 99 100 101 102
add_expr (145)
on left: 100 101 102, on right: 101 102 103 104 105
shift_expr (146)
on left: 103 104 105, on right: 104 105 106 107 108
relational_expr (147)
on left: 106 107 108, on right: 107 108 109 110 111
equality_expr (148)
on left: 109 110 111, on right: 110 111 112 113
and_expr (149)
on left: 112 113, on right: 113 114 115
exor_expr (150)
on left: 114 115, on right: 115 116
or_expr (151)
on left: 116 117, on right: 117 118 119
logand_expr (152)
on left: 118 119, on right: 119 120 121
logor_expr (153)
on left: 120 121, on right: 121 122 125
cond_expr (154)
on left: 122, on right: 124
colon_expr (155)
on left: 123, on right: 122
expr (156)
on left: 124 125, on right: 67 82 86 87 88 89 90 123 158 238 239
291
pin_equivalence (157)
on left: 127, on right: 35 36
@1 (158)
on left: 126, on right: 127
equivalent_pins (159)
on left: 128 129 130, on right: 127 128
equivalent_pin (160)
on left: 131, on right: 128 129
vhdl_region (161)
on left: 132, on right: 15
vhdl_blocks (162)
on left: 133 134, on right: 132 133
vhdl_block (163)
on left: 135 136 137 138 139 140, on right: 133 134
vhdl_chip_decl (164)
on left: 142, on right: 135
@2 (165)
on left: 141, on right: 142
hdl_entityname_decl (166)
on left: 143, on right: 142
vhdl_generic_decl_opt (167)
on left: 144 145, on right: 142 177
vhdl_generic_decl (168)
on left: 147, on right: 144
@3 (169)
on left: 146, on right: 147
vhdl_port_decl_opt (170)
on left: 148 149, on right: 142 177
vhdl_port_decl (171)
on left: 150, on right: 148
vhdl_port_list (172)
on left: 151 152 153, on right: 150 151
vhdl_port_item (173)
on left: 154, on right: 151 152
vhdl_name_list (174)
on left: 155 156, on right: 154 155
hdl_name_part (175)
on left: 157, on right: 155 156 237
vhdl_assign_opt (176)
on left: 158 159, on right: 154
vhdl_architecture (177)
on left: 160, on right: 136
vhdl_architecture_declarations (178)
on left: 161 162 163, on right: 160 161
vhdl_architecture_decl (179)
on left: 164 165 166 167, on right: 161 162
vhdl_package_decl (180)
on left: 168, on right: 137
package_name (181)
on left: 169, on right: 168
vhdl_package_declarations (182)
on left: 170 171 172, on right: 168 170
vhdl_package_decl_item (183)
on left: 173 174 175 176, on right: 170 171
vhdl_component_decl (184)
on left: 177, on right: 164 173
hdl_compname_decl (185)
on left: 178, on right: 177 228
vhdl_constant_decl (186)
on left: 180, on right: 165 174
@4 (187)
on left: 179, on right: 180
vhdl_signal_decl (188)
on left: 182, on right: 166 175
@5 (189)
on left: 181, on right: 182
hdl_signal_names (190)
on left: 183 184, on right: 182 183 246 250
hdl_signal_name (191)
on left: 185, on right: 183 184
vhdl_configuration_decl (192)
on left: 186, on right: 167 176
vhdl_architecture_body_items (193)
on left: 187 188 189, on right: 160 187
vhdl_architecture_body_item (194)
on left: 190 191, on right: 187 188
vhdl_component_instance (195)
on left: 192, on right: 191
vhdl_inst_comp_binding (196)
on left: 193, on right: 192
vhdl_inst_generic_map (197)
on left: 195 196, on right: 192
@6 (198)
on left: 194, on right: 195
vhdl_inst_port_map (199)
on left: 197 198, on right: 192
vhdl_gen_map_list (200)
on left: 199 200, on right: 195 199
vhdl_gen_map (201)
on left: 201, on right: 199 200
vhdl_port_map_list (202)
on left: 202 203, on right: 197 202
vhdl_port_map (203)
on left: 204 205 206 207, on right: 202 203
vhdl_port_map_slice_opt (204)
on left: 208 209, on right: 204 205 206
vhdl_concurrent_assignment (205)
on left: 210, on right: 190 316
vhdl_library_decl (206)
on left: 211, on right: 138
vhdl_library_list (207)
on left: 212 213, on right: 211 212
vhdl_library_name (208)
on left: 214, on right: 212 213
vhdl_use_decl (209)
on left: 215, on right: 139
vhdl_lib_members (210)
on left: 216 217, on right: 215 216
vhdl_lib_member (211)
on left: 218 219, on right: 216 217
vhdl_lib_member_select (212)
on left: 220 221, on right: 186 218 219
verilog_region (213)
on left: 222, on right: 16
verilog_blocks (214)
on left: 223 224, on right: 222 223
verilog_block (215)
on left: 225 226 227, on right: 223 224
verilog_module_header (216)
on left: 228, on right: 229 230
verilog_toplevel_decl (217)
on left: 229, on right: 226
verilog_module_decl (218)
on left: 230, on right: 225
verilog_port_list (219)
on left: 232 233, on right: 228
@7 (220)
on left: 231, on right: 232
verilog_ports (221)
on left: 234 235 236, on right: 232 234
verilog_port (222)
on left: 237, on right: 234 235
verilog_bus_expr (223)
on left: 238 239 240, on right: 246 250 262
verilog_module_body (224)
on left: 241, on right: 229
verilog_pindir_block (225)
on left: 242 243 244, on right: 228 232 242
verilog_pindir_decl (226)
on left: 246, on right: 242 243
@8 (227)
on left: 245, on right: 246
verilog_wires_block (228)
on left: 247 248 249, on right: 241 247
verilog_wires_decl (229)
on left: 250, on right: 247 248
verilog_wire_start (230)
on left: 251, on right: 250
verilog_wire_end (231)
on left: 252, on right: 250
verilog_module_instance_block (232)
on left: 253, on right: 241
verilog_module_instances (233)
on left: 254 255 256, on right: 253 254
verilog_module_instance (234)
on left: 257, on right: 254 255
verilog_port_map_list (235)
on left: 258 259, on right: 257
verilog_port_maps (236)
on left: 260 261, on right: 258 260
verilog_port_map (237)
on left: 262 263, on right: 260 261
global_generic_decl (238)
on left: 265, on right: 14
@9 (239)
on left: 264, on right: 265
chip_generic_decl (240)
on left: 267, on right: 33 376
@10 (241)
on left: 266, on right: 267
generic_defn_lines (242)
on left: 268 269 270, on right: 147 265 267 268
generic_const_opt (243)
on left: 271 272, on right: 275
generic_pindir_opt (244)
on left: 273 274, on right: 275
generic_defn_text (245)
on left: 275, on right: 180 268 269
generic_defn_name_list (246)
on left: 276 277, on right: 275 276
generic_defn_name (247)
on left: 278, on right: 276 277
generic_defn_type (248)
on left: 279 280 281 283 285 287 289 290, on right: 275
@11 (249)
on left: 282, on right: 283
@12 (250)
on left: 284, on right: 285
@13 (251)
on left: 286, on right: 287
@14 (252)
on left: 288, on right: 289
opt_integer (253)
on left: 291 292, on right: 279 280 290
opt_bus_range (254)
on left: 293 294, on right: 281
assign_words (255)
on left: 295 296, on right: 283 285 287 289
several_words (256)
on left: 297 298, on right: 295 297
word (257)
on left: 299, on right: 297 298
components_decl (258)
on left: 300, on right: 9
comp_defn_lines (259)
on left: 301 302 303, on right: 300 301
comp_defn_line (260)
on left: 304, on right: 301 302
chip_ident (261)
on left: 305, on right: 304
chip_name (262)
on left: 306, on right: 304
chip_type (263)
on left: 307, on right: 304
chip_value (264)
on left: 308, on right: 304
joined_decl (265)
on left: 309, on right: 11
join_decls (266)
on left: 310 311 312, on right: 309 310
join_decl (267)
on left: 313 315 316, on right: 310 311
@15 (268)
on left: 314, on right: 315
alias_part (269)
on left: 317 318 319, on right: 313
root_net (270)
on left: 320, on right: 313
joined_nets (271)
on left: 321 322, on right: 313 321
joined_net (272)
on left: 323 324, on right: 321 322
single_net (273)
on left: 325, on right: 323
jumper_node (274)
on left: 326, on right: 324
rename_pins_block (275)
on left: 327, on right: 13
rename_pin_decls (276)
on left: 328 329, on right: 327 328
rename_pin_decl (277)
on left: 330, on right: 328 329
rename_new_name (278)
on left: 331 332, on right: 204 206 330
rename_pin_items (279)
on left: 333 334, on right: 330 333
rename_pin_item (280)
on left: 335 336, on right: 333 334
nets_decl (281)
on left: 338, on right: 12
@16 (282)
on left: 337, on right: 338
connection_block (283)
on left: 339 340, on right: 338 339
connection_block_item (284)
on left: 341 342 343 344 345, on right: 339 340
routed_decl (285)
on left: 346, on right: 341
unrouted_decl (286)
on left: 347, on right: 342
named_decl (287)
on left: 348, on right: 343
conn_decls (288)
on left: 349 350, on right: 344 349
conn_decl (289)
on left: 352, on right: 349 350
@17 (290)
on left: 351, on right: 352
conn_ident (291)
on left: 353, on right: 352
conn_name (292)
on left: 354, on right: 352
last_route_status (293)
on left: 355, on right: 352
nodelist (294)
on left: 356 357 358, on right: 352 356
net_node (295)
on left: 359, on right: 356 357
force_pin_dir (296)
on left: 360 361, on right: 359
skt_id (297)
on left: 362, on right: 359
node_id (298)
on left: 363, on right: 359
fix_loc_part (299)
on left: 364 365, on right: 359
node_group (300)
on left: 366 367, on right: 359
netname (301)
on left: 368 369 370, on right: 46 53 157 320 325 326 331 332 353
363
template_decl (302)
on left: 371, on right: 10
template_id_decl (303)
on left: 372, on right: 371
template_name (304)
on left: 373, on right: 372
template_info_lines (305)
on left: 374 375, on right: 371 374
template_info_line (306)
on left: 376 377 378, on right: 374 375
alias_to_another_template (307)
on left: 379, on right: 377
ahdl_region (308)
on left: 380, on right: 17
ahdl_chip_decls (309)
on left: 381 382, on right: 380 381
ahdl_chip_decl (310)
on left: 383 384 385, on right: 381 382
ahdl_entityname_decl (311)
on left: 386, on right: 383
ahdl_port_decl (312)
on left: 387, on right: 384
ahdl_port_list (313)
on left: 388 389 390, on right: 387 388
ahdl_port_item (314)
on left: 391, on right: 388 389
ahdl_name_list (315)
on left: 392 393, on right: 391 392
ahdl_name_part (316)
on left: 394, on right: 392 393
state 0
FILEMODE shift, and go to state 1
CMDMODE shift, and go to state 2
file go to state 698
state 1
file -> FILEMODE . objects (rule 1)
CHIP shift, and go to state 3
COMPONENTS shift, and go to state 4
WIRED_NETS shift, and go to state 5
JOINED_NETS shift, and go to state 6
RENAME_PINS shift, and go to state 7
TEMPLATE shift, and go to state 8
AHDL shift, and go to state 9
VERILOG shift, and go to state 10
GENERIC shift, and go to state 11
VHDL shift, and go to state 12
CHIP [reduce using rule 18 (object)]
COMPONENTS [reduce using rule 18 (object)]
WIRED_NETS [reduce using rule 18 (object)]
JOINED_NETS [reduce using rule 18 (object)]
RENAME_PINS [reduce using rule 18 (object)]
TEMPLATE [reduce using rule 18 (object)]
AHDL [reduce using rule 18 (object)]
VERILOG [reduce using rule 18 (object)]
GENERIC [reduce using rule 18 (object)]
VHDL [reduce using rule 18 (object)]
$default reduce using rule 18 (object)
objects go to state 13
object go to state 14
chip_decl go to state 15
chip_id_decl go to state 16
vhdl_region go to state 17
verilog_region go to state 18
global_generic_decl go to state 19
components_decl go to state 20
joined_decl go to state 21
rename_pins_block go to state 22
nets_decl go to state 23
template_decl go to state 24
template_id_decl go to state 25
ahdl_region go to state 26
state 2
file -> CMDMODE . cmd_objects (rule 2)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
QUOTE shift, and go to state 29
QUOTED_STRING shift, and go to state 30
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
cmd_objects go to state 36
cmd_object go to state 37
bus_range go to state 38
expr1 go to state 39
simple_range_expr go to state 40
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 53
state 3
chip_id_decl -> CHIP . astring (rule 26)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 57
state 4
components_decl -> COMPONENTS . BEGIN_TOK comp_defn_lines END end_item (rule 300)
BEGIN_TOK shift, and go to state 58
state 5
nets_decl -> WIRED_NETS . @16 BEGIN_TOK connection_block END end_item (rule 338)
$default reduce using rule 337 (@16)
@16 go to state 59
state 6
joined_decl -> JOINED_NETS . BEGIN_TOK join_decls END end_item (rule 309)
BEGIN_TOK shift, and go to state 60
state 7
rename_pins_block -> RENAME_PINS . BEGIN_TOK rename_pin_decls END end_item (rule 327)
BEGIN_TOK shift, and go to state 61
state 8
template_id_decl -> TEMPLATE . template_name (rule 372)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 62
template_name go to state 63
state 9
ahdl_region -> AHDL . ahdl_chip_decls END end_item (rule 380)
SUBDESIGN shift, and go to state 64
'(' shift, and go to state 65
SUBDESIGN [reduce using rule 385 (ahdl_chip_decl)]
'(' [reduce using rule 385 (ahdl_chip_decl)]
$default reduce using rule 385 (ahdl_chip_decl)
ahdl_chip_decls go to state 66
ahdl_chip_decl go to state 67
ahdl_entityname_decl go to state 68
ahdl_port_decl go to state 69
state 10
verilog_region -> VERILOG . verilog_blocks END end_item (rule 222)
MODULE shift, and go to state 70
MODULE [reduce using rule 227 (verilog_block)]
$default reduce using rule 227 (verilog_block)
verilog_blocks go to state 71
verilog_block go to state 72
verilog_module_header go to state 73
verilog_toplevel_decl go to state 74
verilog_module_decl go to state 75
state 11
global_generic_decl -> GENERIC . @9 generic_defn_lines END end_item (rule 265)
$default reduce using rule 264 (@9)
@9 go to state 76
state 12
vhdl_region -> VHDL . vhdl_blocks END end_item (rule 132)
ENTITY shift, and go to state 77
ARCHITECTURE shift, and go to state 78
LIBRARY shift, and go to state 79
USE shift, and go to state 80
PACKAGE shift, and go to state 81
ENTITY [reduce using rule 140 (vhdl_block)]
ARCHITECTURE [reduce using rule 140 (vhdl_block)]
LIBRARY [reduce using rule 140 (vhdl_block)]
USE [reduce using rule 140 (vhdl_block)]
PACKAGE [reduce using rule 140 (vhdl_block)]
$default reduce using rule 140 (vhdl_block)
vhdl_blocks go to state 82
vhdl_block go to state 83
vhdl_chip_decl go to state 84
vhdl_architecture go to state 85
vhdl_package_decl go to state 86
vhdl_library_decl go to state 87
vhdl_use_decl go to state 88
state 13
file -> FILEMODE objects . (rule 1)
objects -> objects . object (rule 6)
CHIP shift, and go to state 3
COMPONENTS shift, and go to state 4
WIRED_NETS shift, and go to state 5
JOINED_NETS shift, and go to state 6
RENAME_PINS shift, and go to state 7
TEMPLATE shift, and go to state 8
AHDL shift, and go to state 9
VERILOG shift, and go to state 10
GENERIC shift, and go to state 11
VHDL shift, and go to state 12
$ reduce using rule 1 (file)
$ [reduce using rule 18 (object)]
CHIP [reduce using rule 18 (object)]
COMPONENTS [reduce using rule 18 (object)]
WIRED_NETS [reduce using rule 18 (object)]
JOINED_NETS [reduce using rule 18 (object)]
RENAME_PINS [reduce using rule 18 (object)]
TEMPLATE [reduce using rule 18 (object)]
AHDL [reduce using rule 18 (object)]
VERILOG [reduce using rule 18 (object)]
GENERIC [reduce using rule 18 (object)]
VHDL [reduce using rule 18 (object)]
$default reduce using rule 1 (file)
object go to state 89
chip_decl go to state 15
chip_id_decl go to state 16
vhdl_region go to state 17
verilog_region go to state 18
global_generic_decl go to state 19
components_decl go to state 20
joined_decl go to state 21
rename_pins_block go to state 22
nets_decl go to state 23
template_decl go to state 24
template_id_decl go to state 25
ahdl_region go to state 26
state 14
objects -> object . (rule 7)
$default reduce using rule 7 (objects)
state 15
object -> chip_decl . (rule 8)
$default reduce using rule 8 (object)
state 16
chip_decl -> chip_id_decl . chip_body (rule 22)
BEGIN_TOK shift, and go to state 90
ASSIGNED shift, and go to state 91
chip_body go to state 92
state 17
object -> vhdl_region . (rule 15)
$default reduce using rule 15 (object)
state 18
object -> verilog_region . (rule 16)
$default reduce using rule 16 (object)
state 19
object -> global_generic_decl . (rule 14)
$default reduce using rule 14 (object)
state 20
object -> components_decl . (rule 9)
$default reduce using rule 9 (object)
state 21
object -> joined_decl . (rule 11)
$default reduce using rule 11 (object)
state 22
object -> rename_pins_block . (rule 13)
$default reduce using rule 13 (object)
state 23
object -> nets_decl . (rule 12)
$default reduce using rule 12 (object)
state 24
object -> template_decl . (rule 10)
$default reduce using rule 10 (object)
state 25
template_decl -> template_id_decl . BEGIN_TOK template_info_lines pin_declarations pin_equivalences END end_item (rule 371)
BEGIN_TOK shift, and go to state 93
state 26
object -> ahdl_region . (rule 17)
$default reduce using rule 17 (object)
state 27
primary_expr -> TRUE . (rule 93)
$default reduce using rule 93 (primary_expr)
state 28
primary_expr -> FALSE . (rule 94)
$default reduce using rule 94 (primary_expr)
state 29
expr1 -> QUOTE . astring QUOTE (rule 85)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 94
state 30
expr1 -> QUOTED_STRING . (rule 84)
$default reduce using rule 84 (expr1)
state 31
primary_expr -> TXT_STRING . (rule 92)
$default reduce using rule 92 (primary_expr)
state 32
primary_expr -> NUM_STRING . (rule 91)
$default reduce using rule 91 (primary_expr)
state 33
primary_expr -> '~' . expr (rule 89)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 95
state 34
primary_expr -> '(' . expr ')' (rule 88)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 96
state 35
primary_expr -> '-' . expr (rule 90)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 97
state 36
file -> CMDMODE cmd_objects . (rule 2)
cmd_objects -> cmd_objects . cmd_object (rule 3)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
QUOTE shift, and go to state 29
QUOTED_STRING shift, and go to state 30
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
$default reduce using rule 2 (file)
cmd_object go to state 98
bus_range go to state 38
expr1 go to state 39
simple_range_expr go to state 40
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 53
state 37
cmd_objects -> cmd_object . (rule 4)
$default reduce using rule 4 (cmd_objects)
state 38
cmd_object -> bus_range . (rule 5)
$default reduce using rule 5 (cmd_object)
state 39
bus_range -> expr1 . (rule 81)
$default reduce using rule 81 (bus_range)
state 40
expr1 -> simple_range_expr . (rule 83)
$default reduce using rule 83 (expr1)
state 41
mult_expr -> primary_expr . (rule 95)
$default reduce using rule 95 (mult_expr)
state 42
mult_expr -> mult_expr . '*' primary_expr (rule 96)
mult_expr -> mult_expr . '/' primary_expr (rule 97)
mult_expr -> mult_expr . '%' primary_expr (rule 98)
mult_expr -> mult_expr . TO_POW primary_expr (rule 99)
add_expr -> mult_expr . (rule 100)
TO_POW shift, and go to state 99
'*' shift, and go to state 100
'/' shift, and go to state 101
'%' shift, and go to state 102
TO_POW [reduce using rule 100 (add_expr)]
'*' [reduce using rule 100 (add_expr)]
'/' [reduce using rule 100 (add_expr)]
'%' [reduce using rule 100 (add_expr)]
$default reduce using rule 100 (add_expr)
state 43
add_expr -> add_expr . '+' mult_expr (rule 101)
add_expr -> add_expr . '-' mult_expr (rule 102)
shift_expr -> add_expr . (rule 103)
'-' shift, and go to state 103
'+' shift, and go to state 104
'-' [reduce using rule 103 (shift_expr)]
'+' [reduce using rule 103 (shift_expr)]
$default reduce using rule 103 (shift_expr)
state 44
shift_expr -> shift_expr . SHL add_expr (rule 104)
shift_expr -> shift_expr . SHR add_expr (rule 105)
relational_expr -> shift_expr . (rule 106)
SHL shift, and go to state 105
SHR shift, and go to state 106
SHL [reduce using rule 106 (relational_expr)]
SHR [reduce using rule 106 (relational_expr)]
$default reduce using rule 106 (relational_expr)
state 45
relational_expr -> relational_expr . '>' shift_expr (rule 107)
relational_expr -> relational_expr . '<' shift_expr (rule 108)
equality_expr -> relational_expr . (rule 109)
'>' shift, and go to state 107
'<' shift, and go to state 108
'>' [reduce using rule 109 (equality_expr)]
'<' [reduce using rule 109 (equality_expr)]
$default reduce using rule 109 (equality_expr)
state 46
equality_expr -> equality_expr . EQ_EQ relational_expr (rule 110)
equality_expr -> equality_expr . N_EQ relational_expr (rule 111)
and_expr -> equality_expr . (rule 112)
EQ_EQ shift, and go to state 109
N_EQ shift, and go to state 110
EQ_EQ [reduce using rule 112 (and_expr)]
N_EQ [reduce using rule 112 (and_expr)]
$default reduce using rule 112 (and_expr)
state 47
and_expr -> and_expr . '&' equality_expr (rule 113)
exor_expr -> and_expr . (rule 114)
'&' shift, and go to state 111
'&' [reduce using rule 114 (exor_expr)]
$default reduce using rule 114 (exor_expr)
state 48
exor_expr -> exor_expr . '^' and_expr (rule 115)
or_expr -> exor_expr . (rule 116)
'^' shift, and go to state 112
'^' [reduce using rule 116 (or_expr)]
$default reduce using rule 116 (or_expr)
state 49
or_expr -> or_expr . '|' or_expr (rule 117)
logand_expr -> or_expr . (rule 118)
'|' shift, and go to state 113
'|' [reduce using rule 118 (logand_expr)]
$default reduce using rule 118 (logand_expr)
state 50
logand_expr -> logand_expr . LOG_AND or_expr (rule 119)
logor_expr -> logand_expr . (rule 120)
LOG_AND shift, and go to state 114
LOG_AND [reduce using rule 120 (logor_expr)]
$default reduce using rule 120 (logor_expr)
state 51
logor_expr -> logor_expr . LOG_OR logand_expr (rule 121)
cond_expr -> logor_expr . '?' colon_expr (rule 122)
expr -> logor_expr . (rule 125)
LOG_OR shift, and go to state 115
'?' shift, and go to state 116
LOG_OR [reduce using rule 125 (expr)]
'?' [reduce using rule 125 (expr)]
$default reduce using rule 125 (expr)
state 52
expr -> cond_expr . (rule 124)
$default reduce using rule 124 (expr)
state 53
bus_range -> expr . (rule 82)
simple_range_expr -> expr . TO expr (rule 86)
simple_range_expr -> expr . DOWNTO expr (rule 87)
TO shift, and go to state 117
DOWNTO shift, and go to state 118
$default reduce using rule 82 (bus_range)
state 54
astring -> QUOTED_STRING . (rule 19)
$default reduce using rule 19 (astring)
state 55
astring -> TXT_STRING . (rule 20)
$default reduce using rule 20 (astring)
state 56
astring -> NUM_STRING . (rule 21)
$default reduce using rule 21 (astring)
state 57
chip_id_decl -> CHIP astring . (rule 26)
$default reduce using rule 26 (chip_id_decl)
state 58
components_decl -> COMPONENTS BEGIN_TOK . comp_defn_lines END end_item (rule 300)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
QUOTED_STRING [reduce using rule 303 (comp_defn_lines)]
TXT_STRING [reduce using rule 303 (comp_defn_lines)]
NUM_STRING [reduce using rule 303 (comp_defn_lines)]
$default reduce using rule 303 (comp_defn_lines)
astring go to state 119
comp_defn_lines go to state 120
comp_defn_line go to state 121
chip_ident go to state 122
state 59
nets_decl -> WIRED_NETS @16 . BEGIN_TOK connection_block END end_item (rule 338)
BEGIN_TOK shift, and go to state 123
state 60
joined_decl -> JOINED_NETS BEGIN_TOK . join_decls END end_item (rule 309)
CONN shift, and go to state 124
ALIAS shift, and go to state 125
JUMPER shift, and go to state 126
VHDL_CONN shift, and go to state 127
CONN [reduce using rule 312 (join_decls)]
ALIAS [reduce using rule 312 (join_decls)]
JUMPER [reduce using rule 312 (join_decls)]
GND reduce using rule 312 (join_decls)
GND [reduce using rule 319 (alias_part)]
VCC reduce using rule 312 (join_decls)
VCC [reduce using rule 319 (alias_part)]
VHDL_CONN [reduce using rule 312 (join_decls)]
QUOTED_STRING reduce using rule 312 (join_decls)
QUOTED_STRING [reduce using rule 319 (alias_part)]
TXT_STRING reduce using rule 312 (join_decls)
TXT_STRING [reduce using rule 319 (alias_part)]
NUM_STRING reduce using rule 312 (join_decls)
NUM_STRING [reduce using rule 319 (alias_part)]
$default reduce using rule 312 (join_decls)
join_decls go to state 128
join_decl go to state 129
alias_part go to state 130
state 61
rename_pins_block -> RENAME_PINS BEGIN_TOK . rename_pin_decls END end_item (rule 327)
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 133
rename_pin_decls go to state 134
rename_pin_decl go to state 135
rename_new_name go to state 136
netname go to state 137
state 62
template_name -> astring . (rule 373)
$default reduce using rule 373 (template_name)
state 63
template_id_decl -> TEMPLATE template_name . (rule 372)
$default reduce using rule 372 (template_id_decl)
state 64
ahdl_entityname_decl -> SUBDESIGN . TXT_STRING (rule 386)
TXT_STRING shift, and go to state 138
state 65
ahdl_port_decl -> '(' . ahdl_port_list ')' (rule 387)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
$default reduce using rule 390 (ahdl_port_list)
astring go to state 139
ahdl_port_list go to state 140
ahdl_port_item go to state 141
ahdl_name_list go to state 142
ahdl_name_part go to state 143
state 66
ahdl_region -> AHDL ahdl_chip_decls . END end_item (rule 380)
END shift, and go to state 144
state 67
ahdl_chip_decls -> ahdl_chip_decl . ahdl_chip_decls (rule 381)
ahdl_chip_decls -> ahdl_chip_decl . (rule 382)
SUBDESIGN shift, and go to state 64
'(' shift, and go to state 65
END reduce using rule 382 (ahdl_chip_decls)
END [reduce using rule 385 (ahdl_chip_decl)]
SUBDESIGN [reduce using rule 385 (ahdl_chip_decl)]
'(' [reduce using rule 385 (ahdl_chip_decl)]
$default reduce using rule 382 (ahdl_chip_decls)
ahdl_chip_decls go to state 145
ahdl_chip_decl go to state 67
ahdl_entityname_decl go to state 68
ahdl_port_decl go to state 69
state 68
ahdl_chip_decl -> ahdl_entityname_decl . (rule 383)
$default reduce using rule 383 (ahdl_chip_decl)
state 69
ahdl_chip_decl -> ahdl_port_decl . (rule 384)
$default reduce using rule 384 (ahdl_chip_decl)
state 70
verilog_module_header -> MODULE . hdl_compname_decl verilog_port_list verilog_pindir_block (rule 228)
TXT_STRING shift, and go to state 146
hdl_compname_decl go to state 147
state 71
verilog_region -> VERILOG verilog_blocks . END end_item (rule 222)
verilog_blocks -> verilog_blocks . verilog_block (rule 223)
END shift, and go to state 148
MODULE shift, and go to state 70
END [reduce using rule 227 (verilog_block)]
MODULE [reduce using rule 227 (verilog_block)]
$default reduce using rule 227 (verilog_block)
verilog_block go to state 149
verilog_module_header go to state 73
verilog_toplevel_decl go to state 74
verilog_module_decl go to state 75
state 72
verilog_blocks -> verilog_block . (rule 224)
$default reduce using rule 224 (verilog_blocks)
state 73
verilog_toplevel_decl -> verilog_module_header . verilog_module_body ENDMODULE (rule 229)
verilog_module_decl -> verilog_module_header . ENDMODULE (rule 230)
ENDMODULE shift, and go to state 150
WIRE shift, and go to state 151
ENDMODULE [reduce using rule 249 (verilog_wires_block)]
$default reduce using rule 249 (verilog_wires_block)
verilog_module_body go to state 152
verilog_wires_block go to state 153
verilog_wires_decl go to state 154
verilog_wire_start go to state 155
state 74
verilog_block -> verilog_toplevel_decl . (rule 226)
$default reduce using rule 226 (verilog_block)
state 75
verilog_block -> verilog_module_decl . (rule 225)
$default reduce using rule 225 (verilog_block)
state 76
global_generic_decl -> GENERIC @9 . generic_defn_lines END end_item (rule 265)
CONSTANT shift, and go to state 156
END reduce using rule 270 (generic_defn_lines)
';' reduce using rule 270 (generic_defn_lines)
$default reduce using rule 272 (generic_const_opt)
generic_defn_lines go to state 157
generic_const_opt go to state 158
generic_defn_text go to state 159
state 77
vhdl_chip_decl -> ENTITY . hdl_entityname_decl IS @2 vhdl_generic_decl_opt vhdl_port_decl_opt END TXT_STRING end_item (rule 142)
TXT_STRING shift, and go to state 160
hdl_entityname_decl go to state 161
state 78
vhdl_architecture -> ARCHITECTURE . astring OF astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring end_item (rule 160)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 162
state 79
vhdl_library_decl -> LIBRARY . vhdl_library_list ';' (rule 211)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 163
vhdl_library_list go to state 164
vhdl_library_name go to state 165
state 80
vhdl_use_decl -> USE . vhdl_lib_members ';' (rule 215)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 166
vhdl_lib_members go to state 167
vhdl_lib_member go to state 168
state 81
vhdl_package_decl -> PACKAGE . package_name IS vhdl_package_declarations END astring end_item (rule 168)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 169
package_name go to state 170
state 82
vhdl_region -> VHDL vhdl_blocks . END end_item (rule 132)
vhdl_blocks -> vhdl_blocks . vhdl_block (rule 133)
END shift, and go to state 171
ENTITY shift, and go to state 77
ARCHITECTURE shift, and go to state 78
LIBRARY shift, and go to state 79
USE shift, and go to state 80
PACKAGE shift, and go to state 81
END [reduce using rule 140 (vhdl_block)]
ENTITY [reduce using rule 140 (vhdl_block)]
ARCHITECTURE [reduce using rule 140 (vhdl_block)]
LIBRARY [reduce using rule 140 (vhdl_block)]
USE [reduce using rule 140 (vhdl_block)]
PACKAGE [reduce using rule 140 (vhdl_block)]
$default reduce using rule 140 (vhdl_block)
vhdl_block go to state 172
vhdl_chip_decl go to state 84
vhdl_architecture go to state 85
vhdl_package_decl go to state 86
vhdl_library_decl go to state 87
vhdl_use_decl go to state 88
state 83
vhdl_blocks -> vhdl_block . (rule 134)
$default reduce using rule 134 (vhdl_blocks)
state 84
vhdl_block -> vhdl_chip_decl . (rule 135)
$default reduce using rule 135 (vhdl_block)
state 85
vhdl_block -> vhdl_architecture . (rule 136)
$default reduce using rule 136 (vhdl_block)
state 86
vhdl_block -> vhdl_package_decl . (rule 137)
$default reduce using rule 137 (vhdl_block)
state 87
vhdl_block -> vhdl_library_decl . (rule 138)
$default reduce using rule 138 (vhdl_block)
state 88
vhdl_block -> vhdl_use_decl . (rule 139)
$default reduce using rule 139 (vhdl_block)
state 89
objects -> objects object . (rule 6)
$default reduce using rule 6 (objects)
state 90
chip_body -> BEGIN_TOK . flex_chip_body (rule 23)
DEVICE shift, and go to state 173
UNROUTED shift, and go to state 174
ROUTE_FLAGS shift, and go to state 175
GENERIC shift, and go to state 176
DEVICE [reduce using rule 29 (chip_info_lines)]
UNROUTED [reduce using rule 29 (chip_info_lines)]
ROUTE_FLAGS [reduce using rule 29 (chip_info_lines)]
GENERIC [reduce using rule 29 (chip_info_lines)]
$default reduce using rule 29 (chip_info_lines)
flex_chip_body go to state 177
chip_info_lines go to state 178
chip_info_line go to state 179
device_declaration go to state 180
routing_status go to state 181
route_flags_info go to state 182
chip_generic_decl go to state 183
state 91
chip_body -> ASSIGNED . apex_chip_body (rule 24)
TO shift, and go to state 184
apex_chip_body go to state 185
apex_device_declaration go to state 186
state 92
chip_decl -> chip_id_decl chip_body . (rule 22)
$default reduce using rule 22 (chip_decl)
state 93
template_decl -> template_id_decl BEGIN_TOK . template_info_lines pin_declarations pin_equivalences END end_item (rule 371)
ALIAS shift, and go to state 187
GENERIC shift, and go to state 176
ALIAS [reduce using rule 378 (template_info_line)]
GENERIC [reduce using rule 378 (template_info_line)]
$default reduce using rule 378 (template_info_line)
chip_generic_decl go to state 188
template_info_lines go to state 189
template_info_line go to state 190
alias_to_another_template go to state 191
state 94
expr1 -> QUOTE astring . QUOTE (rule 85)
QUOTE shift, and go to state 192
state 95
primary_expr -> '~' expr . (rule 89)
$default reduce using rule 89 (primary_expr)
state 96
primary_expr -> '(' expr . ')' (rule 88)
')' shift, and go to state 193
state 97
primary_expr -> '-' expr . (rule 90)
$default reduce using rule 90 (primary_expr)
state 98
cmd_objects -> cmd_objects cmd_object . (rule 3)
$default reduce using rule 3 (cmd_objects)
state 99
mult_expr -> mult_expr TO_POW . primary_expr (rule 99)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 194
state 100
mult_expr -> mult_expr '*' . primary_expr (rule 96)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 195
state 101
mult_expr -> mult_expr '/' . primary_expr (rule 97)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 196
state 102
mult_expr -> mult_expr '%' . primary_expr (rule 98)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 197
state 103
add_expr -> add_expr '-' . mult_expr (rule 102)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 198
state 104
add_expr -> add_expr '+' . mult_expr (rule 101)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 199
state 105
shift_expr -> shift_expr SHL . add_expr (rule 104)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 200
state 106
shift_expr -> shift_expr SHR . add_expr (rule 105)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 201
state 107
relational_expr -> relational_expr '>' . shift_expr (rule 107)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 202
state 108
relational_expr -> relational_expr '<' . shift_expr (rule 108)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 203
state 109
equality_expr -> equality_expr EQ_EQ . relational_expr (rule 110)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 204
state 110
equality_expr -> equality_expr N_EQ . relational_expr (rule 111)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 205
state 111
and_expr -> and_expr '&' . equality_expr (rule 113)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 206
state 112
exor_expr -> exor_expr '^' . and_expr (rule 115)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 207
state 113
or_expr -> or_expr '|' . or_expr (rule 117)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 208
state 114
logand_expr -> logand_expr LOG_AND . or_expr (rule 119)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 209
state 115
logor_expr -> logor_expr LOG_OR . logand_expr (rule 121)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 210
state 116
cond_expr -> logor_expr '?' . colon_expr (rule 122)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
colon_expr go to state 211
expr go to state 212
state 117
simple_range_expr -> expr TO . expr (rule 86)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 213
state 118
simple_range_expr -> expr DOWNTO . expr (rule 87)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 214
state 119
chip_ident -> astring . (rule 305)
$default reduce using rule 305 (chip_ident)
state 120
components_decl -> COMPONENTS BEGIN_TOK comp_defn_lines . END end_item (rule 300)
comp_defn_lines -> comp_defn_lines . comp_defn_line (rule 301)
END shift, and go to state 215
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 119
comp_defn_line go to state 216
chip_ident go to state 122
state 121
comp_defn_lines -> comp_defn_line . (rule 302)
$default reduce using rule 302 (comp_defn_lines)
state 122
comp_defn_line -> chip_ident . ':' chip_name chip_type chip_value end_item (rule 304)
':' shift, and go to state 217
state 123
nets_decl -> WIRED_NETS @16 BEGIN_TOK . connection_block END end_item (rule 338)
CONN shift, and go to state 218
UNROUTED shift, and go to state 219
ROUTED shift, and go to state 220
NAMED shift, and go to state 221
CONN [reduce using rule 345 (connection_block_item)]
UNROUTED [reduce using rule 345 (connection_block_item)]
ROUTED [reduce using rule 345 (connection_block_item)]
NAMED [reduce using rule 345 (connection_block_item)]
$default reduce using rule 345 (connection_block_item)
connection_block go to state 222
connection_block_item go to state 223
routed_decl go to state 224
unrouted_decl go to state 225
named_decl go to state 226
conn_decls go to state 227
conn_decl go to state 228
state 124
join_decl -> CONN . astring astring @15 end_item (rule 315)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 229
state 125
alias_part -> ALIAS . (rule 317)
$default reduce using rule 317 (alias_part)
state 126
alias_part -> JUMPER . (rule 318)
$default reduce using rule 318 (alias_part)
state 127
join_decl -> VHDL_CONN . vhdl_concurrent_assignment (rule 316)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 230
vhdl_concurrent_assignment go to state 231
state 128
joined_decl -> JOINED_NETS BEGIN_TOK join_decls . END end_item (rule 309)
join_decls -> join_decls . join_decl (rule 310)
END shift, and go to state 232
CONN shift, and go to state 124
ALIAS shift, and go to state 125
JUMPER shift, and go to state 126
VHDL_CONN shift, and go to state 127
$default reduce using rule 319 (alias_part)
join_decl go to state 233
alias_part go to state 130
state 129
join_decls -> join_decl . (rule 311)
$default reduce using rule 311 (join_decls)
state 130
join_decl -> alias_part . root_net '=' '(' joined_nets ')' end_item (rule 313)
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 133
root_net go to state 234
netname go to state 235
state 131
netname -> GND . (rule 369)
$default reduce using rule 369 (netname)
state 132
netname -> VCC . (rule 368)
$default reduce using rule 368 (netname)
state 133
netname -> astring . (rule 370)
$default reduce using rule 370 (netname)
state 134
rename_pins_block -> RENAME_PINS BEGIN_TOK rename_pin_decls . END end_item (rule 327)
rename_pin_decls -> rename_pin_decls . rename_pin_decl (rule 328)
END shift, and go to state 236
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 133
rename_pin_decl go to state 237
rename_new_name go to state 136
netname go to state 137
state 135
rename_pin_decls -> rename_pin_decl . (rule 329)
$default reduce using rule 329 (rename_pin_decls)
state 136
rename_pin_decl -> rename_new_name . '=' '(' rename_pin_items ')' end_item (rule 330)
'=' shift, and go to state 238
state 137
rename_new_name -> netname . (rule 331)
rename_new_name -> netname . '(' bus_range ')' (rule 332)
'(' shift, and go to state 239
'(' [reduce using rule 331 (rename_new_name)]
$default reduce using rule 331 (rename_new_name)
state 138
ahdl_entityname_decl -> SUBDESIGN TXT_STRING . (rule 386)
$default reduce using rule 386 (ahdl_entityname_decl)
state 139
ahdl_name_part -> astring . (rule 394)
$default reduce using rule 394 (ahdl_name_part)
state 140
ahdl_port_decl -> '(' ahdl_port_list . ')' (rule 387)
ahdl_port_list -> ahdl_port_list . end_item ahdl_port_item (rule 388)
';' shift, and go to state 240
')' shift, and go to state 241
end_item go to state 242
state 141
ahdl_port_list -> ahdl_port_item . (rule 389)
$default reduce using rule 389 (ahdl_port_list)
state 142
ahdl_port_item -> ahdl_name_list . ':' pin_dir (rule 391)
ahdl_name_list -> ahdl_name_list . ',' ahdl_name_part (rule 392)
':' shift, and go to state 243
',' shift, and go to state 244
state 143
ahdl_name_list -> ahdl_name_part . (rule 393)
$default reduce using rule 393 (ahdl_name_list)
state 144
ahdl_region -> AHDL ahdl_chip_decls END . end_item (rule 380)
';' shift, and go to state 240
end_item go to state 245
state 145
ahdl_chip_decls -> ahdl_chip_decl ahdl_chip_decls . (rule 381)
$default reduce using rule 381 (ahdl_chip_decls)
state 146
hdl_compname_decl -> TXT_STRING . (rule 178)
$default reduce using rule 178 (hdl_compname_decl)
state 147
verilog_module_header -> MODULE hdl_compname_decl . verilog_port_list verilog_pindir_block (rule 228)
'(' shift, and go to state 246
$default reduce using rule 233 (verilog_port_list)
verilog_port_list go to state 247
state 148
verilog_region -> VERILOG verilog_blocks END . end_item (rule 222)
';' shift, and go to state 240
end_item go to state 248
state 149
verilog_blocks -> verilog_blocks verilog_block . (rule 223)
$default reduce using rule 223 (verilog_blocks)
state 150
verilog_module_decl -> verilog_module_header ENDMODULE . (rule 230)
$default reduce using rule 230 (verilog_module_decl)
state 151
verilog_wire_start -> WIRE . (rule 251)
$default reduce using rule 251 (verilog_wire_start)
state 152
verilog_toplevel_decl -> verilog_module_header verilog_module_body . ENDMODULE (rule 229)
ENDMODULE shift, and go to state 249
state 153
verilog_module_body -> verilog_wires_block . verilog_module_instance_block (rule 241)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
QUOTED_STRING [reduce using rule 256 (verilog_module_instances)]
TXT_STRING [reduce using rule 256 (verilog_module_instances)]
NUM_STRING [reduce using rule 256 (verilog_module_instances)]
$default reduce using rule 256 (verilog_module_instances)
astring go to state 250
verilog_module_instance_block go to state 251
verilog_module_instances go to state 252
verilog_module_instance go to state 253
state 154
verilog_wires_block -> verilog_wires_decl . verilog_wires_block (rule 247)
verilog_wires_block -> verilog_wires_decl . (rule 248)
WIRE shift, and go to state 151
ENDMODULE reduce using rule 248 (verilog_wires_block)
ENDMODULE [reduce using rule 249 (verilog_wires_block)]
QUOTED_STRING reduce using rule 248 (verilog_wires_block)
QUOTED_STRING [reduce using rule 249 (verilog_wires_block)]
TXT_STRING reduce using rule 248 (verilog_wires_block)
TXT_STRING [reduce using rule 249 (verilog_wires_block)]
NUM_STRING reduce using rule 248 (verilog_wires_block)
NUM_STRING [reduce using rule 249 (verilog_wires_block)]
$default reduce using rule 248 (verilog_wires_block)
verilog_wires_block go to state 254
verilog_wires_decl go to state 154
verilog_wire_start go to state 155
state 155
verilog_wires_decl -> verilog_wire_start . verilog_bus_expr hdl_signal_names verilog_wire_end (rule 250)
'[' shift, and go to state 255
$default reduce using rule 240 (verilog_bus_expr)
verilog_bus_expr go to state 256
state 156
generic_const_opt -> CONSTANT . (rule 271)
$default reduce using rule 271 (generic_const_opt)
state 157
global_generic_decl -> GENERIC @9 generic_defn_lines . END end_item (rule 265)
generic_defn_lines -> generic_defn_lines . end_item generic_defn_text (rule 268)
END shift, and go to state 257
';' shift, and go to state 240
end_item go to state 258
state 158
generic_defn_text -> generic_const_opt . generic_defn_name_list ':' generic_pindir_opt generic_defn_type (rule 275)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 259
generic_defn_name_list go to state 260
generic_defn_name go to state 261
state 159
generic_defn_lines -> generic_defn_text . (rule 269)
$default reduce using rule 269 (generic_defn_lines)
state 160
hdl_entityname_decl -> TXT_STRING . (rule 143)
$default reduce using rule 143 (hdl_entityname_decl)
state 161
vhdl_chip_decl -> ENTITY hdl_entityname_decl . IS @2 vhdl_generic_decl_opt vhdl_port_decl_opt END TXT_STRING end_item (rule 142)
IS shift, and go to state 262
state 162
vhdl_architecture -> ARCHITECTURE astring . OF astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring end_item (rule 160)
OF shift, and go to state 263
state 163
vhdl_library_name -> astring . (rule 214)
$default reduce using rule 214 (vhdl_library_name)
state 164
vhdl_library_decl -> LIBRARY vhdl_library_list . ';' (rule 211)
';' shift, and go to state 264
state 165
vhdl_library_list -> vhdl_library_name . ',' vhdl_library_list (rule 212)
vhdl_library_list -> vhdl_library_name . (rule 213)
',' shift, and go to state 265
$default reduce using rule 213 (vhdl_library_list)
state 166
vhdl_lib_member -> astring . '.' astring '.' vhdl_lib_member_select (rule 218)
vhdl_lib_member -> astring . '.' vhdl_lib_member_select (rule 219)
'.' shift, and go to state 266
state 167
vhdl_use_decl -> USE vhdl_lib_members . ';' (rule 215)
';' shift, and go to state 267
state 168
vhdl_lib_members -> vhdl_lib_member . ',' vhdl_lib_members (rule 216)
vhdl_lib_members -> vhdl_lib_member . (rule 217)
',' shift, and go to state 268
$default reduce using rule 217 (vhdl_lib_members)
state 169
package_name -> astring . (rule 169)
$default reduce using rule 169 (package_name)
state 170
vhdl_package_decl -> PACKAGE package_name . IS vhdl_package_declarations END astring end_item (rule 168)
IS shift, and go to state 269
state 171
vhdl_region -> VHDL vhdl_blocks END . end_item (rule 132)
';' shift, and go to state 240
end_item go to state 270
state 172
vhdl_blocks -> vhdl_blocks vhdl_block . (rule 133)
$default reduce using rule 133 (vhdl_blocks)
state 173
device_declaration -> DEVICE . '=' astring end_item (rule 34)
'=' shift, and go to state 271
state 174
routing_status -> UNROUTED . end_item (rule 39)
';' shift, and go to state 240
end_item go to state 272
state 175
route_flags_info -> ROUTE_FLAGS . '=' route_flag_value end_item (rule 40)
'=' shift, and go to state 273
state 176
chip_generic_decl -> GENERIC . @10 generic_defn_lines END end_item (rule 267)
$default reduce using rule 266 (@10)
@10 go to state 274
state 177
chip_body -> BEGIN_TOK flex_chip_body . (rule 23)
$default reduce using rule 23 (chip_body)
state 178
flex_chip_body -> chip_info_lines . pin_declarations pin_equivalences END end_item (rule 25)
chip_info_lines -> chip_info_lines . chip_info_line (rule 27)
DEVICE shift, and go to state 173
UNROUTED shift, and go to state 174
ROUTE_FLAGS shift, and go to state 175
GENERIC shift, and go to state 176
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
GND [reduce using rule 44 (pin_declarations)]
VCC [reduce using rule 44 (pin_declarations)]
QUOTED_STRING [reduce using rule 44 (pin_declarations)]
TXT_STRING [reduce using rule 44 (pin_declarations)]
NUM_STRING [reduce using rule 44 (pin_declarations)]
$default reduce using rule 44 (pin_declarations)
astring go to state 133
chip_info_line go to state 275
device_declaration go to state 180
routing_status go to state 181
route_flags_info go to state 182
pin_declarations go to state 276
pin_declaration go to state 277
name_part go to state 278
chip_generic_decl go to state 183
netname go to state 279
state 179
chip_info_lines -> chip_info_line . (rule 28)
$default reduce using rule 28 (chip_info_lines)
state 180
chip_info_line -> device_declaration . (rule 30)
$default reduce using rule 30 (chip_info_line)
state 181
chip_info_line -> routing_status . (rule 32)
$default reduce using rule 32 (chip_info_line)
state 182
chip_info_line -> route_flags_info . (rule 31)
$default reduce using rule 31 (chip_info_line)
state 183
chip_info_line -> chip_generic_decl . (rule 33)
$default reduce using rule 33 (chip_info_line)
state 184
apex_device_declaration -> TO . AN astring apex_speed_grade (rule 55)
AN shift, and go to state 280
state 185
chip_body -> ASSIGNED apex_chip_body . (rule 24)
$default reduce using rule 24 (chip_body)
state 186
apex_chip_body -> apex_device_declaration . apex_info_lines (rule 54)
GND shift, and go to state 281
GND_RES_IO shift, and go to state 282
GND_RES_IN shift, and go to state 283
VCC shift, and go to state 284
TXT_STRING shift, and go to state 285
apex_info_lines go to state 286
apex_info_line go to state 287
state 187
alias_to_another_template -> ALIAS . astring end_item (rule 379)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 288
state 188
template_info_line -> chip_generic_decl . (rule 376)
$default reduce using rule 376 (template_info_line)
state 189
template_decl -> template_id_decl BEGIN_TOK template_info_lines . pin_declarations pin_equivalences END end_item (rule 371)
template_info_lines -> template_info_lines . template_info_line (rule 374)
ALIAS shift, and go to state 187
GENERIC shift, and go to state 176
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
END reduce using rule 44 (pin_declarations)
END [reduce using rule 378 (template_info_line)]
ALIAS [reduce using rule 378 (template_info_line)]
GENERIC [reduce using rule 378 (template_info_line)]
EQUIVALENT reduce using rule 44 (pin_declarations)
EQUIVALENT [reduce using rule 378 (template_info_line)]
GND [reduce using rule 44 (pin_declarations)]
GND [reduce using rule 378 (template_info_line)]
VCC [reduce using rule 44 (pin_declarations)]
VCC [reduce using rule 378 (template_info_line)]
QUOTED_STRING [reduce using rule 44 (pin_declarations)]
QUOTED_STRING [reduce using rule 378 (template_info_line)]
TXT_STRING [reduce using rule 44 (pin_declarations)]
TXT_STRING [reduce using rule 378 (template_info_line)]
NUM_STRING [reduce using rule 44 (pin_declarations)]
NUM_STRING [reduce using rule 378 (template_info_line)]
$default reduce using rule 44 (pin_declarations)
astring go to state 133
pin_declarations go to state 289
pin_declaration go to state 277
name_part go to state 278
chip_generic_decl go to state 188
netname go to state 279
template_info_line go to state 290
alias_to_another_template go to state 191
state 190
template_info_lines -> template_info_line . (rule 375)
$default reduce using rule 375 (template_info_lines)
state 191
template_info_line -> alias_to_another_template . (rule 377)
$default reduce using rule 377 (template_info_line)
state 192
expr1 -> QUOTE astring QUOTE . (rule 85)
$default reduce using rule 85 (expr1)
state 193
primary_expr -> '(' expr ')' . (rule 88)
$default reduce using rule 88 (primary_expr)
state 194
mult_expr -> mult_expr TO_POW primary_expr . (rule 99)
$default reduce using rule 99 (mult_expr)
state 195
mult_expr -> mult_expr '*' primary_expr . (rule 96)
$default reduce using rule 96 (mult_expr)
state 196
mult_expr -> mult_expr '/' primary_expr . (rule 97)
$default reduce using rule 97 (mult_expr)
state 197
mult_expr -> mult_expr '%' primary_expr . (rule 98)
$default reduce using rule 98 (mult_expr)
state 198
mult_expr -> mult_expr . '*' primary_expr (rule 96)
mult_expr -> mult_expr . '/' primary_expr (rule 97)
mult_expr -> mult_expr . '%' primary_expr (rule 98)
mult_expr -> mult_expr . TO_POW primary_expr (rule 99)
add_expr -> add_expr '-' mult_expr . (rule 102)
TO_POW shift, and go to state 99
'*' shift, and go to state 100
'/' shift, and go to state 101
'%' shift, and go to state 102
TO_POW [reduce using rule 102 (add_expr)]
'*' [reduce using rule 102 (add_expr)]
'/' [reduce using rule 102 (add_expr)]
'%' [reduce using rule 102 (add_expr)]
$default reduce using rule 102 (add_expr)
state 199
mult_expr -> mult_expr . '*' primary_expr (rule 96)
mult_expr -> mult_expr . '/' primary_expr (rule 97)
mult_expr -> mult_expr . '%' primary_expr (rule 98)
mult_expr -> mult_expr . TO_POW primary_expr (rule 99)
add_expr -> add_expr '+' mult_expr . (rule 101)
TO_POW shift, and go to state 99
'*' shift, and go to state 100
'/' shift, and go to state 101
'%' shift, and go to state 102
TO_POW [reduce using rule 101 (add_expr)]
'*' [reduce using rule 101 (add_expr)]
'/' [reduce using rule 101 (add_expr)]
'%' [reduce using rule 101 (add_expr)]
$default reduce using rule 101 (add_expr)
state 200
add_expr -> add_expr . '+' mult_expr (rule 101)
add_expr -> add_expr . '-' mult_expr (rule 102)
shift_expr -> shift_expr SHL add_expr . (rule 104)
'-' shift, and go to state 103
'+' shift, and go to state 104
'-' [reduce using rule 104 (shift_expr)]
'+' [reduce using rule 104 (shift_expr)]
$default reduce using rule 104 (shift_expr)
state 201
add_expr -> add_expr . '+' mult_expr (rule 101)
add_expr -> add_expr . '-' mult_expr (rule 102)
shift_expr -> shift_expr SHR add_expr . (rule 105)
'-' shift, and go to state 103
'+' shift, and go to state 104
'-' [reduce using rule 105 (shift_expr)]
'+' [reduce using rule 105 (shift_expr)]
$default reduce using rule 105 (shift_expr)
state 202
shift_expr -> shift_expr . SHL add_expr (rule 104)
shift_expr -> shift_expr . SHR add_expr (rule 105)
relational_expr -> relational_expr '>' shift_expr . (rule 107)
SHL shift, and go to state 105
SHR shift, and go to state 106
SHL [reduce using rule 107 (relational_expr)]
SHR [reduce using rule 107 (relational_expr)]
$default reduce using rule 107 (relational_expr)
state 203
shift_expr -> shift_expr . SHL add_expr (rule 104)
shift_expr -> shift_expr . SHR add_expr (rule 105)
relational_expr -> relational_expr '<' shift_expr . (rule 108)
SHL shift, and go to state 105
SHR shift, and go to state 106
SHL [reduce using rule 108 (relational_expr)]
SHR [reduce using rule 108 (relational_expr)]
$default reduce using rule 108 (relational_expr)
state 204
relational_expr -> relational_expr . '>' shift_expr (rule 107)
relational_expr -> relational_expr . '<' shift_expr (rule 108)
equality_expr -> equality_expr EQ_EQ relational_expr . (rule 110)
'>' shift, and go to state 107
'<' shift, and go to state 108
'>' [reduce using rule 110 (equality_expr)]
'<' [reduce using rule 110 (equality_expr)]
$default reduce using rule 110 (equality_expr)
state 205
relational_expr -> relational_expr . '>' shift_expr (rule 107)
relational_expr -> relational_expr . '<' shift_expr (rule 108)
equality_expr -> equality_expr N_EQ relational_expr . (rule 111)
'>' shift, and go to state 107
'<' shift, and go to state 108
'>' [reduce using rule 111 (equality_expr)]
'<' [reduce using rule 111 (equality_expr)]
$default reduce using rule 111 (equality_expr)
state 206
equality_expr -> equality_expr . EQ_EQ relational_expr (rule 110)
equality_expr -> equality_expr . N_EQ relational_expr (rule 111)
and_expr -> and_expr '&' equality_expr . (rule 113)
EQ_EQ shift, and go to state 109
N_EQ shift, and go to state 110
EQ_EQ [reduce using rule 113 (and_expr)]
N_EQ [reduce using rule 113 (and_expr)]
$default reduce using rule 113 (and_expr)
state 207
and_expr -> and_expr . '&' equality_expr (rule 113)
exor_expr -> exor_expr '^' and_expr . (rule 115)
'&' shift, and go to state 111
'&' [reduce using rule 115 (exor_expr)]
$default reduce using rule 115 (exor_expr)
state 208
or_expr -> or_expr . '|' or_expr (rule 117)
or_expr -> or_expr '|' or_expr . (rule 117)
'|' shift, and go to state 113
'|' [reduce using rule 117 (or_expr)]
$default reduce using rule 117 (or_expr)
state 209
or_expr -> or_expr . '|' or_expr (rule 117)
logand_expr -> logand_expr LOG_AND or_expr . (rule 119)
'|' shift, and go to state 113
'|' [reduce using rule 119 (logand_expr)]
$default reduce using rule 119 (logand_expr)
state 210
logand_expr -> logand_expr . LOG_AND or_expr (rule 119)
logor_expr -> logor_expr LOG_OR logand_expr . (rule 121)
LOG_AND shift, and go to state 114
LOG_AND [reduce using rule 121 (logor_expr)]
$default reduce using rule 121 (logor_expr)
state 211
cond_expr -> logor_expr '?' colon_expr . (rule 122)
$default reduce using rule 122 (cond_expr)
state 212
colon_expr -> expr . ':' expr (rule 123)
':' shift, and go to state 291
state 213
simple_range_expr -> expr TO expr . (rule 86)
$default reduce using rule 86 (simple_range_expr)
state 214
simple_range_expr -> expr DOWNTO expr . (rule 87)
$default reduce using rule 87 (simple_range_expr)
state 215
components_decl -> COMPONENTS BEGIN_TOK comp_defn_lines END . end_item (rule 300)
';' shift, and go to state 240
end_item go to state 292
state 216
comp_defn_lines -> comp_defn_lines comp_defn_line . (rule 301)
$default reduce using rule 301 (comp_defn_lines)
state 217
comp_defn_line -> chip_ident ':' . chip_name chip_type chip_value end_item (rule 304)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 293
chip_name go to state 294
state 218
conn_decl -> CONN . conn_ident conn_name last_route_status end_item nodelist END_CONN @17 end_item (rule 352)
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 133
conn_ident go to state 295
netname go to state 296
state 219
unrouted_decl -> UNROUTED . (rule 347)
$default reduce using rule 347 (unrouted_decl)
state 220
routed_decl -> ROUTED . (rule 346)
$default reduce using rule 346 (routed_decl)
state 221
named_decl -> NAMED . (rule 348)
$default reduce using rule 348 (named_decl)
state 222
nets_decl -> WIRED_NETS @16 BEGIN_TOK connection_block . END end_item (rule 338)
connection_block -> connection_block . connection_block_item (rule 339)
END shift, and go to state 297
CONN shift, and go to state 218
UNROUTED shift, and go to state 219
ROUTED shift, and go to state 220
NAMED shift, and go to state 221
END [reduce using rule 345 (connection_block_item)]
CONN [reduce using rule 345 (connection_block_item)]
UNROUTED [reduce using rule 345 (connection_block_item)]
ROUTED [reduce using rule 345 (connection_block_item)]
NAMED [reduce using rule 345 (connection_block_item)]
$default reduce using rule 345 (connection_block_item)
connection_block_item go to state 298
routed_decl go to state 224
unrouted_decl go to state 225
named_decl go to state 226
conn_decls go to state 227
conn_decl go to state 228
state 223
connection_block -> connection_block_item . (rule 340)
$default reduce using rule 340 (connection_block)
state 224
connection_block_item -> routed_decl . (rule 341)
$default reduce using rule 341 (connection_block_item)
state 225
connection_block_item -> unrouted_decl . (rule 342)
$default reduce using rule 342 (connection_block_item)
state 226
connection_block_item -> named_decl . (rule 343)
$default reduce using rule 343 (connection_block_item)
state 227
connection_block_item -> conn_decls . (rule 344)
conn_decls -> conn_decls . conn_decl (rule 349)
CONN shift, and go to state 218
CONN [reduce using rule 344 (connection_block_item)]
$default reduce using rule 344 (connection_block_item)
conn_decl go to state 299
state 228
conn_decls -> conn_decl . (rule 350)
$default reduce using rule 350 (conn_decls)
state 229
join_decl -> CONN astring . astring @15 end_item (rule 315)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 300
state 230
vhdl_concurrent_assignment -> astring . SIG_ASSIGN astring end_item (rule 210)
SIG_ASSIGN shift, and go to state 301
state 231
join_decl -> VHDL_CONN vhdl_concurrent_assignment . (rule 316)
$default reduce using rule 316 (join_decl)
state 232
joined_decl -> JOINED_NETS BEGIN_TOK join_decls END . end_item (rule 309)
';' shift, and go to state 240
end_item go to state 302
state 233
join_decls -> join_decls join_decl . (rule 310)
$default reduce using rule 310 (join_decls)
state 234
join_decl -> alias_part root_net . '=' '(' joined_nets ')' end_item (rule 313)
'=' shift, and go to state 303
state 235
root_net -> netname . (rule 320)
$default reduce using rule 320 (root_net)
state 236
rename_pins_block -> RENAME_PINS BEGIN_TOK rename_pin_decls END . end_item (rule 327)
';' shift, and go to state 240
end_item go to state 304
state 237
rename_pin_decls -> rename_pin_decls rename_pin_decl . (rule 328)
$default reduce using rule 328 (rename_pin_decls)
state 238
rename_pin_decl -> rename_new_name '=' . '(' rename_pin_items ')' end_item (rule 330)
'(' shift, and go to state 305
state 239
rename_new_name -> netname '(' . bus_range ')' (rule 332)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
QUOTE shift, and go to state 29
QUOTED_STRING shift, and go to state 30
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
bus_range go to state 306
expr1 go to state 39
simple_range_expr go to state 40
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 53
state 240
end_item -> ';' . (rule 38)
$default reduce using rule 38 (end_item)
state 241
ahdl_port_decl -> '(' ahdl_port_list ')' . (rule 387)
$default reduce using rule 387 (ahdl_port_decl)
state 242
ahdl_port_list -> ahdl_port_list end_item . ahdl_port_item (rule 388)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 139
ahdl_port_item go to state 307
ahdl_name_list go to state 142
ahdl_name_part go to state 143
state 243
ahdl_port_item -> ahdl_name_list ':' . pin_dir (rule 391)
PINDIR shift, and go to state 308
pin_dir go to state 309
state 244
ahdl_name_list -> ahdl_name_list ',' . ahdl_name_part (rule 392)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 139
ahdl_name_part go to state 310
state 245
ahdl_region -> AHDL ahdl_chip_decls END end_item . (rule 380)
$default reduce using rule 380 (ahdl_region)
state 246
verilog_port_list -> '(' . verilog_ports ')' ';' @7 verilog_pindir_block (rule 232)
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
$default reduce using rule 236 (verilog_ports)
astring go to state 133
hdl_name_part go to state 311
verilog_ports go to state 312
verilog_port go to state 313
netname go to state 314
state 247
verilog_module_header -> MODULE hdl_compname_decl verilog_port_list . verilog_pindir_block (rule 228)
PINDIR shift, and go to state 308
PINDIR [reduce using rule 244 (verilog_pindir_block)]
$default reduce using rule 244 (verilog_pindir_block)
pin_dir go to state 315
verilog_pindir_block go to state 316
verilog_pindir_decl go to state 317
state 248
verilog_region -> VERILOG verilog_blocks END end_item . (rule 222)
$default reduce using rule 222 (verilog_region)
state 249
verilog_toplevel_decl -> verilog_module_header verilog_module_body ENDMODULE . (rule 229)
$default reduce using rule 229 (verilog_toplevel_decl)
state 250
verilog_module_instance -> astring . astring '(' verilog_port_map_list ')' ';' (rule 257)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 318
state 251
verilog_module_body -> verilog_wires_block verilog_module_instance_block . (rule 241)
$default reduce using rule 241 (verilog_module_body)
state 252
verilog_module_instance_block -> verilog_module_instances . (rule 253)
verilog_module_instances -> verilog_module_instances . verilog_module_instance (rule 254)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
$default reduce using rule 253 (verilog_module_instance_block)
astring go to state 250
verilog_module_instance go to state 319
state 253
verilog_module_instances -> verilog_module_instance . (rule 255)
$default reduce using rule 255 (verilog_module_instances)
state 254
verilog_wires_block -> verilog_wires_decl verilog_wires_block . (rule 247)
$default reduce using rule 247 (verilog_wires_block)
state 255
verilog_bus_expr -> '[' . expr ']' (rule 238)
verilog_bus_expr -> '[' . expr ':' expr ']' (rule 239)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 320
state 256
verilog_wires_decl -> verilog_wire_start verilog_bus_expr . hdl_signal_names verilog_wire_end (rule 250)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 321
hdl_signal_names go to state 322
hdl_signal_name go to state 323
state 257
global_generic_decl -> GENERIC @9 generic_defn_lines END . end_item (rule 265)
';' shift, and go to state 240
end_item go to state 324
state 258
generic_defn_lines -> generic_defn_lines end_item . generic_defn_text (rule 268)
CONSTANT shift, and go to state 156
$default reduce using rule 272 (generic_const_opt)
generic_const_opt go to state 158
generic_defn_text go to state 325
state 259
generic_defn_name -> astring . (rule 278)
$default reduce using rule 278 (generic_defn_name)
state 260
generic_defn_text -> generic_const_opt generic_defn_name_list . ':' generic_pindir_opt generic_defn_type (rule 275)
generic_defn_name_list -> generic_defn_name_list . ',' generic_defn_name (rule 276)
':' shift, and go to state 326
',' shift, and go to state 327
state 261
generic_defn_name_list -> generic_defn_name . (rule 277)
$default reduce using rule 277 (generic_defn_name_list)
state 262
vhdl_chip_decl -> ENTITY hdl_entityname_decl IS . @2 vhdl_generic_decl_opt vhdl_port_decl_opt END TXT_STRING end_item (rule 142)
$default reduce using rule 141 (@2)
@2 go to state 328
state 263
vhdl_architecture -> ARCHITECTURE astring OF . astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring end_item (rule 160)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 329
state 264
vhdl_library_decl -> LIBRARY vhdl_library_list ';' . (rule 211)
$default reduce using rule 211 (vhdl_library_decl)
state 265
vhdl_library_list -> vhdl_library_name ',' . vhdl_library_list (rule 212)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 163
vhdl_library_list go to state 330
vhdl_library_name go to state 165
state 266
vhdl_lib_member -> astring '.' . astring '.' vhdl_lib_member_select (rule 218)
vhdl_lib_member -> astring '.' . vhdl_lib_member_select (rule 219)
ALL shift, and go to state 331
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 332
vhdl_lib_member_select go to state 333
state 267
vhdl_use_decl -> USE vhdl_lib_members ';' . (rule 215)
$default reduce using rule 215 (vhdl_use_decl)
state 268
vhdl_lib_members -> vhdl_lib_member ',' . vhdl_lib_members (rule 216)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 166
vhdl_lib_members go to state 334
vhdl_lib_member go to state 168
state 269
vhdl_package_decl -> PACKAGE package_name IS . vhdl_package_declarations END astring end_item (rule 168)
SIGNAL shift, and go to state 335
CONSTANT shift, and go to state 336
COMPONENT shift, and go to state 337
FOR shift, and go to state 338
SIGNAL [reduce using rule 172 (vhdl_package_declarations)]
CONSTANT [reduce using rule 172 (vhdl_package_declarations)]
COMPONENT [reduce using rule 172 (vhdl_package_declarations)]
FOR [reduce using rule 172 (vhdl_package_declarations)]
$default reduce using rule 172 (vhdl_package_declarations)
vhdl_package_declarations go to state 339
vhdl_package_decl_item go to state 340
vhdl_component_decl go to state 341
vhdl_constant_decl go to state 342
vhdl_signal_decl go to state 343
vhdl_configuration_decl go to state 344
state 270
vhdl_region -> VHDL vhdl_blocks END end_item . (rule 132)
$default reduce using rule 132 (vhdl_region)
state 271
device_declaration -> DEVICE '=' . astring end_item (rule 34)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 345
state 272
routing_status -> UNROUTED end_item . (rule 39)
$default reduce using rule 39 (routing_status)
state 273
route_flags_info -> ROUTE_FLAGS '=' . route_flag_value end_item (rule 40)
NUM_STRING shift, and go to state 346
route_flag_value go to state 347
state 274
chip_generic_decl -> GENERIC @10 . generic_defn_lines END end_item (rule 267)
CONSTANT shift, and go to state 156
END reduce using rule 270 (generic_defn_lines)
';' reduce using rule 270 (generic_defn_lines)
$default reduce using rule 272 (generic_const_opt)
generic_defn_lines go to state 348
generic_const_opt go to state 158
generic_defn_text go to state 159
state 275
chip_info_lines -> chip_info_lines chip_info_line . (rule 27)
$default reduce using rule 27 (chip_info_lines)
state 276
flex_chip_body -> chip_info_lines pin_declarations . pin_equivalences END end_item (rule 25)
pin_declarations -> pin_declarations . pin_declaration (rule 42)
EQUIVALENT shift, and go to state 349
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
$default reduce using rule 37 (pin_equivalences)
astring go to state 133
pin_equivalences go to state 350
pin_declaration go to state 351
name_part go to state 278
pin_equivalence go to state 352
netname go to state 279
state 277
pin_declarations -> pin_declaration . (rule 43)
$default reduce using rule 43 (pin_declarations)
state 278
pin_declaration -> name_part . ':' pin_rest end_item (rule 45)
':' shift, and go to state 353
state 279
name_part -> netname . (rule 46)
$default reduce using rule 46 (name_part)
state 280
apex_device_declaration -> TO AN . astring apex_speed_grade (rule 55)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 354
state 281
apex_info_line -> GND . ':' astring more_colons (rule 60)
':' shift, and go to state 355
state 282
apex_info_line -> GND_RES_IO . ':' astring more_colons (rule 61)
':' shift, and go to state 356
state 283
apex_info_line -> GND_RES_IN . ':' astring more_colons (rule 62)
':' shift, and go to state 357
state 284
apex_info_line -> VCC . ':' astring ':' NUM_STRING (rule 63)
apex_info_line -> VCC . ':' astring more_colons (rule 64)
':' shift, and go to state 358
state 285
apex_info_line -> TXT_STRING . ':' astring more_colons (rule 65)
apex_info_line -> TXT_STRING . ':' astring ':' PINDIR ':' astring ':' (rule 66)
apex_info_line -> TXT_STRING . '[' expr ']' ':' astring ':' PINDIR ':' astring ':' (rule 67)
':' shift, and go to state 359
'[' shift, and go to state 360
state 286
apex_chip_body -> apex_device_declaration apex_info_lines . (rule 54)
apex_info_lines -> apex_info_lines . apex_info_line (rule 58)
GND shift, and go to state 281
GND_RES_IO shift, and go to state 282
GND_RES_IN shift, and go to state 283
VCC shift, and go to state 284
TXT_STRING shift, and go to state 285
$default reduce using rule 54 (apex_chip_body)
apex_info_line go to state 361
state 287
apex_info_lines -> apex_info_line . (rule 59)
$default reduce using rule 59 (apex_info_lines)
state 288
alias_to_another_template -> ALIAS astring . end_item (rule 379)
';' shift, and go to state 240
end_item go to state 362
state 289
pin_declarations -> pin_declarations . pin_declaration (rule 42)
template_decl -> template_id_decl BEGIN_TOK template_info_lines pin_declarations . pin_equivalences END end_item (rule 371)
EQUIVALENT shift, and go to state 349
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
$default reduce using rule 37 (pin_equivalences)
astring go to state 133
pin_equivalences go to state 363
pin_declaration go to state 351
name_part go to state 278
pin_equivalence go to state 352
netname go to state 279
state 290
template_info_lines -> template_info_lines template_info_line . (rule 374)
$default reduce using rule 374 (template_info_lines)
state 291
colon_expr -> expr ':' . expr (rule 123)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 364
state 292
components_decl -> COMPONENTS BEGIN_TOK comp_defn_lines END end_item . (rule 300)
$default reduce using rule 300 (components_decl)
state 293
chip_name -> astring . (rule 306)
$default reduce using rule 306 (chip_name)
state 294
comp_defn_line -> chip_ident ':' chip_name . chip_type chip_value end_item (rule 304)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 365
chip_type go to state 366
state 295
conn_decl -> CONN conn_ident . conn_name last_route_status end_item nodelist END_CONN @17 end_item (rule 352)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 367
conn_name go to state 368
state 296
conn_ident -> netname . (rule 353)
$default reduce using rule 353 (conn_ident)
state 297
nets_decl -> WIRED_NETS @16 BEGIN_TOK connection_block END . end_item (rule 338)
';' shift, and go to state 240
end_item go to state 369
state 298
connection_block -> connection_block connection_block_item . (rule 339)
$default reduce using rule 339 (connection_block)
state 299
conn_decls -> conn_decls conn_decl . (rule 349)
$default reduce using rule 349 (conn_decls)
state 300
join_decl -> CONN astring astring . @15 end_item (rule 315)
$default reduce using rule 314 (@15)
@15 go to state 370
state 301
vhdl_concurrent_assignment -> astring SIG_ASSIGN . astring end_item (rule 210)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 371
state 302
joined_decl -> JOINED_NETS BEGIN_TOK join_decls END end_item . (rule 309)
$default reduce using rule 309 (joined_decl)
state 303
join_decl -> alias_part root_net '=' . '(' joined_nets ')' end_item (rule 313)
'(' shift, and go to state 372
state 304
rename_pins_block -> RENAME_PINS BEGIN_TOK rename_pin_decls END end_item . (rule 327)
$default reduce using rule 327 (rename_pins_block)
state 305
rename_pin_decl -> rename_new_name '=' '(' . rename_pin_items ')' end_item (rule 330)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
QUOTED_STRING [reduce using rule 336 (rename_pin_item)]
TXT_STRING [reduce using rule 336 (rename_pin_item)]
NUM_STRING [reduce using rule 336 (rename_pin_item)]
$default reduce using rule 336 (rename_pin_item)
astring go to state 373
rename_pin_items go to state 374
rename_pin_item go to state 375
state 306
rename_new_name -> netname '(' bus_range . ')' (rule 332)
')' shift, and go to state 376
state 307
ahdl_port_list -> ahdl_port_list end_item ahdl_port_item . (rule 388)
$default reduce using rule 388 (ahdl_port_list)
state 308
pin_dir -> PINDIR . (rule 50)
$default reduce using rule 50 (pin_dir)
state 309
ahdl_port_item -> ahdl_name_list ':' pin_dir . (rule 391)
$default reduce using rule 391 (ahdl_port_item)
state 310
ahdl_name_list -> ahdl_name_list ',' ahdl_name_part . (rule 392)
$default reduce using rule 392 (ahdl_name_list)
state 311
verilog_port -> hdl_name_part . (rule 237)
$default reduce using rule 237 (verilog_port)
state 312
verilog_port_list -> '(' verilog_ports . ')' ';' @7 verilog_pindir_block (rule 232)
verilog_ports -> verilog_ports . ',' verilog_port (rule 234)
')' shift, and go to state 377
',' shift, and go to state 378
state 313
verilog_ports -> verilog_port . (rule 235)
$default reduce using rule 235 (verilog_ports)
state 314
hdl_name_part -> netname . (rule 157)
$default reduce using rule 157 (hdl_name_part)
state 315
verilog_pindir_decl -> pin_dir . @8 verilog_bus_expr hdl_signal_names ';' (rule 246)
$default reduce using rule 245 (@8)
@8 go to state 379
state 316
verilog_module_header -> MODULE hdl_compname_decl verilog_port_list verilog_pindir_block . (rule 228)
verilog_pindir_block -> verilog_pindir_block . verilog_pindir_decl (rule 242)
PINDIR shift, and go to state 308
$default reduce using rule 228 (verilog_module_header)
pin_dir go to state 315
verilog_pindir_decl go to state 380
state 317
verilog_pindir_block -> verilog_pindir_decl . (rule 243)
$default reduce using rule 243 (verilog_pindir_block)
state 318
verilog_module_instance -> astring astring . '(' verilog_port_map_list ')' ';' (rule 257)
'(' shift, and go to state 381
state 319
verilog_module_instances -> verilog_module_instances verilog_module_instance . (rule 254)
$default reduce using rule 254 (verilog_module_instances)
state 320
verilog_bus_expr -> '[' expr . ']' (rule 238)
verilog_bus_expr -> '[' expr . ':' expr ']' (rule 239)
':' shift, and go to state 382
']' shift, and go to state 383
state 321
hdl_signal_name -> astring . (rule 185)
$default reduce using rule 185 (hdl_signal_name)
state 322
hdl_signal_names -> hdl_signal_names . ',' hdl_signal_name (rule 183)
verilog_wires_decl -> verilog_wire_start verilog_bus_expr hdl_signal_names . verilog_wire_end (rule 250)
';' shift, and go to state 384
',' shift, and go to state 385
verilog_wire_end go to state 386
state 323
hdl_signal_names -> hdl_signal_name . (rule 184)
$default reduce using rule 184 (hdl_signal_names)
state 324
global_generic_decl -> GENERIC @9 generic_defn_lines END end_item . (rule 265)
$default reduce using rule 265 (global_generic_decl)
state 325
generic_defn_lines -> generic_defn_lines end_item generic_defn_text . (rule 268)
$default reduce using rule 268 (generic_defn_lines)
state 326
generic_defn_text -> generic_const_opt generic_defn_name_list ':' . generic_pindir_opt generic_defn_type (rule 275)
PINDIR shift, and go to state 387
$default reduce using rule 274 (generic_pindir_opt)
generic_pindir_opt go to state 388
state 327
generic_defn_name_list -> generic_defn_name_list ',' . generic_defn_name (rule 276)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 259
generic_defn_name go to state 389
state 328
vhdl_chip_decl -> ENTITY hdl_entityname_decl IS @2 . vhdl_generic_decl_opt vhdl_port_decl_opt END TXT_STRING end_item (rule 142)
GENERIC shift, and go to state 390
$default reduce using rule 145 (vhdl_generic_decl_opt)
vhdl_generic_decl_opt go to state 391
vhdl_generic_decl go to state 392
state 329
vhdl_architecture -> ARCHITECTURE astring OF astring . IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring end_item (rule 160)
IS shift, and go to state 393
state 330
vhdl_library_list -> vhdl_library_name ',' vhdl_library_list . (rule 212)
$default reduce using rule 212 (vhdl_library_list)
state 331
vhdl_lib_member_select -> ALL . (rule 220)
$default reduce using rule 220 (vhdl_lib_member_select)
state 332
vhdl_lib_member -> astring '.' astring . '.' vhdl_lib_member_select (rule 218)
vhdl_lib_member_select -> astring . (rule 221)
'.' shift, and go to state 394
$default reduce using rule 221 (vhdl_lib_member_select)
state 333
vhdl_lib_member -> astring '.' vhdl_lib_member_select . (rule 219)
$default reduce using rule 219 (vhdl_lib_member)
state 334
vhdl_lib_members -> vhdl_lib_member ',' vhdl_lib_members . (rule 216)
$default reduce using rule 216 (vhdl_lib_members)
state 335
vhdl_signal_decl -> SIGNAL . @5 hdl_signal_names ':' vhdl_type end_item (rule 182)
$default reduce using rule 181 (@5)
@5 go to state 395
state 336
vhdl_constant_decl -> CONSTANT . @4 generic_defn_text end_item (rule 180)
$default reduce using rule 179 (@4)
@4 go to state 396
state 337
vhdl_component_decl -> COMPONENT . hdl_compname_decl vhdl_generic_decl_opt vhdl_port_decl_opt END COMPONENT end_item (rule 177)
TXT_STRING shift, and go to state 146
hdl_compname_decl go to state 397
state 338
vhdl_configuration_decl -> FOR . vhdl_lib_member_select ':' astring USE ENTITY astring '.' astring '(' astring ')' ';' (rule 186)
ALL shift, and go to state 331
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 398
vhdl_lib_member_select go to state 399
state 339
vhdl_package_decl -> PACKAGE package_name IS vhdl_package_declarations . END astring end_item (rule 168)
vhdl_package_declarations -> vhdl_package_declarations . vhdl_package_decl_item (rule 170)
END shift, and go to state 400
SIGNAL shift, and go to state 335
CONSTANT shift, and go to state 336
COMPONENT shift, and go to state 337
FOR shift, and go to state 338
vhdl_package_decl_item go to state 401
vhdl_component_decl go to state 341
vhdl_constant_decl go to state 342
vhdl_signal_decl go to state 343
vhdl_configuration_decl go to state 344
state 340
vhdl_package_declarations -> vhdl_package_decl_item . (rule 171)
$default reduce using rule 171 (vhdl_package_declarations)
state 341
vhdl_package_decl_item -> vhdl_component_decl . (rule 173)
$default reduce using rule 173 (vhdl_package_decl_item)
state 342
vhdl_package_decl_item -> vhdl_constant_decl . (rule 174)
$default reduce using rule 174 (vhdl_package_decl_item)
state 343
vhdl_package_decl_item -> vhdl_signal_decl . (rule 175)
$default reduce using rule 175 (vhdl_package_decl_item)
state 344
vhdl_package_decl_item -> vhdl_configuration_decl . (rule 176)
$default reduce using rule 176 (vhdl_package_decl_item)
state 345
device_declaration -> DEVICE '=' astring . end_item (rule 34)
';' shift, and go to state 240
end_item go to state 402
state 346
route_flag_value -> NUM_STRING . (rule 41)
$default reduce using rule 41 (route_flag_value)
state 347
route_flags_info -> ROUTE_FLAGS '=' route_flag_value . end_item (rule 40)
';' shift, and go to state 240
end_item go to state 403
state 348
chip_generic_decl -> GENERIC @10 generic_defn_lines . END end_item (rule 267)
generic_defn_lines -> generic_defn_lines . end_item generic_defn_text (rule 268)
END shift, and go to state 404
';' shift, and go to state 240
end_item go to state 258
state 349
pin_equivalence -> EQUIVALENT . @1 '(' equivalent_pins ')' end_item (rule 127)
$default reduce using rule 126 (@1)
@1 go to state 405
state 350
flex_chip_body -> chip_info_lines pin_declarations pin_equivalences . END end_item (rule 25)
END shift, and go to state 406
state 351
pin_declarations -> pin_declarations pin_declaration . (rule 42)
$default reduce using rule 42 (pin_declarations)
state 352
pin_equivalences -> pin_equivalence . pin_equivalences (rule 35)
pin_equivalences -> pin_equivalence . (rule 36)
EQUIVALENT shift, and go to state 349
END reduce using rule 36 (pin_equivalences)
END [reduce using rule 37 (pin_equivalences)]
$default reduce using rule 36 (pin_equivalences)
pin_equivalences go to state 407
pin_equivalence go to state 352
state 353
pin_declaration -> name_part ':' . pin_rest end_item (rule 45)
LOCATION shift, and go to state 408
UNROUTED shift, and go to state 409
PINDIR shift, and go to state 308
pin_rest go to state 410
pin_dir go to state 411
state 354
apex_device_declaration -> TO AN astring . apex_speed_grade (rule 55)
'-' shift, and go to state 412
$default reduce using rule 57 (apex_speed_grade)
apex_speed_grade go to state 413
state 355
apex_info_line -> GND ':' . astring more_colons (rule 60)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 414
state 356
apex_info_line -> GND_RES_IO ':' . astring more_colons (rule 61)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 415
state 357
apex_info_line -> GND_RES_IN ':' . astring more_colons (rule 62)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 416
state 358
apex_info_line -> VCC ':' . astring ':' NUM_STRING (rule 63)
apex_info_line -> VCC ':' . astring more_colons (rule 64)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 417
state 359
apex_info_line -> TXT_STRING ':' . astring more_colons (rule 65)
apex_info_line -> TXT_STRING ':' . astring ':' PINDIR ':' astring ':' (rule 66)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 418
state 360
apex_info_line -> TXT_STRING '[' . expr ']' ':' astring ':' PINDIR ':' astring ':' (rule 67)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 419
state 361
apex_info_lines -> apex_info_lines apex_info_line . (rule 58)
$default reduce using rule 58 (apex_info_lines)
state 362
alias_to_another_template -> ALIAS astring end_item . (rule 379)
$default reduce using rule 379 (alias_to_another_template)
state 363
template_decl -> template_id_decl BEGIN_TOK template_info_lines pin_declarations pin_equivalences . END end_item (rule 371)
END shift, and go to state 420
state 364
colon_expr -> expr ':' expr . (rule 123)
$default reduce using rule 123 (colon_expr)
state 365
chip_type -> astring . (rule 307)
$default reduce using rule 307 (chip_type)
state 366
comp_defn_line -> chip_ident ':' chip_name chip_type . chip_value end_item (rule 304)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 421
chip_value go to state 422
state 367
conn_name -> astring . (rule 354)
$default reduce using rule 354 (conn_name)
state 368
conn_decl -> CONN conn_ident conn_name . last_route_status end_item nodelist END_CONN @17 end_item (rule 352)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 423
last_route_status go to state 424
state 369
nets_decl -> WIRED_NETS @16 BEGIN_TOK connection_block END end_item . (rule 338)
$default reduce using rule 338 (nets_decl)
state 370
join_decl -> CONN astring astring @15 . end_item (rule 315)
';' shift, and go to state 240
end_item go to state 425
state 371
vhdl_concurrent_assignment -> astring SIG_ASSIGN astring . end_item (rule 210)
';' shift, and go to state 240
end_item go to state 426
state 372
join_decl -> alias_part root_net '=' '(' . joined_nets ')' end_item (rule 313)
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 133
joined_nets go to state 427
joined_net go to state 428
single_net go to state 429
jumper_node go to state 430
netname go to state 431
state 373
rename_pin_item -> astring . '.' astring end_item (rule 335)
'.' shift, and go to state 432
state 374
rename_pin_decl -> rename_new_name '=' '(' rename_pin_items . ')' end_item (rule 330)
rename_pin_items -> rename_pin_items . rename_pin_item (rule 333)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
')' shift, and go to state 433
QUOTED_STRING [reduce using rule 336 (rename_pin_item)]
TXT_STRING [reduce using rule 336 (rename_pin_item)]
NUM_STRING [reduce using rule 336 (rename_pin_item)]
')' [reduce using rule 336 (rename_pin_item)]
$default reduce using rule 336 (rename_pin_item)
astring go to state 373
rename_pin_item go to state 434
state 375
rename_pin_items -> rename_pin_item . (rule 334)
$default reduce using rule 334 (rename_pin_items)
state 376
rename_new_name -> netname '(' bus_range ')' . (rule 332)
$default reduce using rule 332 (rename_new_name)
state 377
verilog_port_list -> '(' verilog_ports ')' . ';' @7 verilog_pindir_block (rule 232)
';' shift, and go to state 435
state 378
verilog_ports -> verilog_ports ',' . verilog_port (rule 234)
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 133
hdl_name_part go to state 311
verilog_port go to state 436
netname go to state 314
state 379
verilog_pindir_decl -> pin_dir @8 . verilog_bus_expr hdl_signal_names ';' (rule 246)
'[' shift, and go to state 255
$default reduce using rule 240 (verilog_bus_expr)
verilog_bus_expr go to state 437
state 380
verilog_pindir_block -> verilog_pindir_block verilog_pindir_decl . (rule 242)
$default reduce using rule 242 (verilog_pindir_block)
state 381
verilog_module_instance -> astring astring '(' . verilog_port_map_list ')' ';' (rule 257)
'.' shift, and go to state 438
$default reduce using rule 259 (verilog_port_map_list)
verilog_port_map_list go to state 439
verilog_port_maps go to state 440
verilog_port_map go to state 441
state 382
verilog_bus_expr -> '[' expr ':' . expr ']' (rule 239)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 442
state 383
verilog_bus_expr -> '[' expr ']' . (rule 238)
$default reduce using rule 238 (verilog_bus_expr)
state 384
verilog_wire_end -> ';' . (rule 252)
$default reduce using rule 252 (verilog_wire_end)
state 385
hdl_signal_names -> hdl_signal_names ',' . hdl_signal_name (rule 183)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 321
hdl_signal_name go to state 443
state 386
verilog_wires_decl -> verilog_wire_start verilog_bus_expr hdl_signal_names verilog_wire_end . (rule 250)
$default reduce using rule 250 (verilog_wires_decl)
state 387
generic_pindir_opt -> PINDIR . (rule 273)
$default reduce using rule 273 (generic_pindir_opt)
state 388
generic_defn_text -> generic_const_opt generic_defn_name_list ':' generic_pindir_opt . generic_defn_type (rule 275)
DECLARATION shift, and go to state 444
INSTANCE shift, and go to state 445
BOOLEAN shift, and go to state 446
INTEGER shift, and go to state 447
ATTRIBUTE shift, and go to state 448
ENV_STRING shift, and go to state 449
STRING shift, and go to state 450
generic_defn_type go to state 451
state 389
generic_defn_name_list -> generic_defn_name_list ',' generic_defn_name . (rule 276)
$default reduce using rule 276 (generic_defn_name_list)
state 390
vhdl_generic_decl -> GENERIC . '(' @3 generic_defn_lines ')' end_item (rule 147)
'(' shift, and go to state 452
state 391
vhdl_chip_decl -> ENTITY hdl_entityname_decl IS @2 vhdl_generic_decl_opt . vhdl_port_decl_opt END TXT_STRING end_item (rule 142)
PORT shift, and go to state 453
$default reduce using rule 149 (vhdl_port_decl_opt)
vhdl_port_decl_opt go to state 454
vhdl_port_decl go to state 455
state 392
vhdl_generic_decl_opt -> vhdl_generic_decl . (rule 144)
$default reduce using rule 144 (vhdl_generic_decl_opt)
state 393
vhdl_architecture -> ARCHITECTURE astring OF astring IS . vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring end_item (rule 160)
SIGNAL shift, and go to state 335
CONSTANT shift, and go to state 336
COMPONENT shift, and go to state 337
FOR shift, and go to state 338
SIGNAL [reduce using rule 163 (vhdl_architecture_declarations)]
CONSTANT [reduce using rule 163 (vhdl_architecture_declarations)]
COMPONENT [reduce using rule 163 (vhdl_architecture_declarations)]
FOR [reduce using rule 163 (vhdl_architecture_declarations)]
$default reduce using rule 163 (vhdl_architecture_declarations)
vhdl_architecture_declarations go to state 456
vhdl_architecture_decl go to state 457
vhdl_component_decl go to state 458
vhdl_constant_decl go to state 459
vhdl_signal_decl go to state 460
vhdl_configuration_decl go to state 461
state 394
vhdl_lib_member -> astring '.' astring '.' . vhdl_lib_member_select (rule 218)
ALL shift, and go to state 331
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 398
vhdl_lib_member_select go to state 462
state 395
vhdl_signal_decl -> SIGNAL @5 . hdl_signal_names ':' vhdl_type end_item (rule 182)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 321
hdl_signal_names go to state 463
hdl_signal_name go to state 323
state 396
vhdl_constant_decl -> CONSTANT @4 . generic_defn_text end_item (rule 180)
CONSTANT shift, and go to state 156
$default reduce using rule 272 (generic_const_opt)
generic_const_opt go to state 158
generic_defn_text go to state 464
state 397
vhdl_component_decl -> COMPONENT hdl_compname_decl . vhdl_generic_decl_opt vhdl_port_decl_opt END COMPONENT end_item (rule 177)
GENERIC shift, and go to state 390
$default reduce using rule 145 (vhdl_generic_decl_opt)
vhdl_generic_decl_opt go to state 465
vhdl_generic_decl go to state 392
state 398
vhdl_lib_member_select -> astring . (rule 221)
$default reduce using rule 221 (vhdl_lib_member_select)
state 399
vhdl_configuration_decl -> FOR vhdl_lib_member_select . ':' astring USE ENTITY astring '.' astring '(' astring ')' ';' (rule 186)
':' shift, and go to state 466
state 400
vhdl_package_decl -> PACKAGE package_name IS vhdl_package_declarations END . astring end_item (rule 168)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 467
state 401
vhdl_package_declarations -> vhdl_package_declarations vhdl_package_decl_item . (rule 170)
$default reduce using rule 170 (vhdl_package_declarations)
state 402
device_declaration -> DEVICE '=' astring end_item . (rule 34)
$default reduce using rule 34 (device_declaration)
state 403
route_flags_info -> ROUTE_FLAGS '=' route_flag_value end_item . (rule 40)
$default reduce using rule 40 (route_flags_info)
state 404
chip_generic_decl -> GENERIC @10 generic_defn_lines END . end_item (rule 267)
';' shift, and go to state 240
end_item go to state 468
state 405
pin_equivalence -> EQUIVALENT @1 . '(' equivalent_pins ')' end_item (rule 127)
'(' shift, and go to state 469
state 406
flex_chip_body -> chip_info_lines pin_declarations pin_equivalences END . end_item (rule 25)
';' shift, and go to state 240
end_item go to state 470
state 407
pin_equivalences -> pin_equivalence pin_equivalences . (rule 35)
$default reduce using rule 35 (pin_equivalences)
state 408
pin_rest -> LOCATION . '=' astring (rule 49)
'=' shift, and go to state 471
state 409
pin_rest -> UNROUTED . (rule 48)
$default reduce using rule 48 (pin_rest)
state 410
pin_declaration -> name_part ':' pin_rest . end_item (rule 45)
';' shift, and go to state 240
end_item go to state 472
state 411
pin_rest -> pin_dir . pin_group '=' pin_ident vhdl_type_opt (rule 47)
'(' shift, and go to state 473
$default reduce using rule 52 (pin_group)
pin_group go to state 474
state 412
apex_speed_grade -> '-' . NUM_STRING (rule 56)
NUM_STRING shift, and go to state 475
state 413
apex_device_declaration -> TO AN astring apex_speed_grade . (rule 55)
$default reduce using rule 55 (apex_device_declaration)
state 414
apex_info_line -> GND ':' astring . more_colons (rule 60)
':' shift, and go to state 476
more_colons go to state 477
state 415
apex_info_line -> GND_RES_IO ':' astring . more_colons (rule 61)
':' shift, and go to state 476
more_colons go to state 478
state 416
apex_info_line -> GND_RES_IN ':' astring . more_colons (rule 62)
':' shift, and go to state 476
more_colons go to state 479
state 417
apex_info_line -> VCC ':' astring . ':' NUM_STRING (rule 63)
apex_info_line -> VCC ':' astring . more_colons (rule 64)
':' shift, and go to state 480
more_colons go to state 481
state 418
apex_info_line -> TXT_STRING ':' astring . more_colons (rule 65)
apex_info_line -> TXT_STRING ':' astring . ':' PINDIR ':' astring ':' (rule 66)
':' shift, and go to state 482
more_colons go to state 483
state 419
apex_info_line -> TXT_STRING '[' expr . ']' ':' astring ':' PINDIR ':' astring ':' (rule 67)
']' shift, and go to state 484
state 420
template_decl -> template_id_decl BEGIN_TOK template_info_lines pin_declarations pin_equivalences END . end_item (rule 371)
';' shift, and go to state 240
end_item go to state 485
state 421
chip_value -> astring . (rule 308)
$default reduce using rule 308 (chip_value)
state 422
comp_defn_line -> chip_ident ':' chip_name chip_type chip_value . end_item (rule 304)
';' shift, and go to state 240
end_item go to state 486
state 423
last_route_status -> astring . (rule 355)
$default reduce using rule 355 (last_route_status)
state 424
conn_decl -> CONN conn_ident conn_name last_route_status . end_item nodelist END_CONN @17 end_item (rule 352)
';' shift, and go to state 240
end_item go to state 487
state 425
join_decl -> CONN astring astring @15 end_item . (rule 315)
$default reduce using rule 315 (join_decl)
state 426
vhdl_concurrent_assignment -> astring SIG_ASSIGN astring end_item . (rule 210)
$default reduce using rule 210 (vhdl_concurrent_assignment)
state 427
join_decl -> alias_part root_net '=' '(' joined_nets . ')' end_item (rule 313)
joined_nets -> joined_nets . joined_net (rule 321)
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
')' shift, and go to state 488
astring go to state 133
joined_net go to state 489
single_net go to state 429
jumper_node go to state 430
netname go to state 431
state 428
joined_nets -> joined_net . (rule 322)
$default reduce using rule 322 (joined_nets)
state 429
joined_net -> single_net . end_item (rule 323)
';' shift, and go to state 240
end_item go to state 490
state 430
joined_net -> jumper_node . end_item (rule 324)
';' shift, and go to state 240
end_item go to state 491
state 431
single_net -> netname . (rule 325)
jumper_node -> netname . '(' astring ')' (rule 326)
'(' shift, and go to state 492
$default reduce using rule 325 (single_net)
state 432
rename_pin_item -> astring '.' . astring end_item (rule 335)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 493
state 433
rename_pin_decl -> rename_new_name '=' '(' rename_pin_items ')' . end_item (rule 330)
';' shift, and go to state 240
end_item go to state 494
state 434
rename_pin_items -> rename_pin_items rename_pin_item . (rule 333)
$default reduce using rule 333 (rename_pin_items)
state 435
verilog_port_list -> '(' verilog_ports ')' ';' . @7 verilog_pindir_block (rule 232)
$default reduce using rule 231 (@7)
@7 go to state 495
state 436
verilog_ports -> verilog_ports ',' verilog_port . (rule 234)
$default reduce using rule 234 (verilog_ports)
state 437
verilog_pindir_decl -> pin_dir @8 verilog_bus_expr . hdl_signal_names ';' (rule 246)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 321
hdl_signal_names go to state 496
hdl_signal_name go to state 323
state 438
verilog_port_map -> '.' . astring '(' astring verilog_bus_expr ')' (rule 262)
verilog_port_map -> '.' . astring '(' ')' (rule 263)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 497
state 439
verilog_module_instance -> astring astring '(' verilog_port_map_list . ')' ';' (rule 257)
')' shift, and go to state 498
state 440
verilog_port_map_list -> verilog_port_maps . (rule 258)
verilog_port_maps -> verilog_port_maps . ',' verilog_port_map (rule 260)
',' shift, and go to state 499
$default reduce using rule 258 (verilog_port_map_list)
state 441
verilog_port_maps -> verilog_port_map . (rule 261)
$default reduce using rule 261 (verilog_port_maps)
state 442
verilog_bus_expr -> '[' expr ':' expr . ']' (rule 239)
']' shift, and go to state 500
state 443
hdl_signal_names -> hdl_signal_names ',' hdl_signal_name . (rule 183)
$default reduce using rule 183 (hdl_signal_names)
state 444
generic_defn_type -> DECLARATION . @11 assign_words (rule 283)
$default reduce using rule 282 (@11)
@11 go to state 501
state 445
generic_defn_type -> INSTANCE . @12 assign_words (rule 285)
$default reduce using rule 284 (@12)
@12 go to state 502
state 446
generic_defn_type -> BOOLEAN . opt_integer (rule 280)
ASSIGN shift, and go to state 503
$default reduce using rule 292 (opt_integer)
opt_integer go to state 504
state 447
generic_defn_type -> INTEGER . opt_integer (rule 279)
generic_defn_type -> INTEGER . RANGE opt_bus_range (rule 281)
ASSIGN shift, and go to state 503
RANGE shift, and go to state 505
$default reduce using rule 292 (opt_integer)
opt_integer go to state 506
state 448
generic_defn_type -> ATTRIBUTE . opt_integer (rule 290)
ASSIGN shift, and go to state 503
$default reduce using rule 292 (opt_integer)
opt_integer go to state 507
state 449
generic_defn_type -> ENV_STRING . @14 assign_words (rule 289)
$default reduce using rule 288 (@14)
@14 go to state 508
state 450
generic_defn_type -> STRING . @13 assign_words (rule 287)
$default reduce using rule 286 (@13)
@13 go to state 509
state 451
generic_defn_text -> generic_const_opt generic_defn_name_list ':' generic_pindir_opt generic_defn_type . (rule 275)
$default reduce using rule 275 (generic_defn_text)
state 452
vhdl_generic_decl -> GENERIC '(' . @3 generic_defn_lines ')' end_item (rule 147)
$default reduce using rule 146 (@3)
@3 go to state 510
state 453
vhdl_port_decl -> PORT . '(' vhdl_port_list ')' end_item (rule 150)
'(' shift, and go to state 511
state 454
vhdl_chip_decl -> ENTITY hdl_entityname_decl IS @2 vhdl_generic_decl_opt vhdl_port_decl_opt . END TXT_STRING end_item (rule 142)
END shift, and go to state 512
state 455
vhdl_port_decl_opt -> vhdl_port_decl . (rule 148)
$default reduce using rule 148 (vhdl_port_decl_opt)
state 456
vhdl_architecture -> ARCHITECTURE astring OF astring IS vhdl_architecture_declarations . BEGIN_TOK vhdl_architecture_body_items END astring end_item (rule 160)
vhdl_architecture_declarations -> vhdl_architecture_declarations . vhdl_architecture_decl (rule 161)
BEGIN_TOK shift, and go to state 513
SIGNAL shift, and go to state 335
CONSTANT shift, and go to state 336
COMPONENT shift, and go to state 337
FOR shift, and go to state 338
vhdl_architecture_decl go to state 514
vhdl_component_decl go to state 458
vhdl_constant_decl go to state 459
vhdl_signal_decl go to state 460
vhdl_configuration_decl go to state 461
state 457
vhdl_architecture_declarations -> vhdl_architecture_decl . (rule 162)
$default reduce using rule 162 (vhdl_architecture_declarations)
state 458
vhdl_architecture_decl -> vhdl_component_decl . (rule 164)
$default reduce using rule 164 (vhdl_architecture_decl)
state 459
vhdl_architecture_decl -> vhdl_constant_decl . (rule 165)
$default reduce using rule 165 (vhdl_architecture_decl)
state 460
vhdl_architecture_decl -> vhdl_signal_decl . (rule 166)
$default reduce using rule 166 (vhdl_architecture_decl)
state 461
vhdl_architecture_decl -> vhdl_configuration_decl . (rule 167)
$default reduce using rule 167 (vhdl_architecture_decl)
state 462
vhdl_lib_member -> astring '.' astring '.' vhdl_lib_member_select . (rule 218)
$default reduce using rule 218 (vhdl_lib_member)
state 463
vhdl_signal_decl -> SIGNAL @5 hdl_signal_names . ':' vhdl_type end_item (rule 182)
hdl_signal_names -> hdl_signal_names . ',' hdl_signal_name (rule 183)
':' shift, and go to state 515
',' shift, and go to state 385
state 464
vhdl_constant_decl -> CONSTANT @4 generic_defn_text . end_item (rule 180)
';' shift, and go to state 240
end_item go to state 516
state 465
vhdl_component_decl -> COMPONENT hdl_compname_decl vhdl_generic_decl_opt . vhdl_port_decl_opt END COMPONENT end_item (rule 177)
PORT shift, and go to state 453
$default reduce using rule 149 (vhdl_port_decl_opt)
vhdl_port_decl_opt go to state 517
vhdl_port_decl go to state 455
state 466
vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' . astring USE ENTITY astring '.' astring '(' astring ')' ';' (rule 186)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 518
state 467
vhdl_package_decl -> PACKAGE package_name IS vhdl_package_declarations END astring . end_item (rule 168)
';' shift, and go to state 240
end_item go to state 519
state 468
chip_generic_decl -> GENERIC @10 generic_defn_lines END end_item . (rule 267)
$default reduce using rule 267 (chip_generic_decl)
state 469
pin_equivalence -> EQUIVALENT @1 '(' . equivalent_pins ')' end_item (rule 127)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
$default reduce using rule 130 (equivalent_pins)
astring go to state 520
equivalent_pins go to state 521
equivalent_pin go to state 522
state 470
flex_chip_body -> chip_info_lines pin_declarations pin_equivalences END end_item . (rule 25)
$default reduce using rule 25 (flex_chip_body)
state 471
pin_rest -> LOCATION '=' . astring (rule 49)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 523
state 472
pin_declaration -> name_part ':' pin_rest end_item . (rule 45)
$default reduce using rule 45 (pin_declaration)
state 473
pin_group -> '(' . NUM_STRING ')' (rule 51)
NUM_STRING shift, and go to state 524
state 474
pin_rest -> pin_dir pin_group . '=' pin_ident vhdl_type_opt (rule 47)
'=' shift, and go to state 525
state 475
apex_speed_grade -> '-' NUM_STRING . (rule 56)
$default reduce using rule 56 (apex_speed_grade)
state 476
more_colons -> ':' . more_colons (rule 68)
more_colons -> ':' . (rule 69)
':' shift, and go to state 476
$default reduce using rule 69 (more_colons)
more_colons go to state 526
state 477
apex_info_line -> GND ':' astring more_colons . (rule 60)
$default reduce using rule 60 (apex_info_line)
state 478
apex_info_line -> GND_RES_IO ':' astring more_colons . (rule 61)
$default reduce using rule 61 (apex_info_line)
state 479
apex_info_line -> GND_RES_IN ':' astring more_colons . (rule 62)
$default reduce using rule 62 (apex_info_line)
state 480
apex_info_line -> VCC ':' astring ':' . NUM_STRING (rule 63)
more_colons -> ':' . more_colons (rule 68)
more_colons -> ':' . (rule 69)
NUM_STRING shift, and go to state 527
':' shift, and go to state 476
$default reduce using rule 69 (more_colons)
more_colons go to state 526
state 481
apex_info_line -> VCC ':' astring more_colons . (rule 64)
$default reduce using rule 64 (apex_info_line)
state 482
apex_info_line -> TXT_STRING ':' astring ':' . PINDIR ':' astring ':' (rule 66)
more_colons -> ':' . more_colons (rule 68)
more_colons -> ':' . (rule 69)
PINDIR shift, and go to state 528
':' shift, and go to state 476
$default reduce using rule 69 (more_colons)
more_colons go to state 526
state 483
apex_info_line -> TXT_STRING ':' astring more_colons . (rule 65)
$default reduce using rule 65 (apex_info_line)
state 484
apex_info_line -> TXT_STRING '[' expr ']' . ':' astring ':' PINDIR ':' astring ':' (rule 67)
':' shift, and go to state 529
state 485
template_decl -> template_id_decl BEGIN_TOK template_info_lines pin_declarations pin_equivalences END end_item . (rule 371)
$default reduce using rule 371 (template_decl)
state 486
comp_defn_line -> chip_ident ':' chip_name chip_type chip_value end_item . (rule 304)
$default reduce using rule 304 (comp_defn_line)
state 487
conn_decl -> CONN conn_ident conn_name last_route_status end_item . nodelist END_CONN @17 end_item (rule 352)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
QUOTED_STRING [reduce using rule 358 (nodelist)]
TXT_STRING [reduce using rule 358 (nodelist)]
NUM_STRING [reduce using rule 358 (nodelist)]
$default reduce using rule 358 (nodelist)
astring go to state 530
nodelist go to state 531
net_node go to state 532
skt_id go to state 533
state 488
join_decl -> alias_part root_net '=' '(' joined_nets ')' . end_item (rule 313)
';' shift, and go to state 240
end_item go to state 534
state 489
joined_nets -> joined_nets joined_net . (rule 321)
$default reduce using rule 321 (joined_nets)
state 490
joined_net -> single_net end_item . (rule 323)
$default reduce using rule 323 (joined_net)
state 491
joined_net -> jumper_node end_item . (rule 324)
$default reduce using rule 324 (joined_net)
state 492
jumper_node -> netname '(' . astring ')' (rule 326)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 535
state 493
rename_pin_item -> astring '.' astring . end_item (rule 335)
';' shift, and go to state 240
end_item go to state 536
state 494
rename_pin_decl -> rename_new_name '=' '(' rename_pin_items ')' end_item . (rule 330)
$default reduce using rule 330 (rename_pin_decl)
state 495
verilog_port_list -> '(' verilog_ports ')' ';' @7 . verilog_pindir_block (rule 232)
PINDIR shift, and go to state 308
PINDIR [reduce using rule 244 (verilog_pindir_block)]
$default reduce using rule 244 (verilog_pindir_block)
pin_dir go to state 315
verilog_pindir_block go to state 537
verilog_pindir_decl go to state 317
state 496
hdl_signal_names -> hdl_signal_names . ',' hdl_signal_name (rule 183)
verilog_pindir_decl -> pin_dir @8 verilog_bus_expr hdl_signal_names . ';' (rule 246)
';' shift, and go to state 538
',' shift, and go to state 385
state 497
verilog_port_map -> '.' astring . '(' astring verilog_bus_expr ')' (rule 262)
verilog_port_map -> '.' astring . '(' ')' (rule 263)
'(' shift, and go to state 539
state 498
verilog_module_instance -> astring astring '(' verilog_port_map_list ')' . ';' (rule 257)
';' shift, and go to state 540
state 499
verilog_port_maps -> verilog_port_maps ',' . verilog_port_map (rule 260)
'.' shift, and go to state 438
verilog_port_map go to state 541
state 500
verilog_bus_expr -> '[' expr ':' expr ']' . (rule 239)
$default reduce using rule 239 (verilog_bus_expr)
state 501
generic_defn_type -> DECLARATION @11 . assign_words (rule 283)
ASSIGN shift, and go to state 542
$default reduce using rule 296 (assign_words)
assign_words go to state 543
state 502
generic_defn_type -> INSTANCE @12 . assign_words (rule 285)
ASSIGN shift, and go to state 542
$default reduce using rule 296 (assign_words)
assign_words go to state 544
state 503
opt_integer -> ASSIGN . expr (rule 291)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 545
state 504
generic_defn_type -> BOOLEAN opt_integer . (rule 280)
$default reduce using rule 280 (generic_defn_type)
state 505
generic_defn_type -> INTEGER RANGE . opt_bus_range (rule 281)
ASSIGN shift, and go to state 546
$default reduce using rule 294 (opt_bus_range)
opt_bus_range go to state 547
state 506
generic_defn_type -> INTEGER opt_integer . (rule 279)
$default reduce using rule 279 (generic_defn_type)
state 507
generic_defn_type -> ATTRIBUTE opt_integer . (rule 290)
$default reduce using rule 290 (generic_defn_type)
state 508
generic_defn_type -> ENV_STRING @14 . assign_words (rule 289)
ASSIGN shift, and go to state 542
$default reduce using rule 296 (assign_words)
assign_words go to state 548
state 509
generic_defn_type -> STRING @13 . assign_words (rule 287)
ASSIGN shift, and go to state 542
$default reduce using rule 296 (assign_words)
assign_words go to state 549
state 510
vhdl_generic_decl -> GENERIC '(' @3 . generic_defn_lines ')' end_item (rule 147)
CONSTANT shift, and go to state 156
';' reduce using rule 270 (generic_defn_lines)
')' reduce using rule 270 (generic_defn_lines)
$default reduce using rule 272 (generic_const_opt)
generic_defn_lines go to state 550
generic_const_opt go to state 158
generic_defn_text go to state 159
state 511
vhdl_port_decl -> PORT '(' . vhdl_port_list ')' end_item (rule 150)
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
$default reduce using rule 153 (vhdl_port_list)
astring go to state 133
vhdl_port_list go to state 551
vhdl_port_item go to state 552
vhdl_name_list go to state 553
hdl_name_part go to state 554
netname go to state 314
state 512
vhdl_chip_decl -> ENTITY hdl_entityname_decl IS @2 vhdl_generic_decl_opt vhdl_port_decl_opt END . TXT_STRING end_item (rule 142)
TXT_STRING shift, and go to state 555
state 513
vhdl_architecture -> ARCHITECTURE astring OF astring IS vhdl_architecture_declarations BEGIN_TOK . vhdl_architecture_body_items END astring end_item (rule 160)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 556
NUM_STRING shift, and go to state 56
QUOTED_STRING [reduce using rule 189 (vhdl_architecture_body_items)]
TXT_STRING [reduce using rule 189 (vhdl_architecture_body_items)]
NUM_STRING [reduce using rule 189 (vhdl_architecture_body_items)]
$default reduce using rule 189 (vhdl_architecture_body_items)
astring go to state 230
vhdl_architecture_body_items go to state 557
vhdl_architecture_body_item go to state 558
vhdl_component_instance go to state 559
vhdl_inst_comp_binding go to state 560
vhdl_concurrent_assignment go to state 561
state 514
vhdl_architecture_declarations -> vhdl_architecture_declarations vhdl_architecture_decl . (rule 161)
$default reduce using rule 161 (vhdl_architecture_declarations)
state 515
vhdl_signal_decl -> SIGNAL @5 hdl_signal_names ':' . vhdl_type end_item (rule 182)
BOOLEAN shift, and go to state 562
INTEGER shift, and go to state 563
NATURAL shift, and go to state 564
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 565
vhdl_type go to state 566
state 516
vhdl_constant_decl -> CONSTANT @4 generic_defn_text end_item . (rule 180)
$default reduce using rule 180 (vhdl_constant_decl)
state 517
vhdl_component_decl -> COMPONENT hdl_compname_decl vhdl_generic_decl_opt vhdl_port_decl_opt . END COMPONENT end_item (rule 177)
END shift, and go to state 567
state 518
vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring . USE ENTITY astring '.' astring '(' astring ')' ';' (rule 186)
USE shift, and go to state 568
state 519
vhdl_package_decl -> PACKAGE package_name IS vhdl_package_declarations END astring end_item . (rule 168)
$default reduce using rule 168 (vhdl_package_decl)
state 520
equivalent_pin -> astring . (rule 131)
$default reduce using rule 131 (equivalent_pin)
state 521
pin_equivalence -> EQUIVALENT @1 '(' equivalent_pins . ')' end_item (rule 127)
')' shift, and go to state 569
state 522
equivalent_pins -> equivalent_pin . end_item equivalent_pins (rule 128)
equivalent_pins -> equivalent_pin . (rule 129)
';' shift, and go to state 240
$default reduce using rule 129 (equivalent_pins)
end_item go to state 570
state 523
pin_rest -> LOCATION '=' astring . (rule 49)
$default reduce using rule 49 (pin_rest)
state 524
pin_group -> '(' NUM_STRING . ')' (rule 51)
')' shift, and go to state 571
state 525
pin_rest -> pin_dir pin_group '=' . pin_ident vhdl_type_opt (rule 47)
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 133
pin_ident go to state 572
netname go to state 573
state 526
more_colons -> ':' more_colons . (rule 68)
$default reduce using rule 68 (more_colons)
state 527
apex_info_line -> VCC ':' astring ':' NUM_STRING . (rule 63)
$default reduce using rule 63 (apex_info_line)
state 528
apex_info_line -> TXT_STRING ':' astring ':' PINDIR . ':' astring ':' (rule 66)
':' shift, and go to state 574
state 529
apex_info_line -> TXT_STRING '[' expr ']' ':' . astring ':' PINDIR ':' astring ':' (rule 67)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 575
state 530
skt_id -> astring . (rule 362)
$default reduce using rule 362 (skt_id)
state 531
conn_decl -> CONN conn_ident conn_name last_route_status end_item nodelist . END_CONN @17 end_item (rule 352)
nodelist -> nodelist . net_node (rule 356)
END_CONN shift, and go to state 576
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 530
net_node go to state 577
skt_id go to state 533
state 532
nodelist -> net_node . (rule 357)
$default reduce using rule 357 (nodelist)
state 533
net_node -> skt_id . '(' node_id ')' fix_loc_part force_pin_dir node_group end_item (rule 359)
'(' shift, and go to state 578
state 534
join_decl -> alias_part root_net '=' '(' joined_nets ')' end_item . (rule 313)
$default reduce using rule 313 (join_decl)
state 535
jumper_node -> netname '(' astring . ')' (rule 326)
')' shift, and go to state 579
state 536
rename_pin_item -> astring '.' astring end_item . (rule 335)
$default reduce using rule 335 (rename_pin_item)
state 537
verilog_port_list -> '(' verilog_ports ')' ';' @7 verilog_pindir_block . (rule 232)
verilog_pindir_block -> verilog_pindir_block . verilog_pindir_decl (rule 242)
PINDIR shift, and go to state 308
PINDIR [reduce using rule 232 (verilog_port_list)]
$default reduce using rule 232 (verilog_port_list)
pin_dir go to state 315
verilog_pindir_decl go to state 380
state 538
verilog_pindir_decl -> pin_dir @8 verilog_bus_expr hdl_signal_names ';' . (rule 246)
$default reduce using rule 246 (verilog_pindir_decl)
state 539
verilog_port_map -> '.' astring '(' . astring verilog_bus_expr ')' (rule 262)
verilog_port_map -> '.' astring '(' . ')' (rule 263)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
')' shift, and go to state 580
astring go to state 581
state 540
verilog_module_instance -> astring astring '(' verilog_port_map_list ')' ';' . (rule 257)
$default reduce using rule 257 (verilog_module_instance)
state 541
verilog_port_maps -> verilog_port_maps ',' verilog_port_map . (rule 260)
$default reduce using rule 260 (verilog_port_maps)
state 542
assign_words -> ASSIGN . several_words (rule 295)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 582
several_words go to state 583
word go to state 584
state 543
generic_defn_type -> DECLARATION @11 assign_words . (rule 283)
$default reduce using rule 283 (generic_defn_type)
state 544
generic_defn_type -> INSTANCE @12 assign_words . (rule 285)
$default reduce using rule 285 (generic_defn_type)
state 545
opt_integer -> ASSIGN expr . (rule 291)
$default reduce using rule 291 (opt_integer)
state 546
opt_bus_range -> ASSIGN . bus_range (rule 293)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
QUOTE shift, and go to state 29
QUOTED_STRING shift, and go to state 30
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
bus_range go to state 585
expr1 go to state 39
simple_range_expr go to state 40
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 53
state 547
generic_defn_type -> INTEGER RANGE opt_bus_range . (rule 281)
$default reduce using rule 281 (generic_defn_type)
state 548
generic_defn_type -> ENV_STRING @14 assign_words . (rule 289)
$default reduce using rule 289 (generic_defn_type)
state 549
generic_defn_type -> STRING @13 assign_words . (rule 287)
$default reduce using rule 287 (generic_defn_type)
state 550
vhdl_generic_decl -> GENERIC '(' @3 generic_defn_lines . ')' end_item (rule 147)
generic_defn_lines -> generic_defn_lines . end_item generic_defn_text (rule 268)
';' shift, and go to state 240
')' shift, and go to state 586
end_item go to state 258
state 551
vhdl_port_decl -> PORT '(' vhdl_port_list . ')' end_item (rule 150)
vhdl_port_list -> vhdl_port_list . end_item vhdl_port_item (rule 151)
';' shift, and go to state 240
')' shift, and go to state 587
end_item go to state 588
state 552
vhdl_port_list -> vhdl_port_item . (rule 152)
$default reduce using rule 152 (vhdl_port_list)
state 553
vhdl_port_item -> vhdl_name_list . ':' pin_dir vhdl_type vhdl_assign_opt (rule 154)
vhdl_name_list -> vhdl_name_list . ',' hdl_name_part (rule 155)
':' shift, and go to state 589
',' shift, and go to state 590
state 554
vhdl_name_list -> hdl_name_part . (rule 156)
$default reduce using rule 156 (vhdl_name_list)
state 555
vhdl_chip_decl -> ENTITY hdl_entityname_decl IS @2 vhdl_generic_decl_opt vhdl_port_decl_opt END TXT_STRING . end_item (rule 142)
';' shift, and go to state 240
end_item go to state 591
state 556
astring -> TXT_STRING . (rule 20)
vhdl_inst_comp_binding -> TXT_STRING . ':' TXT_STRING (rule 193)
':' shift, and go to state 592
$default reduce using rule 20 (astring)
state 557
vhdl_architecture -> ARCHITECTURE astring OF astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items . END astring end_item (rule 160)
vhdl_architecture_body_items -> vhdl_architecture_body_items . vhdl_architecture_body_item (rule 187)
END shift, and go to state 593
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 556
NUM_STRING shift, and go to state 56
astring go to state 230
vhdl_architecture_body_item go to state 594
vhdl_component_instance go to state 559
vhdl_inst_comp_binding go to state 560
vhdl_concurrent_assignment go to state 561
state 558
vhdl_architecture_body_items -> vhdl_architecture_body_item . (rule 188)
$default reduce using rule 188 (vhdl_architecture_body_items)
state 559
vhdl_architecture_body_item -> vhdl_component_instance . (rule 191)
$default reduce using rule 191 (vhdl_architecture_body_item)
state 560
vhdl_component_instance -> vhdl_inst_comp_binding . vhdl_inst_generic_map vhdl_inst_port_map end_item (rule 192)
GENERIC shift, and go to state 595
$default reduce using rule 196 (vhdl_inst_generic_map)
vhdl_inst_generic_map go to state 596
state 561
vhdl_architecture_body_item -> vhdl_concurrent_assignment . (rule 190)
$default reduce using rule 190 (vhdl_architecture_body_item)
state 562
vhdl_type -> BOOLEAN . vhdl_type_default_value_opt (rule 78)
ASSIGN shift, and go to state 597
ASSIGN [reduce using rule 80 (vhdl_type_default_value_opt)]
$default reduce using rule 80 (vhdl_type_default_value_opt)
vhdl_type_default_value_opt go to state 598
state 563
vhdl_type -> INTEGER . vhdl_type_default_value_opt (rule 74)
vhdl_type -> INTEGER . RANGE simple_range_expr vhdl_type_default_value_opt (rule 75)
ASSIGN shift, and go to state 597
RANGE shift, and go to state 599
ASSIGN [reduce using rule 80 (vhdl_type_default_value_opt)]
$default reduce using rule 80 (vhdl_type_default_value_opt)
vhdl_type_default_value_opt go to state 600
state 564
vhdl_type -> NATURAL . vhdl_type_default_value_opt (rule 76)
vhdl_type -> NATURAL . RANGE simple_range_expr vhdl_type_default_value_opt (rule 77)
ASSIGN shift, and go to state 597
RANGE shift, and go to state 601
ASSIGN [reduce using rule 80 (vhdl_type_default_value_opt)]
$default reduce using rule 80 (vhdl_type_default_value_opt)
vhdl_type_default_value_opt go to state 602
state 565
vhdl_type -> astring . vhdl_type_default_value_opt (rule 72)
vhdl_type -> astring . '(' bus_range ')' vhdl_type_default_value_opt (rule 73)
ASSIGN shift, and go to state 597
'(' shift, and go to state 603
ASSIGN [reduce using rule 80 (vhdl_type_default_value_opt)]
$default reduce using rule 80 (vhdl_type_default_value_opt)
vhdl_type_default_value_opt go to state 604
state 566
vhdl_signal_decl -> SIGNAL @5 hdl_signal_names ':' vhdl_type . end_item (rule 182)
';' shift, and go to state 240
end_item go to state 605
state 567
vhdl_component_decl -> COMPONENT hdl_compname_decl vhdl_generic_decl_opt vhdl_port_decl_opt END . COMPONENT end_item (rule 177)
COMPONENT shift, and go to state 606
state 568
vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE . ENTITY astring '.' astring '(' astring ')' ';' (rule 186)
ENTITY shift, and go to state 607
state 569
pin_equivalence -> EQUIVALENT @1 '(' equivalent_pins ')' . end_item (rule 127)
';' shift, and go to state 240
end_item go to state 608
state 570
equivalent_pins -> equivalent_pin end_item . equivalent_pins (rule 128)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
$default reduce using rule 130 (equivalent_pins)
astring go to state 520
equivalent_pins go to state 609
equivalent_pin go to state 522
state 571
pin_group -> '(' NUM_STRING ')' . (rule 51)
$default reduce using rule 51 (pin_group)
state 572
pin_rest -> pin_dir pin_group '=' pin_ident . vhdl_type_opt (rule 47)
':' shift, and go to state 610
$default reduce using rule 71 (vhdl_type_opt)
vhdl_type_opt go to state 611
state 573
pin_ident -> netname . (rule 53)
$default reduce using rule 53 (pin_ident)
state 574
apex_info_line -> TXT_STRING ':' astring ':' PINDIR ':' . astring ':' (rule 66)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 612
state 575
apex_info_line -> TXT_STRING '[' expr ']' ':' astring . ':' PINDIR ':' astring ':' (rule 67)
':' shift, and go to state 613
state 576
conn_decl -> CONN conn_ident conn_name last_route_status end_item nodelist END_CONN . @17 end_item (rule 352)
$default reduce using rule 351 (@17)
@17 go to state 614
state 577
nodelist -> nodelist net_node . (rule 356)
$default reduce using rule 356 (nodelist)
state 578
net_node -> skt_id '(' . node_id ')' fix_loc_part force_pin_dir node_group end_item (rule 359)
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 133
node_id go to state 615
netname go to state 616
state 579
jumper_node -> netname '(' astring ')' . (rule 326)
$default reduce using rule 326 (jumper_node)
state 580
verilog_port_map -> '.' astring '(' ')' . (rule 263)
$default reduce using rule 263 (verilog_port_map)
state 581
verilog_port_map -> '.' astring '(' astring . verilog_bus_expr ')' (rule 262)
'[' shift, and go to state 255
$default reduce using rule 240 (verilog_bus_expr)
verilog_bus_expr go to state 617
state 582
word -> astring . (rule 299)
$default reduce using rule 299 (word)
state 583
assign_words -> ASSIGN several_words . (rule 295)
$default reduce using rule 295 (assign_words)
state 584
several_words -> word . several_words (rule 297)
several_words -> word . (rule 298)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
$default reduce using rule 298 (several_words)
astring go to state 582
several_words go to state 618
word go to state 584
state 585
opt_bus_range -> ASSIGN bus_range . (rule 293)
$default reduce using rule 293 (opt_bus_range)
state 586
vhdl_generic_decl -> GENERIC '(' @3 generic_defn_lines ')' . end_item (rule 147)
';' shift, and go to state 240
end_item go to state 619
state 587
vhdl_port_decl -> PORT '(' vhdl_port_list ')' . end_item (rule 150)
';' shift, and go to state 240
end_item go to state 620
state 588
vhdl_port_list -> vhdl_port_list end_item . vhdl_port_item (rule 151)
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 133
vhdl_port_item go to state 621
vhdl_name_list go to state 553
hdl_name_part go to state 554
netname go to state 314
state 589
vhdl_port_item -> vhdl_name_list ':' . pin_dir vhdl_type vhdl_assign_opt (rule 154)
PINDIR shift, and go to state 308
pin_dir go to state 622
state 590
vhdl_name_list -> vhdl_name_list ',' . hdl_name_part (rule 155)
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 133
hdl_name_part go to state 623
netname go to state 314
state 591
vhdl_chip_decl -> ENTITY hdl_entityname_decl IS @2 vhdl_generic_decl_opt vhdl_port_decl_opt END TXT_STRING end_item . (rule 142)
$default reduce using rule 142 (vhdl_chip_decl)
state 592
vhdl_inst_comp_binding -> TXT_STRING ':' . TXT_STRING (rule 193)
TXT_STRING shift, and go to state 624
state 593
vhdl_architecture -> ARCHITECTURE astring OF astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END . astring end_item (rule 160)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 625
state 594
vhdl_architecture_body_items -> vhdl_architecture_body_items vhdl_architecture_body_item . (rule 187)
$default reduce using rule 187 (vhdl_architecture_body_items)
state 595
vhdl_inst_generic_map -> GENERIC . MAP @6 '(' vhdl_gen_map_list ')' (rule 195)
MAP shift, and go to state 626
state 596
vhdl_component_instance -> vhdl_inst_comp_binding vhdl_inst_generic_map . vhdl_inst_port_map end_item (rule 192)
PORT shift, and go to state 627
$default reduce using rule 198 (vhdl_inst_port_map)
vhdl_inst_port_map go to state 628
state 597
vhdl_type_default_value_opt -> ASSIGN . bus_range (rule 79)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
QUOTE shift, and go to state 29
QUOTED_STRING shift, and go to state 30
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
bus_range go to state 629
expr1 go to state 39
simple_range_expr go to state 40
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 53
state 598
vhdl_type -> BOOLEAN vhdl_type_default_value_opt . (rule 78)
$default reduce using rule 78 (vhdl_type)
state 599
vhdl_type -> INTEGER RANGE . simple_range_expr vhdl_type_default_value_opt (rule 75)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
simple_range_expr go to state 630
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 631
state 600
vhdl_type -> INTEGER vhdl_type_default_value_opt . (rule 74)
$default reduce using rule 74 (vhdl_type)
state 601
vhdl_type -> NATURAL RANGE . simple_range_expr vhdl_type_default_value_opt (rule 77)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
simple_range_expr go to state 632
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 631
state 602
vhdl_type -> NATURAL vhdl_type_default_value_opt . (rule 76)
$default reduce using rule 76 (vhdl_type)
state 603
vhdl_type -> astring '(' . bus_range ')' vhdl_type_default_value_opt (rule 73)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
QUOTE shift, and go to state 29
QUOTED_STRING shift, and go to state 30
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
bus_range go to state 633
expr1 go to state 39
simple_range_expr go to state 40
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 53
state 604
vhdl_type -> astring vhdl_type_default_value_opt . (rule 72)
$default reduce using rule 72 (vhdl_type)
state 605
vhdl_signal_decl -> SIGNAL @5 hdl_signal_names ':' vhdl_type end_item . (rule 182)
$default reduce using rule 182 (vhdl_signal_decl)
state 606
vhdl_component_decl -> COMPONENT hdl_compname_decl vhdl_generic_decl_opt vhdl_port_decl_opt END COMPONENT . end_item (rule 177)
';' shift, and go to state 240
end_item go to state 634
state 607
vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY . astring '.' astring '(' astring ')' ';' (rule 186)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 635
state 608
pin_equivalence -> EQUIVALENT @1 '(' equivalent_pins ')' end_item . (rule 127)
$default reduce using rule 127 (pin_equivalence)
state 609
equivalent_pins -> equivalent_pin end_item equivalent_pins . (rule 128)
$default reduce using rule 128 (equivalent_pins)
state 610
vhdl_type_opt -> ':' . vhdl_type (rule 70)
BOOLEAN shift, and go to state 562
INTEGER shift, and go to state 563
NATURAL shift, and go to state 564
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 565
vhdl_type go to state 636
state 611
pin_rest -> pin_dir pin_group '=' pin_ident vhdl_type_opt . (rule 47)
$default reduce using rule 47 (pin_rest)
state 612
apex_info_line -> TXT_STRING ':' astring ':' PINDIR ':' astring . ':' (rule 66)
':' shift, and go to state 637
state 613
apex_info_line -> TXT_STRING '[' expr ']' ':' astring ':' . PINDIR ':' astring ':' (rule 67)
PINDIR shift, and go to state 638
state 614
conn_decl -> CONN conn_ident conn_name last_route_status end_item nodelist END_CONN @17 . end_item (rule 352)
';' shift, and go to state 240
end_item go to state 639
state 615
net_node -> skt_id '(' node_id . ')' fix_loc_part force_pin_dir node_group end_item (rule 359)
')' shift, and go to state 640
state 616
node_id -> netname . (rule 363)
$default reduce using rule 363 (node_id)
state 617
verilog_port_map -> '.' astring '(' astring verilog_bus_expr . ')' (rule 262)
')' shift, and go to state 641
state 618
several_words -> word several_words . (rule 297)
$default reduce using rule 297 (several_words)
state 619
vhdl_generic_decl -> GENERIC '(' @3 generic_defn_lines ')' end_item . (rule 147)
$default reduce using rule 147 (vhdl_generic_decl)
state 620
vhdl_port_decl -> PORT '(' vhdl_port_list ')' end_item . (rule 150)
$default reduce using rule 150 (vhdl_port_decl)
state 621
vhdl_port_list -> vhdl_port_list end_item vhdl_port_item . (rule 151)
$default reduce using rule 151 (vhdl_port_list)
state 622
vhdl_port_item -> vhdl_name_list ':' pin_dir . vhdl_type vhdl_assign_opt (rule 154)
BOOLEAN shift, and go to state 562
INTEGER shift, and go to state 563
NATURAL shift, and go to state 564
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 565
vhdl_type go to state 642
state 623
vhdl_name_list -> vhdl_name_list ',' hdl_name_part . (rule 155)
$default reduce using rule 155 (vhdl_name_list)
state 624
vhdl_inst_comp_binding -> TXT_STRING ':' TXT_STRING . (rule 193)
$default reduce using rule 193 (vhdl_inst_comp_binding)
state 625
vhdl_architecture -> ARCHITECTURE astring OF astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring . end_item (rule 160)
';' shift, and go to state 240
end_item go to state 643
state 626
vhdl_inst_generic_map -> GENERIC MAP . @6 '(' vhdl_gen_map_list ')' (rule 195)
$default reduce using rule 194 (@6)
@6 go to state 644
state 627
vhdl_inst_port_map -> PORT . MAP '(' vhdl_port_map_list ')' (rule 197)
MAP shift, and go to state 645
state 628
vhdl_component_instance -> vhdl_inst_comp_binding vhdl_inst_generic_map vhdl_inst_port_map . end_item (rule 192)
';' shift, and go to state 240
end_item go to state 646
state 629
vhdl_type_default_value_opt -> ASSIGN bus_range . (rule 79)
$default reduce using rule 79 (vhdl_type_default_value_opt)
state 630
vhdl_type -> INTEGER RANGE simple_range_expr . vhdl_type_default_value_opt (rule 75)
ASSIGN shift, and go to state 597
ASSIGN [reduce using rule 80 (vhdl_type_default_value_opt)]
$default reduce using rule 80 (vhdl_type_default_value_opt)
vhdl_type_default_value_opt go to state 647
state 631
simple_range_expr -> expr . TO expr (rule 86)
simple_range_expr -> expr . DOWNTO expr (rule 87)
TO shift, and go to state 117
DOWNTO shift, and go to state 118
state 632
vhdl_type -> NATURAL RANGE simple_range_expr . vhdl_type_default_value_opt (rule 77)
ASSIGN shift, and go to state 597
ASSIGN [reduce using rule 80 (vhdl_type_default_value_opt)]
$default reduce using rule 80 (vhdl_type_default_value_opt)
vhdl_type_default_value_opt go to state 648
state 633
vhdl_type -> astring '(' bus_range . ')' vhdl_type_default_value_opt (rule 73)
')' shift, and go to state 649
state 634
vhdl_component_decl -> COMPONENT hdl_compname_decl vhdl_generic_decl_opt vhdl_port_decl_opt END COMPONENT end_item . (rule 177)
$default reduce using rule 177 (vhdl_component_decl)
state 635
vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring . '.' astring '(' astring ')' ';' (rule 186)
'.' shift, and go to state 650
state 636
vhdl_type_opt -> ':' vhdl_type . (rule 70)
$default reduce using rule 70 (vhdl_type_opt)
state 637
apex_info_line -> TXT_STRING ':' astring ':' PINDIR ':' astring ':' . (rule 66)
$default reduce using rule 66 (apex_info_line)
state 638
apex_info_line -> TXT_STRING '[' expr ']' ':' astring ':' PINDIR . ':' astring ':' (rule 67)
':' shift, and go to state 651
state 639
conn_decl -> CONN conn_ident conn_name last_route_status end_item nodelist END_CONN @17 end_item . (rule 352)
$default reduce using rule 352 (conn_decl)
state 640
net_node -> skt_id '(' node_id ')' . fix_loc_part force_pin_dir node_group end_item (rule 359)
FIX_LOCATION shift, and go to state 652
$default reduce using rule 365 (fix_loc_part)
fix_loc_part go to state 653
state 641
verilog_port_map -> '.' astring '(' astring verilog_bus_expr ')' . (rule 262)
$default reduce using rule 262 (verilog_port_map)
state 642
vhdl_port_item -> vhdl_name_list ':' pin_dir vhdl_type . vhdl_assign_opt (rule 154)
ASSIGN shift, and go to state 654
$default reduce using rule 159 (vhdl_assign_opt)
vhdl_assign_opt go to state 655
state 643
vhdl_architecture -> ARCHITECTURE astring OF astring IS vhdl_architecture_declarations BEGIN_TOK vhdl_architecture_body_items END astring end_item . (rule 160)
$default reduce using rule 160 (vhdl_architecture)
state 644
vhdl_inst_generic_map -> GENERIC MAP @6 . '(' vhdl_gen_map_list ')' (rule 195)
'(' shift, and go to state 656
state 645
vhdl_inst_port_map -> PORT MAP . '(' vhdl_port_map_list ')' (rule 197)
'(' shift, and go to state 657
state 646
vhdl_component_instance -> vhdl_inst_comp_binding vhdl_inst_generic_map vhdl_inst_port_map end_item . (rule 192)
$default reduce using rule 192 (vhdl_component_instance)
state 647
vhdl_type -> INTEGER RANGE simple_range_expr vhdl_type_default_value_opt . (rule 75)
$default reduce using rule 75 (vhdl_type)
state 648
vhdl_type -> NATURAL RANGE simple_range_expr vhdl_type_default_value_opt . (rule 77)
$default reduce using rule 77 (vhdl_type)
state 649
vhdl_type -> astring '(' bus_range ')' . vhdl_type_default_value_opt (rule 73)
ASSIGN shift, and go to state 597
ASSIGN [reduce using rule 80 (vhdl_type_default_value_opt)]
$default reduce using rule 80 (vhdl_type_default_value_opt)
vhdl_type_default_value_opt go to state 658
state 650
vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring '.' . astring '(' astring ')' ';' (rule 186)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 659
state 651
apex_info_line -> TXT_STRING '[' expr ']' ':' astring ':' PINDIR ':' . astring ':' (rule 67)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 660
state 652
fix_loc_part -> FIX_LOCATION . (rule 364)
$default reduce using rule 364 (fix_loc_part)
state 653
net_node -> skt_id '(' node_id ')' fix_loc_part . force_pin_dir node_group end_item (rule 359)
PINDIR shift, and go to state 661
$default reduce using rule 361 (force_pin_dir)
force_pin_dir go to state 662
state 654
vhdl_assign_opt -> ASSIGN . expr (rule 158)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 663
state 655
vhdl_port_item -> vhdl_name_list ':' pin_dir vhdl_type vhdl_assign_opt . (rule 154)
$default reduce using rule 154 (vhdl_port_item)
state 656
vhdl_inst_generic_map -> GENERIC MAP @6 '(' . vhdl_gen_map_list ')' (rule 195)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 664
vhdl_gen_map_list go to state 665
vhdl_gen_map go to state 666
state 657
vhdl_inst_port_map -> PORT MAP '(' . vhdl_port_map_list ')' (rule 197)
OPEN shift, and go to state 667
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 668
vhdl_port_map_list go to state 669
vhdl_port_map go to state 670
rename_new_name go to state 671
netname go to state 137
state 658
vhdl_type -> astring '(' bus_range ')' vhdl_type_default_value_opt . (rule 73)
$default reduce using rule 73 (vhdl_type)
state 659
vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring '.' astring . '(' astring ')' ';' (rule 186)
'(' shift, and go to state 672
state 660
apex_info_line -> TXT_STRING '[' expr ']' ':' astring ':' PINDIR ':' astring . ':' (rule 67)
':' shift, and go to state 673
state 661
force_pin_dir -> PINDIR . (rule 360)
$default reduce using rule 360 (force_pin_dir)
state 662
net_node -> skt_id '(' node_id ')' fix_loc_part force_pin_dir . node_group end_item (rule 359)
'(' shift, and go to state 674
$default reduce using rule 367 (node_group)
node_group go to state 675
state 663
vhdl_assign_opt -> ASSIGN expr . (rule 158)
$default reduce using rule 158 (vhdl_assign_opt)
state 664
vhdl_gen_map -> astring . CONNECTED bus_range (rule 201)
CONNECTED shift, and go to state 676
state 665
vhdl_inst_generic_map -> GENERIC MAP @6 '(' vhdl_gen_map_list . ')' (rule 195)
vhdl_gen_map_list -> vhdl_gen_map_list . ',' vhdl_gen_map (rule 199)
')' shift, and go to state 677
',' shift, and go to state 678
state 666
vhdl_gen_map_list -> vhdl_gen_map . (rule 200)
$default reduce using rule 200 (vhdl_gen_map_list)
state 667
vhdl_port_map -> OPEN . (rule 207)
$default reduce using rule 207 (vhdl_port_map)
state 668
vhdl_port_map -> astring . vhdl_port_map_slice_opt CONNECTED rename_new_name (rule 204)
vhdl_port_map -> astring . vhdl_port_map_slice_opt CONNECTED OPEN (rule 205)
netname -> astring . (rule 370)
'(' shift, and go to state 679
CONNECTED reduce using rule 209 (vhdl_port_map_slice_opt)
'(' [reduce using rule 370 (netname)]
$default reduce using rule 370 (netname)
vhdl_port_map_slice_opt go to state 680
state 669
vhdl_inst_port_map -> PORT MAP '(' vhdl_port_map_list . ')' (rule 197)
vhdl_port_map_list -> vhdl_port_map_list . ',' vhdl_port_map (rule 202)
')' shift, and go to state 681
',' shift, and go to state 682
state 670
vhdl_port_map_list -> vhdl_port_map . (rule 203)
$default reduce using rule 203 (vhdl_port_map_list)
state 671
vhdl_port_map -> rename_new_name . vhdl_port_map_slice_opt (rule 206)
'(' shift, and go to state 679
$default reduce using rule 209 (vhdl_port_map_slice_opt)
vhdl_port_map_slice_opt go to state 683
state 672
vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring '.' astring '(' . astring ')' ';' (rule 186)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 684
state 673
apex_info_line -> TXT_STRING '[' expr ']' ':' astring ':' PINDIR ':' astring ':' . (rule 67)
$default reduce using rule 67 (apex_info_line)
state 674
node_group -> '(' . NUM_STRING ')' (rule 366)
NUM_STRING shift, and go to state 685
state 675
net_node -> skt_id '(' node_id ')' fix_loc_part force_pin_dir node_group . end_item (rule 359)
';' shift, and go to state 240
end_item go to state 686
state 676
vhdl_gen_map -> astring CONNECTED . bus_range (rule 201)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
QUOTE shift, and go to state 29
QUOTED_STRING shift, and go to state 30
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
bus_range go to state 687
expr1 go to state 39
simple_range_expr go to state 40
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 53
state 677
vhdl_inst_generic_map -> GENERIC MAP @6 '(' vhdl_gen_map_list ')' . (rule 195)
$default reduce using rule 195 (vhdl_inst_generic_map)
state 678
vhdl_gen_map_list -> vhdl_gen_map_list ',' . vhdl_gen_map (rule 199)
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 664
vhdl_gen_map go to state 688
state 679
vhdl_port_map_slice_opt -> '(' . bus_range ')' (rule 208)
TRUE shift, and go to state 27
FALSE shift, and go to state 28
QUOTE shift, and go to state 29
QUOTED_STRING shift, and go to state 30
TXT_STRING shift, and go to state 31
NUM_STRING shift, and go to state 32
'~' shift, and go to state 33
'(' shift, and go to state 34
'-' shift, and go to state 35
bus_range go to state 689
expr1 go to state 39
simple_range_expr go to state 40
primary_expr go to state 41
mult_expr go to state 42
add_expr go to state 43
shift_expr go to state 44
relational_expr go to state 45
equality_expr go to state 46
and_expr go to state 47
exor_expr go to state 48
or_expr go to state 49
logand_expr go to state 50
logor_expr go to state 51
cond_expr go to state 52
expr go to state 53
state 680
vhdl_port_map -> astring vhdl_port_map_slice_opt . CONNECTED rename_new_name (rule 204)
vhdl_port_map -> astring vhdl_port_map_slice_opt . CONNECTED OPEN (rule 205)
CONNECTED shift, and go to state 690
state 681
vhdl_inst_port_map -> PORT MAP '(' vhdl_port_map_list ')' . (rule 197)
$default reduce using rule 197 (vhdl_inst_port_map)
state 682
vhdl_port_map_list -> vhdl_port_map_list ',' . vhdl_port_map (rule 202)
OPEN shift, and go to state 667
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 668
vhdl_port_map go to state 691
rename_new_name go to state 671
netname go to state 137
state 683
vhdl_port_map -> rename_new_name vhdl_port_map_slice_opt . (rule 206)
$default reduce using rule 206 (vhdl_port_map)
state 684
vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring '.' astring '(' astring . ')' ';' (rule 186)
')' shift, and go to state 692
state 685
node_group -> '(' NUM_STRING . ')' (rule 366)
')' shift, and go to state 693
state 686
net_node -> skt_id '(' node_id ')' fix_loc_part force_pin_dir node_group end_item . (rule 359)
$default reduce using rule 359 (net_node)
state 687
vhdl_gen_map -> astring CONNECTED bus_range . (rule 201)
$default reduce using rule 201 (vhdl_gen_map)
state 688
vhdl_gen_map_list -> vhdl_gen_map_list ',' vhdl_gen_map . (rule 199)
$default reduce using rule 199 (vhdl_gen_map_list)
state 689
vhdl_port_map_slice_opt -> '(' bus_range . ')' (rule 208)
')' shift, and go to state 694
state 690
vhdl_port_map -> astring vhdl_port_map_slice_opt CONNECTED . rename_new_name (rule 204)
vhdl_port_map -> astring vhdl_port_map_slice_opt CONNECTED . OPEN (rule 205)
OPEN shift, and go to state 695
GND shift, and go to state 131
VCC shift, and go to state 132
QUOTED_STRING shift, and go to state 54
TXT_STRING shift, and go to state 55
NUM_STRING shift, and go to state 56
astring go to state 133
rename_new_name go to state 696
netname go to state 137
state 691
vhdl_port_map_list -> vhdl_port_map_list ',' vhdl_port_map . (rule 202)
$default reduce using rule 202 (vhdl_port_map_list)
state 692
vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring '.' astring '(' astring ')' . ';' (rule 186)
';' shift, and go to state 697
state 693
node_group -> '(' NUM_STRING ')' . (rule 366)
$default reduce using rule 366 (node_group)
state 694
vhdl_port_map_slice_opt -> '(' bus_range ')' . (rule 208)
$default reduce using rule 208 (vhdl_port_map_slice_opt)
state 695
vhdl_port_map -> astring vhdl_port_map_slice_opt CONNECTED OPEN . (rule 205)
$default reduce using rule 205 (vhdl_port_map)
state 696
vhdl_port_map -> astring vhdl_port_map_slice_opt CONNECTED rename_new_name . (rule 204)
$default reduce using rule 204 (vhdl_port_map)
state 697
vhdl_configuration_decl -> FOR vhdl_lib_member_select ':' astring USE ENTITY astring '.' astring '(' astring ')' ';' . (rule 186)
$default reduce using rule 186 (vhdl_configuration_decl)
state 698
$ go to state 699
state 699
$ go to state 700
state 700
$default accept