/*
* misc.c
*
* Created on: 21 Sep 2016
* Author: Mike
*/
#include "stm32l1xx_hal.h"
#include "misc.h"
#include "main.h"
extern TIM_HandleTypeDef htim2;
extern TIM_HandleTypeDef htim3;
extern TIM_HandleTypeDef htim6;
unsigned volatile long RPM_Time[RPM_SAMPLES]; // sampled on both edges
unsigned volatile char RPM_Level[RPM_SAMPLES]; // active level when sampled
unsigned volatile long RPM_Count; // incremented every reading
void TIM2_IRQHandler(void)
{
if(__HAL_TIM_GET_FLAG(&htim2, TIM_FLAG_CC1))
{
__HAL_TIM_CLEAR_FLAG(&htim2, TIM_FLAG_CC1) ;
RPM_Time[RPM_Count] = __HAL_TIM_GET_COMPARE(&htim2,TIM_CHANNEL_1);
RPM_Level[RPM_Count] =
HAL_GPIO_ReadPin(CB_Pulse_GPIO_Port, CB_Pulse_Pin);
RPM_Count = (RPM_Count+1) % RPM_SAMPLES ;
__HAL_TIM_SET_COUNTER(&htim3,0); // trigger timer 3 by setting the count to zero
}
}
char blink = 0;
// 100mS periodic sampler handler
void TIM6_IRQHandler(void)
{
if(__HAL_TIM_GET_FLAG(&htim6, TIM_FLAG_UPDATE))
{
__HAL_TIM_CLEAR_FLAG(&htim6, TIM_FLAG_UPDATE) ;
blink = !blink;
HAL_GPIO_WritePin(LED_Blink_GPIO_Port, LED_Blink_Pin, blink ? GPIO_PIN_SET : GPIO_PIN_RESET);
TimerFlag = 1;
if (NoSerialInCTR < 5) {
NoSerialInCTR++;
if (NoSerialInCTR == 5) {
NoSerialIn = 1;
}
}
}
}
void resetSerialTimeout(void)
{
__disable_irq();
NoSerialInCTR= 0 ;
NoSerialIn = 0;
__enable_irq();
}
#if OLD_ENGINEBAY
//-----------------------------------------------------------
// This is the 10Hz timer
void interrupt TimerISR1(void) {
TimerFlag = 1;
if (NoSerialInCTR < 5) {
NoSerialInCTR++;
if (NoSerialInCTR == 5) {
NoSerialIn = 1;
}
}
}
//-----------------------------------------------------------
volatile unsigned long RPM_Time[RPM_LIMIT];
volatile unsigned long RPM_Count; // incremented every reading
void TimerISR0(void) {
// check the listing
asm volatile ("STMDB SP!, {r0-r4} ");
// sort out the captures
int stat = REG(TIMER0_IR);
if (stat & (1 << 4)) //CR0
{
RPM_Time[RPM_Count++] = REG(TIMER0_CR0);
if (RPM_Count == RPM_LIMIT) {
RPM_Count = 0;
}
}
if (stat & (1 << 5)) //CR1
{
// TDC_Time = REG(TIMER0_CR1);
// TDC_Count++;
}
REG(TIMER0_IR) = stat; // clear the interrupts just handled.
REG(VICVectAddr) = 0; // reset the VIC
asm volatile ("LDMIA SP!, {r0-r4} ");
asm volatile ("SUBS PC,lr,#4");
}
//-----------------------------------------------------------
// UART management
// serial counter
#define THRE (1<<6)
#define RDR (1<<0)
#define BUFFSIZ 256
volatile char txbuff[BUFFSIZ];
volatile int txptr = 0;
volatile int txcnt = 0;
volatile char rxbuff[BUFFSIZ];
volatile int rxptr = 0;
volatile int rxcnt = 0;
void Uart0ISR(void) __attribute__((naked));
void Uart0ISR(void) __attribute__((noinline));
void Uart0ISR(void) {
asm volatile ("STMDB SP!, {r0-r3} ");
int stat;
while (!((stat = REG(UART0_IIR)) & 1)) { // LSbit is inactive
switch (stat & 0x0E) {
case 4:
case 12: {
char c = REG(UART0_RBR);
NoSerialIn = NoSerialInCTR = 0;
if (rxcnt < (BUFFSIZ - 1)) {
rxbuff[(rxptr + rxcnt) % BUFFSIZ] = c;
rxcnt++;
}
}
break;
case 2: {
if (txcnt > 0) {
REG(UART0_THR) = txbuff[txptr];
txcnt--;
txptr++;
txptr %= BUFFSIZ;
} else {
REG(UART0_IER) &= ~(1 << 1); // disable TX
}
}
break;
}
}
REG(VICVectAddr) = 0; // reset the VIC
asm volatile ("LDMIA SP!, {r0-r3} ");
asm volatile ("SUBS PC,lr,#4");
}
int my_putchar(int c) {
int rc = 0;
{
STI;
if (!(REG(UART0_IER) & (1 << 1))) {
REG(UART0_IER) |= (1 << 1);
REG(UART0_THR) = c;
rc=1;
} else {
if (txcnt < (BUFFSIZ - 1)) {
txbuff[(txptr + txcnt) % BUFFSIZ] = c;
txcnt++;
rc = 1;
}
}
CLI;
}
return rc;
}
int my_getchar(void) {
int c = -1;
STI;
if (rxcnt) {
c = rxbuff[rxptr];
rxcnt--;
rxptr++;
rxptr %= BUFFSIZ;
}
CLI;
return c;
}
#endif