Subversion Repositories EngineBay2

Rev

Rev 2 | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32l1xx_hal_tim.c
  4.   * @author  MCD Application Team
  5.   * @brief   TIM HAL module driver.
  6.   *          This file provides firmware functions to manage the following
  7.   *          functionalities of the Timer (TIM) peripheral:
  8.   *           + TIM Time Base Initialization
  9.   *           + TIM Time Base Start
  10.   *           + TIM Time Base Start Interruption
  11.   *           + TIM Time Base Start DMA
  12.   *           + TIM Output Compare/PWM Initialization
  13.   *           + TIM Output Compare/PWM Channel Configuration
  14.   *           + TIM Output Compare/PWM  Start
  15.   *           + TIM Output Compare/PWM  Start Interruption
  16.   *           + TIM Output Compare/PWM Start DMA
  17.   *           + TIM Input Capture Initialization
  18.   *           + TIM Input Capture Channel Configuration
  19.   *           + TIM Input Capture Start
  20.   *           + TIM Input Capture Start Interruption
  21.   *           + TIM Input Capture Start DMA
  22.   *           + TIM One Pulse Initialization
  23.   *           + TIM One Pulse Channel Configuration
  24.   *           + TIM One Pulse Start
  25.   *           + TIM Encoder Interface Initialization
  26.   *           + TIM Encoder Interface Start
  27.   *           + TIM Encoder Interface Start Interruption
  28.   *           + TIM Encoder Interface Start DMA
  29.   *           + Commutation Event configuration with Interruption and DMA
  30.   *           + TIM OCRef clear configuration
  31.   *           + TIM External Clock configuration
  32.   @verbatim
  33.   ==============================================================================
  34.                       ##### TIMER Generic features #####
  35.   ==============================================================================
  36.   [..] The Timer features include:
  37.        (#) 16-bit up, down, up/down auto-reload counter.
  38.        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
  39.            counter clock frequency either by any factor between 1 and 65536.
  40.        (#) Up to 4 independent channels for:
  41.            (++) Input Capture
  42.            (++) Output Compare
  43.            (++) PWM generation (Edge and Center-aligned Mode)
  44.            (++) One-pulse mode output
  45.        (#) Synchronization circuit to control the timer with external signals and to interconnect
  46.             several timers together.
  47.        (#) Supports incremental encoder for positioning purposes
  48.  
  49.             ##### How to use this driver #####
  50.   ==============================================================================
  51.     [..]
  52.      (#) Initialize the TIM low level resources by implementing the following functions
  53.          depending on the selected feature:
  54.            (++) Time Base : HAL_TIM_Base_MspInit()
  55.            (++) Input Capture : HAL_TIM_IC_MspInit()
  56.            (++) Output Compare : HAL_TIM_OC_MspInit()
  57.            (++) PWM generation : HAL_TIM_PWM_MspInit()
  58.            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
  59.            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
  60.  
  61.      (#) Initialize the TIM low level resources :
  62.         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
  63.         (##) TIM pins configuration
  64.             (+++) Enable the clock for the TIM GPIOs using the following function:
  65.              __HAL_RCC_GPIOx_CLK_ENABLE();
  66.             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
  67.  
  68.      (#) The external Clock can be configured, if needed (the default clock is the
  69.          internal clock from the APBx), using the following function:
  70.          HAL_TIM_ConfigClockSource, the clock configuration should be done before
  71.          any start function.
  72.  
  73.      (#) Configure the TIM in the desired functioning mode using one of the
  74.        Initialization function of this driver:
  75.        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
  76.        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
  77.             Output Compare signal.
  78.        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
  79.             PWM signal.
  80.        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
  81.             external signal.
  82.        (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
  83.             in One Pulse Mode.
  84.        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
  85.  
  86.      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
  87.            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
  88.            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
  89.            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
  90.            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
  91.            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
  92.            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
  93.  
  94.      (#) The DMA Burst is managed with the two following functions:
  95.          HAL_TIM_DMABurst_WriteStart()
  96.          HAL_TIM_DMABurst_ReadStart()
  97.  
  98.     *** Callback registration ***
  99.   =============================================
  100.  
  101.   [..]
  102.   The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
  103.   allows the user to configure dynamically the driver callbacks.
  104.  
  105.   [..]
  106.   Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
  107.   @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
  108.   the Callback ID and a pointer to the user callback function.
  109.  
  110.   [..]
  111.   Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
  112.   weak function.
  113.   @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
  114.   and the Callback ID.
  115.  
  116.   [..]
  117.   These functions allow to register/unregister following callbacks:
  118.     (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
  119.     (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
  120.     (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
  121.     (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
  122.     (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
  123.     (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
  124.     (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
  125.     (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
  126.     (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
  127.     (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
  128.     (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
  129.     (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
  130.     (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
  131.     (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
  132.     (+) TriggerCallback                   : TIM Trigger Callback.
  133.     (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
  134.     (+) IC_CaptureCallback                : TIM Input Capture Callback.
  135.     (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
  136.     (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
  137.     (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
  138.     (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
  139.     (+) ErrorCallback                     : TIM Error Callback.
  140.  
  141.   [..]
  142. By default, after the Init and when the state is HAL_TIM_STATE_RESET
  143. all interrupt callbacks are set to the corresponding weak functions:
  144.   examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
  145.  
  146.   [..]
  147.   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
  148.   functionalities in the Init / DeInit only when these callbacks are null
  149.   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
  150.     keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
  151.  
  152.   [..]
  153.     Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
  154.     Exception done MspInit / MspDeInit that can be registered / unregistered
  155.     in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
  156.     thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
  157.   In that case first register the MspInit/MspDeInit user callbacks
  158.       using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
  159.  
  160.   [..]
  161.       When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
  162.       not defined, the callback registration feature is not available and all callbacks
  163.       are set to the corresponding weak functions.
  164.  
  165.   @endverbatim
  166.   ******************************************************************************
  167.   * @attention
  168.   *
  169.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  170.   * All rights reserved.</center></h2>
  171.   *
  172.   * This software component is licensed by ST under BSD 3-Clause license,
  173.   * the "License"; You may not use this file except in compliance with the
  174.   * License. You may obtain a copy of the License at:
  175.   *                        opensource.org/licenses/BSD-3-Clause
  176.   *
  177.   ******************************************************************************
  178.   */
  179.  
  180. /* Includes ------------------------------------------------------------------*/
  181. #include "stm32l1xx_hal.h"
  182.  
  183. /** @addtogroup STM32L1xx_HAL_Driver
  184.   * @{
  185.   */
  186.  
  187. /** @defgroup TIM TIM
  188.   * @brief TIM HAL module driver
  189.   * @{
  190.   */
  191.  
  192. #ifdef HAL_TIM_MODULE_ENABLED
  193.  
  194. /* Private typedef -----------------------------------------------------------*/
  195. /* Private define ------------------------------------------------------------*/
  196. /* Private macros ------------------------------------------------------------*/
  197. /* Private variables ---------------------------------------------------------*/
  198. /* Private function prototypes -----------------------------------------------*/
  199. /** @addtogroup TIM_Private_Functions
  200.   * @{
  201.   */
  202. static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
  203. static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  204. static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  205. static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  206. static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  207. static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  208.                               uint32_t TIM_ICFilter);
  209. static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
  210. static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  211.                               uint32_t TIM_ICFilter);
  212. static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
  213. static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  214.                               uint32_t TIM_ICFilter);
  215. static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  216.                               uint32_t TIM_ICFilter);
  217. static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
  218. static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
  219.                               uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
  220. static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
  221. static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
  222. static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
  223. static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
  224. static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
  225. static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
  226.                                                   TIM_SlaveConfigTypeDef *sSlaveConfig);
  227. /**
  228.   * @}
  229.   */
  230. /* Exported functions --------------------------------------------------------*/
  231.  
  232. /** @defgroup TIM_Exported_Functions TIM Exported Functions
  233.   * @{
  234.   */
  235.  
  236. /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
  237.   *  @brief    Time Base functions
  238.   *
  239. @verbatim
  240.   ==============================================================================
  241.               ##### Time Base functions #####
  242.   ==============================================================================
  243.   [..]
  244.     This section provides functions allowing to:
  245.     (+) Initialize and configure the TIM base.
  246.     (+) De-initialize the TIM base.
  247.     (+) Start the Time Base.
  248.     (+) Stop the Time Base.
  249.     (+) Start the Time Base and enable interrupt.
  250.     (+) Stop the Time Base and disable interrupt.
  251.     (+) Start the Time Base and enable DMA transfer.
  252.     (+) Stop the Time Base and disable DMA transfer.
  253.  
  254. @endverbatim
  255.   * @{
  256.   */
  257. /**
  258.   * @brief  Initializes the TIM Time base Unit according to the specified
  259.   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
  260.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  261.   *         requires a timer reset to avoid unexpected direction
  262.   *         due to DIR bit readonly in center aligned mode.
  263.   *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  264.   * @param  htim TIM Base handle
  265.   * @retval HAL status
  266.   */
  267. HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
  268. {
  269.   /* Check the TIM handle allocation */
  270.   if (htim == NULL)
  271.   {
  272.     return HAL_ERROR;
  273.   }
  274.  
  275.   /* Check the parameters */
  276.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  277.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  278.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  279.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  280.  
  281.   if (htim->State == HAL_TIM_STATE_RESET)
  282.   {
  283.     /* Allocate lock resource and initialize it */
  284.     htim->Lock = HAL_UNLOCKED;
  285.  
  286. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  287.     /* Reset interrupt callbacks to legacy weak callbacks */
  288.     TIM_ResetCallback(htim);
  289.  
  290.     if (htim->Base_MspInitCallback == NULL)
  291.     {
  292.       htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
  293.     }
  294.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  295.     htim->Base_MspInitCallback(htim);
  296. #else
  297.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  298.     HAL_TIM_Base_MspInit(htim);
  299. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  300.   }
  301.  
  302.   /* Set the TIM state */
  303.   htim->State = HAL_TIM_STATE_BUSY;
  304.  
  305.   /* Set the Time Base configuration */
  306.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  307.  
  308.   /* Initialize the DMA burst operation state */
  309.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  310.  
  311.   /* Initialize the TIM channels state */
  312.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  313.  
  314.   /* Initialize the TIM state*/
  315.   htim->State = HAL_TIM_STATE_READY;
  316.  
  317.   return HAL_OK;
  318. }
  319.  
  320. /**
  321.   * @brief  DeInitializes the TIM Base peripheral
  322.   * @param  htim TIM Base handle
  323.   * @retval HAL status
  324.   */
  325. HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
  326. {
  327.   /* Check the parameters */
  328.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  329.  
  330.   htim->State = HAL_TIM_STATE_BUSY;
  331.  
  332.   /* Disable the TIM Peripheral Clock */
  333.   __HAL_TIM_DISABLE(htim);
  334.  
  335. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  336.   if (htim->Base_MspDeInitCallback == NULL)
  337.   {
  338.     htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
  339.   }
  340.   /* DeInit the low level hardware */
  341.   htim->Base_MspDeInitCallback(htim);
  342. #else
  343.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  344.   HAL_TIM_Base_MspDeInit(htim);
  345. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  346.  
  347.   /* Change the DMA burst operation state */
  348.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  349.  
  350.   /* Change the TIM channels state */
  351.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  352.  
  353.   /* Change TIM state */
  354.   htim->State = HAL_TIM_STATE_RESET;
  355.  
  356.   /* Release Lock */
  357.   __HAL_UNLOCK(htim);
  358.  
  359.   return HAL_OK;
  360. }
  361.  
  362. /**
  363.   * @brief  Initializes the TIM Base MSP.
  364.   * @param  htim TIM Base handle
  365.   * @retval None
  366.   */
  367. __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
  368. {
  369.   /* Prevent unused argument(s) compilation warning */
  370.   UNUSED(htim);
  371.  
  372.   /* NOTE : This function should not be modified, when the callback is needed,
  373.             the HAL_TIM_Base_MspInit could be implemented in the user file
  374.    */
  375. }
  376.  
  377. /**
  378.   * @brief  DeInitializes TIM Base MSP.
  379.   * @param  htim TIM Base handle
  380.   * @retval None
  381.   */
  382. __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
  383. {
  384.   /* Prevent unused argument(s) compilation warning */
  385.   UNUSED(htim);
  386.  
  387.   /* NOTE : This function should not be modified, when the callback is needed,
  388.             the HAL_TIM_Base_MspDeInit could be implemented in the user file
  389.    */
  390. }
  391.  
  392.  
  393. /**
  394.   * @brief  Starts the TIM Base generation.
  395.   * @param  htim TIM Base handle
  396.   * @retval HAL status
  397.   */
  398. HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
  399. {
  400.   uint32_t tmpsmcr;
  401.  
  402.   /* Check the parameters */
  403.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  404.  
  405.   /* Check the TIM state */
  406.   if (htim->State != HAL_TIM_STATE_READY)
  407.   {
  408.     return HAL_ERROR;
  409.   }
  410.  
  411.   /* Set the TIM state */
  412.   htim->State = HAL_TIM_STATE_BUSY;
  413.  
  414.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  415.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  416.   {
  417.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  418.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  419.     {
  420.       __HAL_TIM_ENABLE(htim);
  421.     }
  422.   }
  423.   else
  424.   {
  425.     __HAL_TIM_ENABLE(htim);
  426.   }
  427.  
  428.   /* Return function status */
  429.   return HAL_OK;
  430. }
  431.  
  432. /**
  433.   * @brief  Stops the TIM Base generation.
  434.   * @param  htim TIM Base handle
  435.   * @retval HAL status
  436.   */
  437. HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
  438. {
  439.   /* Check the parameters */
  440.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  441.  
  442.   /* Disable the Peripheral */
  443.   __HAL_TIM_DISABLE(htim);
  444.  
  445.   /* Set the TIM state */
  446.   htim->State = HAL_TIM_STATE_READY;
  447.  
  448.   /* Return function status */
  449.   return HAL_OK;
  450. }
  451.  
  452. /**
  453.   * @brief  Starts the TIM Base generation in interrupt mode.
  454.   * @param  htim TIM Base handle
  455.   * @retval HAL status
  456.   */
  457. HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
  458. {
  459.   uint32_t tmpsmcr;
  460.  
  461.   /* Check the parameters */
  462.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  463.  
  464.   /* Check the TIM state */
  465.   if (htim->State != HAL_TIM_STATE_READY)
  466.   {
  467.     return HAL_ERROR;
  468.   }
  469.  
  470.   /* Set the TIM state */
  471.   htim->State = HAL_TIM_STATE_BUSY;
  472.  
  473.   /* Enable the TIM Update interrupt */
  474.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
  475.  
  476.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  477.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  478.   {
  479.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  480.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  481.     {
  482.       __HAL_TIM_ENABLE(htim);
  483.     }
  484.   }
  485.   else
  486.   {
  487.     __HAL_TIM_ENABLE(htim);
  488.   }
  489.  
  490.   /* Return function status */
  491.   return HAL_OK;
  492. }
  493.  
  494. /**
  495.   * @brief  Stops the TIM Base generation in interrupt mode.
  496.   * @param  htim TIM Base handle
  497.   * @retval HAL status
  498.   */
  499. HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
  500. {
  501.   /* Check the parameters */
  502.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  503.  
  504.   /* Disable the TIM Update interrupt */
  505.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
  506.  
  507.   /* Disable the Peripheral */
  508.   __HAL_TIM_DISABLE(htim);
  509.  
  510.   /* Set the TIM state */
  511.   htim->State = HAL_TIM_STATE_READY;
  512.  
  513.   /* Return function status */
  514.   return HAL_OK;
  515. }
  516.  
  517. /**
  518.   * @brief  Starts the TIM Base generation in DMA mode.
  519.   * @param  htim TIM Base handle
  520.   * @param  pData The source Buffer address.
  521.   * @param  Length The length of data to be transferred from memory to peripheral.
  522.   * @retval HAL status
  523.   */
  524. HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
  525. {
  526.   uint32_t tmpsmcr;
  527.  
  528.   /* Check the parameters */
  529.   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
  530.  
  531.   /* Set the TIM state */
  532.   if (htim->State == HAL_TIM_STATE_BUSY)
  533.   {
  534.     return HAL_BUSY;
  535.   }
  536.   else if (htim->State == HAL_TIM_STATE_READY)
  537.   {
  538.     if ((pData == NULL) && (Length > 0U))
  539.     {
  540.       return HAL_ERROR;
  541.     }
  542.     else
  543.     {
  544.       htim->State = HAL_TIM_STATE_BUSY;
  545.     }
  546.   }
  547.   else
  548.   {
  549.     return HAL_ERROR;
  550.   }
  551.  
  552.   /* Set the DMA Period elapsed callbacks */
  553.   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  554.   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  555.  
  556.   /* Set the DMA error callback */
  557.   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  558.  
  559.   /* Enable the DMA channel */
  560.   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
  561.   {
  562.     return HAL_ERROR;
  563.   }
  564.  
  565.   /* Enable the TIM Update DMA request */
  566.   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
  567.  
  568.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  569.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  570.   {
  571.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  572.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  573.     {
  574.       __HAL_TIM_ENABLE(htim);
  575.     }
  576.   }
  577.   else
  578.   {
  579.     __HAL_TIM_ENABLE(htim);
  580.   }
  581.  
  582.   /* Return function status */
  583.   return HAL_OK;
  584. }
  585.  
  586. /**
  587.   * @brief  Stops the TIM Base generation in DMA mode.
  588.   * @param  htim TIM Base handle
  589.   * @retval HAL status
  590.   */
  591. HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
  592. {
  593.   /* Check the parameters */
  594.   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
  595.  
  596.   /* Disable the TIM Update DMA request */
  597.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
  598.  
  599.   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  600.  
  601.   /* Disable the Peripheral */
  602.   __HAL_TIM_DISABLE(htim);
  603.  
  604.   /* Set the TIM state */
  605.   htim->State = HAL_TIM_STATE_READY;
  606.  
  607.   /* Return function status */
  608.   return HAL_OK;
  609. }
  610.  
  611. /**
  612.   * @}
  613.   */
  614.  
  615. /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
  616.   *  @brief    TIM Output Compare functions
  617.   *
  618. @verbatim
  619.   ==============================================================================
  620.                   ##### TIM Output Compare functions #####
  621.   ==============================================================================
  622.   [..]
  623.     This section provides functions allowing to:
  624.     (+) Initialize and configure the TIM Output Compare.
  625.     (+) De-initialize the TIM Output Compare.
  626.     (+) Start the TIM Output Compare.
  627.     (+) Stop the TIM Output Compare.
  628.     (+) Start the TIM Output Compare and enable interrupt.
  629.     (+) Stop the TIM Output Compare and disable interrupt.
  630.     (+) Start the TIM Output Compare and enable DMA transfer.
  631.     (+) Stop the TIM Output Compare and disable DMA transfer.
  632.  
  633. @endverbatim
  634.   * @{
  635.   */
  636. /**
  637.   * @brief  Initializes the TIM Output Compare according to the specified
  638.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  639.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  640.   *         requires a timer reset to avoid unexpected direction
  641.   *         due to DIR bit readonly in center aligned mode.
  642.   *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
  643.   * @param  htim TIM Output Compare handle
  644.   * @retval HAL status
  645.   */
  646. HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
  647. {
  648.   /* Check the TIM handle allocation */
  649.   if (htim == NULL)
  650.   {
  651.     return HAL_ERROR;
  652.   }
  653.  
  654.   /* Check the parameters */
  655.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  656.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  657.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  658.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  659.  
  660.   if (htim->State == HAL_TIM_STATE_RESET)
  661.   {
  662.     /* Allocate lock resource and initialize it */
  663.     htim->Lock = HAL_UNLOCKED;
  664.  
  665. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  666.     /* Reset interrupt callbacks to legacy weak callbacks */
  667.     TIM_ResetCallback(htim);
  668.  
  669.     if (htim->OC_MspInitCallback == NULL)
  670.     {
  671.       htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
  672.     }
  673.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  674.     htim->OC_MspInitCallback(htim);
  675. #else
  676.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  677.     HAL_TIM_OC_MspInit(htim);
  678. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  679.   }
  680.  
  681.   /* Set the TIM state */
  682.   htim->State = HAL_TIM_STATE_BUSY;
  683.  
  684.   /* Init the base time for the Output Compare */
  685.   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
  686.  
  687.   /* Initialize the DMA burst operation state */
  688.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  689.  
  690.   /* Initialize the TIM channels state */
  691.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  692.  
  693.   /* Initialize the TIM state*/
  694.   htim->State = HAL_TIM_STATE_READY;
  695.  
  696.   return HAL_OK;
  697. }
  698.  
  699. /**
  700.   * @brief  DeInitializes the TIM peripheral
  701.   * @param  htim TIM Output Compare handle
  702.   * @retval HAL status
  703.   */
  704. HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
  705. {
  706.   /* Check the parameters */
  707.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  708.  
  709.   htim->State = HAL_TIM_STATE_BUSY;
  710.  
  711.   /* Disable the TIM Peripheral Clock */
  712.   __HAL_TIM_DISABLE(htim);
  713.  
  714. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  715.   if (htim->OC_MspDeInitCallback == NULL)
  716.   {
  717.     htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
  718.   }
  719.   /* DeInit the low level hardware */
  720.   htim->OC_MspDeInitCallback(htim);
  721. #else
  722.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  723.   HAL_TIM_OC_MspDeInit(htim);
  724. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  725.  
  726.   /* Change the DMA burst operation state */
  727.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  728.  
  729.   /* Change the TIM channels state */
  730.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  731.  
  732.   /* Change TIM state */
  733.   htim->State = HAL_TIM_STATE_RESET;
  734.  
  735.   /* Release Lock */
  736.   __HAL_UNLOCK(htim);
  737.  
  738.   return HAL_OK;
  739. }
  740.  
  741. /**
  742.   * @brief  Initializes the TIM Output Compare MSP.
  743.   * @param  htim TIM Output Compare handle
  744.   * @retval None
  745.   */
  746. __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
  747. {
  748.   /* Prevent unused argument(s) compilation warning */
  749.   UNUSED(htim);
  750.  
  751.   /* NOTE : This function should not be modified, when the callback is needed,
  752.             the HAL_TIM_OC_MspInit could be implemented in the user file
  753.    */
  754. }
  755.  
  756. /**
  757.   * @brief  DeInitializes TIM Output Compare MSP.
  758.   * @param  htim TIM Output Compare handle
  759.   * @retval None
  760.   */
  761. __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
  762. {
  763.   /* Prevent unused argument(s) compilation warning */
  764.   UNUSED(htim);
  765.  
  766.   /* NOTE : This function should not be modified, when the callback is needed,
  767.             the HAL_TIM_OC_MspDeInit could be implemented in the user file
  768.    */
  769. }
  770.  
  771. /**
  772.   * @brief  Starts the TIM Output Compare signal generation.
  773.   * @param  htim TIM Output Compare handle
  774.   * @param  Channel TIM Channel to be enabled
  775.   *          This parameter can be one of the following values:
  776.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  777.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  778.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  779.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  780.   * @retval HAL status
  781.   */
  782. HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  783. {
  784.   uint32_t tmpsmcr;
  785.  
  786.   /* Check the parameters */
  787.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  788.  
  789.   /* Check the TIM channel state */
  790.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  791.   {
  792.     return HAL_ERROR;
  793.   }
  794.  
  795.   /* Set the TIM channel state */
  796.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  797.  
  798.   /* Enable the Output compare channel */
  799.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  800.  
  801.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  802.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  803.   {
  804.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  805.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  806.     {
  807.       __HAL_TIM_ENABLE(htim);
  808.     }
  809.   }
  810.   else
  811.   {
  812.     __HAL_TIM_ENABLE(htim);
  813.   }
  814.  
  815.   /* Return function status */
  816.   return HAL_OK;
  817. }
  818.  
  819. /**
  820.   * @brief  Stops the TIM Output Compare signal generation.
  821.   * @param  htim TIM Output Compare handle
  822.   * @param  Channel TIM Channel to be disabled
  823.   *          This parameter can be one of the following values:
  824.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  825.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  826.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  827.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  828.   * @retval HAL status
  829.   */
  830. HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  831. {
  832.   /* Check the parameters */
  833.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  834.  
  835.   /* Disable the Output compare channel */
  836.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  837.  
  838.   /* Disable the Peripheral */
  839.   __HAL_TIM_DISABLE(htim);
  840.  
  841.   /* Set the TIM channel state */
  842.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  843.  
  844.   /* Return function status */
  845.   return HAL_OK;
  846. }
  847.  
  848. /**
  849.   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
  850.   * @param  htim TIM Output Compare handle
  851.   * @param  Channel TIM Channel to be enabled
  852.   *          This parameter can be one of the following values:
  853.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  854.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  855.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  856.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  857.   * @retval HAL status
  858.   */
  859. HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  860. {
  861.   uint32_t tmpsmcr;
  862.  
  863.   /* Check the parameters */
  864.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  865.  
  866.   /* Check the TIM channel state */
  867.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  868.   {
  869.     return HAL_ERROR;
  870.   }
  871.  
  872.   /* Set the TIM channel state */
  873.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  874.  
  875.   switch (Channel)
  876.   {
  877.     case TIM_CHANNEL_1:
  878.     {
  879.       /* Enable the TIM Capture/Compare 1 interrupt */
  880.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  881.       break;
  882.     }
  883.  
  884.     case TIM_CHANNEL_2:
  885.     {
  886.       /* Enable the TIM Capture/Compare 2 interrupt */
  887.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  888.       break;
  889.     }
  890.  
  891.     case TIM_CHANNEL_3:
  892.     {
  893.       /* Enable the TIM Capture/Compare 3 interrupt */
  894.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  895.       break;
  896.     }
  897.  
  898.     case TIM_CHANNEL_4:
  899.     {
  900.       /* Enable the TIM Capture/Compare 4 interrupt */
  901.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  902.       break;
  903.     }
  904.  
  905.     default:
  906.       break;
  907.   }
  908.  
  909.   /* Enable the Output compare channel */
  910.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  911.  
  912.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  913.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  914.   {
  915.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  916.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  917.     {
  918.       __HAL_TIM_ENABLE(htim);
  919.     }
  920.   }
  921.   else
  922.   {
  923.     __HAL_TIM_ENABLE(htim);
  924.   }
  925.  
  926.   /* Return function status */
  927.   return HAL_OK;
  928. }
  929.  
  930. /**
  931.   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
  932.   * @param  htim TIM Output Compare handle
  933.   * @param  Channel TIM Channel to be disabled
  934.   *          This parameter can be one of the following values:
  935.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  936.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  937.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  938.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  939.   * @retval HAL status
  940.   */
  941. HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  942. {
  943.   /* Check the parameters */
  944.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  945.  
  946.   switch (Channel)
  947.   {
  948.     case TIM_CHANNEL_1:
  949.     {
  950.       /* Disable the TIM Capture/Compare 1 interrupt */
  951.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  952.       break;
  953.     }
  954.  
  955.     case TIM_CHANNEL_2:
  956.     {
  957.       /* Disable the TIM Capture/Compare 2 interrupt */
  958.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  959.       break;
  960.     }
  961.  
  962.     case TIM_CHANNEL_3:
  963.     {
  964.       /* Disable the TIM Capture/Compare 3 interrupt */
  965.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  966.       break;
  967.     }
  968.  
  969.     case TIM_CHANNEL_4:
  970.     {
  971.       /* Disable the TIM Capture/Compare 4 interrupt */
  972.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  973.       break;
  974.     }
  975.  
  976.     default:
  977.       break;
  978.   }
  979.  
  980.   /* Disable the Output compare channel */
  981.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  982.  
  983.   /* Disable the Peripheral */
  984.   __HAL_TIM_DISABLE(htim);
  985.  
  986.   /* Set the TIM channel state */
  987.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  988.  
  989.   /* Return function status */
  990.   return HAL_OK;
  991. }
  992.  
  993. /**
  994.   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
  995.   * @param  htim TIM Output Compare handle
  996.   * @param  Channel TIM Channel to be enabled
  997.   *          This parameter can be one of the following values:
  998.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  999.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1000.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1001.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1002.   * @param  pData The source Buffer address.
  1003.   * @param  Length The length of data to be transferred from memory to TIM peripheral
  1004.   * @retval HAL status
  1005.   */
  1006. HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
  1007. {
  1008.   uint32_t tmpsmcr;
  1009.  
  1010.   /* Check the parameters */
  1011.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1012.  
  1013.   /* Set the TIM channel state */
  1014.   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
  1015.   {
  1016.     return HAL_BUSY;
  1017.   }
  1018.   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
  1019.   {
  1020.     if ((pData == NULL) && (Length > 0U))
  1021.     {
  1022.       return HAL_ERROR;
  1023.     }
  1024.     else
  1025.     {
  1026.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1027.     }
  1028.   }
  1029.   else
  1030.   {
  1031.     return HAL_ERROR;
  1032.   }
  1033.  
  1034.   switch (Channel)
  1035.   {
  1036.     case TIM_CHANNEL_1:
  1037.     {
  1038.       /* Set the DMA compare callbacks */
  1039.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1040.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1041.  
  1042.       /* Set the DMA error callback */
  1043.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  1044.  
  1045.       /* Enable the DMA channel */
  1046.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
  1047.       {
  1048.         return HAL_ERROR;
  1049.       }
  1050.  
  1051.       /* Enable the TIM Capture/Compare 1 DMA request */
  1052.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  1053.       break;
  1054.     }
  1055.  
  1056.     case TIM_CHANNEL_2:
  1057.     {
  1058.       /* Set the DMA compare callbacks */
  1059.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1060.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1061.  
  1062.       /* Set the DMA error callback */
  1063.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  1064.  
  1065.       /* Enable the DMA channel */
  1066.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
  1067.       {
  1068.         return HAL_ERROR;
  1069.       }
  1070.  
  1071.       /* Enable the TIM Capture/Compare 2 DMA request */
  1072.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  1073.       break;
  1074.     }
  1075.  
  1076.     case TIM_CHANNEL_3:
  1077.     {
  1078.       /* Set the DMA compare callbacks */
  1079.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1080.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1081.  
  1082.       /* Set the DMA error callback */
  1083.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  1084.  
  1085.       /* Enable the DMA channel */
  1086.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
  1087.       {
  1088.         return HAL_ERROR;
  1089.       }
  1090.       /* Enable the TIM Capture/Compare 3 DMA request */
  1091.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  1092.       break;
  1093.     }
  1094.  
  1095.     case TIM_CHANNEL_4:
  1096.     {
  1097.       /* Set the DMA compare callbacks */
  1098.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1099.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1100.  
  1101.       /* Set the DMA error callback */
  1102.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  1103.  
  1104.       /* Enable the DMA channel */
  1105.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
  1106.       {
  1107.         return HAL_ERROR;
  1108.       }
  1109.       /* Enable the TIM Capture/Compare 4 DMA request */
  1110.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  1111.       break;
  1112.     }
  1113.  
  1114.     default:
  1115.       break;
  1116.   }
  1117.  
  1118.   /* Enable the Output compare channel */
  1119.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1120.  
  1121.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1122.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1123.   {
  1124.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1125.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1126.     {
  1127.       __HAL_TIM_ENABLE(htim);
  1128.     }
  1129.   }
  1130.   else
  1131.   {
  1132.     __HAL_TIM_ENABLE(htim);
  1133.   }
  1134.  
  1135.   /* Return function status */
  1136.   return HAL_OK;
  1137. }
  1138.  
  1139. /**
  1140.   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
  1141.   * @param  htim TIM Output Compare handle
  1142.   * @param  Channel TIM Channel to be disabled
  1143.   *          This parameter can be one of the following values:
  1144.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1145.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1146.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1147.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1148.   * @retval HAL status
  1149.   */
  1150. HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  1151. {
  1152.   /* Check the parameters */
  1153.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1154.  
  1155.   switch (Channel)
  1156.   {
  1157.     case TIM_CHANNEL_1:
  1158.     {
  1159.       /* Disable the TIM Capture/Compare 1 DMA request */
  1160.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  1161.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  1162.       break;
  1163.     }
  1164.  
  1165.     case TIM_CHANNEL_2:
  1166.     {
  1167.       /* Disable the TIM Capture/Compare 2 DMA request */
  1168.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  1169.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  1170.       break;
  1171.     }
  1172.  
  1173.     case TIM_CHANNEL_3:
  1174.     {
  1175.       /* Disable the TIM Capture/Compare 3 DMA request */
  1176.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  1177.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  1178.       break;
  1179.     }
  1180.  
  1181.     case TIM_CHANNEL_4:
  1182.     {
  1183.       /* Disable the TIM Capture/Compare 4 interrupt */
  1184.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  1185.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  1186.       break;
  1187.     }
  1188.  
  1189.     default:
  1190.       break;
  1191.   }
  1192.  
  1193.   /* Disable the Output compare channel */
  1194.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1195.  
  1196.   /* Disable the Peripheral */
  1197.   __HAL_TIM_DISABLE(htim);
  1198.  
  1199.   /* Set the TIM channel state */
  1200.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1201.  
  1202.   /* Return function status */
  1203.   return HAL_OK;
  1204. }
  1205.  
  1206. /**
  1207.   * @}
  1208.   */
  1209.  
  1210. /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
  1211.   *  @brief    TIM PWM functions
  1212.   *
  1213. @verbatim
  1214.   ==============================================================================
  1215.                           ##### TIM PWM functions #####
  1216.   ==============================================================================
  1217.   [..]
  1218.     This section provides functions allowing to:
  1219.     (+) Initialize and configure the TIM PWM.
  1220.     (+) De-initialize the TIM PWM.
  1221.     (+) Start the TIM PWM.
  1222.     (+) Stop the TIM PWM.
  1223.     (+) Start the TIM PWM and enable interrupt.
  1224.     (+) Stop the TIM PWM and disable interrupt.
  1225.     (+) Start the TIM PWM and enable DMA transfer.
  1226.     (+) Stop the TIM PWM and disable DMA transfer.
  1227.  
  1228. @endverbatim
  1229.   * @{
  1230.   */
  1231. /**
  1232.   * @brief  Initializes the TIM PWM Time Base according to the specified
  1233.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  1234.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  1235.   *         requires a timer reset to avoid unexpected direction
  1236.   *         due to DIR bit readonly in center aligned mode.
  1237.   *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
  1238.   * @param  htim TIM PWM handle
  1239.   * @retval HAL status
  1240.   */
  1241. HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
  1242. {
  1243.   /* Check the TIM handle allocation */
  1244.   if (htim == NULL)
  1245.   {
  1246.     return HAL_ERROR;
  1247.   }
  1248.  
  1249.   /* Check the parameters */
  1250.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1251.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  1252.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  1253.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  1254.  
  1255.   if (htim->State == HAL_TIM_STATE_RESET)
  1256.   {
  1257.     /* Allocate lock resource and initialize it */
  1258.     htim->Lock = HAL_UNLOCKED;
  1259.  
  1260. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1261.     /* Reset interrupt callbacks to legacy weak callbacks */
  1262.     TIM_ResetCallback(htim);
  1263.  
  1264.     if (htim->PWM_MspInitCallback == NULL)
  1265.     {
  1266.       htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
  1267.     }
  1268.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  1269.     htim->PWM_MspInitCallback(htim);
  1270. #else
  1271.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  1272.     HAL_TIM_PWM_MspInit(htim);
  1273. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1274.   }
  1275.  
  1276.   /* Set the TIM state */
  1277.   htim->State = HAL_TIM_STATE_BUSY;
  1278.  
  1279.   /* Init the base time for the PWM */
  1280.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  1281.  
  1282.   /* Initialize the DMA burst operation state */
  1283.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  1284.  
  1285.   /* Initialize the TIM channels state */
  1286.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  1287.  
  1288.   /* Initialize the TIM state*/
  1289.   htim->State = HAL_TIM_STATE_READY;
  1290.  
  1291.   return HAL_OK;
  1292. }
  1293.  
  1294. /**
  1295.   * @brief  DeInitializes the TIM peripheral
  1296.   * @param  htim TIM PWM handle
  1297.   * @retval HAL status
  1298.   */
  1299. HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
  1300. {
  1301.   /* Check the parameters */
  1302.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1303.  
  1304.   htim->State = HAL_TIM_STATE_BUSY;
  1305.  
  1306.   /* Disable the TIM Peripheral Clock */
  1307.   __HAL_TIM_DISABLE(htim);
  1308.  
  1309. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1310.   if (htim->PWM_MspDeInitCallback == NULL)
  1311.   {
  1312.     htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
  1313.   }
  1314.   /* DeInit the low level hardware */
  1315.   htim->PWM_MspDeInitCallback(htim);
  1316. #else
  1317.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  1318.   HAL_TIM_PWM_MspDeInit(htim);
  1319. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1320.  
  1321.   /* Change the DMA burst operation state */
  1322.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  1323.  
  1324.   /* Change the TIM channels state */
  1325.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  1326.  
  1327.   /* Change TIM state */
  1328.   htim->State = HAL_TIM_STATE_RESET;
  1329.  
  1330.   /* Release Lock */
  1331.   __HAL_UNLOCK(htim);
  1332.  
  1333.   return HAL_OK;
  1334. }
  1335.  
  1336. /**
  1337.   * @brief  Initializes the TIM PWM MSP.
  1338.   * @param  htim TIM PWM handle
  1339.   * @retval None
  1340.   */
  1341. __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
  1342. {
  1343.   /* Prevent unused argument(s) compilation warning */
  1344.   UNUSED(htim);
  1345.  
  1346.   /* NOTE : This function should not be modified, when the callback is needed,
  1347.             the HAL_TIM_PWM_MspInit could be implemented in the user file
  1348.    */
  1349. }
  1350.  
  1351. /**
  1352.   * @brief  DeInitializes TIM PWM MSP.
  1353.   * @param  htim TIM PWM handle
  1354.   * @retval None
  1355.   */
  1356. __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
  1357. {
  1358.   /* Prevent unused argument(s) compilation warning */
  1359.   UNUSED(htim);
  1360.  
  1361.   /* NOTE : This function should not be modified, when the callback is needed,
  1362.             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
  1363.    */
  1364. }
  1365.  
  1366. /**
  1367.   * @brief  Starts the PWM signal generation.
  1368.   * @param  htim TIM handle
  1369.   * @param  Channel TIM Channels to be enabled
  1370.   *          This parameter can be one of the following values:
  1371.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1372.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1373.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1374.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1375.   * @retval HAL status
  1376.   */
  1377. HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  1378. {
  1379.   uint32_t tmpsmcr;
  1380.  
  1381.   /* Check the parameters */
  1382.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1383.  
  1384.   /* Check the TIM channel state */
  1385.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  1386.   {
  1387.     return HAL_ERROR;
  1388.   }
  1389.  
  1390.   /* Set the TIM channel state */
  1391.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1392.  
  1393.   /* Enable the Capture compare channel */
  1394.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1395.  
  1396.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1397.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1398.   {
  1399.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1400.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1401.     {
  1402.       __HAL_TIM_ENABLE(htim);
  1403.     }
  1404.   }
  1405.   else
  1406.   {
  1407.     __HAL_TIM_ENABLE(htim);
  1408.   }
  1409.  
  1410.   /* Return function status */
  1411.   return HAL_OK;
  1412. }
  1413.  
  1414. /**
  1415.   * @brief  Stops the PWM signal generation.
  1416.   * @param  htim TIM PWM handle
  1417.   * @param  Channel TIM Channels to be disabled
  1418.   *          This parameter can be one of the following values:
  1419.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1420.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1421.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1422.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1423.   * @retval HAL status
  1424.   */
  1425. HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  1426. {
  1427.   /* Check the parameters */
  1428.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1429.  
  1430.   /* Disable the Capture compare channel */
  1431.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1432.  
  1433.   /* Disable the Peripheral */
  1434.   __HAL_TIM_DISABLE(htim);
  1435.  
  1436.   /* Set the TIM channel state */
  1437.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1438.  
  1439.   /* Return function status */
  1440.   return HAL_OK;
  1441. }
  1442.  
  1443. /**
  1444.   * @brief  Starts the PWM signal generation in interrupt mode.
  1445.   * @param  htim TIM PWM handle
  1446.   * @param  Channel TIM Channel to be enabled
  1447.   *          This parameter can be one of the following values:
  1448.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1449.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1450.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1451.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1452.   * @retval HAL status
  1453.   */
  1454. HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  1455. {
  1456.   uint32_t tmpsmcr;
  1457.   /* Check the parameters */
  1458.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1459.  
  1460.   /* Check the TIM channel state */
  1461.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  1462.   {
  1463.     return HAL_ERROR;
  1464.   }
  1465.  
  1466.   /* Set the TIM channel state */
  1467.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1468.  
  1469.   switch (Channel)
  1470.   {
  1471.     case TIM_CHANNEL_1:
  1472.     {
  1473.       /* Enable the TIM Capture/Compare 1 interrupt */
  1474.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  1475.       break;
  1476.     }
  1477.  
  1478.     case TIM_CHANNEL_2:
  1479.     {
  1480.       /* Enable the TIM Capture/Compare 2 interrupt */
  1481.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  1482.       break;
  1483.     }
  1484.  
  1485.     case TIM_CHANNEL_3:
  1486.     {
  1487.       /* Enable the TIM Capture/Compare 3 interrupt */
  1488.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  1489.       break;
  1490.     }
  1491.  
  1492.     case TIM_CHANNEL_4:
  1493.     {
  1494.       /* Enable the TIM Capture/Compare 4 interrupt */
  1495.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  1496.       break;
  1497.     }
  1498.  
  1499.     default:
  1500.       break;
  1501.   }
  1502.  
  1503.   /* Enable the Capture compare channel */
  1504.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1505.  
  1506.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1507.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1508.   {
  1509.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1510.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1511.     {
  1512.       __HAL_TIM_ENABLE(htim);
  1513.     }
  1514.   }
  1515.   else
  1516.   {
  1517.     __HAL_TIM_ENABLE(htim);
  1518.   }
  1519.  
  1520.   /* Return function status */
  1521.   return HAL_OK;
  1522. }
  1523.  
  1524. /**
  1525.   * @brief  Stops the PWM signal generation in interrupt mode.
  1526.   * @param  htim TIM PWM handle
  1527.   * @param  Channel TIM Channels to be disabled
  1528.   *          This parameter can be one of the following values:
  1529.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1530.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1531.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1532.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1533.   * @retval HAL status
  1534.   */
  1535. HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  1536. {
  1537.   /* Check the parameters */
  1538.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1539.  
  1540.   switch (Channel)
  1541.   {
  1542.     case TIM_CHANNEL_1:
  1543.     {
  1544.       /* Disable the TIM Capture/Compare 1 interrupt */
  1545.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  1546.       break;
  1547.     }
  1548.  
  1549.     case TIM_CHANNEL_2:
  1550.     {
  1551.       /* Disable the TIM Capture/Compare 2 interrupt */
  1552.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  1553.       break;
  1554.     }
  1555.  
  1556.     case TIM_CHANNEL_3:
  1557.     {
  1558.       /* Disable the TIM Capture/Compare 3 interrupt */
  1559.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  1560.       break;
  1561.     }
  1562.  
  1563.     case TIM_CHANNEL_4:
  1564.     {
  1565.       /* Disable the TIM Capture/Compare 4 interrupt */
  1566.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  1567.       break;
  1568.     }
  1569.  
  1570.     default:
  1571.       break;
  1572.   }
  1573.  
  1574.   /* Disable the Capture compare channel */
  1575.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1576.  
  1577.   /* Disable the Peripheral */
  1578.   __HAL_TIM_DISABLE(htim);
  1579.  
  1580.   /* Set the TIM channel state */
  1581.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1582.  
  1583.   /* Return function status */
  1584.   return HAL_OK;
  1585. }
  1586.  
  1587. /**
  1588.   * @brief  Starts the TIM PWM signal generation in DMA mode.
  1589.   * @param  htim TIM PWM handle
  1590.   * @param  Channel TIM Channels to be enabled
  1591.   *          This parameter can be one of the following values:
  1592.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1593.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1594.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1595.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1596.   * @param  pData The source Buffer address.
  1597.   * @param  Length The length of data to be transferred from memory to TIM peripheral
  1598.   * @retval HAL status
  1599.   */
  1600. HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
  1601. {
  1602.   uint32_t tmpsmcr;
  1603.  
  1604.   /* Check the parameters */
  1605.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1606.  
  1607.   /* Set the TIM channel state */
  1608.   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
  1609.   {
  1610.     return HAL_BUSY;
  1611.   }
  1612.   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
  1613.   {
  1614.     if ((pData == NULL) && (Length > 0U))
  1615.     {
  1616.       return HAL_ERROR;
  1617.     }
  1618.     else
  1619.     {
  1620.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1621.     }
  1622.   }
  1623.   else
  1624.   {
  1625.     return HAL_ERROR;
  1626.   }
  1627.  
  1628.   switch (Channel)
  1629.   {
  1630.     case TIM_CHANNEL_1:
  1631.     {
  1632.       /* Set the DMA compare callbacks */
  1633.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1634.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1635.  
  1636.       /* Set the DMA error callback */
  1637.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  1638.  
  1639.       /* Enable the DMA channel */
  1640.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
  1641.       {
  1642.         return HAL_ERROR;
  1643.       }
  1644.  
  1645.       /* Enable the TIM Capture/Compare 1 DMA request */
  1646.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  1647.       break;
  1648.     }
  1649.  
  1650.     case TIM_CHANNEL_2:
  1651.     {
  1652.       /* Set the DMA compare callbacks */
  1653.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1654.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1655.  
  1656.       /* Set the DMA error callback */
  1657.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  1658.  
  1659.       /* Enable the DMA channel */
  1660.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
  1661.       {
  1662.         return HAL_ERROR;
  1663.       }
  1664.       /* Enable the TIM Capture/Compare 2 DMA request */
  1665.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  1666.       break;
  1667.     }
  1668.  
  1669.     case TIM_CHANNEL_3:
  1670.     {
  1671.       /* Set the DMA compare callbacks */
  1672.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1673.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1674.  
  1675.       /* Set the DMA error callback */
  1676.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  1677.  
  1678.       /* Enable the DMA channel */
  1679.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
  1680.       {
  1681.         return HAL_ERROR;
  1682.       }
  1683.       /* Enable the TIM Output Capture/Compare 3 request */
  1684.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  1685.       break;
  1686.     }
  1687.  
  1688.     case TIM_CHANNEL_4:
  1689.     {
  1690.       /* Set the DMA compare callbacks */
  1691.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1692.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1693.  
  1694.       /* Set the DMA error callback */
  1695.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  1696.  
  1697.       /* Enable the DMA channel */
  1698.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
  1699.       {
  1700.         return HAL_ERROR;
  1701.       }
  1702.       /* Enable the TIM Capture/Compare 4 DMA request */
  1703.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  1704.       break;
  1705.     }
  1706.  
  1707.     default:
  1708.       break;
  1709.   }
  1710.  
  1711.   /* Enable the Capture compare channel */
  1712.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1713.  
  1714.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1715.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1716.   {
  1717.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1718.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1719.     {
  1720.       __HAL_TIM_ENABLE(htim);
  1721.     }
  1722.   }
  1723.   else
  1724.   {
  1725.     __HAL_TIM_ENABLE(htim);
  1726.   }
  1727.  
  1728.   /* Return function status */
  1729.   return HAL_OK;
  1730. }
  1731.  
  1732. /**
  1733.   * @brief  Stops the TIM PWM signal generation in DMA mode.
  1734.   * @param  htim TIM PWM handle
  1735.   * @param  Channel TIM Channels to be disabled
  1736.   *          This parameter can be one of the following values:
  1737.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1738.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1739.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1740.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1741.   * @retval HAL status
  1742.   */
  1743. HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  1744. {
  1745.   /* Check the parameters */
  1746.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1747.  
  1748.   switch (Channel)
  1749.   {
  1750.     case TIM_CHANNEL_1:
  1751.     {
  1752.       /* Disable the TIM Capture/Compare 1 DMA request */
  1753.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  1754.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  1755.       break;
  1756.     }
  1757.  
  1758.     case TIM_CHANNEL_2:
  1759.     {
  1760.       /* Disable the TIM Capture/Compare 2 DMA request */
  1761.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  1762.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  1763.       break;
  1764.     }
  1765.  
  1766.     case TIM_CHANNEL_3:
  1767.     {
  1768.       /* Disable the TIM Capture/Compare 3 DMA request */
  1769.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  1770.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  1771.       break;
  1772.     }
  1773.  
  1774.     case TIM_CHANNEL_4:
  1775.     {
  1776.       /* Disable the TIM Capture/Compare 4 interrupt */
  1777.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  1778.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  1779.       break;
  1780.     }
  1781.  
  1782.     default:
  1783.       break;
  1784.   }
  1785.  
  1786.   /* Disable the Capture compare channel */
  1787.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1788.  
  1789.   /* Disable the Peripheral */
  1790.   __HAL_TIM_DISABLE(htim);
  1791.  
  1792.   /* Set the TIM channel state */
  1793.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1794.  
  1795.   /* Return function status */
  1796.   return HAL_OK;
  1797. }
  1798.  
  1799. /**
  1800.   * @}
  1801.   */
  1802.  
  1803. /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
  1804.   *  @brief    TIM Input Capture functions
  1805.   *
  1806. @verbatim
  1807.   ==============================================================================
  1808.               ##### TIM Input Capture functions #####
  1809.   ==============================================================================
  1810.  [..]
  1811.    This section provides functions allowing to:
  1812.    (+) Initialize and configure the TIM Input Capture.
  1813.    (+) De-initialize the TIM Input Capture.
  1814.    (+) Start the TIM Input Capture.
  1815.    (+) Stop the TIM Input Capture.
  1816.    (+) Start the TIM Input Capture and enable interrupt.
  1817.    (+) Stop the TIM Input Capture and disable interrupt.
  1818.    (+) Start the TIM Input Capture and enable DMA transfer.
  1819.    (+) Stop the TIM Input Capture and disable DMA transfer.
  1820.  
  1821. @endverbatim
  1822.   * @{
  1823.   */
  1824. /**
  1825.   * @brief  Initializes the TIM Input Capture Time base according to the specified
  1826.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  1827.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  1828.   *         requires a timer reset to avoid unexpected direction
  1829.   *         due to DIR bit readonly in center aligned mode.
  1830.   *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
  1831.   * @param  htim TIM Input Capture handle
  1832.   * @retval HAL status
  1833.   */
  1834. HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
  1835. {
  1836.   /* Check the TIM handle allocation */
  1837.   if (htim == NULL)
  1838.   {
  1839.     return HAL_ERROR;
  1840.   }
  1841.  
  1842.   /* Check the parameters */
  1843.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1844.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  1845.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  1846.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  1847.  
  1848.   if (htim->State == HAL_TIM_STATE_RESET)
  1849.   {
  1850.     /* Allocate lock resource and initialize it */
  1851.     htim->Lock = HAL_UNLOCKED;
  1852.  
  1853. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1854.     /* Reset interrupt callbacks to legacy weak callbacks */
  1855.     TIM_ResetCallback(htim);
  1856.  
  1857.     if (htim->IC_MspInitCallback == NULL)
  1858.     {
  1859.       htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
  1860.     }
  1861.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  1862.     htim->IC_MspInitCallback(htim);
  1863. #else
  1864.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  1865.     HAL_TIM_IC_MspInit(htim);
  1866. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1867.   }
  1868.  
  1869.   /* Set the TIM state */
  1870.   htim->State = HAL_TIM_STATE_BUSY;
  1871.  
  1872.   /* Init the base time for the input capture */
  1873.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  1874.  
  1875.   /* Initialize the DMA burst operation state */
  1876.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  1877.  
  1878.   /* Initialize the TIM channels state */
  1879.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  1880.  
  1881.   /* Initialize the TIM state*/
  1882.   htim->State = HAL_TIM_STATE_READY;
  1883.  
  1884.   return HAL_OK;
  1885. }
  1886.  
  1887. /**
  1888.   * @brief  DeInitializes the TIM peripheral
  1889.   * @param  htim TIM Input Capture handle
  1890.   * @retval HAL status
  1891.   */
  1892. HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
  1893. {
  1894.   /* Check the parameters */
  1895.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1896.  
  1897.   htim->State = HAL_TIM_STATE_BUSY;
  1898.  
  1899.   /* Disable the TIM Peripheral Clock */
  1900.   __HAL_TIM_DISABLE(htim);
  1901.  
  1902. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1903.   if (htim->IC_MspDeInitCallback == NULL)
  1904.   {
  1905.     htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
  1906.   }
  1907.   /* DeInit the low level hardware */
  1908.   htim->IC_MspDeInitCallback(htim);
  1909. #else
  1910.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  1911.   HAL_TIM_IC_MspDeInit(htim);
  1912. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1913.  
  1914.   /* Change the DMA burst operation state */
  1915.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  1916.  
  1917.   /* Change the TIM channels state */
  1918.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  1919.  
  1920.   /* Change TIM state */
  1921.   htim->State = HAL_TIM_STATE_RESET;
  1922.  
  1923.   /* Release Lock */
  1924.   __HAL_UNLOCK(htim);
  1925.  
  1926.   return HAL_OK;
  1927. }
  1928.  
  1929. /**
  1930.   * @brief  Initializes the TIM Input Capture MSP.
  1931.   * @param  htim TIM Input Capture handle
  1932.   * @retval None
  1933.   */
  1934. __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
  1935. {
  1936.   /* Prevent unused argument(s) compilation warning */
  1937.   UNUSED(htim);
  1938.  
  1939.   /* NOTE : This function should not be modified, when the callback is needed,
  1940.             the HAL_TIM_IC_MspInit could be implemented in the user file
  1941.    */
  1942. }
  1943.  
  1944. /**
  1945.   * @brief  DeInitializes TIM Input Capture MSP.
  1946.   * @param  htim TIM handle
  1947.   * @retval None
  1948.   */
  1949. __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
  1950. {
  1951.   /* Prevent unused argument(s) compilation warning */
  1952.   UNUSED(htim);
  1953.  
  1954.   /* NOTE : This function should not be modified, when the callback is needed,
  1955.             the HAL_TIM_IC_MspDeInit could be implemented in the user file
  1956.    */
  1957. }
  1958.  
  1959. /**
  1960.   * @brief  Starts the TIM Input Capture measurement.
  1961.   * @param  htim TIM Input Capture handle
  1962.   * @param  Channel TIM Channels to be enabled
  1963.   *          This parameter can be one of the following values:
  1964.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1965.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1966.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1967.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1968.   * @retval HAL status
  1969.   */
  1970. HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  1971. {
  1972.   uint32_t tmpsmcr;
  1973.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  1974.  
  1975.   /* Check the parameters */
  1976.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1977.  
  1978.   /* Check the TIM channel state */
  1979.   if (channel_state != HAL_TIM_CHANNEL_STATE_READY)
  1980.   {
  1981.     return HAL_ERROR;
  1982.   }
  1983.  
  1984.   /* Set the TIM channel state */
  1985.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1986.  
  1987.   /* Enable the Input Capture channel */
  1988.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1989.  
  1990.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1991.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1992.   {
  1993.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1994.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1995.     {
  1996.       __HAL_TIM_ENABLE(htim);
  1997.     }
  1998.   }
  1999.   else
  2000.   {
  2001.     __HAL_TIM_ENABLE(htim);
  2002.   }
  2003.  
  2004.   /* Return function status */
  2005.   return HAL_OK;
  2006. }
  2007.  
  2008. /**
  2009.   * @brief  Stops the TIM Input Capture measurement.
  2010.   * @param  htim TIM Input Capture handle
  2011.   * @param  Channel TIM Channels to be disabled
  2012.   *          This parameter can be one of the following values:
  2013.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2014.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2015.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2016.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2017.   * @retval HAL status
  2018.   */
  2019. HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  2020. {
  2021.   /* Check the parameters */
  2022.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2023.  
  2024.   /* Disable the Input Capture channel */
  2025.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2026.  
  2027.   /* Disable the Peripheral */
  2028.   __HAL_TIM_DISABLE(htim);
  2029.  
  2030.   /* Set the TIM channel state */
  2031.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2032.  
  2033.   /* Return function status */
  2034.   return HAL_OK;
  2035. }
  2036.  
  2037. /**
  2038.   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
  2039.   * @param  htim TIM Input Capture handle
  2040.   * @param  Channel TIM Channels to be enabled
  2041.   *          This parameter can be one of the following values:
  2042.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2043.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2044.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2045.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2046.   * @retval HAL status
  2047.   */
  2048. HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  2049. {
  2050.   uint32_t tmpsmcr;
  2051.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  2052.  
  2053.   /* Check the parameters */
  2054.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2055.  
  2056.   /* Check the TIM channel state */
  2057.   if (channel_state != HAL_TIM_CHANNEL_STATE_READY)
  2058.   {
  2059.     return HAL_ERROR;
  2060.   }
  2061.  
  2062.   /* Set the TIM channel state */
  2063.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2064.  
  2065.   switch (Channel)
  2066.   {
  2067.     case TIM_CHANNEL_1:
  2068.     {
  2069.       /* Enable the TIM Capture/Compare 1 interrupt */
  2070.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  2071.       break;
  2072.     }
  2073.  
  2074.     case TIM_CHANNEL_2:
  2075.     {
  2076.       /* Enable the TIM Capture/Compare 2 interrupt */
  2077.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  2078.       break;
  2079.     }
  2080.  
  2081.     case TIM_CHANNEL_3:
  2082.     {
  2083.       /* Enable the TIM Capture/Compare 3 interrupt */
  2084.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  2085.       break;
  2086.     }
  2087.  
  2088.     case TIM_CHANNEL_4:
  2089.     {
  2090.       /* Enable the TIM Capture/Compare 4 interrupt */
  2091.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  2092.       break;
  2093.     }
  2094.  
  2095.     default:
  2096.       break;
  2097.   }
  2098.   /* Enable the Input Capture channel */
  2099.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  2100.  
  2101.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  2102.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  2103.   {
  2104.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  2105.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  2106.     {
  2107.       __HAL_TIM_ENABLE(htim);
  2108.     }
  2109.   }
  2110.   else
  2111.   {
  2112.     __HAL_TIM_ENABLE(htim);
  2113.   }
  2114.  
  2115.   /* Return function status */
  2116.   return HAL_OK;
  2117. }
  2118.  
  2119. /**
  2120.   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
  2121.   * @param  htim TIM Input Capture handle
  2122.   * @param  Channel TIM Channels to be disabled
  2123.   *          This parameter can be one of the following values:
  2124.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2125.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2126.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2127.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2128.   * @retval HAL status
  2129.   */
  2130. HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  2131. {
  2132.   /* Check the parameters */
  2133.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2134.  
  2135.   switch (Channel)
  2136.   {
  2137.     case TIM_CHANNEL_1:
  2138.     {
  2139.       /* Disable the TIM Capture/Compare 1 interrupt */
  2140.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  2141.       break;
  2142.     }
  2143.  
  2144.     case TIM_CHANNEL_2:
  2145.     {
  2146.       /* Disable the TIM Capture/Compare 2 interrupt */
  2147.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  2148.       break;
  2149.     }
  2150.  
  2151.     case TIM_CHANNEL_3:
  2152.     {
  2153.       /* Disable the TIM Capture/Compare 3 interrupt */
  2154.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  2155.       break;
  2156.     }
  2157.  
  2158.     case TIM_CHANNEL_4:
  2159.     {
  2160.       /* Disable the TIM Capture/Compare 4 interrupt */
  2161.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  2162.       break;
  2163.     }
  2164.  
  2165.     default:
  2166.       break;
  2167.   }
  2168.  
  2169.   /* Disable the Input Capture channel */
  2170.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2171.  
  2172.   /* Disable the Peripheral */
  2173.   __HAL_TIM_DISABLE(htim);
  2174.  
  2175.   /* Set the TIM channel state */
  2176.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2177.  
  2178.   /* Return function status */
  2179.   return HAL_OK;
  2180. }
  2181.  
  2182. /**
  2183.   * @brief  Starts the TIM Input Capture measurement in DMA mode.
  2184.   * @param  htim TIM Input Capture handle
  2185.   * @param  Channel TIM Channels to be enabled
  2186.   *          This parameter can be one of the following values:
  2187.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2188.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2189.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2190.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2191.   * @param  pData The destination Buffer address.
  2192.   * @param  Length The length of data to be transferred from TIM peripheral to memory.
  2193.   * @retval HAL status
  2194.   */
  2195. HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
  2196. {
  2197.   uint32_t tmpsmcr;
  2198.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  2199.  
  2200.   /* Check the parameters */
  2201.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2202.   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
  2203.  
  2204.   /* Set the TIM channel state */
  2205.   if (channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
  2206.   {
  2207.     return HAL_BUSY;
  2208.   }
  2209.   if (channel_state == HAL_TIM_CHANNEL_STATE_READY)
  2210.   {
  2211.     if ((pData == NULL) && (Length > 0U))
  2212.     {
  2213.       return HAL_ERROR;
  2214.     }
  2215.     else
  2216.     {
  2217.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2218.     }
  2219.   }
  2220.   else
  2221.   {
  2222.     return HAL_ERROR;
  2223.   }
  2224.  
  2225.   switch (Channel)
  2226.   {
  2227.     case TIM_CHANNEL_1:
  2228.     {
  2229.       /* Set the DMA capture callbacks */
  2230.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  2231.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2232.  
  2233.       /* Set the DMA error callback */
  2234.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  2235.  
  2236.       /* Enable the DMA channel */
  2237.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
  2238.       {
  2239.         return HAL_ERROR;
  2240.       }
  2241.       /* Enable the TIM Capture/Compare 1 DMA request */
  2242.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  2243.       break;
  2244.     }
  2245.  
  2246.     case TIM_CHANNEL_2:
  2247.     {
  2248.       /* Set the DMA capture callbacks */
  2249.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  2250.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2251.  
  2252.       /* Set the DMA error callback */
  2253.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  2254.  
  2255.       /* Enable the DMA channel */
  2256.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
  2257.       {
  2258.         return HAL_ERROR;
  2259.       }
  2260.       /* Enable the TIM Capture/Compare 2  DMA request */
  2261.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  2262.       break;
  2263.     }
  2264.  
  2265.     case TIM_CHANNEL_3:
  2266.     {
  2267.       /* Set the DMA capture callbacks */
  2268.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
  2269.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2270.  
  2271.       /* Set the DMA error callback */
  2272.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  2273.  
  2274.       /* Enable the DMA channel */
  2275.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
  2276.       {
  2277.         return HAL_ERROR;
  2278.       }
  2279.       /* Enable the TIM Capture/Compare 3  DMA request */
  2280.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  2281.       break;
  2282.     }
  2283.  
  2284.     case TIM_CHANNEL_4:
  2285.     {
  2286.       /* Set the DMA capture callbacks */
  2287.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
  2288.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2289.  
  2290.       /* Set the DMA error callback */
  2291.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  2292.  
  2293.       /* Enable the DMA channel */
  2294.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
  2295.       {
  2296.         return HAL_ERROR;
  2297.       }
  2298.       /* Enable the TIM Capture/Compare 4  DMA request */
  2299.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  2300.       break;
  2301.     }
  2302.  
  2303.     default:
  2304.       break;
  2305.   }
  2306.  
  2307.   /* Enable the Input Capture channel */
  2308.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  2309.  
  2310.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  2311.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  2312.   {
  2313.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  2314.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  2315.     {
  2316.       __HAL_TIM_ENABLE(htim);
  2317.     }
  2318.   }
  2319.   else
  2320.   {
  2321.     __HAL_TIM_ENABLE(htim);
  2322.   }
  2323.  
  2324.   /* Return function status */
  2325.   return HAL_OK;
  2326. }
  2327.  
  2328. /**
  2329.   * @brief  Stops the TIM Input Capture measurement in DMA mode.
  2330.   * @param  htim TIM Input Capture handle
  2331.   * @param  Channel TIM Channels to be disabled
  2332.   *          This parameter can be one of the following values:
  2333.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2334.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2335.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2336.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2337.   * @retval HAL status
  2338.   */
  2339. HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  2340. {
  2341.   /* Check the parameters */
  2342.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2343.   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
  2344.  
  2345.   /* Disable the Input Capture channel */
  2346.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2347.  
  2348.   switch (Channel)
  2349.   {
  2350.     case TIM_CHANNEL_1:
  2351.     {
  2352.       /* Disable the TIM Capture/Compare 1 DMA request */
  2353.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  2354.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  2355.       break;
  2356.     }
  2357.  
  2358.     case TIM_CHANNEL_2:
  2359.     {
  2360.       /* Disable the TIM Capture/Compare 2 DMA request */
  2361.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  2362.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  2363.       break;
  2364.     }
  2365.  
  2366.     case TIM_CHANNEL_3:
  2367.     {
  2368.       /* Disable the TIM Capture/Compare 3  DMA request */
  2369.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  2370.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  2371.       break;
  2372.     }
  2373.  
  2374.     case TIM_CHANNEL_4:
  2375.     {
  2376.       /* Disable the TIM Capture/Compare 4  DMA request */
  2377.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  2378.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  2379.       break;
  2380.     }
  2381.  
  2382.     default:
  2383.       break;
  2384.   }
  2385.  
  2386.   /* Disable the Peripheral */
  2387.   __HAL_TIM_DISABLE(htim);
  2388.  
  2389.   /* Set the TIM channel state */
  2390.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2391.  
  2392.   /* Return function status */
  2393.   return HAL_OK;
  2394. }
  2395. /**
  2396.   * @}
  2397.   */
  2398.  
  2399. /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
  2400.   *  @brief    TIM One Pulse functions
  2401.   *
  2402. @verbatim
  2403.   ==============================================================================
  2404.                         ##### TIM One Pulse functions #####
  2405.   ==============================================================================
  2406.   [..]
  2407.     This section provides functions allowing to:
  2408.     (+) Initialize and configure the TIM One Pulse.
  2409.     (+) De-initialize the TIM One Pulse.
  2410.     (+) Start the TIM One Pulse.
  2411.     (+) Stop the TIM One Pulse.
  2412.     (+) Start the TIM One Pulse and enable interrupt.
  2413.     (+) Stop the TIM One Pulse and disable interrupt.
  2414.     (+) Start the TIM One Pulse and enable DMA transfer.
  2415.     (+) Stop the TIM One Pulse and disable DMA transfer.
  2416.  
  2417. @endverbatim
  2418.   * @{
  2419.   */
  2420. /**
  2421.   * @brief  Initializes the TIM One Pulse Time Base according to the specified
  2422.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  2423.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  2424.   *         requires a timer reset to avoid unexpected direction
  2425.   *         due to DIR bit readonly in center aligned mode.
  2426.   *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
  2427.   * @note   When the timer instance is initialized in One Pulse mode, timer
  2428.   *         channels 1 and channel 2 are reserved and cannot be used for other
  2429.   *         purpose.
  2430.   * @param  htim TIM One Pulse handle
  2431.   * @param  OnePulseMode Select the One pulse mode.
  2432.   *         This parameter can be one of the following values:
  2433.   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
  2434.   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
  2435.   * @retval HAL status
  2436.   */
  2437. HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
  2438. {
  2439.   /* Check the TIM handle allocation */
  2440.   if (htim == NULL)
  2441.   {
  2442.     return HAL_ERROR;
  2443.   }
  2444.  
  2445.   /* Check the parameters */
  2446.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  2447.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  2448.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  2449.   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
  2450.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  2451.  
  2452.   if (htim->State == HAL_TIM_STATE_RESET)
  2453.   {
  2454.     /* Allocate lock resource and initialize it */
  2455.     htim->Lock = HAL_UNLOCKED;
  2456.  
  2457. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2458.     /* Reset interrupt callbacks to legacy weak callbacks */
  2459.     TIM_ResetCallback(htim);
  2460.  
  2461.     if (htim->OnePulse_MspInitCallback == NULL)
  2462.     {
  2463.       htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
  2464.     }
  2465.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  2466.     htim->OnePulse_MspInitCallback(htim);
  2467. #else
  2468.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  2469.     HAL_TIM_OnePulse_MspInit(htim);
  2470. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2471.   }
  2472.  
  2473.   /* Set the TIM state */
  2474.   htim->State = HAL_TIM_STATE_BUSY;
  2475.  
  2476.   /* Configure the Time base in the One Pulse Mode */
  2477.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  2478.  
  2479.   /* Reset the OPM Bit */
  2480.   htim->Instance->CR1 &= ~TIM_CR1_OPM;
  2481.  
  2482.   /* Configure the OPM Mode */
  2483.   htim->Instance->CR1 |= OnePulseMode;
  2484.  
  2485.   /* Initialize the DMA burst operation state */
  2486.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  2487.  
  2488.   /* Initialize the TIM channels state */
  2489.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2490.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2491.  
  2492.   /* Initialize the TIM state*/
  2493.   htim->State = HAL_TIM_STATE_READY;
  2494.  
  2495.   return HAL_OK;
  2496. }
  2497.  
  2498. /**
  2499.   * @brief  DeInitializes the TIM One Pulse
  2500.   * @param  htim TIM One Pulse handle
  2501.   * @retval HAL status
  2502.   */
  2503. HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
  2504. {
  2505.   /* Check the parameters */
  2506.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  2507.  
  2508.   htim->State = HAL_TIM_STATE_BUSY;
  2509.  
  2510.   /* Disable the TIM Peripheral Clock */
  2511.   __HAL_TIM_DISABLE(htim);
  2512.  
  2513. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2514.   if (htim->OnePulse_MspDeInitCallback == NULL)
  2515.   {
  2516.     htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
  2517.   }
  2518.   /* DeInit the low level hardware */
  2519.   htim->OnePulse_MspDeInitCallback(htim);
  2520. #else
  2521.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  2522.   HAL_TIM_OnePulse_MspDeInit(htim);
  2523. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2524.  
  2525.   /* Change the DMA burst operation state */
  2526.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  2527.  
  2528.   /* Set the TIM channel state */
  2529.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  2530.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  2531.  
  2532.   /* Change TIM state */
  2533.   htim->State = HAL_TIM_STATE_RESET;
  2534.  
  2535.   /* Release Lock */
  2536.   __HAL_UNLOCK(htim);
  2537.  
  2538.   return HAL_OK;
  2539. }
  2540.  
  2541. /**
  2542.   * @brief  Initializes the TIM One Pulse MSP.
  2543.   * @param  htim TIM One Pulse handle
  2544.   * @retval None
  2545.   */
  2546. __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
  2547. {
  2548.   /* Prevent unused argument(s) compilation warning */
  2549.   UNUSED(htim);
  2550.  
  2551.   /* NOTE : This function should not be modified, when the callback is needed,
  2552.             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
  2553.    */
  2554. }
  2555.  
  2556. /**
  2557.   * @brief  DeInitializes TIM One Pulse MSP.
  2558.   * @param  htim TIM One Pulse handle
  2559.   * @retval None
  2560.   */
  2561. __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
  2562. {
  2563.   /* Prevent unused argument(s) compilation warning */
  2564.   UNUSED(htim);
  2565.  
  2566.   /* NOTE : This function should not be modified, when the callback is needed,
  2567.             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
  2568.    */
  2569. }
  2570.  
  2571. /**
  2572.   * @brief  Starts the TIM One Pulse signal generation.
  2573.   * @param  htim TIM One Pulse handle
  2574.   * @param  OutputChannel TIM Channels to be enabled
  2575.   *          This parameter can be one of the following values:
  2576.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2577.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2578.   * @retval HAL status
  2579.   */
  2580. HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2581. {
  2582.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  2583.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  2584.  
  2585.   /* Prevent unused argument(s) compilation warning */
  2586.   UNUSED(OutputChannel);
  2587.  
  2588.   /* Check the TIM channels state */
  2589.   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2590.    || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  2591.   {
  2592.     return HAL_ERROR;
  2593.   }
  2594.  
  2595.   /* Set the TIM channels state */
  2596.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2597.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2598.  
  2599.   /* Enable the Capture compare and the Input Capture channels
  2600.     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2601.     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2602.     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2603.     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
  2604.  
  2605.     No need to enable the counter, it's enabled automatically by hardware
  2606.     (the counter starts in response to a stimulus and generate a pulse */
  2607.  
  2608.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  2609.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  2610.  
  2611.   /* Return function status */
  2612.   return HAL_OK;
  2613. }
  2614.  
  2615. /**
  2616.   * @brief  Stops the TIM One Pulse signal generation.
  2617.   * @param  htim TIM One Pulse handle
  2618.   * @param  OutputChannel TIM Channels to be disable
  2619.   *          This parameter can be one of the following values:
  2620.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2621.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2622.   * @retval HAL status
  2623.   */
  2624. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2625. {
  2626.   /* Prevent unused argument(s) compilation warning */
  2627.   UNUSED(OutputChannel);
  2628.  
  2629.   /* Disable the Capture compare and the Input Capture channels
  2630.   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2631.   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2632.   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2633.   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
  2634.  
  2635.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  2636.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  2637.  
  2638.   /* Disable the Peripheral */
  2639.   __HAL_TIM_DISABLE(htim);
  2640.  
  2641.   /* Set the TIM channels state */
  2642.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2643.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2644.  
  2645.   /* Return function status */
  2646.   return HAL_OK;
  2647. }
  2648.  
  2649. /**
  2650.   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
  2651.   * @param  htim TIM One Pulse handle
  2652.   * @param  OutputChannel TIM Channels to be enabled
  2653.   *          This parameter can be one of the following values:
  2654.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2655.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2656.   * @retval HAL status
  2657.   */
  2658. HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2659. {
  2660.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  2661.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  2662.  
  2663.   /* Prevent unused argument(s) compilation warning */
  2664.   UNUSED(OutputChannel);
  2665.  
  2666.   /* Check the TIM channels state */
  2667.   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2668.    || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  2669.   {
  2670.     return HAL_ERROR;
  2671.   }
  2672.  
  2673.   /* Set the TIM channels state */
  2674.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2675.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2676.  
  2677.   /* Enable the Capture compare and the Input Capture channels
  2678.     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2679.     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2680.     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2681.     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
  2682.  
  2683.     No need to enable the counter, it's enabled automatically by hardware
  2684.     (the counter starts in response to a stimulus and generate a pulse */
  2685.  
  2686.   /* Enable the TIM Capture/Compare 1 interrupt */
  2687.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  2688.  
  2689.   /* Enable the TIM Capture/Compare 2 interrupt */
  2690.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  2691.  
  2692.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  2693.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  2694.  
  2695.   /* Return function status */
  2696.   return HAL_OK;
  2697. }
  2698.  
  2699. /**
  2700.   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
  2701.   * @param  htim TIM One Pulse handle
  2702.   * @param  OutputChannel TIM Channels to be enabled
  2703.   *          This parameter can be one of the following values:
  2704.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2705.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2706.   * @retval HAL status
  2707.   */
  2708. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2709. {
  2710.   /* Prevent unused argument(s) compilation warning */
  2711.   UNUSED(OutputChannel);
  2712.  
  2713.   /* Disable the TIM Capture/Compare 1 interrupt */
  2714.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  2715.  
  2716.   /* Disable the TIM Capture/Compare 2 interrupt */
  2717.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  2718.  
  2719.   /* Disable the Capture compare and the Input Capture channels
  2720.   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2721.   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2722.   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2723.   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
  2724.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  2725.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  2726.  
  2727.   /* Disable the Peripheral */
  2728.   __HAL_TIM_DISABLE(htim);
  2729.  
  2730.   /* Set the TIM channels state */
  2731.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2732.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2733.  
  2734.   /* Return function status */
  2735.   return HAL_OK;
  2736. }
  2737.  
  2738. /**
  2739.   * @}
  2740.   */
  2741.  
  2742. /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
  2743.   *  @brief    TIM Encoder functions
  2744.   *
  2745. @verbatim
  2746.   ==============================================================================
  2747.                           ##### TIM Encoder functions #####
  2748.   ==============================================================================
  2749.   [..]
  2750.     This section provides functions allowing to:
  2751.     (+) Initialize and configure the TIM Encoder.
  2752.     (+) De-initialize the TIM Encoder.
  2753.     (+) Start the TIM Encoder.
  2754.     (+) Stop the TIM Encoder.
  2755.     (+) Start the TIM Encoder and enable interrupt.
  2756.     (+) Stop the TIM Encoder and disable interrupt.
  2757.     (+) Start the TIM Encoder and enable DMA transfer.
  2758.     (+) Stop the TIM Encoder and disable DMA transfer.
  2759.  
  2760. @endverbatim
  2761.   * @{
  2762.   */
  2763. /**
  2764.   * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
  2765.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  2766.   *         requires a timer reset to avoid unexpected direction
  2767.   *         due to DIR bit readonly in center aligned mode.
  2768.   *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
  2769.   * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
  2770.   *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
  2771.   *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
  2772.   * @note   When the timer instance is initialized in Encoder mode, timer
  2773.   *         channels 1 and channel 2 are reserved and cannot be used for other
  2774.   *         purpose.
  2775.   * @param  htim TIM Encoder Interface handle
  2776.   * @param  sConfig TIM Encoder Interface configuration structure
  2777.   * @retval HAL status
  2778.   */
  2779. HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
  2780. {
  2781.   uint32_t tmpsmcr;
  2782.   uint32_t tmpccmr1;
  2783.   uint32_t tmpccer;
  2784.  
  2785.   /* Check the TIM handle allocation */
  2786.   if (htim == NULL)
  2787.   {
  2788.     return HAL_ERROR;
  2789.   }
  2790.  
  2791.   /* Check the parameters */
  2792.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  2793.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  2794.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  2795.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  2796.   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
  2797.   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
  2798.   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
  2799.   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
  2800.   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
  2801.   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
  2802.   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
  2803.   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
  2804.   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
  2805.  
  2806.   if (htim->State == HAL_TIM_STATE_RESET)
  2807.   {
  2808.     /* Allocate lock resource and initialize it */
  2809.     htim->Lock = HAL_UNLOCKED;
  2810.  
  2811. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2812.     /* Reset interrupt callbacks to legacy weak callbacks */
  2813.     TIM_ResetCallback(htim);
  2814.  
  2815.     if (htim->Encoder_MspInitCallback == NULL)
  2816.     {
  2817.       htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
  2818.     }
  2819.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  2820.     htim->Encoder_MspInitCallback(htim);
  2821. #else
  2822.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  2823.     HAL_TIM_Encoder_MspInit(htim);
  2824. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2825.   }
  2826.  
  2827.   /* Set the TIM state */
  2828.   htim->State = HAL_TIM_STATE_BUSY;
  2829.  
  2830.   /* Reset the SMS and ECE bits */
  2831.   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
  2832.  
  2833.   /* Configure the Time base in the Encoder Mode */
  2834.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  2835.  
  2836.   /* Get the TIMx SMCR register value */
  2837.   tmpsmcr = htim->Instance->SMCR;
  2838.  
  2839.   /* Get the TIMx CCMR1 register value */
  2840.   tmpccmr1 = htim->Instance->CCMR1;
  2841.  
  2842.   /* Get the TIMx CCER register value */
  2843.   tmpccer = htim->Instance->CCER;
  2844.  
  2845.   /* Set the encoder Mode */
  2846.   tmpsmcr |= sConfig->EncoderMode;
  2847.  
  2848.   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
  2849.   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
  2850.   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
  2851.  
  2852.   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
  2853.   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
  2854.   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
  2855.   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
  2856.   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
  2857.  
  2858.   /* Set the TI1 and the TI2 Polarities */
  2859.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
  2860.   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
  2861.   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
  2862.  
  2863.   /* Write to TIMx SMCR */
  2864.   htim->Instance->SMCR = tmpsmcr;
  2865.  
  2866.   /* Write to TIMx CCMR1 */
  2867.   htim->Instance->CCMR1 = tmpccmr1;
  2868.  
  2869.   /* Write to TIMx CCER */
  2870.   htim->Instance->CCER = tmpccer;
  2871.  
  2872.   /* Initialize the DMA burst operation state */
  2873.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  2874.  
  2875.   /* Set the TIM channels state */
  2876.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2877.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2878.  
  2879.   /* Initialize the TIM state*/
  2880.   htim->State = HAL_TIM_STATE_READY;
  2881.  
  2882.   return HAL_OK;
  2883. }
  2884.  
  2885.  
  2886. /**
  2887.   * @brief  DeInitializes the TIM Encoder interface
  2888.   * @param  htim TIM Encoder Interface handle
  2889.   * @retval HAL status
  2890.   */
  2891. HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
  2892. {
  2893.   /* Check the parameters */
  2894.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  2895.  
  2896.   htim->State = HAL_TIM_STATE_BUSY;
  2897.  
  2898.   /* Disable the TIM Peripheral Clock */
  2899.   __HAL_TIM_DISABLE(htim);
  2900.  
  2901. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2902.   if (htim->Encoder_MspDeInitCallback == NULL)
  2903.   {
  2904.     htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
  2905.   }
  2906.   /* DeInit the low level hardware */
  2907.   htim->Encoder_MspDeInitCallback(htim);
  2908. #else
  2909.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  2910.   HAL_TIM_Encoder_MspDeInit(htim);
  2911. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2912.  
  2913.   /* Change the DMA burst operation state */
  2914.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  2915.  
  2916.   /* Set the TIM channels state */
  2917.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  2918.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  2919.  
  2920.   /* Change TIM state */
  2921.   htim->State = HAL_TIM_STATE_RESET;
  2922.  
  2923.   /* Release Lock */
  2924.   __HAL_UNLOCK(htim);
  2925.  
  2926.   return HAL_OK;
  2927. }
  2928.  
  2929. /**
  2930.   * @brief  Initializes the TIM Encoder Interface MSP.
  2931.   * @param  htim TIM Encoder Interface handle
  2932.   * @retval None
  2933.   */
  2934. __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
  2935. {
  2936.   /* Prevent unused argument(s) compilation warning */
  2937.   UNUSED(htim);
  2938.  
  2939.   /* NOTE : This function should not be modified, when the callback is needed,
  2940.             the HAL_TIM_Encoder_MspInit could be implemented in the user file
  2941.    */
  2942. }
  2943.  
  2944. /**
  2945.   * @brief  DeInitializes TIM Encoder Interface MSP.
  2946.   * @param  htim TIM Encoder Interface handle
  2947.   * @retval None
  2948.   */
  2949. __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
  2950. {
  2951.   /* Prevent unused argument(s) compilation warning */
  2952.   UNUSED(htim);
  2953.  
  2954.   /* NOTE : This function should not be modified, when the callback is needed,
  2955.             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
  2956.    */
  2957. }
  2958.  
  2959. /**
  2960.   * @brief  Starts the TIM Encoder Interface.
  2961.   * @param  htim TIM Encoder Interface handle
  2962.   * @param  Channel TIM Channels to be enabled
  2963.   *          This parameter can be one of the following values:
  2964.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2965.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2966.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  2967.   * @retval HAL status
  2968.   */
  2969. HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  2970. {
  2971.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  2972.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  2973.  
  2974.   /* Check the parameters */
  2975.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  2976.  
  2977.   /* Set the TIM channel(s) state */
  2978.   if (Channel == TIM_CHANNEL_1)
  2979.   {
  2980.     if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2981.     {
  2982.       return HAL_ERROR;
  2983.     }
  2984.     else
  2985.     {
  2986.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2987.     }
  2988.   }
  2989.   else if (Channel == TIM_CHANNEL_2)
  2990.   {
  2991.     if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  2992.     {
  2993.       return HAL_ERROR;
  2994.     }
  2995.     else
  2996.     {
  2997.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2998.     }
  2999.   }
  3000.   else
  3001.   {
  3002.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3003.      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3004.     {
  3005.       return HAL_ERROR;
  3006.     }
  3007.     else
  3008.     {
  3009.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3010.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3011.     }
  3012.   }
  3013.  
  3014.   /* Enable the encoder interface channels */
  3015.   switch (Channel)
  3016.   {
  3017.     case TIM_CHANNEL_1:
  3018.     {
  3019.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3020.       break;
  3021.     }
  3022.  
  3023.     case TIM_CHANNEL_2:
  3024.     {
  3025.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3026.       break;
  3027.     }
  3028.  
  3029.     default :
  3030.     {
  3031.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3032.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3033.       break;
  3034.     }
  3035.   }
  3036.   /* Enable the Peripheral */
  3037.   __HAL_TIM_ENABLE(htim);
  3038.  
  3039.   /* Return function status */
  3040.   return HAL_OK;
  3041. }
  3042.  
  3043. /**
  3044.   * @brief  Stops the TIM Encoder Interface.
  3045.   * @param  htim TIM Encoder Interface handle
  3046.   * @param  Channel TIM Channels to be disabled
  3047.   *          This parameter can be one of the following values:
  3048.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3049.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3050.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3051.   * @retval HAL status
  3052.   */
  3053. HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  3054. {
  3055.   /* Check the parameters */
  3056.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3057.  
  3058.   /* Disable the Input Capture channels 1 and 2
  3059.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3060.   switch (Channel)
  3061.   {
  3062.     case TIM_CHANNEL_1:
  3063.     {
  3064.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3065.       break;
  3066.     }
  3067.  
  3068.     case TIM_CHANNEL_2:
  3069.     {
  3070.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3071.       break;
  3072.     }
  3073.  
  3074.     default :
  3075.     {
  3076.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3077.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3078.       break;
  3079.     }
  3080.   }
  3081.  
  3082.   /* Disable the Peripheral */
  3083.   __HAL_TIM_DISABLE(htim);
  3084.  
  3085.   /* Set the TIM channel(s) state */
  3086.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3087.   {
  3088.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3089.   }
  3090.   else
  3091.   {
  3092.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3093.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3094.   }
  3095.  
  3096.   /* Return function status */
  3097.   return HAL_OK;
  3098. }
  3099.  
  3100. /**
  3101.   * @brief  Starts the TIM Encoder Interface in interrupt mode.
  3102.   * @param  htim TIM Encoder Interface handle
  3103.   * @param  Channel TIM Channels to be enabled
  3104.   *          This parameter can be one of the following values:
  3105.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3106.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3107.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3108.   * @retval HAL status
  3109.   */
  3110. HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  3111. {
  3112.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  3113.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  3114.  
  3115.   /* Check the parameters */
  3116.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3117.  
  3118.   /* Set the TIM channel(s) state */
  3119.   if (Channel == TIM_CHANNEL_1)
  3120.   {
  3121.     if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3122.     {
  3123.       return HAL_ERROR;
  3124.     }
  3125.     else
  3126.     {
  3127.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3128.     }
  3129.   }
  3130.   else if (Channel == TIM_CHANNEL_2)
  3131.   {
  3132.     if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3133.     {
  3134.       return HAL_ERROR;
  3135.     }
  3136.     else
  3137.     {
  3138.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3139.     }
  3140.   }
  3141.   else
  3142.   {
  3143.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3144.      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3145.     {
  3146.       return HAL_ERROR;
  3147.     }
  3148.     else
  3149.     {
  3150.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3151.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3152.     }
  3153.   }
  3154.  
  3155.   /* Enable the encoder interface channels */
  3156.   /* Enable the capture compare Interrupts 1 and/or 2 */
  3157.   switch (Channel)
  3158.   {
  3159.     case TIM_CHANNEL_1:
  3160.     {
  3161.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3162.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  3163.       break;
  3164.     }
  3165.  
  3166.     case TIM_CHANNEL_2:
  3167.     {
  3168.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3169.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  3170.       break;
  3171.     }
  3172.  
  3173.     default :
  3174.     {
  3175.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3176.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3177.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  3178.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  3179.       break;
  3180.     }
  3181.   }
  3182.  
  3183.   /* Enable the Peripheral */
  3184.   __HAL_TIM_ENABLE(htim);
  3185.  
  3186.   /* Return function status */
  3187.   return HAL_OK;
  3188. }
  3189.  
  3190. /**
  3191.   * @brief  Stops the TIM Encoder Interface in interrupt mode.
  3192.   * @param  htim TIM Encoder Interface handle
  3193.   * @param  Channel TIM Channels to be disabled
  3194.   *          This parameter can be one of the following values:
  3195.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3196.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3197.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3198.   * @retval HAL status
  3199.   */
  3200. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  3201. {
  3202.   /* Check the parameters */
  3203.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3204.  
  3205.   /* Disable the Input Capture channels 1 and 2
  3206.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3207.   if (Channel == TIM_CHANNEL_1)
  3208.   {
  3209.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3210.  
  3211.     /* Disable the capture compare Interrupts 1 */
  3212.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  3213.   }
  3214.   else if (Channel == TIM_CHANNEL_2)
  3215.   {
  3216.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3217.  
  3218.     /* Disable the capture compare Interrupts 2 */
  3219.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  3220.   }
  3221.   else
  3222.   {
  3223.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3224.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3225.  
  3226.     /* Disable the capture compare Interrupts 1 and 2 */
  3227.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  3228.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  3229.   }
  3230.  
  3231.   /* Disable the Peripheral */
  3232.   __HAL_TIM_DISABLE(htim);
  3233.  
  3234.   /* Set the TIM channel(s) state */
  3235.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3236.   {
  3237.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3238.   }
  3239.   else
  3240.   {
  3241.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3242.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3243.   }
  3244.  
  3245.   /* Return function status */
  3246.   return HAL_OK;
  3247. }
  3248.  
  3249. /**
  3250.   * @brief  Starts the TIM Encoder Interface in DMA mode.
  3251.   * @param  htim TIM Encoder Interface handle
  3252.   * @param  Channel TIM Channels to be enabled
  3253.   *          This parameter can be one of the following values:
  3254.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3255.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3256.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3257.   * @param  pData1 The destination Buffer address for IC1.
  3258.   * @param  pData2 The destination Buffer address for IC2.
  3259.   * @param  Length The length of data to be transferred from TIM peripheral to memory.
  3260.   * @retval HAL status
  3261.   */
  3262. HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
  3263.                                             uint32_t *pData2, uint16_t Length)
  3264. {
  3265.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  3266.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  3267.  
  3268.   /* Check the parameters */
  3269.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3270.  
  3271.   /* Set the TIM channel(s) state */
  3272.   if (Channel == TIM_CHANNEL_1)
  3273.   {
  3274.     if (channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3275.     {
  3276.       return HAL_BUSY;
  3277.     }
  3278.     else if (channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
  3279.     {
  3280.       if ((pData1 == NULL) && (Length > 0U))
  3281.       {
  3282.         return HAL_ERROR;
  3283.       }
  3284.       else
  3285.       {
  3286.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3287.       }
  3288.     }
  3289.     else
  3290.     {
  3291.       return HAL_ERROR;
  3292.     }
  3293.   }
  3294.   else if (Channel == TIM_CHANNEL_2)
  3295.   {
  3296.     if (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3297.     {
  3298.       return HAL_BUSY;
  3299.     }
  3300.     else if (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
  3301.     {
  3302.       if ((pData2 == NULL) && (Length > 0U))
  3303.       {
  3304.         return HAL_ERROR;
  3305.       }
  3306.       else
  3307.       {
  3308.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3309.       }
  3310.     }
  3311.     else
  3312.     {
  3313.       return HAL_ERROR;
  3314.     }
  3315.   }
  3316.   else
  3317.   {
  3318.     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3319.      || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
  3320.     {
  3321.       return HAL_BUSY;
  3322.     }
  3323.     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
  3324.           && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
  3325.     {
  3326.       if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
  3327.       {
  3328.         return HAL_ERROR;
  3329.       }
  3330.       else
  3331.       {
  3332.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3333.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3334.       }
  3335.     }
  3336.     else
  3337.     {
  3338.       return HAL_ERROR;
  3339.     }
  3340.   }
  3341.  
  3342.   switch (Channel)
  3343.   {
  3344.     case TIM_CHANNEL_1:
  3345.     {
  3346.       /* Set the DMA capture callbacks */
  3347.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  3348.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3349.  
  3350.       /* Set the DMA error callback */
  3351.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  3352.  
  3353.       /* Enable the DMA channel */
  3354.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
  3355.       {
  3356.         return HAL_ERROR;
  3357.       }
  3358.       /* Enable the TIM Input Capture DMA request */
  3359.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  3360.  
  3361.       /* Enable the Peripheral */
  3362.       __HAL_TIM_ENABLE(htim);
  3363.  
  3364.       /* Enable the Capture compare channel */
  3365.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3366.       break;
  3367.     }
  3368.  
  3369.     case TIM_CHANNEL_2:
  3370.     {
  3371.       /* Set the DMA capture callbacks */
  3372.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  3373.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3374.  
  3375.       /* Set the DMA error callback */
  3376.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
  3377.       /* Enable the DMA channel */
  3378.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
  3379.       {
  3380.         return HAL_ERROR;
  3381.       }
  3382.       /* Enable the TIM Input Capture  DMA request */
  3383.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  3384.  
  3385.       /* Enable the Peripheral */
  3386.       __HAL_TIM_ENABLE(htim);
  3387.  
  3388.       /* Enable the Capture compare channel */
  3389.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3390.       break;
  3391.     }
  3392.  
  3393.     case TIM_CHANNEL_ALL:
  3394.     {
  3395.       /* Set the DMA capture callbacks */
  3396.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  3397.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3398.  
  3399.       /* Set the DMA error callback */
  3400.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  3401.  
  3402.       /* Enable the DMA channel */
  3403.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
  3404.       {
  3405.         return HAL_ERROR;
  3406.       }
  3407.  
  3408.       /* Set the DMA capture callbacks */
  3409.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  3410.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3411.  
  3412.       /* Set the DMA error callback */
  3413.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  3414.  
  3415.       /* Enable the DMA channel */
  3416.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
  3417.       {
  3418.         return HAL_ERROR;
  3419.       }
  3420.       /* Enable the Peripheral */
  3421.       __HAL_TIM_ENABLE(htim);
  3422.  
  3423.       /* Enable the Capture compare channel */
  3424.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3425.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3426.  
  3427.       /* Enable the TIM Input Capture  DMA request */
  3428.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  3429.       /* Enable the TIM Input Capture  DMA request */
  3430.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  3431.       break;
  3432.     }
  3433.  
  3434.     default:
  3435.       break;
  3436.   }
  3437.  
  3438.   /* Return function status */
  3439.   return HAL_OK;
  3440. }
  3441.  
  3442. /**
  3443.   * @brief  Stops the TIM Encoder Interface in DMA mode.
  3444.   * @param  htim TIM Encoder Interface handle
  3445.   * @param  Channel TIM Channels to be enabled
  3446.   *          This parameter can be one of the following values:
  3447.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3448.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3449.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3450.   * @retval HAL status
  3451.   */
  3452. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  3453. {
  3454.   /* Check the parameters */
  3455.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3456.  
  3457.   /* Disable the Input Capture channels 1 and 2
  3458.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3459.   if (Channel == TIM_CHANNEL_1)
  3460.   {
  3461.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3462.  
  3463.     /* Disable the capture compare DMA Request 1 */
  3464.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  3465.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  3466.   }
  3467.   else if (Channel == TIM_CHANNEL_2)
  3468.   {
  3469.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3470.  
  3471.     /* Disable the capture compare DMA Request 2 */
  3472.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  3473.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  3474.   }
  3475.   else
  3476.   {
  3477.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3478.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3479.  
  3480.     /* Disable the capture compare DMA Request 1 and 2 */
  3481.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  3482.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  3483.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  3484.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  3485.   }
  3486.  
  3487.   /* Disable the Peripheral */
  3488.   __HAL_TIM_DISABLE(htim);
  3489.  
  3490.   /* Set the TIM channel(s) state */
  3491.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3492.   {
  3493.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3494.   }
  3495.   else
  3496.   {
  3497.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3498.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3499.   }
  3500.  
  3501.   /* Return function status */
  3502.   return HAL_OK;
  3503. }
  3504.  
  3505. /**
  3506.   * @}
  3507.   */
  3508. /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
  3509.   *  @brief    TIM IRQ handler management
  3510.   *
  3511. @verbatim
  3512.   ==============================================================================
  3513.                         ##### IRQ handler management #####
  3514.   ==============================================================================
  3515.   [..]
  3516.     This section provides Timer IRQ handler function.
  3517.  
  3518. @endverbatim
  3519.   * @{
  3520.   */
  3521. /**
  3522.   * @brief  This function handles TIM interrupts requests.
  3523.   * @param  htim TIM  handle
  3524.   * @retval None
  3525.   */
  3526. void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
  3527. {
  3528.   /* Capture compare 1 event */
  3529.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
  3530.   {
  3531.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
  3532.     {
  3533.       {
  3534.         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
  3535.         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  3536.  
  3537.         /* Input capture event */
  3538.         if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
  3539.         {
  3540. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3541.           htim->IC_CaptureCallback(htim);
  3542. #else
  3543.           HAL_TIM_IC_CaptureCallback(htim);
  3544. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3545.         }
  3546.         /* Output compare event */
  3547.         else
  3548.         {
  3549. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3550.           htim->OC_DelayElapsedCallback(htim);
  3551.           htim->PWM_PulseFinishedCallback(htim);
  3552. #else
  3553.           HAL_TIM_OC_DelayElapsedCallback(htim);
  3554.           HAL_TIM_PWM_PulseFinishedCallback(htim);
  3555. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3556.         }
  3557.         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3558.       }
  3559.     }
  3560.   }
  3561.   /* Capture compare 2 event */
  3562.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
  3563.   {
  3564.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
  3565.     {
  3566.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
  3567.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  3568.       /* Input capture event */
  3569.       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
  3570.       {
  3571. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3572.         htim->IC_CaptureCallback(htim);
  3573. #else
  3574.         HAL_TIM_IC_CaptureCallback(htim);
  3575. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3576.       }
  3577.       /* Output compare event */
  3578.       else
  3579.       {
  3580. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3581.         htim->OC_DelayElapsedCallback(htim);
  3582.         htim->PWM_PulseFinishedCallback(htim);
  3583. #else
  3584.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3585.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3586. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3587.       }
  3588.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3589.     }
  3590.   }
  3591.   /* Capture compare 3 event */
  3592.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
  3593.   {
  3594.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
  3595.     {
  3596.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
  3597.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  3598.       /* Input capture event */
  3599.       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
  3600.       {
  3601. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3602.         htim->IC_CaptureCallback(htim);
  3603. #else
  3604.         HAL_TIM_IC_CaptureCallback(htim);
  3605. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3606.       }
  3607.       /* Output compare event */
  3608.       else
  3609.       {
  3610. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3611.         htim->OC_DelayElapsedCallback(htim);
  3612.         htim->PWM_PulseFinishedCallback(htim);
  3613. #else
  3614.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3615.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3616. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3617.       }
  3618.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3619.     }
  3620.   }
  3621.   /* Capture compare 4 event */
  3622.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
  3623.   {
  3624.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
  3625.     {
  3626.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
  3627.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  3628.       /* Input capture event */
  3629.       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
  3630.       {
  3631. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3632.         htim->IC_CaptureCallback(htim);
  3633. #else
  3634.         HAL_TIM_IC_CaptureCallback(htim);
  3635. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3636.       }
  3637.       /* Output compare event */
  3638.       else
  3639.       {
  3640. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3641.         htim->OC_DelayElapsedCallback(htim);
  3642.         htim->PWM_PulseFinishedCallback(htim);
  3643. #else
  3644.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3645.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3646. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3647.       }
  3648.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3649.     }
  3650.   }
  3651.   /* TIM Update event */
  3652.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
  3653.   {
  3654.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
  3655.     {
  3656.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
  3657. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3658.       htim->PeriodElapsedCallback(htim);
  3659. #else
  3660.       HAL_TIM_PeriodElapsedCallback(htim);
  3661. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3662.     }
  3663.   }
  3664.   /* TIM Trigger detection event */
  3665.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
  3666.   {
  3667.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
  3668.     {
  3669.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
  3670. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3671.       htim->TriggerCallback(htim);
  3672. #else
  3673.       HAL_TIM_TriggerCallback(htim);
  3674. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3675.     }
  3676.   }
  3677. }
  3678.  
  3679. /**
  3680.   * @}
  3681.   */
  3682.  
  3683. /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
  3684.   *  @brief    TIM Peripheral Control functions
  3685.   *
  3686. @verbatim
  3687.   ==============================================================================
  3688.                    ##### Peripheral Control functions #####
  3689.   ==============================================================================
  3690.  [..]
  3691.    This section provides functions allowing to:
  3692.       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
  3693.       (+) Configure External Clock source.
  3694.       (+) Configure Master and the Slave synchronization.
  3695.       (+) Configure the DMA Burst Mode.
  3696.  
  3697. @endverbatim
  3698.   * @{
  3699.   */
  3700.  
  3701. /**
  3702.   * @brief  Initializes the TIM Output Compare Channels according to the specified
  3703.   *         parameters in the TIM_OC_InitTypeDef.
  3704.   * @param  htim TIM Output Compare handle
  3705.   * @param  sConfig TIM Output Compare configuration structure
  3706.   * @param  Channel TIM Channels to configure
  3707.   *          This parameter can be one of the following values:
  3708.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3709.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3710.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  3711.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  3712.   * @retval HAL status
  3713.   */
  3714. HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
  3715.                                            TIM_OC_InitTypeDef *sConfig,
  3716.                                            uint32_t Channel)
  3717. {
  3718.   /* Check the parameters */
  3719.   assert_param(IS_TIM_CHANNELS(Channel));
  3720.   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
  3721.   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
  3722.  
  3723.   /* Process Locked */
  3724.   __HAL_LOCK(htim);
  3725.  
  3726.   switch (Channel)
  3727.   {
  3728.     case TIM_CHANNEL_1:
  3729.     {
  3730.       /* Check the parameters */
  3731.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  3732.  
  3733.       /* Configure the TIM Channel 1 in Output Compare */
  3734.       TIM_OC1_SetConfig(htim->Instance, sConfig);
  3735.       break;
  3736.     }
  3737.  
  3738.     case TIM_CHANNEL_2:
  3739.     {
  3740.       /* Check the parameters */
  3741.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  3742.  
  3743.       /* Configure the TIM Channel 2 in Output Compare */
  3744.       TIM_OC2_SetConfig(htim->Instance, sConfig);
  3745.       break;
  3746.     }
  3747.  
  3748.     case TIM_CHANNEL_3:
  3749.     {
  3750.       /* Check the parameters */
  3751.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  3752.  
  3753.       /* Configure the TIM Channel 3 in Output Compare */
  3754.       TIM_OC3_SetConfig(htim->Instance, sConfig);
  3755.       break;
  3756.     }
  3757.  
  3758.     case TIM_CHANNEL_4:
  3759.     {
  3760.       /* Check the parameters */
  3761.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  3762.  
  3763.       /* Configure the TIM Channel 4 in Output Compare */
  3764.       TIM_OC4_SetConfig(htim->Instance, sConfig);
  3765.       break;
  3766.     }
  3767.  
  3768.     default:
  3769.       break;
  3770.   }
  3771.  
  3772.   __HAL_UNLOCK(htim);
  3773.  
  3774.   return HAL_OK;
  3775. }
  3776.  
  3777. /**
  3778.   * @brief  Initializes the TIM Input Capture Channels according to the specified
  3779.   *         parameters in the TIM_IC_InitTypeDef.
  3780.   * @param  htim TIM IC handle
  3781.   * @param  sConfig TIM Input Capture configuration structure
  3782.   * @param  Channel TIM Channel to configure
  3783.   *          This parameter can be one of the following values:
  3784.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3785.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3786.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  3787.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  3788.   * @retval HAL status
  3789.   */
  3790. HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
  3791. {
  3792.   /* Check the parameters */
  3793.   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  3794.   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
  3795.   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
  3796.   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
  3797.   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
  3798.  
  3799.   /* Process Locked */
  3800.   __HAL_LOCK(htim);
  3801.  
  3802.   if (Channel == TIM_CHANNEL_1)
  3803.   {
  3804.     /* TI1 Configuration */
  3805.     TIM_TI1_SetConfig(htim->Instance,
  3806.                       sConfig->ICPolarity,
  3807.                       sConfig->ICSelection,
  3808.                       sConfig->ICFilter);
  3809.  
  3810.     /* Reset the IC1PSC Bits */
  3811.     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
  3812.  
  3813.     /* Set the IC1PSC value */
  3814.     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
  3815.   }
  3816.   else if (Channel == TIM_CHANNEL_2)
  3817.   {
  3818.     /* TI2 Configuration */
  3819.     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  3820.  
  3821.     TIM_TI2_SetConfig(htim->Instance,
  3822.                       sConfig->ICPolarity,
  3823.                       sConfig->ICSelection,
  3824.                       sConfig->ICFilter);
  3825.  
  3826.     /* Reset the IC2PSC Bits */
  3827.     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
  3828.  
  3829.     /* Set the IC2PSC value */
  3830.     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
  3831.   }
  3832.   else if (Channel == TIM_CHANNEL_3)
  3833.   {
  3834.     /* TI3 Configuration */
  3835.     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  3836.  
  3837.     TIM_TI3_SetConfig(htim->Instance,
  3838.                       sConfig->ICPolarity,
  3839.                       sConfig->ICSelection,
  3840.                       sConfig->ICFilter);
  3841.  
  3842.     /* Reset the IC3PSC Bits */
  3843.     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
  3844.  
  3845.     /* Set the IC3PSC value */
  3846.     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
  3847.   }
  3848.   else
  3849.   {
  3850.     /* TI4 Configuration */
  3851.     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  3852.  
  3853.     TIM_TI4_SetConfig(htim->Instance,
  3854.                       sConfig->ICPolarity,
  3855.                       sConfig->ICSelection,
  3856.                       sConfig->ICFilter);
  3857.  
  3858.     /* Reset the IC4PSC Bits */
  3859.     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
  3860.  
  3861.     /* Set the IC4PSC value */
  3862.     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
  3863.   }
  3864.  
  3865.   __HAL_UNLOCK(htim);
  3866.  
  3867.   return HAL_OK;
  3868. }
  3869.  
  3870. /**
  3871.   * @brief  Initializes the TIM PWM  channels according to the specified
  3872.   *         parameters in the TIM_OC_InitTypeDef.
  3873.   * @param  htim TIM PWM handle
  3874.   * @param  sConfig TIM PWM configuration structure
  3875.   * @param  Channel TIM Channels to be configured
  3876.   *          This parameter can be one of the following values:
  3877.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3878.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3879.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  3880.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  3881.   * @retval HAL status
  3882.   */
  3883. HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
  3884.                                             TIM_OC_InitTypeDef *sConfig,
  3885.                                             uint32_t Channel)
  3886. {
  3887.   /* Check the parameters */
  3888.   assert_param(IS_TIM_CHANNELS(Channel));
  3889.   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
  3890.   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
  3891.   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
  3892.  
  3893.   /* Process Locked */
  3894.   __HAL_LOCK(htim);
  3895.  
  3896.   switch (Channel)
  3897.   {
  3898.     case TIM_CHANNEL_1:
  3899.     {
  3900.       /* Check the parameters */
  3901.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  3902.  
  3903.       /* Configure the Channel 1 in PWM mode */
  3904.       TIM_OC1_SetConfig(htim->Instance, sConfig);
  3905.  
  3906.       /* Set the Preload enable bit for channel1 */
  3907.       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
  3908.  
  3909.       /* Configure the Output Fast mode */
  3910.       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
  3911.       htim->Instance->CCMR1 |= sConfig->OCFastMode;
  3912.       break;
  3913.     }
  3914.  
  3915.     case TIM_CHANNEL_2:
  3916.     {
  3917.       /* Check the parameters */
  3918.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  3919.  
  3920.       /* Configure the Channel 2 in PWM mode */
  3921.       TIM_OC2_SetConfig(htim->Instance, sConfig);
  3922.  
  3923.       /* Set the Preload enable bit for channel2 */
  3924.       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
  3925.  
  3926.       /* Configure the Output Fast mode */
  3927.       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
  3928.       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
  3929.       break;
  3930.     }
  3931.  
  3932.     case TIM_CHANNEL_3:
  3933.     {
  3934.       /* Check the parameters */
  3935.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  3936.  
  3937.       /* Configure the Channel 3 in PWM mode */
  3938.       TIM_OC3_SetConfig(htim->Instance, sConfig);
  3939.  
  3940.       /* Set the Preload enable bit for channel3 */
  3941.       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
  3942.  
  3943.       /* Configure the Output Fast mode */
  3944.       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
  3945.       htim->Instance->CCMR2 |= sConfig->OCFastMode;
  3946.       break;
  3947.     }
  3948.  
  3949.     case TIM_CHANNEL_4:
  3950.     {
  3951.       /* Check the parameters */
  3952.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  3953.  
  3954.       /* Configure the Channel 4 in PWM mode */
  3955.       TIM_OC4_SetConfig(htim->Instance, sConfig);
  3956.  
  3957.       /* Set the Preload enable bit for channel4 */
  3958.       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
  3959.  
  3960.       /* Configure the Output Fast mode */
  3961.       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
  3962.       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
  3963.       break;
  3964.     }
  3965.  
  3966.     default:
  3967.       break;
  3968.   }
  3969.  
  3970.   __HAL_UNLOCK(htim);
  3971.  
  3972.   return HAL_OK;
  3973. }
  3974.  
  3975. /**
  3976.   * @brief  Initializes the TIM One Pulse Channels according to the specified
  3977.   *         parameters in the TIM_OnePulse_InitTypeDef.
  3978.   * @param  htim TIM One Pulse handle
  3979.   * @param  sConfig TIM One Pulse configuration structure
  3980.   * @param  OutputChannel TIM output channel to configure
  3981.   *          This parameter can be one of the following values:
  3982.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3983.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3984.   * @param  InputChannel TIM input Channel to configure
  3985.   *          This parameter can be one of the following values:
  3986.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3987.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3988.   * @note  To output a waveform with a minimum delay user can enable the fast
  3989.   *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
  3990.   *        output is forced in response to the edge detection on TIx input,
  3991.   *        without taking in account the comparison.
  3992.   * @retval HAL status
  3993.   */
  3994. HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
  3995.                                                  uint32_t OutputChannel,  uint32_t InputChannel)
  3996. {
  3997.   TIM_OC_InitTypeDef temp1;
  3998.  
  3999.   /* Check the parameters */
  4000.   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
  4001.   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
  4002.  
  4003.   if (OutputChannel != InputChannel)
  4004.   {
  4005.     /* Process Locked */
  4006.     __HAL_LOCK(htim);
  4007.  
  4008.     htim->State = HAL_TIM_STATE_BUSY;
  4009.  
  4010.     /* Extract the Output compare configuration from sConfig structure */
  4011.     temp1.OCMode = sConfig->OCMode;
  4012.     temp1.Pulse = sConfig->Pulse;
  4013.     temp1.OCPolarity = sConfig->OCPolarity;
  4014.  
  4015.     switch (OutputChannel)
  4016.     {
  4017.       case TIM_CHANNEL_1:
  4018.       {
  4019.         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4020.  
  4021.         TIM_OC1_SetConfig(htim->Instance, &temp1);
  4022.         break;
  4023.       }
  4024.       case TIM_CHANNEL_2:
  4025.       {
  4026.         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4027.  
  4028.         TIM_OC2_SetConfig(htim->Instance, &temp1);
  4029.         break;
  4030.       }
  4031.       default:
  4032.         break;
  4033.     }
  4034.  
  4035.     switch (InputChannel)
  4036.     {
  4037.       case TIM_CHANNEL_1:
  4038.       {
  4039.         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4040.  
  4041.         TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
  4042.                           sConfig->ICSelection, sConfig->ICFilter);
  4043.  
  4044.         /* Reset the IC1PSC Bits */
  4045.         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
  4046.  
  4047.         /* Select the Trigger source */
  4048.         htim->Instance->SMCR &= ~TIM_SMCR_TS;
  4049.         htim->Instance->SMCR |= TIM_TS_TI1FP1;
  4050.  
  4051.         /* Select the Slave Mode */
  4052.         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
  4053.         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
  4054.         break;
  4055.       }
  4056.       case TIM_CHANNEL_2:
  4057.       {
  4058.         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4059.  
  4060.         TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
  4061.                           sConfig->ICSelection, sConfig->ICFilter);
  4062.  
  4063.         /* Reset the IC2PSC Bits */
  4064.         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
  4065.  
  4066.         /* Select the Trigger source */
  4067.         htim->Instance->SMCR &= ~TIM_SMCR_TS;
  4068.         htim->Instance->SMCR |= TIM_TS_TI2FP2;
  4069.  
  4070.         /* Select the Slave Mode */
  4071.         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
  4072.         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
  4073.         break;
  4074.       }
  4075.  
  4076.       default:
  4077.         break;
  4078.     }
  4079.  
  4080.     htim->State = HAL_TIM_STATE_READY;
  4081.  
  4082.     __HAL_UNLOCK(htim);
  4083.  
  4084.     return HAL_OK;
  4085.   }
  4086.   else
  4087.   {
  4088.     return HAL_ERROR;
  4089.   }
  4090. }
  4091.  
  4092. /**
  4093.   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
  4094.   * @param  htim TIM handle
  4095.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
  4096.   *         This parameter can be one of the following values:
  4097.   *            @arg TIM_DMABASE_CR1
  4098.   *            @arg TIM_DMABASE_CR2
  4099.   *            @arg TIM_DMABASE_SMCR
  4100.   *            @arg TIM_DMABASE_DIER
  4101.   *            @arg TIM_DMABASE_SR
  4102.   *            @arg TIM_DMABASE_EGR
  4103.   *            @arg TIM_DMABASE_CCMR1
  4104.   *            @arg TIM_DMABASE_CCMR2
  4105.   *            @arg TIM_DMABASE_CCER
  4106.   *            @arg TIM_DMABASE_CNT
  4107.   *            @arg TIM_DMABASE_PSC
  4108.   *            @arg TIM_DMABASE_ARR
  4109.   *            @arg TIM_DMABASE_CCR1
  4110.   *            @arg TIM_DMABASE_CCR2
  4111.   *            @arg TIM_DMABASE_CCR3
  4112.   *            @arg TIM_DMABASE_CCR4
  4113.   *            @arg TIM_DMABASE_OR
  4114.   * @param  BurstRequestSrc TIM DMA Request sources
  4115.   *         This parameter can be one of the following values:
  4116.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4117.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4118.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4119.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4120.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4121.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4122.   * @param  BurstBuffer The Buffer address.
  4123.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4124.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4125.   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
  4126.   * @retval HAL status
  4127.   */
  4128. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4129.                                               uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)
  4130. {
  4131.   return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
  4132.                                           ((BurstLength) >> 8U) + 1U);
  4133. }
  4134.  
  4135. /**
  4136.   * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
  4137.   * @param  htim TIM handle
  4138.   * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
  4139.   *         This parameter can be one of the following values:
  4140.   *            @arg TIM_DMABASE_CR1
  4141.   *            @arg TIM_DMABASE_CR2
  4142.   *            @arg TIM_DMABASE_SMCR
  4143.   *            @arg TIM_DMABASE_DIER
  4144.   *            @arg TIM_DMABASE_SR
  4145.   *            @arg TIM_DMABASE_EGR
  4146.   *            @arg TIM_DMABASE_CCMR1
  4147.   *            @arg TIM_DMABASE_CCMR2
  4148.   *            @arg TIM_DMABASE_CCER
  4149.   *            @arg TIM_DMABASE_CNT
  4150.   *            @arg TIM_DMABASE_PSC
  4151.   *            @arg TIM_DMABASE_ARR
  4152.   *            @arg TIM_DMABASE_CCR1
  4153.   *            @arg TIM_DMABASE_CCR2
  4154.   *            @arg TIM_DMABASE_CCR3
  4155.   *            @arg TIM_DMABASE_CCR4
  4156.   *            @arg TIM_DMABASE_OR
  4157.   * @param  BurstRequestSrc TIM DMA Request sources
  4158.   *         This parameter can be one of the following values:
  4159.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4160.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4161.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4162.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4163.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4164.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4165.   * @param  BurstBuffer The Buffer address.
  4166.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4167.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4168.   * @param  DataLength Data length. This parameter can be one value
  4169.   *         between 1 and 0xFFFF.
  4170.   * @retval HAL status
  4171.   */
  4172. HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4173.                                                    uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
  4174.                                                    uint32_t  BurstLength,  uint32_t  DataLength)
  4175. {
  4176.   /* Check the parameters */
  4177.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  4178.   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
  4179.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4180.   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
  4181.   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
  4182.  
  4183.   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
  4184.   {
  4185.     return HAL_BUSY;
  4186.   }
  4187.   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
  4188.   {
  4189.     if ((BurstBuffer == NULL) && (BurstLength > 0U))
  4190.     {
  4191.       return HAL_ERROR;
  4192.     }
  4193.     else
  4194.     {
  4195.       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
  4196.     }
  4197.   }
  4198.   else
  4199.   {
  4200.     /* nothing to do */
  4201.   }
  4202.   switch (BurstRequestSrc)
  4203.   {
  4204.     case TIM_DMA_UPDATE:
  4205.     {
  4206.       /* Set the DMA Period elapsed callbacks */
  4207.       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  4208.       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  4209.  
  4210.       /* Set the DMA error callback */
  4211.       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  4212.  
  4213.       /* Enable the DMA channel */
  4214.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
  4215.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4216.       {
  4217.         return HAL_ERROR;
  4218.       }
  4219.       break;
  4220.     }
  4221.     case TIM_DMA_CC1:
  4222.     {
  4223.       /* Set the DMA compare callbacks */
  4224.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4225.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4226.  
  4227.       /* Set the DMA error callback */
  4228.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  4229.  
  4230.       /* Enable the DMA channel */
  4231.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
  4232.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4233.       {
  4234.         return HAL_ERROR;
  4235.       }
  4236.       break;
  4237.     }
  4238.     case TIM_DMA_CC2:
  4239.     {
  4240.       /* Set the DMA compare callbacks */
  4241.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4242.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4243.  
  4244.       /* Set the DMA error callback */
  4245.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  4246.  
  4247.       /* Enable the DMA channel */
  4248.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
  4249.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4250.       {
  4251.         return HAL_ERROR;
  4252.       }
  4253.       break;
  4254.     }
  4255.     case TIM_DMA_CC3:
  4256.     {
  4257.       /* Set the DMA compare callbacks */
  4258.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4259.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4260.  
  4261.       /* Set the DMA error callback */
  4262.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  4263.  
  4264.       /* Enable the DMA channel */
  4265.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
  4266.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4267.       {
  4268.         return HAL_ERROR;
  4269.       }
  4270.       break;
  4271.     }
  4272.     case TIM_DMA_CC4:
  4273.     {
  4274.       /* Set the DMA compare callbacks */
  4275.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4276.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4277.  
  4278.       /* Set the DMA error callback */
  4279.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  4280.  
  4281.       /* Enable the DMA channel */
  4282.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
  4283.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4284.       {
  4285.         return HAL_ERROR;
  4286.       }
  4287.       break;
  4288.     }
  4289.     case TIM_DMA_TRIGGER:
  4290.     {
  4291.       /* Set the DMA trigger callbacks */
  4292.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
  4293.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
  4294.  
  4295.       /* Set the DMA error callback */
  4296.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
  4297.  
  4298.       /* Enable the DMA channel */
  4299.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
  4300.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4301.       {
  4302.         return HAL_ERROR;
  4303.       }
  4304.       break;
  4305.     }
  4306.     default:
  4307.       break;
  4308.   }
  4309.  
  4310.   /* Configure the DMA Burst Mode */
  4311.   htim->Instance->DCR = (BurstBaseAddress | BurstLength);
  4312.   /* Enable the TIM DMA Request */
  4313.   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
  4314.  
  4315.   /* Return function status */
  4316.   return HAL_OK;
  4317. }
  4318.  
  4319. /**
  4320.   * @brief  Stops the TIM DMA Burst mode
  4321.   * @param  htim TIM handle
  4322.   * @param  BurstRequestSrc TIM DMA Request sources to disable
  4323.   * @retval HAL status
  4324.   */
  4325. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
  4326. {
  4327.   HAL_StatusTypeDef status = HAL_OK;
  4328.   /* Check the parameters */
  4329.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4330.  
  4331.   /* Abort the DMA transfer (at least disable the DMA channel) */
  4332.   switch (BurstRequestSrc)
  4333.   {
  4334.     case TIM_DMA_UPDATE:
  4335.     {
  4336.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  4337.       break;
  4338.     }
  4339.     case TIM_DMA_CC1:
  4340.     {
  4341.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  4342.       break;
  4343.     }
  4344.     case TIM_DMA_CC2:
  4345.     {
  4346.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  4347.       break;
  4348.     }
  4349.     case TIM_DMA_CC3:
  4350.     {
  4351.       status =  HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  4352.       break;
  4353.     }
  4354.     case TIM_DMA_CC4:
  4355.     {
  4356.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  4357.       break;
  4358.     }
  4359.     case TIM_DMA_TRIGGER:
  4360.     {
  4361.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
  4362.       break;
  4363.     }
  4364.     default:
  4365.       break;
  4366.   }
  4367.  
  4368.   if (HAL_OK == status)
  4369.   {
  4370.     /* Disable the TIM Update DMA request */
  4371.     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
  4372.   }
  4373.  
  4374.   /* Change the DMA burst operation state */
  4375.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  4376.  
  4377.   /* Return function status */
  4378.   return status;
  4379. }
  4380.  
  4381. /**
  4382.   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
  4383.   * @param  htim TIM handle
  4384.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
  4385.   *         This parameter can be one of the following values:
  4386.   *            @arg TIM_DMABASE_CR1
  4387.   *            @arg TIM_DMABASE_CR2
  4388.   *            @arg TIM_DMABASE_SMCR
  4389.   *            @arg TIM_DMABASE_DIER
  4390.   *            @arg TIM_DMABASE_SR
  4391.   *            @arg TIM_DMABASE_EGR
  4392.   *            @arg TIM_DMABASE_CCMR1
  4393.   *            @arg TIM_DMABASE_CCMR2
  4394.   *            @arg TIM_DMABASE_CCER
  4395.   *            @arg TIM_DMABASE_CNT
  4396.   *            @arg TIM_DMABASE_PSC
  4397.   *            @arg TIM_DMABASE_ARR
  4398.   *            @arg TIM_DMABASE_CCR1
  4399.   *            @arg TIM_DMABASE_CCR2
  4400.   *            @arg TIM_DMABASE_CCR3
  4401.   *            @arg TIM_DMABASE_CCR4
  4402.   *            @arg TIM_DMABASE_OR
  4403.   * @param  BurstRequestSrc TIM DMA Request sources
  4404.   *         This parameter can be one of the following values:
  4405.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4406.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4407.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4408.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4409.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4410.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4411.   * @param  BurstBuffer The Buffer address.
  4412.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4413.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4414.   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
  4415.   * @retval HAL status
  4416.   */
  4417. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4418.                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
  4419. {
  4420.   return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
  4421.                                          ((BurstLength) >> 8U) + 1U);
  4422. }
  4423.  
  4424. /**
  4425.   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
  4426.   * @param  htim TIM handle
  4427.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
  4428.   *         This parameter can be one of the following values:
  4429.   *            @arg TIM_DMABASE_CR1
  4430.   *            @arg TIM_DMABASE_CR2
  4431.   *            @arg TIM_DMABASE_SMCR
  4432.   *            @arg TIM_DMABASE_DIER
  4433.   *            @arg TIM_DMABASE_SR
  4434.   *            @arg TIM_DMABASE_EGR
  4435.   *            @arg TIM_DMABASE_CCMR1
  4436.   *            @arg TIM_DMABASE_CCMR2
  4437.   *            @arg TIM_DMABASE_CCER
  4438.   *            @arg TIM_DMABASE_CNT
  4439.   *            @arg TIM_DMABASE_PSC
  4440.   *            @arg TIM_DMABASE_ARR
  4441.   *            @arg TIM_DMABASE_CCR1
  4442.   *            @arg TIM_DMABASE_CCR2
  4443.   *            @arg TIM_DMABASE_CCR3
  4444.   *            @arg TIM_DMABASE_CCR4
  4445.   *            @arg TIM_DMABASE_OR
  4446.   * @param  BurstRequestSrc TIM DMA Request sources
  4447.   *         This parameter can be one of the following values:
  4448.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4449.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4450.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4451.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4452.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4453.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4454.   * @param  BurstBuffer The Buffer address.
  4455.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4456.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4457.   * @param  DataLength Data length. This parameter can be one value
  4458.   *         between 1 and 0xFFFF.
  4459.   * @retval HAL status
  4460.   */
  4461. HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4462.                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
  4463.                                                   uint32_t  BurstLength, uint32_t  DataLength)
  4464. {
  4465.   /* Check the parameters */
  4466.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  4467.   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
  4468.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4469.   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
  4470.   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
  4471.  
  4472.   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
  4473.   {
  4474.     return HAL_BUSY;
  4475.   }
  4476.   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
  4477.   {
  4478.     if ((BurstBuffer == NULL) && (BurstLength > 0U))
  4479.     {
  4480.       return HAL_ERROR;
  4481.     }
  4482.     else
  4483.     {
  4484.       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
  4485.     }
  4486.   }
  4487.   else
  4488.   {
  4489.     /* nothing to do */
  4490.   }
  4491.   switch (BurstRequestSrc)
  4492.   {
  4493.     case TIM_DMA_UPDATE:
  4494.     {
  4495.       /* Set the DMA Period elapsed callbacks */
  4496.       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  4497.       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  4498.  
  4499.       /* Set the DMA error callback */
  4500.       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  4501.  
  4502.       /* Enable the DMA channel */
  4503.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4504.                            DataLength) != HAL_OK)
  4505.       {
  4506.         return HAL_ERROR;
  4507.       }
  4508.       break;
  4509.     }
  4510.     case TIM_DMA_CC1:
  4511.     {
  4512.       /* Set the DMA capture callbacks */
  4513.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  4514.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4515.  
  4516.       /* Set the DMA error callback */
  4517.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  4518.  
  4519.       /* Enable the DMA channel */
  4520.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4521.                            DataLength) != HAL_OK)
  4522.       {
  4523.         return HAL_ERROR;
  4524.       }
  4525.       break;
  4526.     }
  4527.     case TIM_DMA_CC2:
  4528.     {
  4529.       /* Set the DMA capture callbacks */
  4530.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  4531.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4532.  
  4533.       /* Set the DMA error callback */
  4534.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  4535.  
  4536.       /* Enable the DMA channel */
  4537.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4538.                            DataLength) != HAL_OK)
  4539.       {
  4540.         return HAL_ERROR;
  4541.       }
  4542.       break;
  4543.     }
  4544.     case TIM_DMA_CC3:
  4545.     {
  4546.       /* Set the DMA capture callbacks */
  4547.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
  4548.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4549.  
  4550.       /* Set the DMA error callback */
  4551.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  4552.  
  4553.       /* Enable the DMA channel */
  4554.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4555.                            DataLength) != HAL_OK)
  4556.       {
  4557.         return HAL_ERROR;
  4558.       }
  4559.       break;
  4560.     }
  4561.     case TIM_DMA_CC4:
  4562.     {
  4563.       /* Set the DMA capture callbacks */
  4564.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
  4565.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4566.  
  4567.       /* Set the DMA error callback */
  4568.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  4569.  
  4570.       /* Enable the DMA channel */
  4571.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4572.                            DataLength) != HAL_OK)
  4573.       {
  4574.         return HAL_ERROR;
  4575.       }
  4576.       break;
  4577.     }
  4578.     case TIM_DMA_TRIGGER:
  4579.     {
  4580.       /* Set the DMA trigger callbacks */
  4581.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
  4582.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
  4583.  
  4584.       /* Set the DMA error callback */
  4585.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
  4586.  
  4587.       /* Enable the DMA channel */
  4588.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4589.                            DataLength) != HAL_OK)
  4590.       {
  4591.         return HAL_ERROR;
  4592.       }
  4593.       break;
  4594.     }
  4595.     default:
  4596.       break;
  4597.   }
  4598.  
  4599.   /* Configure the DMA Burst Mode */
  4600.   htim->Instance->DCR = (BurstBaseAddress | BurstLength);
  4601.  
  4602.   /* Enable the TIM DMA Request */
  4603.   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
  4604.  
  4605.   /* Return function status */
  4606.   return HAL_OK;
  4607. }
  4608.  
  4609. /**
  4610.   * @brief  Stop the DMA burst reading
  4611.   * @param  htim TIM handle
  4612.   * @param  BurstRequestSrc TIM DMA Request sources to disable.
  4613.   * @retval HAL status
  4614.   */
  4615. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
  4616. {
  4617.   HAL_StatusTypeDef status = HAL_OK;
  4618.   /* Check the parameters */
  4619.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4620.  
  4621.   /* Abort the DMA transfer (at least disable the DMA channel) */
  4622.   switch (BurstRequestSrc)
  4623.   {
  4624.     case TIM_DMA_UPDATE:
  4625.     {
  4626.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  4627.       break;
  4628.     }
  4629.     case TIM_DMA_CC1:
  4630.     {
  4631.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  4632.       break;
  4633.     }
  4634.     case TIM_DMA_CC2:
  4635.     {
  4636.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  4637.       break;
  4638.     }
  4639.     case TIM_DMA_CC3:
  4640.     {
  4641.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  4642.       break;
  4643.     }
  4644.     case TIM_DMA_CC4:
  4645.     {
  4646.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  4647.       break;
  4648.     }
  4649.     case TIM_DMA_TRIGGER:
  4650.     {
  4651.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
  4652.       break;
  4653.     }
  4654.     default:
  4655.       break;
  4656.   }
  4657.  
  4658.   if (HAL_OK == status)
  4659.   {
  4660.     /* Disable the TIM Update DMA request */
  4661.     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
  4662.   }
  4663.  
  4664.   /* Change the DMA burst operation state */
  4665.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  4666.  
  4667.   /* Return function status */
  4668.   return status;
  4669. }
  4670.  
  4671. /**
  4672.   * @brief  Generate a software event
  4673.   * @param  htim TIM handle
  4674.   * @param  EventSource specifies the event source.
  4675.   *          This parameter can be one of the following values:
  4676.   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
  4677.   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
  4678.   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
  4679.   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
  4680.   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
  4681.   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
  4682.   * @note   Basic timers can only generate an update event.
  4683.   * @retval HAL status
  4684.   */
  4685.  
  4686. HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
  4687. {
  4688.   /* Check the parameters */
  4689.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  4690.   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
  4691.  
  4692.   /* Process Locked */
  4693.   __HAL_LOCK(htim);
  4694.  
  4695.   /* Change the TIM state */
  4696.   htim->State = HAL_TIM_STATE_BUSY;
  4697.  
  4698.   /* Set the event sources */
  4699.   htim->Instance->EGR = EventSource;
  4700.  
  4701.   /* Change the TIM state */
  4702.   htim->State = HAL_TIM_STATE_READY;
  4703.  
  4704.   __HAL_UNLOCK(htim);
  4705.  
  4706.   /* Return function status */
  4707.   return HAL_OK;
  4708. }
  4709.  
  4710. /**
  4711.   * @brief  Configures the OCRef clear feature
  4712.   * @param  htim TIM handle
  4713.   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
  4714.   *         contains the OCREF clear feature and parameters for the TIM peripheral.
  4715.   * @param  Channel specifies the TIM Channel
  4716.   *          This parameter can be one of the following values:
  4717.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  4718.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  4719.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  4720.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  4721.   * @retval HAL status
  4722.   */
  4723. HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
  4724.                                            TIM_ClearInputConfigTypeDef *sClearInputConfig,
  4725.                                            uint32_t Channel)
  4726. {
  4727.   /* Check the parameters */
  4728.   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
  4729.   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
  4730.  
  4731.   /* Process Locked */
  4732.   __HAL_LOCK(htim);
  4733.  
  4734.   htim->State = HAL_TIM_STATE_BUSY;
  4735.  
  4736.   switch (sClearInputConfig->ClearInputSource)
  4737.   {
  4738.     case TIM_CLEARINPUTSOURCE_NONE:
  4739.     {
  4740.       /* Clear the OCREF clear selection bit and the the ETR Bits */
  4741.       CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
  4742.       break;
  4743.     }
  4744.     case TIM_CLEARINPUTSOURCE_OCREFCLR:
  4745.     {
  4746.       /* Clear the OCREF clear selection bit */
  4747.       CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
  4748.     }
  4749.     break;
  4750.  
  4751.     case TIM_CLEARINPUTSOURCE_ETR:
  4752.     {
  4753.       /* Check the parameters */
  4754.       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
  4755.       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
  4756.       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
  4757.  
  4758.       /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
  4759.       if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
  4760.       {
  4761.         htim->State = HAL_TIM_STATE_READY;
  4762.         __HAL_UNLOCK(htim);
  4763.         return HAL_ERROR;
  4764.       }
  4765.  
  4766.       TIM_ETR_SetConfig(htim->Instance,
  4767.                         sClearInputConfig->ClearInputPrescaler,
  4768.                         sClearInputConfig->ClearInputPolarity,
  4769.                         sClearInputConfig->ClearInputFilter);
  4770.  
  4771.       /* Set the OCREF clear selection bit */
  4772.       SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
  4773.       break;
  4774.     }
  4775.  
  4776.     default:
  4777.       break;
  4778.   }
  4779.  
  4780.   switch (Channel)
  4781.   {
  4782.     case TIM_CHANNEL_1:
  4783.     {
  4784.       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  4785.       {
  4786.         /* Enable the OCREF clear feature for Channel 1 */
  4787.         SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
  4788.       }
  4789.       else
  4790.       {
  4791.         /* Disable the OCREF clear feature for Channel 1 */
  4792.         CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
  4793.       }
  4794.       break;
  4795.     }
  4796.     case TIM_CHANNEL_2:
  4797.     {
  4798.       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  4799.       {
  4800.         /* Enable the OCREF clear feature for Channel 2 */
  4801.         SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
  4802.       }
  4803.       else
  4804.       {
  4805.         /* Disable the OCREF clear feature for Channel 2 */
  4806.         CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
  4807.       }
  4808.       break;
  4809.     }
  4810.     case TIM_CHANNEL_3:
  4811.     {
  4812.       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  4813.       {
  4814.         /* Enable the OCREF clear feature for Channel 3 */
  4815.         SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
  4816.       }
  4817.       else
  4818.       {
  4819.         /* Disable the OCREF clear feature for Channel 3 */
  4820.         CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
  4821.       }
  4822.       break;
  4823.     }
  4824.     case TIM_CHANNEL_4:
  4825.     {
  4826.       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  4827.       {
  4828.         /* Enable the OCREF clear feature for Channel 4 */
  4829.         SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
  4830.       }
  4831.       else
  4832.       {
  4833.         /* Disable the OCREF clear feature for Channel 4 */
  4834.         CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
  4835.       }
  4836.       break;
  4837.     }
  4838.     default:
  4839.       break;
  4840.   }
  4841.  
  4842.   htim->State = HAL_TIM_STATE_READY;
  4843.  
  4844.   __HAL_UNLOCK(htim);
  4845.  
  4846.   return HAL_OK;
  4847. }
  4848.  
  4849. /**
  4850.   * @brief   Configures the clock source to be used
  4851.   * @param  htim TIM handle
  4852.   * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
  4853.   *         contains the clock source information for the TIM peripheral.
  4854.   * @retval HAL status
  4855.   */
  4856. HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
  4857. {
  4858.   uint32_t tmpsmcr;
  4859.  
  4860.   /* Process Locked */
  4861.   __HAL_LOCK(htim);
  4862.  
  4863.   htim->State = HAL_TIM_STATE_BUSY;
  4864.  
  4865.   /* Check the parameters */
  4866.   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
  4867.  
  4868.   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
  4869.   tmpsmcr = htim->Instance->SMCR;
  4870.   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
  4871.   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  4872.   htim->Instance->SMCR = tmpsmcr;
  4873.  
  4874.   switch (sClockSourceConfig->ClockSource)
  4875.   {
  4876.     case TIM_CLOCKSOURCE_INTERNAL:
  4877.     {
  4878.       assert_param(IS_TIM_INSTANCE(htim->Instance));
  4879.       break;
  4880.     }
  4881.  
  4882.     case TIM_CLOCKSOURCE_ETRMODE1:
  4883.     {
  4884.       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
  4885.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
  4886.  
  4887.       /* Check ETR input conditioning related parameters */
  4888.       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
  4889.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  4890.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  4891.  
  4892.       /* Configure the ETR Clock source */
  4893.       TIM_ETR_SetConfig(htim->Instance,
  4894.                         sClockSourceConfig->ClockPrescaler,
  4895.                         sClockSourceConfig->ClockPolarity,
  4896.                         sClockSourceConfig->ClockFilter);
  4897.  
  4898.       /* Select the External clock mode1 and the ETRF trigger */
  4899.       tmpsmcr = htim->Instance->SMCR;
  4900.       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
  4901.       /* Write to TIMx SMCR */
  4902.       htim->Instance->SMCR = tmpsmcr;
  4903.       break;
  4904.     }
  4905.  
  4906.     case TIM_CLOCKSOURCE_ETRMODE2:
  4907.     {
  4908.       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
  4909.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
  4910.  
  4911.       /* Check ETR input conditioning related parameters */
  4912.       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
  4913.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  4914.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  4915.  
  4916.       /* Configure the ETR Clock source */
  4917.       TIM_ETR_SetConfig(htim->Instance,
  4918.                         sClockSourceConfig->ClockPrescaler,
  4919.                         sClockSourceConfig->ClockPolarity,
  4920.                         sClockSourceConfig->ClockFilter);
  4921.       /* Enable the External clock mode2 */
  4922.       htim->Instance->SMCR |= TIM_SMCR_ECE;
  4923.       break;
  4924.     }
  4925.  
  4926.     case TIM_CLOCKSOURCE_TI1:
  4927.     {
  4928.       /* Check whether or not the timer instance supports external clock mode 1 */
  4929.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  4930.  
  4931.       /* Check TI1 input conditioning related parameters */
  4932.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  4933.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  4934.  
  4935.       TIM_TI1_ConfigInputStage(htim->Instance,
  4936.                                sClockSourceConfig->ClockPolarity,
  4937.                                sClockSourceConfig->ClockFilter);
  4938.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
  4939.       break;
  4940.     }
  4941.  
  4942.     case TIM_CLOCKSOURCE_TI2:
  4943.     {
  4944.       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
  4945.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  4946.  
  4947.       /* Check TI2 input conditioning related parameters */
  4948.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  4949.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  4950.  
  4951.       TIM_TI2_ConfigInputStage(htim->Instance,
  4952.                                sClockSourceConfig->ClockPolarity,
  4953.                                sClockSourceConfig->ClockFilter);
  4954.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
  4955.       break;
  4956.     }
  4957.  
  4958.     case TIM_CLOCKSOURCE_TI1ED:
  4959.     {
  4960.       /* Check whether or not the timer instance supports external clock mode 1 */
  4961.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  4962.  
  4963.       /* Check TI1 input conditioning related parameters */
  4964.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  4965.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  4966.  
  4967.       TIM_TI1_ConfigInputStage(htim->Instance,
  4968.                                sClockSourceConfig->ClockPolarity,
  4969.                                sClockSourceConfig->ClockFilter);
  4970.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
  4971.       break;
  4972.     }
  4973.  
  4974.     case TIM_CLOCKSOURCE_ITR0:
  4975.     case TIM_CLOCKSOURCE_ITR1:
  4976.     case TIM_CLOCKSOURCE_ITR2:
  4977.     case TIM_CLOCKSOURCE_ITR3:
  4978.       {
  4979.         /* Check whether or not the timer instance supports internal trigger input */
  4980.         assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
  4981.  
  4982.         TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
  4983.         break;
  4984.       }
  4985.  
  4986.     default:
  4987.       break;
  4988.   }
  4989.   htim->State = HAL_TIM_STATE_READY;
  4990.  
  4991.   __HAL_UNLOCK(htim);
  4992.  
  4993.   return HAL_OK;
  4994. }
  4995.  
  4996. /**
  4997.   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
  4998.   *         or a XOR combination between CH1_input, CH2_input & CH3_input
  4999.   * @param  htim TIM handle.
  5000.   * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
  5001.   *         output of a XOR gate.
  5002.   *          This parameter can be one of the following values:
  5003.   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  5004.   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
  5005.   *            pins are connected to the TI1 input (XOR combination)
  5006.   * @retval HAL status
  5007.   */
  5008. HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
  5009. {
  5010.   uint32_t tmpcr2;
  5011.  
  5012.   /* Check the parameters */
  5013.   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
  5014.   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
  5015.  
  5016.   /* Get the TIMx CR2 register value */
  5017.   tmpcr2 = htim->Instance->CR2;
  5018.  
  5019.   /* Reset the TI1 selection */
  5020.   tmpcr2 &= ~TIM_CR2_TI1S;
  5021.  
  5022.   /* Set the TI1 selection */
  5023.   tmpcr2 |= TI1_Selection;
  5024.  
  5025.   /* Write to TIMxCR2 */
  5026.   htim->Instance->CR2 = tmpcr2;
  5027.  
  5028.   return HAL_OK;
  5029. }
  5030.  
  5031. /**
  5032.   * @brief  Configures the TIM in Slave mode
  5033.   * @param  htim TIM handle.
  5034.   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
  5035.   *         contains the selected trigger (internal trigger input, filtered
  5036.   *         timer input or external trigger input) and the Slave mode
  5037.   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
  5038.   * @retval HAL status
  5039.   */
  5040. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
  5041. {
  5042.   /* Check the parameters */
  5043.   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
  5044.   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
  5045.   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
  5046.  
  5047.   __HAL_LOCK(htim);
  5048.  
  5049.   htim->State = HAL_TIM_STATE_BUSY;
  5050.  
  5051.   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
  5052.   {
  5053.     htim->State = HAL_TIM_STATE_READY;
  5054.     __HAL_UNLOCK(htim);
  5055.     return HAL_ERROR;
  5056.   }
  5057.  
  5058.   /* Disable Trigger Interrupt */
  5059.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
  5060.  
  5061.   /* Disable Trigger DMA request */
  5062.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
  5063.  
  5064.   htim->State = HAL_TIM_STATE_READY;
  5065.  
  5066.   __HAL_UNLOCK(htim);
  5067.  
  5068.   return HAL_OK;
  5069. }
  5070.  
  5071. /**
  5072.   * @brief  Configures the TIM in Slave mode in interrupt mode
  5073.   * @param  htim TIM handle.
  5074.   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
  5075.   *         contains the selected trigger (internal trigger input, filtered
  5076.   *         timer input or external trigger input) and the Slave mode
  5077.   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
  5078.   * @retval HAL status
  5079.   */
  5080. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
  5081.                                                 TIM_SlaveConfigTypeDef *sSlaveConfig)
  5082. {
  5083.   /* Check the parameters */
  5084.   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
  5085.   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
  5086.   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
  5087.  
  5088.   __HAL_LOCK(htim);
  5089.  
  5090.   htim->State = HAL_TIM_STATE_BUSY;
  5091.  
  5092.   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
  5093.   {
  5094.     htim->State = HAL_TIM_STATE_READY;
  5095.     __HAL_UNLOCK(htim);
  5096.     return HAL_ERROR;
  5097.   }
  5098.  
  5099.   /* Enable Trigger Interrupt */
  5100.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
  5101.  
  5102.   /* Disable Trigger DMA request */
  5103.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
  5104.  
  5105.   htim->State = HAL_TIM_STATE_READY;
  5106.  
  5107.   __HAL_UNLOCK(htim);
  5108.  
  5109.   return HAL_OK;
  5110. }
  5111.  
  5112. /**
  5113.   * @brief  Read the captured value from Capture Compare unit
  5114.   * @param  htim TIM handle.
  5115.   * @param  Channel TIM Channels to be enabled
  5116.   *          This parameter can be one of the following values:
  5117.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  5118.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  5119.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  5120.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  5121.   * @retval Captured value
  5122.   */
  5123. uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
  5124. {
  5125.   uint32_t tmpreg = 0U;
  5126.  
  5127.   switch (Channel)
  5128.   {
  5129.     case TIM_CHANNEL_1:
  5130.     {
  5131.       /* Check the parameters */
  5132.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  5133.  
  5134.       /* Return the capture 1 value */
  5135.       tmpreg =  htim->Instance->CCR1;
  5136.  
  5137.       break;
  5138.     }
  5139.     case TIM_CHANNEL_2:
  5140.     {
  5141.       /* Check the parameters */
  5142.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  5143.  
  5144.       /* Return the capture 2 value */
  5145.       tmpreg =   htim->Instance->CCR2;
  5146.  
  5147.       break;
  5148.     }
  5149.  
  5150.     case TIM_CHANNEL_3:
  5151.     {
  5152.       /* Check the parameters */
  5153.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  5154.  
  5155.       /* Return the capture 3 value */
  5156.       tmpreg =   htim->Instance->CCR3;
  5157.  
  5158.       break;
  5159.     }
  5160.  
  5161.     case TIM_CHANNEL_4:
  5162.     {
  5163.       /* Check the parameters */
  5164.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  5165.  
  5166.       /* Return the capture 4 value */
  5167.       tmpreg =   htim->Instance->CCR4;
  5168.  
  5169.       break;
  5170.     }
  5171.  
  5172.     default:
  5173.       break;
  5174.   }
  5175.  
  5176.   return tmpreg;
  5177. }
  5178.  
  5179. /**
  5180.   * @}
  5181.   */
  5182.  
  5183. /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
  5184.   *  @brief    TIM Callbacks functions
  5185.   *
  5186. @verbatim
  5187.   ==============================================================================
  5188.                         ##### TIM Callbacks functions #####
  5189.   ==============================================================================
  5190.  [..]
  5191.    This section provides TIM callback functions:
  5192.    (+) TIM Period elapsed callback
  5193.    (+) TIM Output Compare callback
  5194.    (+) TIM Input capture callback
  5195.    (+) TIM Trigger callback
  5196.    (+) TIM Error callback
  5197.  
  5198. @endverbatim
  5199.   * @{
  5200.   */
  5201.  
  5202. /**
  5203.   * @brief  Period elapsed callback in non-blocking mode
  5204.   * @param  htim TIM handle
  5205.   * @retval None
  5206.   */
  5207. __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
  5208. {
  5209.   /* Prevent unused argument(s) compilation warning */
  5210.   UNUSED(htim);
  5211.  
  5212.   /* NOTE : This function should not be modified, when the callback is needed,
  5213.             the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
  5214.    */
  5215. }
  5216.  
  5217. /**
  5218.   * @brief  Period elapsed half complete callback in non-blocking mode
  5219.   * @param  htim TIM handle
  5220.   * @retval None
  5221.   */
  5222. __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
  5223. {
  5224.   /* Prevent unused argument(s) compilation warning */
  5225.   UNUSED(htim);
  5226.  
  5227.   /* NOTE : This function should not be modified, when the callback is needed,
  5228.             the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
  5229.    */
  5230. }
  5231.  
  5232. /**
  5233.   * @brief  Output Compare callback in non-blocking mode
  5234.   * @param  htim TIM OC handle
  5235.   * @retval None
  5236.   */
  5237. __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
  5238. {
  5239.   /* Prevent unused argument(s) compilation warning */
  5240.   UNUSED(htim);
  5241.  
  5242.   /* NOTE : This function should not be modified, when the callback is needed,
  5243.             the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
  5244.    */
  5245. }
  5246.  
  5247. /**
  5248.   * @brief  Input Capture callback in non-blocking mode
  5249.   * @param  htim TIM IC handle
  5250.   * @retval None
  5251.   */
  5252. __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
  5253. {
  5254.   /* Prevent unused argument(s) compilation warning */
  5255.   UNUSED(htim);
  5256.  
  5257.   /* NOTE : This function should not be modified, when the callback is needed,
  5258.             the HAL_TIM_IC_CaptureCallback could be implemented in the user file
  5259.    */
  5260. }
  5261.  
  5262. /**
  5263.   * @brief  Input Capture half complete callback in non-blocking mode
  5264.   * @param  htim TIM IC handle
  5265.   * @retval None
  5266.   */
  5267. __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
  5268. {
  5269.   /* Prevent unused argument(s) compilation warning */
  5270.   UNUSED(htim);
  5271.  
  5272.   /* NOTE : This function should not be modified, when the callback is needed,
  5273.             the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
  5274.    */
  5275. }
  5276.  
  5277. /**
  5278.   * @brief  PWM Pulse finished callback in non-blocking mode
  5279.   * @param  htim TIM handle
  5280.   * @retval None
  5281.   */
  5282. __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
  5283. {
  5284.   /* Prevent unused argument(s) compilation warning */
  5285.   UNUSED(htim);
  5286.  
  5287.   /* NOTE : This function should not be modified, when the callback is needed,
  5288.             the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
  5289.    */
  5290. }
  5291.  
  5292. /**
  5293.   * @brief  PWM Pulse finished half complete callback in non-blocking mode
  5294.   * @param  htim TIM handle
  5295.   * @retval None
  5296.   */
  5297. __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
  5298. {
  5299.   /* Prevent unused argument(s) compilation warning */
  5300.   UNUSED(htim);
  5301.  
  5302.   /* NOTE : This function should not be modified, when the callback is needed,
  5303.             the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
  5304.    */
  5305. }
  5306.  
  5307. /**
  5308.   * @brief  Hall Trigger detection callback in non-blocking mode
  5309.   * @param  htim TIM handle
  5310.   * @retval None
  5311.   */
  5312. __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
  5313. {
  5314.   /* Prevent unused argument(s) compilation warning */
  5315.   UNUSED(htim);
  5316.  
  5317.   /* NOTE : This function should not be modified, when the callback is needed,
  5318.             the HAL_TIM_TriggerCallback could be implemented in the user file
  5319.    */
  5320. }
  5321.  
  5322. /**
  5323.   * @brief  Hall Trigger detection half complete callback in non-blocking mode
  5324.   * @param  htim TIM handle
  5325.   * @retval None
  5326.   */
  5327. __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
  5328. {
  5329.   /* Prevent unused argument(s) compilation warning */
  5330.   UNUSED(htim);
  5331.  
  5332.   /* NOTE : This function should not be modified, when the callback is needed,
  5333.             the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
  5334.    */
  5335. }
  5336.  
  5337. /**
  5338.   * @brief  Timer error callback in non-blocking mode
  5339.   * @param  htim TIM handle
  5340.   * @retval None
  5341.   */
  5342. __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
  5343. {
  5344.   /* Prevent unused argument(s) compilation warning */
  5345.   UNUSED(htim);
  5346.  
  5347.   /* NOTE : This function should not be modified, when the callback is needed,
  5348.             the HAL_TIM_ErrorCallback could be implemented in the user file
  5349.    */
  5350. }
  5351.  
  5352. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  5353. /**
  5354.   * @brief  Register a User TIM callback to be used instead of the weak predefined callback
  5355.   * @param htim tim handle
  5356.   * @param CallbackID ID of the callback to be registered
  5357.   *        This parameter can be one of the following values:
  5358.   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  5359.   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  5360.   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  5361.   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  5362.   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  5363.   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  5364.   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  5365.   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  5366.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  5367.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  5368.   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  5369.   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  5370.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  5371.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  5372.   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  5373.   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  5374.   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  5375.   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  5376.   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  5377.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  5378.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  5379.   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
  5380.   *          @param pCallback pointer to the callback function
  5381.   *          @retval status
  5382.   */
  5383. HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
  5384.                                            pTIM_CallbackTypeDef pCallback)
  5385. {
  5386.   HAL_StatusTypeDef status = HAL_OK;
  5387.  
  5388.   if (pCallback == NULL)
  5389.   {
  5390.     return HAL_ERROR;
  5391.   }
  5392.   /* Process locked */
  5393.   __HAL_LOCK(htim);
  5394.  
  5395.   if (htim->State == HAL_TIM_STATE_READY)
  5396.   {
  5397.     switch (CallbackID)
  5398.     {
  5399.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5400.         htim->Base_MspInitCallback                 = pCallback;
  5401.         break;
  5402.  
  5403.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5404.         htim->Base_MspDeInitCallback               = pCallback;
  5405.         break;
  5406.  
  5407.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5408.         htim->IC_MspInitCallback                   = pCallback;
  5409.         break;
  5410.  
  5411.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5412.         htim->IC_MspDeInitCallback                 = pCallback;
  5413.         break;
  5414.  
  5415.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5416.         htim->OC_MspInitCallback                   = pCallback;
  5417.         break;
  5418.  
  5419.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5420.         htim->OC_MspDeInitCallback                 = pCallback;
  5421.         break;
  5422.  
  5423.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5424.         htim->PWM_MspInitCallback                  = pCallback;
  5425.         break;
  5426.  
  5427.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  5428.         htim->PWM_MspDeInitCallback                = pCallback;
  5429.         break;
  5430.  
  5431.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  5432.         htim->OnePulse_MspInitCallback             = pCallback;
  5433.         break;
  5434.  
  5435.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  5436.         htim->OnePulse_MspDeInitCallback           = pCallback;
  5437.         break;
  5438.  
  5439.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  5440.         htim->Encoder_MspInitCallback              = pCallback;
  5441.         break;
  5442.  
  5443.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  5444.         htim->Encoder_MspDeInitCallback            = pCallback;
  5445.         break;
  5446.  
  5447.       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
  5448.         htim->PeriodElapsedCallback                = pCallback;
  5449.         break;
  5450.  
  5451.       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
  5452.         htim->PeriodElapsedHalfCpltCallback        = pCallback;
  5453.         break;
  5454.  
  5455.       case HAL_TIM_TRIGGER_CB_ID :
  5456.         htim->TriggerCallback                      = pCallback;
  5457.         break;
  5458.  
  5459.       case HAL_TIM_TRIGGER_HALF_CB_ID :
  5460.         htim->TriggerHalfCpltCallback              = pCallback;
  5461.         break;
  5462.  
  5463.       case HAL_TIM_IC_CAPTURE_CB_ID :
  5464.         htim->IC_CaptureCallback                   = pCallback;
  5465.         break;
  5466.  
  5467.       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
  5468.         htim->IC_CaptureHalfCpltCallback           = pCallback;
  5469.         break;
  5470.  
  5471.       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
  5472.         htim->OC_DelayElapsedCallback              = pCallback;
  5473.         break;
  5474.  
  5475.       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
  5476.         htim->PWM_PulseFinishedCallback            = pCallback;
  5477.         break;
  5478.  
  5479.       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
  5480.         htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
  5481.         break;
  5482.  
  5483.       case HAL_TIM_ERROR_CB_ID :
  5484.         htim->ErrorCallback                        = pCallback;
  5485.         break;
  5486.  
  5487.       default :
  5488.         /* Return error status */
  5489.         status =  HAL_ERROR;
  5490.         break;
  5491.     }
  5492.   }
  5493.   else if (htim->State == HAL_TIM_STATE_RESET)
  5494.   {
  5495.     switch (CallbackID)
  5496.     {
  5497.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5498.         htim->Base_MspInitCallback         = pCallback;
  5499.         break;
  5500.  
  5501.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5502.         htim->Base_MspDeInitCallback       = pCallback;
  5503.         break;
  5504.  
  5505.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5506.         htim->IC_MspInitCallback           = pCallback;
  5507.         break;
  5508.  
  5509.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5510.         htim->IC_MspDeInitCallback         = pCallback;
  5511.         break;
  5512.  
  5513.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5514.         htim->OC_MspInitCallback           = pCallback;
  5515.         break;
  5516.  
  5517.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5518.         htim->OC_MspDeInitCallback         = pCallback;
  5519.         break;
  5520.  
  5521.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5522.         htim->PWM_MspInitCallback          = pCallback;
  5523.         break;
  5524.  
  5525.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  5526.         htim->PWM_MspDeInitCallback        = pCallback;
  5527.         break;
  5528.  
  5529.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  5530.         htim->OnePulse_MspInitCallback     = pCallback;
  5531.         break;
  5532.  
  5533.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  5534.         htim->OnePulse_MspDeInitCallback   = pCallback;
  5535.         break;
  5536.  
  5537.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  5538.         htim->Encoder_MspInitCallback      = pCallback;
  5539.         break;
  5540.  
  5541.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  5542.         htim->Encoder_MspDeInitCallback    = pCallback;
  5543.         break;
  5544.  
  5545.       default :
  5546.         /* Return error status */
  5547.         status =  HAL_ERROR;
  5548.         break;
  5549.     }
  5550.   }
  5551.   else
  5552.   {
  5553.     /* Return error status */
  5554.     status =  HAL_ERROR;
  5555.   }
  5556.  
  5557.   /* Release Lock */
  5558.   __HAL_UNLOCK(htim);
  5559.  
  5560.   return status;
  5561. }
  5562.  
  5563. /**
  5564.   * @brief  Unregister a TIM callback
  5565.   *         TIM callback is redirected to the weak predefined callback
  5566.   * @param htim tim handle
  5567.   * @param CallbackID ID of the callback to be unregistered
  5568.   *        This parameter can be one of the following values:
  5569.   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  5570.   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  5571.   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  5572.   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  5573.   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  5574.   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  5575.   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  5576.   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  5577.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  5578.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  5579.   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  5580.   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  5581.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  5582.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  5583.   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  5584.   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  5585.   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  5586.   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  5587.   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  5588.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  5589.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  5590.   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
  5591.   *          @retval status
  5592.   */
  5593. HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
  5594. {
  5595.   HAL_StatusTypeDef status = HAL_OK;
  5596.  
  5597.   /* Process locked */
  5598.   __HAL_LOCK(htim);
  5599.  
  5600.   if (htim->State == HAL_TIM_STATE_READY)
  5601.   {
  5602.     switch (CallbackID)
  5603.     {
  5604.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5605.         htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;                      /* Legacy weak Base MspInit Callback */
  5606.         break;
  5607.  
  5608.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5609.         htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;                    /* Legacy weak Base Msp DeInit Callback */
  5610.         break;
  5611.  
  5612.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5613.         htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;                        /* Legacy weak IC Msp Init Callback */
  5614.         break;
  5615.  
  5616.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5617.         htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;                      /* Legacy weak IC Msp DeInit Callback */
  5618.         break;
  5619.  
  5620.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5621.         htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;                        /* Legacy weak OC Msp Init Callback */
  5622.         break;
  5623.  
  5624.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5625.         htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;                      /* Legacy weak OC Msp DeInit Callback */
  5626.         break;
  5627.  
  5628.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5629.         htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;                       /* Legacy weak PWM Msp Init Callback */
  5630.         break;
  5631.  
  5632.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  5633.         htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;                     /* Legacy weak PWM Msp DeInit Callback */
  5634.         break;
  5635.  
  5636.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  5637.         htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;                  /* Legacy weak One Pulse Msp Init Callback */
  5638.         break;
  5639.  
  5640.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  5641.         htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;                /* Legacy weak One Pulse Msp DeInit Callback */
  5642.         break;
  5643.  
  5644.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  5645.         htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;                   /* Legacy weak Encoder Msp Init Callback */
  5646.         break;
  5647.  
  5648.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  5649.         htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;                 /* Legacy weak Encoder Msp DeInit Callback */
  5650.         break;
  5651.  
  5652.       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
  5653.         htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak Period Elapsed Callback */
  5654.         break;
  5655.  
  5656.       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
  5657.         htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak Period Elapsed half complete Callback */
  5658.         break;
  5659.  
  5660.       case HAL_TIM_TRIGGER_CB_ID :
  5661.         htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak Trigger Callback */
  5662.         break;
  5663.  
  5664.       case HAL_TIM_TRIGGER_HALF_CB_ID :
  5665.         htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak Trigger half complete Callback */
  5666.         break;
  5667.  
  5668.       case HAL_TIM_IC_CAPTURE_CB_ID :
  5669.         htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC Capture Callback */
  5670.         break;
  5671.  
  5672.       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
  5673.         htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC Capture half complete Callback */
  5674.         break;
  5675.  
  5676.       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
  5677.         htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC Delay Elapsed Callback */
  5678.         break;
  5679.  
  5680.       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
  5681.         htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM Pulse Finished Callback */
  5682.         break;
  5683.  
  5684.       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
  5685.         htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
  5686.         break;
  5687.  
  5688.       case HAL_TIM_ERROR_CB_ID :
  5689.         htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak Error Callback */
  5690.         break;
  5691.  
  5692.       default :
  5693.         /* Return error status */
  5694.         status =  HAL_ERROR;
  5695.         break;
  5696.     }
  5697.   }
  5698.   else if (htim->State == HAL_TIM_STATE_RESET)
  5699.   {
  5700.     switch (CallbackID)
  5701.     {
  5702.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5703.         htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */
  5704.         break;
  5705.  
  5706.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5707.         htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */
  5708.         break;
  5709.  
  5710.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5711.         htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */
  5712.         break;
  5713.  
  5714.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5715.         htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */
  5716.         break;
  5717.  
  5718.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5719.         htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */
  5720.         break;
  5721.  
  5722.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5723.         htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */
  5724.         break;
  5725.  
  5726.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5727.         htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */
  5728.         break;
  5729.  
  5730.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  5731.         htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */
  5732.         break;
  5733.  
  5734.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  5735.         htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */
  5736.         break;
  5737.  
  5738.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  5739.         htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */
  5740.         break;
  5741.  
  5742.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  5743.         htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */
  5744.         break;
  5745.  
  5746.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  5747.         htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */
  5748.         break;
  5749.  
  5750.       default :
  5751.         /* Return error status */
  5752.         status =  HAL_ERROR;
  5753.         break;
  5754.     }
  5755.   }
  5756.   else
  5757.   {
  5758.     /* Return error status */
  5759.     status =  HAL_ERROR;
  5760.   }
  5761.  
  5762.   /* Release Lock */
  5763.   __HAL_UNLOCK(htim);
  5764.  
  5765.   return status;
  5766. }
  5767. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  5768.  
  5769. /**
  5770.   * @}
  5771.   */
  5772.  
  5773. /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
  5774.   *  @brief   TIM Peripheral State functions
  5775.   *
  5776. @verbatim
  5777.   ==============================================================================
  5778.                         ##### Peripheral State functions #####
  5779.   ==============================================================================
  5780.     [..]
  5781.     This subsection permits to get in run-time the status of the peripheral
  5782.     and the data flow.
  5783.  
  5784. @endverbatim
  5785.   * @{
  5786.   */
  5787.  
  5788. /**
  5789.   * @brief  Return the TIM Base handle state.
  5790.   * @param  htim TIM Base handle
  5791.   * @retval HAL state
  5792.   */
  5793. HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
  5794. {
  5795.   return htim->State;
  5796. }
  5797.  
  5798. /**
  5799.   * @brief  Return the TIM OC handle state.
  5800.   * @param  htim TIM Output Compare handle
  5801.   * @retval HAL state
  5802.   */
  5803. HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
  5804. {
  5805.   return htim->State;
  5806. }
  5807.  
  5808. /**
  5809.   * @brief  Return the TIM PWM handle state.
  5810.   * @param  htim TIM handle
  5811.   * @retval HAL state
  5812.   */
  5813. HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
  5814. {
  5815.   return htim->State;
  5816. }
  5817.  
  5818. /**
  5819.   * @brief  Return the TIM Input Capture handle state.
  5820.   * @param  htim TIM IC handle
  5821.   * @retval HAL state
  5822.   */
  5823. HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
  5824. {
  5825.   return htim->State;
  5826. }
  5827.  
  5828. /**
  5829.   * @brief  Return the TIM One Pulse Mode handle state.
  5830.   * @param  htim TIM OPM handle
  5831.   * @retval HAL state
  5832.   */
  5833. HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
  5834. {
  5835.   return htim->State;
  5836. }
  5837.  
  5838. /**
  5839.   * @brief  Return the TIM Encoder Mode handle state.
  5840.   * @param  htim TIM Encoder Interface handle
  5841.   * @retval HAL state
  5842.   */
  5843. HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
  5844. {
  5845.   return htim->State;
  5846. }
  5847.  
  5848. /**
  5849.   * @brief  Return the TIM Encoder Mode handle state.
  5850.   * @param  htim TIM handle
  5851.   * @retval Active channel
  5852.   */
  5853. HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
  5854. {
  5855.   return htim->Channel;
  5856. }
  5857.  
  5858. /**
  5859.   * @brief  Return actual state of the TIM channel.
  5860.   * @param  htim TIM handle
  5861.   * @param  Channel TIM Channel
  5862.   *          This parameter can be one of the following values:
  5863.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  5864.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  5865.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  5866.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  5867.   *            @arg TIM_CHANNEL_5: TIM Channel 5
  5868.   *            @arg TIM_CHANNEL_6: TIM Channel 6
  5869.   * @retval TIM Channel state
  5870.   */
  5871. HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel)
  5872. {
  5873.   HAL_TIM_ChannelStateTypeDef channel_state;
  5874.  
  5875.   /* Check the parameters */
  5876.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  5877.  
  5878.   channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  5879.    
  5880.   return channel_state;
  5881. }
  5882.  
  5883. /**
  5884.   * @brief  Return actual state of a DMA burst operation.
  5885.   * @param  htim TIM handle
  5886.   * @retval DMA burst state
  5887.   */
  5888. HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
  5889. {
  5890.   /* Check the parameters */
  5891.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  5892.  
  5893.   return htim->DMABurstState;
  5894. }
  5895.  
  5896. /**
  5897.   * @}
  5898.   */
  5899.  
  5900. /**
  5901.   * @}
  5902.   */
  5903.  
  5904. /** @defgroup TIM_Private_Functions TIM Private Functions
  5905.   * @{
  5906.   */
  5907.  
  5908. /**
  5909.   * @brief  TIM DMA error callback
  5910.   * @param  hdma pointer to DMA handle.
  5911.   * @retval None
  5912.   */
  5913. void TIM_DMAError(DMA_HandleTypeDef *hdma)
  5914. {
  5915.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  5916.  
  5917.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  5918.   {
  5919.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  5920.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  5921.   }
  5922.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  5923.   {
  5924.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  5925.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  5926.   }
  5927.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  5928.   {
  5929.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  5930.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  5931.   }
  5932.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  5933.   {
  5934.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  5935.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  5936.   }
  5937.   else
  5938.   {
  5939.     htim->State = HAL_TIM_STATE_READY;
  5940.   }
  5941.  
  5942. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  5943.   htim->ErrorCallback(htim);
  5944. #else
  5945.   HAL_TIM_ErrorCallback(htim);
  5946. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  5947.  
  5948.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  5949. }
  5950.  
  5951. /**
  5952.   * @brief  TIM DMA Delay Pulse complete callback.
  5953.   * @param  hdma pointer to DMA handle.
  5954.   * @retval None
  5955.   */
  5956. void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
  5957. {
  5958.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  5959.  
  5960.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  5961.   {
  5962.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  5963.    
  5964.     if (hdma->Init.Mode == DMA_NORMAL)
  5965.     {
  5966.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  5967.     }
  5968.   }
  5969.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  5970.   {
  5971.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  5972.    
  5973.     if (hdma->Init.Mode == DMA_NORMAL)
  5974.     {
  5975.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  5976.     }
  5977.   }
  5978.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  5979.   {
  5980.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  5981.    
  5982.     if (hdma->Init.Mode == DMA_NORMAL)
  5983.     {
  5984.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  5985.     }
  5986.   }
  5987.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  5988.   {
  5989.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  5990.    
  5991.     if (hdma->Init.Mode == DMA_NORMAL)
  5992.     {
  5993.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  5994.     }
  5995.   }
  5996.   else
  5997.   {
  5998.     /* nothing to do */
  5999.   }
  6000.  
  6001. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6002.   htim->PWM_PulseFinishedCallback(htim);
  6003. #else
  6004.   HAL_TIM_PWM_PulseFinishedCallback(htim);
  6005. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6006.  
  6007.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6008. }
  6009.  
  6010. /**
  6011.   * @brief  TIM DMA Delay Pulse half complete callback.
  6012.   * @param  hdma pointer to DMA handle.
  6013.   * @retval None
  6014.   */
  6015. void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
  6016. {
  6017.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6018.  
  6019.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6020.   {
  6021.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6022.   }
  6023.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6024.   {
  6025.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6026.   }
  6027.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6028.   {
  6029.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6030.   }
  6031.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6032.   {
  6033.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6034.   }
  6035.   else
  6036.   {
  6037.     /* nothing to do */
  6038.   }
  6039.  
  6040. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6041.   htim->PWM_PulseFinishedHalfCpltCallback(htim);
  6042. #else
  6043.   HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
  6044. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6045.  
  6046.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6047. }
  6048.  
  6049. /**
  6050.   * @brief  TIM DMA Capture complete callback.
  6051.   * @param  hdma pointer to DMA handle.
  6052.   * @retval None
  6053.   */
  6054. void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
  6055. {
  6056.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6057.  
  6058.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6059.   {
  6060.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6061.    
  6062.     if (hdma->Init.Mode == DMA_NORMAL)
  6063.     {
  6064.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6065.     }
  6066.   }
  6067.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6068.   {
  6069.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6070.    
  6071.     if (hdma->Init.Mode == DMA_NORMAL)
  6072.     {
  6073.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6074.     }
  6075.   }
  6076.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6077.   {
  6078.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6079.    
  6080.     if (hdma->Init.Mode == DMA_NORMAL)
  6081.     {
  6082.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6083.     }
  6084.   }
  6085.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6086.   {
  6087.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6088.    
  6089.     if (hdma->Init.Mode == DMA_NORMAL)
  6090.     {
  6091.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6092.     }
  6093.   }
  6094.   else
  6095.   {
  6096.     /* nothing to do */
  6097.   }
  6098.  
  6099. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6100.   htim->IC_CaptureCallback(htim);
  6101. #else
  6102.   HAL_TIM_IC_CaptureCallback(htim);
  6103. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6104.  
  6105.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6106. }
  6107.  
  6108. /**
  6109.   * @brief  TIM DMA Capture half complete callback.
  6110.   * @param  hdma pointer to DMA handle.
  6111.   * @retval None
  6112.   */
  6113. void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
  6114. {
  6115.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6116.  
  6117.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6118.   {
  6119.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6120.   }
  6121.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6122.   {
  6123.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6124.   }
  6125.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6126.   {
  6127.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6128.   }
  6129.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6130.   {
  6131.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6132.   }
  6133.   else
  6134.   {
  6135.     /* nothing to do */
  6136.   }
  6137.  
  6138. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6139.   htim->IC_CaptureHalfCpltCallback(htim);
  6140. #else
  6141.   HAL_TIM_IC_CaptureHalfCpltCallback(htim);
  6142. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6143.  
  6144.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6145. }
  6146.  
  6147. /**
  6148.   * @brief  TIM DMA Period Elapse complete callback.
  6149.   * @param  hdma pointer to DMA handle.
  6150.   * @retval None
  6151.   */
  6152. static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
  6153. {
  6154.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6155.  
  6156.   if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
  6157.   {
  6158.     htim->State = HAL_TIM_STATE_READY;
  6159.   }
  6160.  
  6161. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6162.   htim->PeriodElapsedCallback(htim);
  6163. #else
  6164.   HAL_TIM_PeriodElapsedCallback(htim);
  6165. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6166. }
  6167.  
  6168. /**
  6169.   * @brief  TIM DMA Period Elapse half complete callback.
  6170.   * @param  hdma pointer to DMA handle.
  6171.   * @retval None
  6172.   */
  6173. static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
  6174. {
  6175.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6176.  
  6177. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6178.   htim->PeriodElapsedHalfCpltCallback(htim);
  6179. #else
  6180.   HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
  6181. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6182. }
  6183.  
  6184. /**
  6185.   * @brief  TIM DMA Trigger callback.
  6186.   * @param  hdma pointer to DMA handle.
  6187.   * @retval None
  6188.   */
  6189. static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
  6190. {
  6191.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6192.  
  6193.   if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
  6194.   {
  6195.     htim->State = HAL_TIM_STATE_READY;
  6196.   }
  6197.  
  6198. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6199.   htim->TriggerCallback(htim);
  6200. #else
  6201.   HAL_TIM_TriggerCallback(htim);
  6202. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6203. }
  6204.  
  6205. /**
  6206.   * @brief  TIM DMA Trigger half complete callback.
  6207.   * @param  hdma pointer to DMA handle.
  6208.   * @retval None
  6209.   */
  6210. static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
  6211. {
  6212.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6213.  
  6214. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6215.   htim->TriggerHalfCpltCallback(htim);
  6216. #else
  6217.   HAL_TIM_TriggerHalfCpltCallback(htim);
  6218. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6219. }
  6220.  
  6221. /**
  6222.   * @brief  Time Base configuration
  6223.   * @param  TIMx TIM peripheral
  6224.   * @param  Structure TIM Base configuration structure
  6225.   * @retval None
  6226.   */
  6227. void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
  6228. {
  6229.   uint32_t tmpcr1;
  6230.   tmpcr1 = TIMx->CR1;
  6231.  
  6232.   /* Set TIM Time Base Unit parameters ---------------------------------------*/
  6233.   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  6234.   {
  6235.     /* Select the Counter Mode */
  6236.     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
  6237.     tmpcr1 |= Structure->CounterMode;
  6238.   }
  6239.  
  6240.   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  6241.   {
  6242.     /* Set the clock division */
  6243.     tmpcr1 &= ~TIM_CR1_CKD;
  6244.     tmpcr1 |= (uint32_t)Structure->ClockDivision;
  6245.   }
  6246.  
  6247.   /* Set the auto-reload preload */
  6248.   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
  6249.  
  6250.   TIMx->CR1 = tmpcr1;
  6251.  
  6252.   /* Set the Autoreload value */
  6253.   TIMx->ARR = (uint32_t)Structure->Period ;
  6254.  
  6255.   /* Set the Prescaler value */
  6256.   TIMx->PSC = Structure->Prescaler;
  6257.  
  6258.   /* Generate an update event to reload the Prescaler
  6259.      and the repetition counter (only for advanced timer) value immediately */
  6260.   TIMx->EGR = TIM_EGR_UG;
  6261. }
  6262.  
  6263. /**
  6264.   * @brief  Timer Output Compare 1 configuration
  6265.   * @param  TIMx to select the TIM peripheral
  6266.   * @param  OC_Config The output configuration structure
  6267.   * @retval None
  6268.   */
  6269. static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6270. {
  6271.   uint32_t tmpccmrx;
  6272.   uint32_t tmpccer;
  6273.   uint32_t tmpcr2;
  6274.  
  6275.   /* Disable the Channel 1: Reset the CC1E Bit */
  6276.   TIMx->CCER &= ~TIM_CCER_CC1E;
  6277.  
  6278.   /* Get the TIMx CCER register value */
  6279.   tmpccer = TIMx->CCER;
  6280.   /* Get the TIMx CR2 register value */
  6281.   tmpcr2 =  TIMx->CR2;
  6282.  
  6283.   /* Get the TIMx CCMR1 register value */
  6284.   tmpccmrx = TIMx->CCMR1;
  6285.  
  6286.   /* Reset the Output Compare Mode Bits */
  6287.   tmpccmrx &= ~TIM_CCMR1_OC1M;
  6288.   tmpccmrx &= ~TIM_CCMR1_CC1S;
  6289.   /* Select the Output Compare Mode */
  6290.   tmpccmrx |= OC_Config->OCMode;
  6291.  
  6292.   /* Reset the Output Polarity level */
  6293.   tmpccer &= ~TIM_CCER_CC1P;
  6294.   /* Set the Output Compare Polarity */
  6295.   tmpccer |= OC_Config->OCPolarity;
  6296.  
  6297.   /* Write to TIMx CR2 */
  6298.   TIMx->CR2 = tmpcr2;
  6299.  
  6300.   /* Write to TIMx CCMR1 */
  6301.   TIMx->CCMR1 = tmpccmrx;
  6302.  
  6303.   /* Set the Capture Compare Register value */
  6304.   TIMx->CCR1 = OC_Config->Pulse;
  6305.  
  6306.   /* Write to TIMx CCER */
  6307.   TIMx->CCER = tmpccer;
  6308. }
  6309.  
  6310. /**
  6311.   * @brief  Timer Output Compare 2 configuration
  6312.   * @param  TIMx to select the TIM peripheral
  6313.   * @param  OC_Config The output configuration structure
  6314.   * @retval None
  6315.   */
  6316. static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6317. {
  6318.   uint32_t tmpccmrx;
  6319.   uint32_t tmpccer;
  6320.   uint32_t tmpcr2;
  6321.  
  6322.   /* Disable the Channel 2: Reset the CC2E Bit */
  6323.   TIMx->CCER &= ~TIM_CCER_CC2E;
  6324.  
  6325.   /* Get the TIMx CCER register value */
  6326.   tmpccer = TIMx->CCER;
  6327.   /* Get the TIMx CR2 register value */
  6328.   tmpcr2 =  TIMx->CR2;
  6329.  
  6330.   /* Get the TIMx CCMR1 register value */
  6331.   tmpccmrx = TIMx->CCMR1;
  6332.  
  6333.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  6334.   tmpccmrx &= ~TIM_CCMR1_OC2M;
  6335.   tmpccmrx &= ~TIM_CCMR1_CC2S;
  6336.  
  6337.   /* Select the Output Compare Mode */
  6338.   tmpccmrx |= (OC_Config->OCMode << 8U);
  6339.  
  6340.   /* Reset the Output Polarity level */
  6341.   tmpccer &= ~TIM_CCER_CC2P;
  6342.   /* Set the Output Compare Polarity */
  6343.   tmpccer |= (OC_Config->OCPolarity << 4U);
  6344.  
  6345.   /* Write to TIMx CR2 */
  6346.   TIMx->CR2 = tmpcr2;
  6347.  
  6348.   /* Write to TIMx CCMR1 */
  6349.   TIMx->CCMR1 = tmpccmrx;
  6350.  
  6351.   /* Set the Capture Compare Register value */
  6352.   TIMx->CCR2 = OC_Config->Pulse;
  6353.  
  6354.   /* Write to TIMx CCER */
  6355.   TIMx->CCER = tmpccer;
  6356. }
  6357.  
  6358. /**
  6359.   * @brief  Timer Output Compare 3 configuration
  6360.   * @param  TIMx to select the TIM peripheral
  6361.   * @param  OC_Config The output configuration structure
  6362.   * @retval None
  6363.   */
  6364. static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6365. {
  6366.   uint32_t tmpccmrx;
  6367.   uint32_t tmpccer;
  6368.   uint32_t tmpcr2;
  6369.  
  6370.   /* Disable the Channel 3: Reset the CC2E Bit */
  6371.   TIMx->CCER &= ~TIM_CCER_CC3E;
  6372.  
  6373.   /* Get the TIMx CCER register value */
  6374.   tmpccer = TIMx->CCER;
  6375.   /* Get the TIMx CR2 register value */
  6376.   tmpcr2 =  TIMx->CR2;
  6377.  
  6378.   /* Get the TIMx CCMR2 register value */
  6379.   tmpccmrx = TIMx->CCMR2;
  6380.  
  6381.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  6382.   tmpccmrx &= ~TIM_CCMR2_OC3M;
  6383.   tmpccmrx &= ~TIM_CCMR2_CC3S;
  6384.   /* Select the Output Compare Mode */
  6385.   tmpccmrx |= OC_Config->OCMode;
  6386.  
  6387.   /* Reset the Output Polarity level */
  6388.   tmpccer &= ~TIM_CCER_CC3P;
  6389.   /* Set the Output Compare Polarity */
  6390.   tmpccer |= (OC_Config->OCPolarity << 8U);
  6391.  
  6392.   /* Write to TIMx CR2 */
  6393.   TIMx->CR2 = tmpcr2;
  6394.  
  6395.   /* Write to TIMx CCMR2 */
  6396.   TIMx->CCMR2 = tmpccmrx;
  6397.  
  6398.   /* Set the Capture Compare Register value */
  6399.   TIMx->CCR3 = OC_Config->Pulse;
  6400.  
  6401.   /* Write to TIMx CCER */
  6402.   TIMx->CCER = tmpccer;
  6403. }
  6404.  
  6405. /**
  6406.   * @brief  Timer Output Compare 4 configuration
  6407.   * @param  TIMx to select the TIM peripheral
  6408.   * @param  OC_Config The output configuration structure
  6409.   * @retval None
  6410.   */
  6411. static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6412. {
  6413.   uint32_t tmpccmrx;
  6414.   uint32_t tmpccer;
  6415.   uint32_t tmpcr2;
  6416.  
  6417.   /* Disable the Channel 4: Reset the CC4E Bit */
  6418.   TIMx->CCER &= ~TIM_CCER_CC4E;
  6419.  
  6420.   /* Get the TIMx CCER register value */
  6421.   tmpccer = TIMx->CCER;
  6422.   /* Get the TIMx CR2 register value */
  6423.   tmpcr2 =  TIMx->CR2;
  6424.  
  6425.   /* Get the TIMx CCMR2 register value */
  6426.   tmpccmrx = TIMx->CCMR2;
  6427.  
  6428.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  6429.   tmpccmrx &= ~TIM_CCMR2_OC4M;
  6430.   tmpccmrx &= ~TIM_CCMR2_CC4S;
  6431.  
  6432.   /* Select the Output Compare Mode */
  6433.   tmpccmrx |= (OC_Config->OCMode << 8U);
  6434.  
  6435.   /* Reset the Output Polarity level */
  6436.   tmpccer &= ~TIM_CCER_CC4P;
  6437.   /* Set the Output Compare Polarity */
  6438.   tmpccer |= (OC_Config->OCPolarity << 12U);
  6439.  
  6440.   /* Write to TIMx CR2 */
  6441.   TIMx->CR2 = tmpcr2;
  6442.  
  6443.   /* Write to TIMx CCMR2 */
  6444.   TIMx->CCMR2 = tmpccmrx;
  6445.  
  6446.   /* Set the Capture Compare Register value */
  6447.   TIMx->CCR4 = OC_Config->Pulse;
  6448.  
  6449.   /* Write to TIMx CCER */
  6450.   TIMx->CCER = tmpccer;
  6451. }
  6452.  
  6453. /**
  6454.   * @brief  Slave Timer configuration function
  6455.   * @param  htim TIM handle
  6456.   * @param  sSlaveConfig Slave timer configuration
  6457.   * @retval None
  6458.   */
  6459. static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
  6460.                                                   TIM_SlaveConfigTypeDef *sSlaveConfig)
  6461. {
  6462.   uint32_t tmpsmcr;
  6463.   uint32_t tmpccmr1;
  6464.   uint32_t tmpccer;
  6465.  
  6466.   /* Get the TIMx SMCR register value */
  6467.   tmpsmcr = htim->Instance->SMCR;
  6468.  
  6469.   /* Reset the Trigger Selection Bits */
  6470.   tmpsmcr &= ~TIM_SMCR_TS;
  6471.   /* Set the Input Trigger source */
  6472.   tmpsmcr |= sSlaveConfig->InputTrigger;
  6473.  
  6474.   /* Reset the slave mode Bits */
  6475.   tmpsmcr &= ~TIM_SMCR_SMS;
  6476.   /* Set the slave mode */
  6477.   tmpsmcr |= sSlaveConfig->SlaveMode;
  6478.  
  6479.   /* Write to TIMx SMCR */
  6480.   htim->Instance->SMCR = tmpsmcr;
  6481.  
  6482.   /* Configure the trigger prescaler, filter, and polarity */
  6483.   switch (sSlaveConfig->InputTrigger)
  6484.   {
  6485.     case TIM_TS_ETRF:
  6486.     {
  6487.       /* Check the parameters */
  6488.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
  6489.       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
  6490.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  6491.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  6492.       /* Configure the ETR Trigger source */
  6493.       TIM_ETR_SetConfig(htim->Instance,
  6494.                         sSlaveConfig->TriggerPrescaler,
  6495.                         sSlaveConfig->TriggerPolarity,
  6496.                         sSlaveConfig->TriggerFilter);
  6497.       break;
  6498.     }
  6499.  
  6500.     case TIM_TS_TI1F_ED:
  6501.     {
  6502.       /* Check the parameters */
  6503.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  6504.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  6505.  
  6506.       if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
  6507.       {
  6508.         return HAL_ERROR;
  6509.       }
  6510.  
  6511.       /* Disable the Channel 1: Reset the CC1E Bit */
  6512.       tmpccer = htim->Instance->CCER;
  6513.       htim->Instance->CCER &= ~TIM_CCER_CC1E;
  6514.       tmpccmr1 = htim->Instance->CCMR1;
  6515.  
  6516.       /* Set the filter */
  6517.       tmpccmr1 &= ~TIM_CCMR1_IC1F;
  6518.       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
  6519.  
  6520.       /* Write to TIMx CCMR1 and CCER registers */
  6521.       htim->Instance->CCMR1 = tmpccmr1;
  6522.       htim->Instance->CCER = tmpccer;
  6523.       break;
  6524.     }
  6525.  
  6526.     case TIM_TS_TI1FP1:
  6527.     {
  6528.       /* Check the parameters */
  6529.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  6530.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  6531.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  6532.  
  6533.       /* Configure TI1 Filter and Polarity */
  6534.       TIM_TI1_ConfigInputStage(htim->Instance,
  6535.                                sSlaveConfig->TriggerPolarity,
  6536.                                sSlaveConfig->TriggerFilter);
  6537.       break;
  6538.     }
  6539.  
  6540.     case TIM_TS_TI2FP2:
  6541.     {
  6542.       /* Check the parameters */
  6543.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  6544.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  6545.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  6546.  
  6547.       /* Configure TI2 Filter and Polarity */
  6548.       TIM_TI2_ConfigInputStage(htim->Instance,
  6549.                                sSlaveConfig->TriggerPolarity,
  6550.                                sSlaveConfig->TriggerFilter);
  6551.       break;
  6552.     }
  6553.  
  6554.     case TIM_TS_ITR0:
  6555.     case TIM_TS_ITR1:
  6556.     case TIM_TS_ITR2:
  6557.     case TIM_TS_ITR3:
  6558.       {
  6559.         /* Check the parameter */
  6560.         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  6561.         break;
  6562.       }
  6563.  
  6564.     default:
  6565.       break;
  6566.   }
  6567.   return HAL_OK;
  6568. }
  6569.  
  6570. /**
  6571.   * @brief  Configure the TI1 as Input.
  6572.   * @param  TIMx to select the TIM peripheral.
  6573.   * @param  TIM_ICPolarity The Input Polarity.
  6574.   *          This parameter can be one of the following values:
  6575.   *            @arg TIM_ICPOLARITY_RISING
  6576.   *            @arg TIM_ICPOLARITY_FALLING
  6577.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  6578.   * @param  TIM_ICSelection specifies the input to be used.
  6579.   *          This parameter can be one of the following values:
  6580.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
  6581.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
  6582.   *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
  6583.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  6584.   *          This parameter must be a value between 0x00 and 0x0F.
  6585.   * @retval None
  6586.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
  6587.   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
  6588.   *        protected against un-initialized filter and polarity values.
  6589.   */
  6590. static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  6591.                               uint32_t TIM_ICFilter)
  6592. {
  6593.   uint32_t tmpccmr1;
  6594.   uint32_t tmpccer;
  6595.  
  6596.   /* Disable the Channel 1: Reset the CC1E Bit */
  6597.   TIMx->CCER &= ~TIM_CCER_CC1E;
  6598.   tmpccmr1 = TIMx->CCMR1;
  6599.   tmpccer = TIMx->CCER;
  6600.  
  6601.   /* Select the Input */
  6602.   if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
  6603.   {
  6604.     tmpccmr1 &= ~TIM_CCMR1_CC1S;
  6605.     tmpccmr1 |= TIM_ICSelection;
  6606.   }
  6607.   else
  6608.   {
  6609.     tmpccmr1 |= TIM_CCMR1_CC1S_0;
  6610.   }
  6611.  
  6612.   /* Set the filter */
  6613.   tmpccmr1 &= ~TIM_CCMR1_IC1F;
  6614.   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
  6615.  
  6616.   /* Select the Polarity and set the CC1E Bit */
  6617.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  6618.   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
  6619.  
  6620.   /* Write to TIMx CCMR1 and CCER registers */
  6621.   TIMx->CCMR1 = tmpccmr1;
  6622.   TIMx->CCER = tmpccer;
  6623. }
  6624.  
  6625. /**
  6626.   * @brief  Configure the Polarity and Filter for TI1.
  6627.   * @param  TIMx to select the TIM peripheral.
  6628.   * @param  TIM_ICPolarity The Input Polarity.
  6629.   *          This parameter can be one of the following values:
  6630.   *            @arg TIM_ICPOLARITY_RISING
  6631.   *            @arg TIM_ICPOLARITY_FALLING
  6632.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  6633.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  6634.   *          This parameter must be a value between 0x00 and 0x0F.
  6635.   * @retval None
  6636.   */
  6637. static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
  6638. {
  6639.   uint32_t tmpccmr1;
  6640.   uint32_t tmpccer;
  6641.  
  6642.   /* Disable the Channel 1: Reset the CC1E Bit */
  6643.   tmpccer = TIMx->CCER;
  6644.   TIMx->CCER &= ~TIM_CCER_CC1E;
  6645.   tmpccmr1 = TIMx->CCMR1;
  6646.  
  6647.   /* Set the filter */
  6648.   tmpccmr1 &= ~TIM_CCMR1_IC1F;
  6649.   tmpccmr1 |= (TIM_ICFilter << 4U);
  6650.  
  6651.   /* Select the Polarity and set the CC1E Bit */
  6652.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  6653.   tmpccer |= TIM_ICPolarity;
  6654.  
  6655.   /* Write to TIMx CCMR1 and CCER registers */
  6656.   TIMx->CCMR1 = tmpccmr1;
  6657.   TIMx->CCER = tmpccer;
  6658. }
  6659.  
  6660. /**
  6661.   * @brief  Configure the TI2 as Input.
  6662.   * @param  TIMx to select the TIM peripheral
  6663.   * @param  TIM_ICPolarity The Input Polarity.
  6664.   *          This parameter can be one of the following values:
  6665.   *            @arg TIM_ICPOLARITY_RISING
  6666.   *            @arg TIM_ICPOLARITY_FALLING
  6667.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  6668.   * @param  TIM_ICSelection specifies the input to be used.
  6669.   *          This parameter can be one of the following values:
  6670.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
  6671.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
  6672.   *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
  6673.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  6674.   *          This parameter must be a value between 0x00 and 0x0F.
  6675.   * @retval None
  6676.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
  6677.   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
  6678.   *        protected against un-initialized filter and polarity values.
  6679.   */
  6680. static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  6681.                               uint32_t TIM_ICFilter)
  6682. {
  6683.   uint32_t tmpccmr1;
  6684.   uint32_t tmpccer;
  6685.  
  6686.   /* Disable the Channel 2: Reset the CC2E Bit */
  6687.   TIMx->CCER &= ~TIM_CCER_CC2E;
  6688.   tmpccmr1 = TIMx->CCMR1;
  6689.   tmpccer = TIMx->CCER;
  6690.  
  6691.   /* Select the Input */
  6692.   tmpccmr1 &= ~TIM_CCMR1_CC2S;
  6693.   tmpccmr1 |= (TIM_ICSelection << 8U);
  6694.  
  6695.   /* Set the filter */
  6696.   tmpccmr1 &= ~TIM_CCMR1_IC2F;
  6697.   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
  6698.  
  6699.   /* Select the Polarity and set the CC2E Bit */
  6700.   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  6701.   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
  6702.  
  6703.   /* Write to TIMx CCMR1 and CCER registers */
  6704.   TIMx->CCMR1 = tmpccmr1 ;
  6705.   TIMx->CCER = tmpccer;
  6706. }
  6707.  
  6708. /**
  6709.   * @brief  Configure the Polarity and Filter for TI2.
  6710.   * @param  TIMx to select the TIM peripheral.
  6711.   * @param  TIM_ICPolarity The Input Polarity.
  6712.   *          This parameter can be one of the following values:
  6713.   *            @arg TIM_ICPOLARITY_RISING
  6714.   *            @arg TIM_ICPOLARITY_FALLING
  6715.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  6716.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  6717.   *          This parameter must be a value between 0x00 and 0x0F.
  6718.   * @retval None
  6719.   */
  6720. static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
  6721. {
  6722.   uint32_t tmpccmr1;
  6723.   uint32_t tmpccer;
  6724.  
  6725.   /* Disable the Channel 2: Reset the CC2E Bit */
  6726.   TIMx->CCER &= ~TIM_CCER_CC2E;
  6727.   tmpccmr1 = TIMx->CCMR1;
  6728.   tmpccer = TIMx->CCER;
  6729.  
  6730.   /* Set the filter */
  6731.   tmpccmr1 &= ~TIM_CCMR1_IC2F;
  6732.   tmpccmr1 |= (TIM_ICFilter << 12U);
  6733.  
  6734.   /* Select the Polarity and set the CC2E Bit */
  6735.   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  6736.   tmpccer |= (TIM_ICPolarity << 4U);
  6737.  
  6738.   /* Write to TIMx CCMR1 and CCER registers */
  6739.   TIMx->CCMR1 = tmpccmr1 ;
  6740.   TIMx->CCER = tmpccer;
  6741. }
  6742.  
  6743. /**
  6744.   * @brief  Configure the TI3 as Input.
  6745.   * @param  TIMx to select the TIM peripheral
  6746.   * @param  TIM_ICPolarity The Input Polarity.
  6747.   *          This parameter can be one of the following values:
  6748.   *            @arg TIM_ICPOLARITY_RISING
  6749.   *            @arg TIM_ICPOLARITY_FALLING
  6750.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  6751.   * @param  TIM_ICSelection specifies the input to be used.
  6752.   *          This parameter can be one of the following values:
  6753.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
  6754.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
  6755.   *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
  6756.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  6757.   *          This parameter must be a value between 0x00 and 0x0F.
  6758.   * @retval None
  6759.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
  6760.   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
  6761.   *        protected against un-initialized filter and polarity values.
  6762.   */
  6763. static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  6764.                               uint32_t TIM_ICFilter)
  6765. {
  6766.   uint32_t tmpccmr2;
  6767.   uint32_t tmpccer;
  6768.  
  6769.   /* Disable the Channel 3: Reset the CC3E Bit */
  6770.   TIMx->CCER &= ~TIM_CCER_CC3E;
  6771.   tmpccmr2 = TIMx->CCMR2;
  6772.   tmpccer = TIMx->CCER;
  6773.  
  6774.   /* Select the Input */
  6775.   tmpccmr2 &= ~TIM_CCMR2_CC3S;
  6776.   tmpccmr2 |= TIM_ICSelection;
  6777.  
  6778.   /* Set the filter */
  6779.   tmpccmr2 &= ~TIM_CCMR2_IC3F;
  6780.   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
  6781.  
  6782.   /* Select the Polarity and set the CC3E Bit */
  6783.   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
  6784.   tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
  6785.  
  6786.   /* Write to TIMx CCMR2 and CCER registers */
  6787.   TIMx->CCMR2 = tmpccmr2;
  6788.   TIMx->CCER = tmpccer;
  6789. }
  6790.  
  6791. /**
  6792.   * @brief  Configure the TI4 as Input.
  6793.   * @param  TIMx to select the TIM peripheral
  6794.   * @param  TIM_ICPolarity The Input Polarity.
  6795.   *          This parameter can be one of the following values:
  6796.   *            @arg TIM_ICPOLARITY_RISING
  6797.   *            @arg TIM_ICPOLARITY_FALLING
  6798.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  6799.   * @param  TIM_ICSelection specifies the input to be used.
  6800.   *          This parameter can be one of the following values:
  6801.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
  6802.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
  6803.   *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
  6804.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  6805.   *          This parameter must be a value between 0x00 and 0x0F.
  6806.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
  6807.   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
  6808.   *        protected against un-initialized filter and polarity values.
  6809.   * @retval None
  6810.   */
  6811. static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  6812.                               uint32_t TIM_ICFilter)
  6813. {
  6814.   uint32_t tmpccmr2;
  6815.   uint32_t tmpccer;
  6816.  
  6817.   /* Disable the Channel 4: Reset the CC4E Bit */
  6818.   TIMx->CCER &= ~TIM_CCER_CC4E;
  6819.   tmpccmr2 = TIMx->CCMR2;
  6820.   tmpccer = TIMx->CCER;
  6821.  
  6822.   /* Select the Input */
  6823.   tmpccmr2 &= ~TIM_CCMR2_CC4S;
  6824.   tmpccmr2 |= (TIM_ICSelection << 8U);
  6825.  
  6826.   /* Set the filter */
  6827.   tmpccmr2 &= ~TIM_CCMR2_IC4F;
  6828.   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
  6829.  
  6830.   /* Select the Polarity and set the CC4E Bit */
  6831.   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
  6832.   tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
  6833.  
  6834.   /* Write to TIMx CCMR2 and CCER registers */
  6835.   TIMx->CCMR2 = tmpccmr2;
  6836.   TIMx->CCER = tmpccer ;
  6837. }
  6838.  
  6839. /**
  6840.   * @brief  Selects the Input Trigger source
  6841.   * @param  TIMx to select the TIM peripheral
  6842.   * @param  InputTriggerSource The Input Trigger source.
  6843.   *          This parameter can be one of the following values:
  6844.   *            @arg TIM_TS_ITR0: Internal Trigger 0
  6845.   *            @arg TIM_TS_ITR1: Internal Trigger 1
  6846.   *            @arg TIM_TS_ITR2: Internal Trigger 2
  6847.   *            @arg TIM_TS_ITR3: Internal Trigger 3
  6848.   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
  6849.   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
  6850.   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
  6851.   *            @arg TIM_TS_ETRF: External Trigger input
  6852.   * @retval None
  6853.   */
  6854. static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
  6855. {
  6856.   uint32_t tmpsmcr;
  6857.  
  6858.   /* Get the TIMx SMCR register value */
  6859.   tmpsmcr = TIMx->SMCR;
  6860.   /* Reset the TS Bits */
  6861.   tmpsmcr &= ~TIM_SMCR_TS;
  6862.   /* Set the Input Trigger source and the slave mode*/
  6863.   tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
  6864.   /* Write to TIMx SMCR */
  6865.   TIMx->SMCR = tmpsmcr;
  6866. }
  6867. /**
  6868.   * @brief  Configures the TIMx External Trigger (ETR).
  6869.   * @param  TIMx to select the TIM peripheral
  6870.   * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
  6871.   *          This parameter can be one of the following values:
  6872.   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
  6873.   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
  6874.   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
  6875.   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
  6876.   * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
  6877.   *          This parameter can be one of the following values:
  6878.   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
  6879.   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
  6880.   * @param  ExtTRGFilter External Trigger Filter.
  6881.   *          This parameter must be a value between 0x00 and 0x0F
  6882.   * @retval None
  6883.   */
  6884. static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
  6885.                               uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
  6886. {
  6887.   uint32_t tmpsmcr;
  6888.  
  6889.   tmpsmcr = TIMx->SMCR;
  6890.  
  6891.   /* Reset the ETR Bits */
  6892.   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  6893.  
  6894.   /* Set the Prescaler, the Filter value and the Polarity */
  6895.   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
  6896.  
  6897.   /* Write to TIMx SMCR */
  6898.   TIMx->SMCR = tmpsmcr;
  6899. }
  6900.  
  6901. /**
  6902.   * @brief  Enables or disables the TIM Capture Compare Channel x.
  6903.   * @param  TIMx to select the TIM peripheral
  6904.   * @param  Channel specifies the TIM Channel
  6905.   *          This parameter can be one of the following values:
  6906.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  6907.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  6908.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  6909.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  6910.   * @param  ChannelState specifies the TIM Channel CCxE bit new state.
  6911.   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
  6912.   * @retval None
  6913.   */
  6914. static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
  6915. {
  6916.   uint32_t tmp;
  6917.  
  6918.   /* Check the parameters */
  6919.   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  6920.   assert_param(IS_TIM_CHANNELS(Channel));
  6921.  
  6922.   tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
  6923.  
  6924.   /* Reset the CCxE Bit */
  6925.   TIMx->CCER &= ~tmp;
  6926.  
  6927.   /* Set or reset the CCxE Bit */
  6928.   TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
  6929. }
  6930.  
  6931. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6932. /**
  6933.   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
  6934.   * @param  htim pointer to a TIM_HandleTypeDef structure that contains
  6935.   *                the configuration information for TIM module.
  6936.   * @retval None
  6937.   */
  6938. void TIM_ResetCallback(TIM_HandleTypeDef *htim)
  6939. {
  6940.   /* Reset the TIM callback to the legacy weak callbacks */
  6941.   htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */
  6942.   htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */
  6943.   htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */
  6944.   htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */
  6945.   htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */
  6946.   htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */
  6947.   htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */
  6948.   htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */
  6949.   htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
  6950.   htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */
  6951. }
  6952. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6953.  
  6954. /**
  6955.   * @}
  6956.   */
  6957.  
  6958. #endif /* HAL_TIM_MODULE_ENABLED */
  6959. /**
  6960.   * @}
  6961.   */
  6962.  
  6963. /**
  6964.   * @}
  6965.   */
  6966. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  6967.