Subversion Repositories EngineBay2

Rev

Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32l1xx_hal_rcc_ex.h
  4.   * @author  MCD Application Team
  5.   * @version V1.2.0
  6.   * @date    01-July-2016
  7.   * @brief   Header file of RCC HAL Extension module.
  8.   ******************************************************************************
  9.   * @attention
  10.   *
  11.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  12.   *
  13.   * Redistribution and use in source and binary forms, with or without modification,
  14.   * are permitted provided that the following conditions are met:
  15.   *   1. Redistributions of source code must retain the above copyright notice,
  16.   *      this list of conditions and the following disclaimer.
  17.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18.   *      this list of conditions and the following disclaimer in the documentation
  19.   *      and/or other materials provided with the distribution.
  20.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21.   *      may be used to endorse or promote products derived from this software
  22.   *      without specific prior written permission.
  23.   *
  24.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34.   *
  35.   ******************************************************************************
  36.   */
  37.  
  38. /* Define to prevent recursive inclusion -------------------------------------*/
  39. #ifndef __STM32L1xx_HAL_RCC_EX_H
  40. #define __STM32L1xx_HAL_RCC_EX_H
  41.  
  42. #ifdef __cplusplus
  43.  extern "C" {
  44. #endif
  45.  
  46. /* Includes ------------------------------------------------------------------*/
  47. #include "stm32l1xx_hal_def.h"
  48.  
  49. /** @addtogroup STM32L1xx_HAL_Driver
  50.   * @{
  51.   */
  52.  
  53. /** @addtogroup RCCEx
  54.   * @{
  55.   */
  56.  
  57. /** @addtogroup RCCEx_Private_Constants
  58.  * @{
  59.  */
  60.  
  61. #define LSI_VALUE                  ((uint32_t)37000)  /* ~37kHz */
  62.  
  63. #if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\
  64.  || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
  65.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  66.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  67.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\
  68.  || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  69.  
  70. /* Alias word address of LSECSSON bit */
  71. #define LSECSSON_BITNUMBER      POSITION_VAL(RCC_CSR_LSECSSON)
  72. #define CSR_LSECSSON_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSECSSON_BITNUMBER * 4)))
  73.  
  74. #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/
  75.  
  76. /**
  77.   * @}
  78.   */
  79.  
  80. /** @addtogroup RCCEx_Private_Macros
  81.   * @{
  82.   */
  83. #if defined(LCD)
  84.  
  85. #define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD))
  86.  
  87. #else /* Not LCD LINE */
  88.  
  89. #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC)
  90.  
  91. #endif /* LCD */
  92.  
  93. /**
  94.   * @}
  95.   */
  96.  
  97. /* Exported types ------------------------------------------------------------*/
  98.  
  99. /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
  100.   * @{
  101.   */
  102.  
  103. /**
  104.   * @brief  RCC extended clocks structure definition  
  105.   */
  106. typedef struct
  107. {
  108.   uint32_t PeriphClockSelection;                /*!< The Extended Clock to be configured.
  109.                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
  110.  
  111.   uint32_t RTCClockSelection;         /*!< specifies the RTC clock source.
  112.                                        This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
  113.  
  114. #if defined(LCD)
  115.  
  116.   uint32_t LCDClockSelection;         /*!< specifies the LCD clock source.
  117.                                        This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
  118.  
  119. #endif /* LCD */
  120. } RCC_PeriphCLKInitTypeDef;
  121.  
  122. /**
  123.   * @}
  124.   */
  125.  
  126. /* Exported constants --------------------------------------------------------*/
  127.  
  128. /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
  129.   * @{
  130.   */
  131.  
  132. /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
  133.   * @{
  134.   */
  135. #define RCC_PERIPHCLK_RTC           ((uint32_t)0x00000001)
  136.  
  137. #if defined(LCD)
  138.  
  139. #define RCC_PERIPHCLK_LCD           ((uint32_t)0x00000002)
  140.  
  141. #endif /* LCD */
  142.  
  143. /**
  144.   * @}
  145.   */
  146.  
  147. #if defined(RCC_LSECSS_SUPPORT)
  148. /** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
  149.   * @{
  150.   */
  151. #define RCC_EXTI_LINE_LSECSS             (EXTI_IMR_IM19)         /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
  152. /**
  153.   * @}
  154.   */
  155. #endif /* RCC_LSECSS_SUPPORT */
  156.  
  157. /**
  158.   * @}
  159.   */
  160.  
  161. /* Exported macro ------------------------------------------------------------*/
  162. /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
  163.  * @{
  164.  */
  165.  
  166. /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
  167.   * @brief  Enables or disables the AHB1 peripheral clock.
  168.   * @note   After reset, the peripheral clock (used for registers read/write access)
  169.   *         is disabled and the application software has to enable this clock before
  170.   *         using it.  
  171.   * @{
  172.   */
  173. #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
  174.  || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
  175.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  176.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  177.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  178.  || defined(STM32L162xE) || defined(STM32L162xDX)
  179.    
  180. #define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
  181.                                         __IO uint32_t tmpreg; \
  182.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
  183.                                         /* Delay after an RCC peripheral clock enabling */ \
  184.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
  185.                                         UNUSED(tmpreg); \
  186.                                       } while(0)
  187. #define __HAL_RCC_GPIOE_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
  188.  
  189. #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  190.  
  191. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  192.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  193.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  194.  
  195. #define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
  196.                                         __IO uint32_t tmpreg; \
  197.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
  198.                                         /* Delay after an RCC peripheral clock enabling */ \
  199.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
  200.                                         UNUSED(tmpreg); \
  201.                                       } while(0)
  202. #define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
  203.                                         __IO uint32_t tmpreg; \
  204.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
  205.                                         /* Delay after an RCC peripheral clock enabling */ \
  206.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
  207.                                         UNUSED(tmpreg); \
  208.                                       } while(0)
  209.  
  210. #define __HAL_RCC_GPIOF_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
  211. #define __HAL_RCC_GPIOG_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
  212.  
  213. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  214.  
  215. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
  216.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  217.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  218.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  219.  || defined(STM32L162xE) || defined(STM32L162xDX)
  220.    
  221. #define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
  222.                                         __IO uint32_t tmpreg; \
  223.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
  224.                                         /* Delay after an RCC peripheral clock enabling */ \
  225.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
  226.                                         UNUSED(tmpreg); \
  227.                                       } while(0)
  228.  
  229. #define __HAL_RCC_DMA2_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
  230.  
  231. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  232.  
  233. #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
  234.  || defined(STM32L162xE) || defined(STM32L162xDX)
  235.  
  236. #define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
  237.                                         __IO uint32_t tmpreg; \
  238.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\
  239.                                         /* Delay after an RCC peripheral clock enabling */ \
  240.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\
  241.                                         UNUSED(tmpreg); \
  242.                                       } while(0)
  243. #define __HAL_RCC_CRYP_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_AESEN))
  244.  
  245. #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
  246.  
  247. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
  248.  
  249. #define __HAL_RCC_FSMC_CLK_ENABLE()   do { \
  250.                                         __IO uint32_t tmpreg; \
  251.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
  252.                                         /* Delay after an RCC peripheral clock enabling */ \
  253.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
  254.                                         UNUSED(tmpreg); \
  255.                                       } while(0)
  256. #define __HAL_RCC_FSMC_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
  257.  
  258. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
  259.  
  260. #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
  261.  || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
  262.  || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
  263.  || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
  264.  || defined(STM32L162xE) || defined(STM32L162xDX)
  265.    
  266. #define __HAL_RCC_LCD_CLK_ENABLE()   do { \
  267.                                         __IO uint32_t tmpreg; \
  268.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
  269.                                         /* Delay after an RCC peripheral clock enabling */ \
  270.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
  271.                                         UNUSED(tmpreg); \
  272.                                       } while(0)
  273. #define __HAL_RCC_LCD_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN))
  274.  
  275. #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  276.  
  277. /** @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
  278.   * @note   After reset, the peripheral clock (used for registers read/write access)
  279.   *         is disabled and the application software has to enable this clock before
  280.   *         using it.
  281.   */
  282. #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
  283.  || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  284.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  285.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  286.  
  287. #define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
  288.                                         __IO uint32_t tmpreg; \
  289.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
  290.                                         /* Delay after an RCC peripheral clock enabling */ \
  291.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
  292.                                         UNUSED(tmpreg); \
  293.                                       } while(0)
  294. #define __HAL_RCC_TIM5_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
  295.  
  296. #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  297.  
  298. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
  299.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  300.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  301.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  302.  || defined(STM32L162xE) || defined(STM32L162xDX)
  303.  
  304. #define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
  305.                                         __IO uint32_t tmpreg; \
  306.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
  307.                                         /* Delay after an RCC peripheral clock enabling */ \
  308.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
  309.                                         UNUSED(tmpreg); \
  310.                                       } while(0)
  311. #define __HAL_RCC_SPI3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
  312.  
  313. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  314.  
  315. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
  316.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  317.  
  318. #define __HAL_RCC_UART4_CLK_ENABLE()   do { \
  319.                                         __IO uint32_t tmpreg; \
  320.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
  321.                                         /* Delay after an RCC peripheral clock enabling */ \
  322.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
  323.                                         UNUSED(tmpreg); \
  324.                                       } while(0)
  325. #define __HAL_RCC_UART5_CLK_ENABLE()   do { \
  326.                                         __IO uint32_t tmpreg; \
  327.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
  328.                                         /* Delay after an RCC peripheral clock enabling */ \
  329.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
  330.                                         UNUSED(tmpreg); \
  331.                                       } while(0)
  332.  
  333. #define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
  334. #define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
  335.  
  336. #endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */
  337.  
  338. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  339.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  340.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE)\
  341.  || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
  342.  || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
  343.  
  344. #define __HAL_RCC_OPAMP_CLK_ENABLE()      __HAL_RCC_COMP_CLK_ENABLE()   /* Peripherals COMP and OPAMP share the same clock domain */
  345. #define __HAL_RCC_OPAMP_CLK_DISABLE()     __HAL_RCC_COMP_CLK_DISABLE()  /* Peripherals COMP and OPAMP share the same clock domain */
  346.      
  347. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */
  348.      
  349. /** @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
  350.   * @note   After reset, the peripheral clock (used for registers read/write access)
  351.   *         is disabled and the application software has to enable this clock before
  352.   *         using it.
  353.   */
  354. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
  355.  
  356. #define __HAL_RCC_SDIO_CLK_ENABLE()   do { \
  357.                                         __IO uint32_t tmpreg; \
  358.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
  359.                                         /* Delay after an RCC peripheral clock enabling */ \
  360.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
  361.                                         UNUSED(tmpreg); \
  362.                                       } while(0)
  363. #define __HAL_RCC_SDIO_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
  364.  
  365. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
  366.  
  367. /**
  368.     * @}
  369.     */
  370.  
  371.  
  372. /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
  373.   * @brief  Forces or releases AHB peripheral reset.
  374.   * @{
  375.   */  
  376. #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
  377.  || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
  378.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  379.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  380.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  381.  || defined(STM32L162xE) || defined(STM32L162xDX)
  382.    
  383. #define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
  384. #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
  385.  
  386. #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  387.  
  388. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  389.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  390.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  391.  
  392. #define __HAL_RCC_GPIOF_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
  393. #define __HAL_RCC_GPIOG_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
  394.  
  395. #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
  396. #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
  397.  
  398. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  399.  
  400. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
  401.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  402.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  403.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  404.  || defined(STM32L162xE) || defined(STM32L162xDX)
  405.    
  406. #define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST))
  407. #define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST))
  408.  
  409. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  410.  
  411. #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
  412.  || defined(STM32L162xE) || defined(STM32L162xDX)
  413.  
  414. #define __HAL_RCC_CRYP_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST))
  415. #define __HAL_RCC_CRYP_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST))
  416.  
  417. #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
  418.  
  419. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
  420.  
  421. #define __HAL_RCC_FSMC_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST))
  422. #define __HAL_RCC_FSMC_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST))
  423.  
  424. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
  425.  
  426. #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
  427.  || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
  428.  || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
  429.  || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
  430.  || defined(STM32L162xE) || defined(STM32L162xDX)
  431.    
  432. #define __HAL_RCC_LCD_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))
  433. #define __HAL_RCC_LCD_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST))
  434.  
  435. #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  436.  
  437. /** @brief  Forces or releases APB1 peripheral reset.
  438.   */
  439. #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
  440.  || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  441.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  442.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  443.  
  444. #define __HAL_RCC_TIM5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
  445. #define __HAL_RCC_TIM5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
  446.  
  447. #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  448.  
  449. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
  450.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  451.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  452.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  453.  || defined(STM32L162xE) || defined(STM32L162xDX)
  454.  
  455. #define __HAL_RCC_SPI3_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
  456. #define __HAL_RCC_SPI3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
  457.  
  458. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  459.  
  460. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
  461.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  462.  
  463. #define __HAL_RCC_UART4_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
  464. #define __HAL_RCC_UART5_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
  465.  
  466. #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
  467. #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
  468.  
  469. #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  470.  
  471. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  472.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  473.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
  474.  || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
  475.  
  476. #define __HAL_RCC_OPAMP_FORCE_RESET()     __HAL_RCC_COMP_FORCE_RESET()   /* Peripherals COMP and OPAMP share the same clock domain */
  477. #define __HAL_RCC_OPAMP_RELEASE_RESET()   __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */
  478.      
  479. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
  480.      
  481. /** @brief  Forces or releases APB2 peripheral reset.
  482.   */
  483. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
  484.  
  485. #define __HAL_RCC_SDIO_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
  486. #define __HAL_RCC_SDIO_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
  487.  
  488. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
  489.  
  490. /**
  491.   * @}
  492.   */
  493.  
  494. /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
  495.   * @brief  Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
  496.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
  497.   *         power consumption.
  498.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
  499.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
  500.   * @{
  501.   */
  502. #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
  503.  || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
  504.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  505.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  506.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  507.  || defined(STM32L162xE) || defined(STM32L162xDX)
  508.    
  509. #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN))
  510. #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN))
  511.  
  512. #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  513.  
  514. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  515.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  516.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  517.  
  518. #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN))
  519. #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN))
  520.  
  521. #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN))
  522. #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN))
  523.  
  524. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  525.  
  526. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
  527.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  528.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  529.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  530.  || defined(STM32L162xE) || defined(STM32L162xDX)
  531.    
  532. #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()   (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN))
  533. #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()  (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN))
  534.  
  535. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  536.  
  537. #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)
  538.  
  539. #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN))
  540. #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN))
  541.  
  542. #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
  543.  
  544. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
  545.  
  546. #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()   (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN))
  547. #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE()  (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN))
  548.  
  549. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
  550.  
  551. #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
  552.  || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
  553.  || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
  554.  || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
  555.  || defined(STM32L162xE) || defined(STM32L162xDX)
  556.    
  557. #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN))
  558. #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN))
  559.  
  560. #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  561.  
  562. /** @brief  Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
  563.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
  564.   *           power consumption.
  565.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
  566.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
  567.   */
  568. #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
  569.  || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  570.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  571.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  572.  
  573. #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
  574. #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
  575.  
  576. #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  577.  
  578. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
  579.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  580.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  581.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  582.  || defined(STM32L162xE) || defined(STM32L162xDX)
  583.  
  584. #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
  585. #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
  586.  
  587. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  588.  
  589. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
  590.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  591.  
  592. #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
  593. #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
  594.  
  595. #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
  596. #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
  597.  
  598. #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  599.  
  600. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  601.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  602.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
  603.  || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
  604.  
  605. #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()      __HAL_RCC_COMP_CLK_SLEEP_ENABLE()   /* Peripherals COMP and OPAMP share the same clock domain */
  606. #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()     __HAL_RCC_COMP_CLK_SLEEP_DISABLE()  /* Peripherals COMP and OPAMP share the same clock domain */
  607.      
  608. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
  609.  
  610. /** @brief  Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
  611.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
  612.   *           power consumption.
  613.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
  614.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
  615.   */
  616. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
  617.  
  618. #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
  619. #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
  620.  
  621. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
  622.  
  623. /**
  624.   * @}
  625.   */
  626.  
  627. /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
  628.   * @brief  Get the enable or disable status of peripheral clock.
  629.   * @note   After reset, the peripheral clock (used for registers read/write access)
  630.   *         is disabled and the application software has to enable this clock before
  631.   *         using it.
  632.   * @{
  633.   */
  634.  
  635. #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
  636.  || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
  637.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  638.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  639.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  640.  || defined(STM32L162xE) || defined(STM32L162xDX)
  641.    
  642. #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
  643. #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
  644.  
  645. #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  646.  
  647. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  648.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  649.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  650.  
  651. #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
  652. #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET)
  653. #define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
  654. #define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET)
  655.  
  656. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  657.  
  658. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
  659.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  660.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  661.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  662.  || defined(STM32L162xE) || defined(STM32L162xDX)
  663.    
  664. #define __HAL_RCC_DMA2_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
  665. #define __HAL_RCC_DMA2_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
  666.  
  667. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  668.  
  669. #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
  670.  || defined(STM32L162xE) || defined(STM32L162xDX)
  671.  
  672. #define __HAL_RCC_CRYP_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != RESET)
  673. #define __HAL_RCC_CRYP_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == RESET)
  674.  
  675. #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
  676.  
  677. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
  678.  
  679. #define __HAL_RCC_FSMC_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
  680. #define __HAL_RCC_FSMC_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
  681.  
  682. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
  683.  
  684. #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
  685.  || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
  686.  || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
  687.  || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
  688.  || defined(STM32L162xE) || defined(STM32L162xDX)
  689.    
  690. #define __HAL_RCC_LCD_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != RESET)
  691. #define __HAL_RCC_LCD_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == RESET)
  692.  
  693. #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  694.  
  695. #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
  696.  || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  697.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  698.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  699.  
  700. #define __HAL_RCC_TIM5_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
  701. #define __HAL_RCC_TIM5_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
  702.  
  703. #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  704.  
  705. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
  706.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  707.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  708.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  709.  || defined(STM32L162xE) || defined(STM32L162xDX)
  710.  
  711. #define __HAL_RCC_SPI3_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
  712. #define __HAL_RCC_SPI3_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
  713.  
  714. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  715.  
  716. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
  717.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  718.  
  719. #define __HAL_RCC_UART4_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
  720. #define __HAL_RCC_UART5_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
  721. #define __HAL_RCC_UART4_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
  722. #define __HAL_RCC_UART5_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
  723.  
  724. #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  725.  
  726. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  727.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  728.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
  729.  || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
  730.  
  731. #define __HAL_RCC_OPAMP_IS_CLK_ENABLED()       __HAL_RCC_COMP_IS_CLK_ENABLED()
  732. #define __HAL_RCC_OPAMP_IS_CLK_DISABLED()      __HAL_RCC_COMP_IS_CLK_DISABLED()
  733.  
  734. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
  735.  
  736. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
  737.  
  738. #define __HAL_RCC_SDIO_IS_CLK_ENABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
  739. #define __HAL_RCC_SDIO_IS_CLK_DISABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
  740.  
  741. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
  742.  
  743. /**
  744.   * @}
  745.   */
  746.  
  747. /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable_Status Peripheral Clock Sleep Enable Disable Status
  748.   * @brief  Get the enable or disable status of peripheral clock during Low Power (Sleep) mode.
  749.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
  750.   *         power consumption.
  751.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
  752.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
  753.   * @{
  754.   */
  755.  
  756. #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
  757.  || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
  758.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  759.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  760.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  761.  || defined(STM32L162xE) || defined(STM32L162xDX)
  762.    
  763. #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != RESET)
  764. #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == RESET)
  765.  
  766. #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  767.  
  768. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  769.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  770.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  771.  
  772. #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != RESET)
  773. #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != RESET)
  774. #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == RESET)
  775. #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == RESET)
  776.  
  777. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  778.  
  779. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
  780.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  781.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  782.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  783.  || defined(STM32L162xE) || defined(STM32L162xDX)
  784.    
  785. #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != RESET)
  786. #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == RESET)
  787.  
  788. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  789.  
  790. #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
  791.  || defined(STM32L162xE) || defined(STM32L162xDX)
  792.  
  793. #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != RESET)
  794. #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == RESET)
  795.  
  796. #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
  797.  
  798. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
  799.  
  800. #define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != RESET)
  801. #define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == RESET)
  802.  
  803. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
  804.  
  805. #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
  806.  || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
  807.  || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
  808.  || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
  809.  || defined(STM32L162xE) || defined(STM32L162xDX)
  810.    
  811. #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != RESET)
  812. #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == RESET)
  813.  
  814. #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  815.  
  816. #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
  817.  || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  818.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  819.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  820.  
  821. #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
  822. #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
  823.  
  824. #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  825.  
  826. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
  827.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
  828.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
  829.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
  830.  || defined(STM32L162xE) || defined(STM32L162xDX)
  831.  
  832. #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
  833. #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
  834.  
  835. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  836.  
  837. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
  838.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
  839.  
  840. #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
  841. #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
  842. #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
  843. #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
  844.  
  845. #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  846.  
  847. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
  848.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
  849.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
  850.  || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
  851.  
  852. #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()       __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED()
  853. #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()      __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED()
  854.  
  855. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
  856.  
  857. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
  858.  
  859. #define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != RESET)
  860. #define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == RESET)
  861.  
  862. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
  863.  
  864. /**
  865.   * @}
  866.   */
  867.  
  868.  
  869. #if defined(RCC_LSECSS_SUPPORT)
  870.  
  871. /**
  872.   * @brief Enable interrupt on RCC LSE CSS EXTI Line 19.
  873.   * @retval None
  874.   */
  875. #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
  876.  
  877. /**
  878.   * @brief Disable interrupt on RCC LSE CSS EXTI Line 19.
  879.   * @retval None
  880.   */
  881. #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
  882.  
  883. /**
  884.   * @brief Enable event on RCC LSE CSS EXTI Line 19.
  885.   * @retval None.
  886.   */
  887. #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
  888.  
  889. /**
  890.   * @brief Disable event on RCC LSE CSS EXTI Line 19.
  891.   * @retval None.
  892.   */
  893. #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
  894.  
  895.  
  896. /**
  897.   * @brief  RCC LSE CSS EXTI line configuration: set falling edge trigger.
  898.   * @retval None.
  899.   */
  900. #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
  901.  
  902.  
  903. /**
  904.   * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
  905.   * @retval None.
  906.   */
  907. #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
  908.  
  909.  
  910. /**
  911.   * @brief  RCC LSE CSS EXTI line configuration: set rising edge trigger.
  912.   * @retval None.
  913.   */
  914. #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
  915.  
  916. /**
  917.   * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
  918.   * @retval None.
  919.   */
  920. #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
  921.  
  922. /**
  923.   * @brief  RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.
  924.   * @retval None.
  925.   */
  926. #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
  927.   do {                                                      \
  928.     __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
  929.     __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
  930.   } while(0)  
  931.  
  932. /**
  933.   * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
  934.   * @retval None.
  935.   */
  936. #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
  937.   do {                                                       \
  938.     __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
  939.     __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
  940.   } while(0)  
  941.  
  942. /**
  943.   * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
  944.   * @retval EXTI RCC LSE CSS Line Status.
  945.   */
  946. #define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (EXTI->PR & (RCC_EXTI_LINE_LSECSS))
  947.  
  948. /**
  949.   * @brief Clear the RCC LSE CSS EXTI flag.
  950.   * @retval None.
  951.   */
  952. #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     (EXTI->PR = (RCC_EXTI_LINE_LSECSS))
  953.  
  954. /**
  955.   * @brief Generate a Software interrupt on selected EXTI line.
  956.   * @retval None.
  957.   */
  958. #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
  959.  
  960. #endif /* RCC_LSECSS_SUPPORT */
  961.  
  962. #if defined(LCD)
  963.    
  964. /** @defgroup RCCEx_LCD_Configuration LCD Configuration
  965.   * @brief  Macros to configure clock source of LCD peripherals.
  966.   * @{
  967.   */  
  968.  
  969. /** @brief Macro to configures LCD clock (LCDCLK).
  970.   *  @note   LCD and RTC use the same configuration
  971.   *  @note   LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
  972.   *          LCD clock source.
  973.   *    
  974.   *  @param  __LCD_CLKSOURCE__ specifies the LCD clock source.
  975.   *          This parameter can be one of the following values:
  976.   *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock
  977.   *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock
  978.   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock
  979.   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock
  980.   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock
  981.   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock
  982.   */
  983. #define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
  984.  
  985. /** @brief Macro to get the LCD clock source.
  986.   */
  987. #define __HAL_RCC_GET_LCD_SOURCE()              __HAL_RCC_GET_RTC_SOURCE()
  988.  
  989. /** @brief Macro to get the LCD clock pre-scaler.
  990.   */
  991. #define  __HAL_RCC_GET_LCD_HSE_PRESCALER()      __HAL_RCC_GET_RTC_HSE_PRESCALER()
  992.  
  993. /**
  994.   * @}
  995.   */
  996.  
  997. #endif /* LCD */
  998.  
  999.  
  1000. /**
  1001.   * @}
  1002.   */
  1003.  
  1004. /* Exported functions --------------------------------------------------------*/
  1005. /** @addtogroup RCCEx_Exported_Functions
  1006.   * @{
  1007.   */
  1008.  
  1009. /** @addtogroup RCCEx_Exported_Functions_Group1
  1010.   * @{
  1011.   */
  1012.  
  1013. HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
  1014. void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
  1015. uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
  1016.  
  1017. #if defined(RCC_LSECSS_SUPPORT)
  1018.  
  1019. void              HAL_RCCEx_EnableLSECSS(void);
  1020. void              HAL_RCCEx_DisableLSECSS(void);
  1021. void              HAL_RCCEx_EnableLSECSS_IT(void);
  1022. void              HAL_RCCEx_LSECSS_IRQHandler(void);
  1023. void              HAL_RCCEx_LSECSS_Callback(void);
  1024.  
  1025. #endif /* RCC_LSECSS_SUPPORT */
  1026.  
  1027. /**
  1028.   * @}
  1029.   */
  1030.  
  1031. /**
  1032.   * @}
  1033.   */
  1034.  
  1035. /**
  1036.   * @}
  1037.   */
  1038.  
  1039. /**
  1040.   * @}
  1041.   */
  1042.  
  1043. #ifdef __cplusplus
  1044. }
  1045. #endif
  1046.  
  1047. #endif /* __STM32L1xx_HAL_RCC_EX_H */
  1048.  
  1049. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1050.  
  1051.