Subversion Repositories EngineBay2

Rev

Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32l1xx_hal_dma.h
  4.   * @author  MCD Application Team
  5.   * @version V1.2.0
  6.   * @date    01-July-2016
  7.   * @brief   Header file of DMA HAL module.
  8.   ******************************************************************************
  9.   * @attention
  10.   *
  11.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  12.   *
  13.   * Redistribution and use in source and binary forms, with or without modification,
  14.   * are permitted provided that the following conditions are met:
  15.   *   1. Redistributions of source code must retain the above copyright notice,
  16.   *      this list of conditions and the following disclaimer.
  17.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18.   *      this list of conditions and the following disclaimer in the documentation
  19.   *      and/or other materials provided with the distribution.
  20.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21.   *      may be used to endorse or promote products derived from this software
  22.   *      without specific prior written permission.
  23.   *
  24.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34.   *
  35.   ******************************************************************************
  36.   */
  37.  
  38. /* Define to prevent recursive inclusion -------------------------------------*/
  39. #ifndef __STM32L1xx_HAL_DMA_H
  40. #define __STM32L1xx_HAL_DMA_H
  41.  
  42. #ifdef __cplusplus
  43.  extern "C" {
  44. #endif
  45.  
  46. /* Includes ------------------------------------------------------------------*/
  47. #include "stm32l1xx_hal_def.h"
  48.  
  49. /** @addtogroup STM32L1xx_HAL_Driver
  50.   * @{
  51.   */
  52.  
  53. /** @addtogroup DMA
  54.   * @{
  55.   */
  56.  
  57. /* Exported types ------------------------------------------------------------*/
  58.  
  59. /** @defgroup DMA_Exported_Types DMA Exported Types
  60.   * @{
  61.   */
  62.    
  63. /**
  64.   * @brief  DMA Configuration Structure definition
  65.   */
  66. typedef struct
  67. {
  68.   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
  69.                                            from memory to memory or from peripheral to memory.
  70.                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
  71.  
  72.   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
  73.                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
  74.                                
  75.   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
  76.                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
  77.  
  78.   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
  79.                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
  80.  
  81.   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
  82.                                            This parameter can be a value of @ref DMA_Memory_data_size */
  83.                                
  84.   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
  85.                                            This parameter can be a value of @ref DMA_mode
  86.                                            @note The circular buffer mode cannot be used if the memory-to-memory
  87.                                                  data transfer is configured on the selected Channel */
  88.  
  89.   uint32_t Priority;                   /*!< Specifies the software priority for the DMAy Channelx.
  90.                                             This parameter can be a value of @ref DMA_Priority_level */
  91. } DMA_InitTypeDef;
  92.  
  93. /**
  94.   * @brief  HAL DMA State structures definition  
  95.   */
  96. typedef enum
  97. {
  98.   HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
  99.   HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use   */
  100.   HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
  101.   HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
  102. }HAL_DMA_StateTypeDef;
  103.  
  104. /**
  105.   * @brief  HAL DMA Error Code structure definition
  106.   */
  107. typedef enum
  108. {
  109.   HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
  110.   HAL_DMA_HALF_TRANSFER      = 0x01     /*!< Half Transfer     */
  111. }HAL_DMA_LevelCompleteTypeDef;
  112.  
  113.  
  114. /**
  115.   * @brief  HAL DMA Callback ID structure definition
  116.   */
  117. typedef enum
  118. {
  119.   HAL_DMA_XFER_CPLT_CB_ID          = 0x00,    /*!< Full transfer     */
  120.   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01,    /*!< Half transfer     */
  121.   HAL_DMA_XFER_ERROR_CB_ID         = 0x02,    /*!< Error             */
  122.   HAL_DMA_XFER_ABORT_CB_ID         = 0x03,    /*!< Abort             */
  123.   HAL_DMA_XFER_ALL_CB_ID           = 0x04     /*!< All               */
  124.    
  125. }HAL_DMA_CallbackIDTypeDef;
  126.  
  127. /**
  128.   * @brief  DMA handle Structure definition
  129.   */
  130. typedef struct __DMA_HandleTypeDef
  131. {
  132.   DMA_Channel_TypeDef   *Instance;                       /*!< Register base address                  */
  133.  
  134.   DMA_InitTypeDef       Init;                            /*!< DMA communication parameters           */
  135.  
  136.   HAL_LockTypeDef       Lock;                            /*!< DMA locking object                     */  
  137.  
  138.   __IO HAL_DMA_StateTypeDef  State;                                                  /*!< DMA transfer state                   */
  139.  
  140.   void                  *Parent;                                                      /*!< Parent object state                    */  
  141.  
  142.   void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
  143.  
  144.   void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
  145.  
  146.   void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
  147.  
  148.   void                  (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer abort callback          */  
  149.  
  150.   __IO uint32_t         ErrorCode;                                                    /*!< DMA Error code                         */
  151.  
  152.   DMA_TypeDef            *DmaBaseAddress;                                            /*!< DMA Channel Base Address             */
  153.  
  154.   uint32_t               ChannelIndex;                                               /*!< DMA Channel Index                    */  
  155.  
  156. } DMA_HandleTypeDef;    
  157. /**
  158.   * @}
  159.   */
  160.  
  161. /* Exported constants --------------------------------------------------------*/
  162.  
  163. /** @defgroup DMA_Exported_Constants DMA Exported Constants
  164.   * @{
  165.   */
  166.  
  167. /** @defgroup DMA_Error_Code DMA Error Code
  168.   * @{
  169.   */
  170. #define HAL_DMA_ERROR_NONE          ((uint32_t)0x00000000)    /*!< No error */
  171. #define HAL_DMA_ERROR_TE            ((uint32_t)0x00000001)    /*!< Transfer error */
  172. #define HAL_DMA_ERROR_NO_XFER       ((uint32_t)0x00000004)    /*!< no ongoing transfer */
  173. #define HAL_DMA_ERROR_TIMEOUT       ((uint32_t)0x00000020)    /*!< Timeout error */
  174. #define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100)    /*!< Not supported mode */    
  175. /**
  176.   * @}
  177.   */
  178.  
  179. /** @defgroup DMA_request DMA request
  180.   * @{
  181.   */
  182. #define DMA_REQUEST_0                     ((uint32_t)0x00000000)
  183. #define DMA_REQUEST_1                     ((uint32_t)0x00000001)
  184. #define DMA_REQUEST_2                     ((uint32_t)0x00000002)
  185. #define DMA_REQUEST_3                     ((uint32_t)0x00000003)
  186. #define DMA_REQUEST_4                     ((uint32_t)0x00000004)
  187. #define DMA_REQUEST_5                     ((uint32_t)0x00000005)
  188. #define DMA_REQUEST_6                     ((uint32_t)0x00000006)
  189. #define DMA_REQUEST_7                     ((uint32_t)0x00000007)
  190.  
  191. /**
  192.   * @}
  193.   */
  194.  
  195. /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
  196.   * @{
  197.   */
  198. #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)      /*!< Peripheral to memory direction */
  199. #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)     /*!< Memory to peripheral direction */
  200. #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
  201.  
  202. /**
  203.   * @}
  204.   */
  205.  
  206. /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
  207.   * @{
  208.   */
  209. #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)   /*!< Peripheral increment mode Enable */
  210. #define DMA_PINC_DISABLE       ((uint32_t)0x00000000)     /*!< Peripheral increment mode Disable */
  211. /**
  212.   * @}
  213.   */
  214.  
  215. /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
  216.   * @{
  217.   */
  218. #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)   /*!< Memory increment mode Enable  */
  219. #define DMA_MINC_DISABLE        ((uint32_t)0x00000000)     /*!< Memory increment mode Disable */
  220. /**
  221.   * @}
  222.   */
  223.  
  224. /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
  225.   * @{
  226.   */
  227. #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Peripheral data alignment: Byte     */
  228. #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)   /*!< Peripheral data alignment: HalfWord */
  229. #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)   /*!< Peripheral data alignment: Word     */
  230. /**
  231.   * @}
  232.   */
  233.  
  234. /** @defgroup DMA_Memory_data_size DMA Memory data size
  235.   * @{
  236.   */
  237. #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Memory data alignment: Byte     */
  238. #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)   /*!< Memory data alignment: HalfWord */
  239. #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)   /*!< Memory data alignment: Word     */
  240. /**
  241.   * @}
  242.   */
  243.  
  244. /** @defgroup DMA_mode DMA mode
  245.   * @{
  246.   */
  247. #define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
  248. #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */
  249. /**
  250.   * @}
  251.   */
  252.  
  253. /** @defgroup DMA_Priority_level DMA Priority level
  254.   * @{
  255.   */
  256. #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)     /*!< Priority level : Low       */
  257. #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)   /*!< Priority level : Medium    */
  258. #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)   /*!< Priority level : High      */
  259. #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)     /*!< Priority level : Very_High */
  260. /**
  261.   * @}
  262.   */
  263.  
  264.  
  265. /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
  266.   * @{
  267.   */
  268. #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
  269. #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
  270. #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
  271. /**
  272.   * @}
  273.   */
  274.  
  275. /** @defgroup DMA_flag_definitions DMA flag definitions
  276.   * @{
  277.   */
  278. #define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
  279. #define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
  280. #define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
  281. #define DMA_FLAG_TE1                      ((uint32_t)0x00000008)
  282. #define DMA_FLAG_GL2                      ((uint32_t)0x00000010)
  283. #define DMA_FLAG_TC2                      ((uint32_t)0x00000020)
  284. #define DMA_FLAG_HT2                      ((uint32_t)0x00000040)
  285. #define DMA_FLAG_TE2                      ((uint32_t)0x00000080)
  286. #define DMA_FLAG_GL3                      ((uint32_t)0x00000100)
  287. #define DMA_FLAG_TC3                      ((uint32_t)0x00000200)
  288. #define DMA_FLAG_HT3                      ((uint32_t)0x00000400)
  289. #define DMA_FLAG_TE3                      ((uint32_t)0x00000800)
  290. #define DMA_FLAG_GL4                      ((uint32_t)0x00001000)
  291. #define DMA_FLAG_TC4                      ((uint32_t)0x00002000)
  292. #define DMA_FLAG_HT4                      ((uint32_t)0x00004000)
  293. #define DMA_FLAG_TE4                      ((uint32_t)0x00008000)
  294. #define DMA_FLAG_GL5                      ((uint32_t)0x00010000)
  295. #define DMA_FLAG_TC5                      ((uint32_t)0x00020000)
  296. #define DMA_FLAG_HT5                      ((uint32_t)0x00040000)
  297. #define DMA_FLAG_TE5                      ((uint32_t)0x00080000)
  298. #define DMA_FLAG_GL6                      ((uint32_t)0x00100000)
  299. #define DMA_FLAG_TC6                      ((uint32_t)0x00200000)
  300. #define DMA_FLAG_HT6                      ((uint32_t)0x00400000)
  301. #define DMA_FLAG_TE6                      ((uint32_t)0x00800000)
  302. #define DMA_FLAG_GL7                      ((uint32_t)0x01000000)
  303. #define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
  304. #define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
  305. #define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
  306. /**
  307.   * @}
  308.   */
  309.  
  310. /**
  311.   * @}
  312.   */
  313.  
  314. /* Exported macros -----------------------------------------------------------*/
  315. /** @defgroup DMA_Exported_Macros DMA Exported Macros
  316.   * @{
  317.   */
  318.  
  319. /** @brief  Reset DMA handle state
  320.   * @param  __HANDLE__: DMA handle
  321.   * @retval None
  322.   */
  323. #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
  324.  
  325. /**
  326.   * @brief  Enable the specified DMA Channel.
  327.   * @param  __HANDLE__: DMA handle
  328.   * @retval None
  329.   */
  330. #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
  331.  
  332. /**
  333.   * @brief  Disable the specified DMA Channel.
  334.   * @param  __HANDLE__: DMA handle
  335.   * @retval None
  336.   */
  337. #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
  338.  
  339.  
  340. /* Interrupt & Flag management */
  341. #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
  342.     defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
  343.     defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
  344.  
  345. /**
  346.   * @brief  Return the current DMA Channel transfer complete flag.
  347.   * @param  __HANDLE__: DMA handle
  348.   * @retval The specified transfer complete flag index.
  349.   */
  350.  
  351. #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
  352. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
  353.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
  354.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
  355.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
  356.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
  357.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
  358.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
  359.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
  360.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
  361.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
  362.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
  363.    DMA_FLAG_TC7)
  364.  
  365. /**
  366.   * @brief  Return the current DMA Channel half transfer complete flag.
  367.   * @param  __HANDLE__: DMA handle
  368.   * @retval The specified half transfer complete flag index.
  369.   */      
  370. #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
  371. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
  372.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
  373.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
  374.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
  375.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
  376.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
  377.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
  378.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
  379.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
  380.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
  381.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
  382.    DMA_FLAG_HT7)
  383.  
  384. /**
  385.   * @brief  Return the current DMA Channel transfer error flag.
  386.   * @param  __HANDLE__: DMA handle
  387.   * @retval The specified transfer error flag index.
  388.   */
  389. #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
  390. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
  391.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
  392.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
  393.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
  394.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
  395.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
  396.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
  397.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
  398.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
  399.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
  400.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
  401.    DMA_FLAG_TE7)
  402.  
  403. /**
  404.   * @brief  Return the current DMA Channel Global interrupt flag.
  405.   * @param  __HANDLE__: DMA handle
  406.   * @retval The specified transfer error flag index.
  407.   */
  408. #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
  409. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
  410.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
  411.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
  412.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
  413.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
  414.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
  415.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
  416.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
  417.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
  418.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
  419.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
  420.    DMA_ISR_GIF7)
  421.  
  422. /**
  423.   * @brief  Get the DMA Channel pending flags.
  424.   * @param  __HANDLE__: DMA handle
  425.   * @param  __FLAG__: Get the specified flag.
  426.   *          This parameter can be any combination of the following values:
  427.   *            @arg DMA_FLAG_TCx: Transfer complete flag
  428.   *            @arg DMA_FLAG_HTx: Half transfer complete flag
  429.   *            @arg DMA_FLAG_TEx: Transfer error flag
  430.   *            @arg DMA_FLAG_GLx: Global interrupt flag
  431.   *         Where x can be from 1 to 7 to select the DMA Channel x flag.
  432.   * @retval The state of FLAG (SET or RESET).
  433.   */
  434. #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
  435.  (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
  436.  
  437. /**
  438.   * @brief  Clear the DMA Channel pending flags.
  439.   * @param  __HANDLE__: DMA handle
  440.   * @param  __FLAG__: specifies the flag to clear.
  441.   *          This parameter can be any combination of the following values:
  442.   *            @arg DMA_FLAG_TCx:  Transfer complete flag
  443.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
  444.   *            @arg DMA_FLAG_TEx:  Transfer error flag
  445.   *            @arg DMA_FLAG_GLx: Global interrupt flag
  446.     *         Where x can be from 1 to 7 to select the DMA Channel x flag.
  447.   * @retval None
  448.   */
  449. #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
  450. (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
  451.  
  452. #else
  453. /**
  454.   * @brief  Return the current DMA Channel transfer complete flag.
  455.   * @param  __HANDLE__: DMA handle
  456.   * @retval The specified transfer complete flag index.
  457.   */
  458.  
  459. #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
  460. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
  461.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
  462.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
  463.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
  464.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
  465.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
  466.    DMA_FLAG_TC7)
  467.  
  468. /**
  469.   * @brief  Return the current DMA Channel half transfer complete flag.
  470.   * @param  __HANDLE__: DMA handle
  471.   * @retval The specified half transfer complete flag index.
  472.   */      
  473. #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
  474. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
  475.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
  476.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
  477.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
  478.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
  479.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
  480.    DMA_FLAG_HT7)
  481.  
  482. /**
  483.   * @brief  Return the current DMA Channel transfer error flag.
  484.   * @param  __HANDLE__: DMA handle
  485.   * @retval The specified transfer error flag index.
  486.   */
  487. #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
  488. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
  489.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
  490.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
  491.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
  492.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
  493.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
  494.    DMA_FLAG_TE7)
  495.  
  496. /**
  497.   * @brief  Return the current DMA Channel Global interrupt flag.
  498.   * @param  __HANDLE__: DMA handle
  499.   * @retval The specified transfer error flag index.
  500.   */
  501. #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
  502. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
  503.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
  504.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
  505.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
  506.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
  507.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
  508.    DMA_ISR_GIF7)
  509.  
  510. /**
  511.   * @brief  Get the DMA Channel pending flags.
  512.   * @param  __HANDLE__: DMA handle
  513.   * @param  __FLAG__: Get the specified flag.
  514.   *          This parameter can be any combination of the following values:
  515.   *            @arg DMA_FLAG_TCx:  Transfer complete flag
  516.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
  517.   *            @arg DMA_FLAG_TEx:  Transfer error flag
  518.   *            @arg DMA_FLAG_GLx: Global interrupt flag
  519.   *         Where x can be from 1 to 7 to select the DMA Channel x flag.
  520.   * @retval The state of FLAG (SET or RESET).
  521.   */
  522. #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))
  523.  
  524. /**
  525.   * @brief  Clear the DMA Channel pending flags.
  526.   * @param  __HANDLE__: DMA handle
  527.   * @param  __FLAG__: specifies the flag to clear.
  528.   *          This parameter can be any combination of the following values:
  529.   *            @arg DMA_FLAG_TCx:  Transfer complete flag
  530.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
  531.   *            @arg DMA_FLAG_TEx:  Transfer error flag
  532.   *            @arg DMA_FLAG_GLx: Global interrupt flag
  533.   *         Where x can be from 1 to 7 to select the DMA Channel x flag.
  534.   * @retval None
  535.   */
  536. #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
  537.  
  538. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  539.  
  540. /**
  541.   * @brief  Enable the specified DMA Channel interrupts.
  542.   * @param  __HANDLE__: DMA handle
  543.   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
  544.   *          This parameter can be any combination of the following values:
  545.   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
  546.   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
  547.   *            @arg DMA_IT_TE:  Transfer error interrupt mask
  548.   * @retval None
  549.   */
  550. #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
  551.  
  552. /**
  553.   * @brief  Disable the specified DMA Channel interrupts.
  554.   * @param  __HANDLE__: DMA handle
  555.   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
  556.   *          This parameter can be any combination of the following values:
  557.   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
  558.   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
  559.   *            @arg DMA_IT_TE:  Transfer error interrupt mask
  560.   * @retval None
  561.   */
  562. #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
  563.  
  564. /**
  565.   * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
  566.   * @param  __HANDLE__: DMA handle
  567.   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
  568.   *          This parameter can be one of the following values:
  569.   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
  570.   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
  571.   *            @arg DMA_IT_TE:  Transfer error interrupt mask
  572.   * @retval The state of DMA_IT (SET or RESET).
  573.   */
  574. #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
  575.  
  576. /**
  577.   * @brief  Return the number of remaining data units in the current DMA Channel transfer.
  578.   * @param  __HANDLE__: DMA handle
  579.   * @retval The number of remaining data units in the current DMA Channel transfer.
  580.   */
  581. #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
  582.  
  583. /**
  584.   * @}
  585.   */
  586.  
  587. /* Exported functions --------------------------------------------------------*/
  588.  
  589. /** @addtogroup DMA_Exported_Functions
  590.   * @{
  591.   */
  592.  
  593. /** @addtogroup DMA_Exported_Functions_Group1
  594.   * @{
  595.   */
  596. /* Initialization and de-initialization functions *****************************/
  597. HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
  598. HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
  599. /**
  600.   * @}
  601.   */
  602.  
  603. /** @addtogroup DMA_Exported_Functions_Group2
  604.   * @{
  605.   */
  606. /* IO operation functions *****************************************************/
  607. HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
  608. HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
  609. HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
  610. HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
  611. HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
  612. void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
  613. HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
  614. HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
  615.  
  616. /**
  617.   * @}
  618.   */
  619.  
  620. /** @addtogroup DMA_Exported_Functions_Group3
  621.   * @{
  622.   */
  623. /* Peripheral State and Error functions ***************************************/
  624. HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
  625. uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
  626. /**
  627.   * @}
  628.   */
  629.  
  630. /**
  631.   * @}
  632.   */
  633.  
  634. /* Private macros ------------------------------------------------------------*/
  635. /** @defgroup DMA_Private_Macros DMA Private Macros
  636.   * @{
  637.   */
  638.  
  639. #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
  640.                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
  641.                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
  642.  
  643. #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
  644.  
  645. #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
  646.                                             ((STATE) == DMA_PINC_DISABLE))
  647.  
  648. #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
  649.                                         ((STATE) == DMA_MINC_DISABLE))
  650.  
  651. #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
  652.                                      ((REQUEST) == DMA_REQUEST_1) || \
  653.                                      ((REQUEST) == DMA_REQUEST_2) || \
  654.                                      ((REQUEST) == DMA_REQUEST_3) || \
  655.                                      ((REQUEST) == DMA_REQUEST_4) || \
  656.                                      ((REQUEST) == DMA_REQUEST_5) || \
  657.                                      ((REQUEST) == DMA_REQUEST_6) || \
  658.                                      ((REQUEST) == DMA_REQUEST_7))
  659. #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
  660.                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
  661.                                            ((SIZE) == DMA_PDATAALIGN_WORD))
  662.  
  663. #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
  664.                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
  665.                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
  666.  
  667. #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
  668.                            ((MODE) == DMA_CIRCULAR))
  669.  
  670. #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
  671.                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
  672.                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
  673.                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
  674.  
  675. /**
  676.   * @}
  677.   */
  678.  
  679. /* Private functions ---------------------------------------------------------*/
  680.  
  681. /**
  682.   * @}
  683.   */
  684.  
  685. /**
  686.   * @}
  687.   */
  688.  
  689. #ifdef __cplusplus
  690. }
  691. #endif
  692.  
  693. #endif /* __STM32L1xx_HAL_DMA_H */
  694.  
  695. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  696.