Subversion Repositories EngineBay2

Rev

Rev 2 | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32l1xx_hal_dma.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of DMA HAL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10.   * All rights reserved.</center></h2>
  11.   *
  12.   * This software component is licensed by ST under BSD 3-Clause license,
  13.   * the "License"; You may not use this file except in compliance with the
  14.   * License. You may obtain a copy of the License at:
  15.   *                        opensource.org/licenses/BSD-3-Clause
  16.   *
  17.   ******************************************************************************
  18.   */
  19.  
  20. /* Define to prevent recursive inclusion -------------------------------------*/
  21. #ifndef STM32L1xx_HAL_DMA_H
  22. #define STM32L1xx_HAL_DMA_H
  23.  
  24. #ifdef __cplusplus
  25.  extern "C" {
  26. #endif
  27.  
  28. /* Includes ------------------------------------------------------------------*/
  29. #include "stm32l1xx_hal_def.h"
  30.  
  31. /** @addtogroup STM32L1xx_HAL_Driver
  32.   * @{
  33.   */
  34.  
  35. /** @addtogroup DMA
  36.   * @{
  37.   */
  38.  
  39. /* Exported types ------------------------------------------------------------*/
  40. /** @defgroup DMA_Exported_Types DMA Exported Types
  41.   * @{
  42.   */
  43.  
  44. /**
  45.   * @brief  DMA Configuration Structure definition
  46.   */
  47. typedef struct
  48. {
  49.   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
  50.                                            from memory to memory or from peripheral to memory.
  51.                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
  52.  
  53.   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
  54.                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
  55.  
  56.   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
  57.                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
  58.  
  59.   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
  60.                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
  61.  
  62.   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
  63.                                            This parameter can be a value of @ref DMA_Memory_data_size */
  64.  
  65.   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
  66.                                            This parameter can be a value of @ref DMA_mode
  67.                                            @note The circular buffer mode cannot be used if the memory-to-memory
  68.                                                  data transfer is configured on the selected Channel */
  69.  
  70.   uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
  71.                                            This parameter can be a value of @ref DMA_Priority_level */
  72. } DMA_InitTypeDef;
  73.  
  74. /**
  75.   * @brief  HAL DMA State structures definition
  76.   */
  77. typedef enum
  78. {
  79.   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
  80.   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
  81.   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
  82.   HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                      */
  83. }HAL_DMA_StateTypeDef;
  84.  
  85. /**
  86.   * @brief  HAL DMA Error Code structure definition
  87.   */
  88. typedef enum
  89. {
  90.   HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
  91.   HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */
  92. }HAL_DMA_LevelCompleteTypeDef;
  93.  
  94.  
  95. /**
  96.   * @brief  HAL DMA Callback ID structure definition
  97.   */
  98. typedef enum
  99. {
  100.   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
  101.   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
  102.   HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */
  103.   HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */
  104.   HAL_DMA_XFER_ALL_CB_ID           = 0x04U     /*!< All               */
  105. }HAL_DMA_CallbackIDTypeDef;
  106.  
  107. /**
  108.   * @brief  DMA handle Structure definition
  109.   */
  110. typedef struct __DMA_HandleTypeDef
  111. {
  112.   DMA_Channel_TypeDef    *Instance;                                                     /*!< Register base address                */
  113.  
  114.   DMA_InitTypeDef       Init;                                                           /*!< DMA communication parameters         */
  115.  
  116.   HAL_LockTypeDef       Lock;                                                           /*!< DMA locking object                   */
  117.  
  118.   __IO HAL_DMA_StateTypeDef  State;                                                     /*!< DMA transfer state                   */
  119.  
  120.   void                  *Parent;                                                        /*!< Parent object state                  */
  121.  
  122.   void                  (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer complete callback       */
  123.  
  124.   void                  (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma);    /*!< DMA Half transfer complete callback  */
  125.  
  126.   void                  (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer error callback          */
  127.  
  128.   void                  (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer abort callback          */
  129.  
  130.   __IO uint32_t         ErrorCode;                                                      /*!< DMA Error code                       */
  131.  
  132.   DMA_TypeDef           *DmaBaseAddress;                                                /*!< DMA Channel Base Address             */
  133.  
  134.   uint32_t              ChannelIndex;                                                   /*!< DMA Channel Index                    */
  135.  
  136. }DMA_HandleTypeDef;
  137.  
  138. /**
  139.   * @}
  140.   */
  141.  
  142. /* Exported constants --------------------------------------------------------*/
  143.  
  144. /** @defgroup DMA_Exported_Constants DMA Exported Constants
  145.   * @{
  146.   */
  147.  
  148. /** @defgroup DMA_Error_Code DMA Error Code
  149.   * @{
  150.   */
  151. #define HAL_DMA_ERROR_NONE                 0x00000000U    /*!< No error                                */
  152. #define HAL_DMA_ERROR_TE                   0x00000001U    /*!< Transfer error                          */
  153. #define HAL_DMA_ERROR_NO_XFER              0x00000004U    /*!< Abort requested with no Xfer ongoing    */
  154. #define HAL_DMA_ERROR_TIMEOUT              0x00000020U    /*!< Timeout error                           */
  155. #define HAL_DMA_ERROR_NOT_SUPPORTED        0x00000100U    /*!< Not supported mode                      */
  156.  
  157. /**
  158.   * @}
  159.   */
  160.  
  161. /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
  162.   * @{
  163.   */
  164. #define DMA_PERIPH_TO_MEMORY         0x00000000U        /*!< Peripheral to memory direction */
  165. #define DMA_MEMORY_TO_PERIPH         DMA_CCR_DIR        /*!< Memory to peripheral direction */
  166. #define DMA_MEMORY_TO_MEMORY         DMA_CCR_MEM2MEM    /*!< Memory to memory direction     */
  167. /**
  168.   * @}
  169.   */
  170.  
  171. /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
  172.   * @{
  173.   */
  174. #define DMA_PINC_ENABLE              DMA_CCR_PINC  /*!< Peripheral increment mode Enable */
  175. #define DMA_PINC_DISABLE             0x00000000U   /*!< Peripheral increment mode Disable */
  176. /**
  177.   * @}
  178.   */
  179.  
  180. /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
  181.   * @{
  182.   */
  183. #define DMA_MINC_ENABLE              DMA_CCR_MINC   /*!< Memory increment mode Enable  */
  184. #define DMA_MINC_DISABLE             0x00000000U    /*!< Memory increment mode Disable */
  185. /**
  186.   * @}
  187.   */
  188.  
  189. /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
  190.   * @{
  191.   */
  192. #define DMA_PDATAALIGN_BYTE          0x00000000U       /*!< Peripheral data alignment : Byte     */
  193. #define DMA_PDATAALIGN_HALFWORD      DMA_CCR_PSIZE_0   /*!< Peripheral data alignment : HalfWord */
  194. #define DMA_PDATAALIGN_WORD          DMA_CCR_PSIZE_1   /*!< Peripheral data alignment : Word     */
  195. /**
  196.   * @}
  197.   */
  198.  
  199. /** @defgroup DMA_Memory_data_size DMA Memory data size
  200.   * @{
  201.   */
  202. #define DMA_MDATAALIGN_BYTE          0x00000000U       /*!< Memory data alignment : Byte     */
  203. #define DMA_MDATAALIGN_HALFWORD      DMA_CCR_MSIZE_0   /*!< Memory data alignment : HalfWord */
  204. #define DMA_MDATAALIGN_WORD          DMA_CCR_MSIZE_1   /*!< Memory data alignment : Word     */
  205. /**
  206.   * @}
  207.   */
  208.  
  209. /** @defgroup DMA_mode DMA mode
  210.   * @{
  211.   */
  212. #define DMA_NORMAL                0x00000000U                /*!< Normal mode                                    */
  213. #define DMA_CIRCULAR              DMA_CCR_CIRC               /*!< Circular mode                                  */
  214. /**
  215.   * @}
  216.   */
  217.  
  218. /** @defgroup DMA_Priority_level DMA Priority level
  219.   * @{
  220.   */
  221. #define DMA_PRIORITY_LOW             0x00000000U     /*!< Priority level : Low       */
  222. #define DMA_PRIORITY_MEDIUM          DMA_CCR_PL_0    /*!< Priority level : Medium    */
  223. #define DMA_PRIORITY_HIGH            DMA_CCR_PL_1    /*!< Priority level : High      */
  224. #define DMA_PRIORITY_VERY_HIGH       DMA_CCR_PL      /*!< Priority level : Very_High */
  225. /**
  226.   * @}
  227.   */
  228.  
  229.  
  230. /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
  231.   * @{
  232.   */
  233. #define DMA_IT_TC                         DMA_CCR_TCIE
  234. #define DMA_IT_HT                         DMA_CCR_HTIE
  235. #define DMA_IT_TE                         DMA_CCR_TEIE
  236. /**
  237.   * @}
  238.   */
  239.  
  240. /** @defgroup DMA_flag_definitions DMA flag definitions
  241.   * @{
  242.   */
  243. #define DMA_FLAG_GL1                      DMA_ISR_GIF1
  244. #define DMA_FLAG_TC1                      DMA_ISR_TCIF1
  245. #define DMA_FLAG_HT1                      DMA_ISR_HTIF1
  246. #define DMA_FLAG_TE1                      DMA_ISR_TEIF1
  247. #define DMA_FLAG_GL2                      DMA_ISR_GIF2
  248. #define DMA_FLAG_TC2                      DMA_ISR_TCIF2
  249. #define DMA_FLAG_HT2                      DMA_ISR_HTIF2
  250. #define DMA_FLAG_TE2                      DMA_ISR_TEIF2
  251. #define DMA_FLAG_GL3                      DMA_ISR_GIF3
  252. #define DMA_FLAG_TC3                      DMA_ISR_TCIF3
  253. #define DMA_FLAG_HT3                      DMA_ISR_HTIF3
  254. #define DMA_FLAG_TE3                      DMA_ISR_TEIF3
  255. #define DMA_FLAG_GL4                      DMA_ISR_GIF4
  256. #define DMA_FLAG_TC4                      DMA_ISR_TCIF4
  257. #define DMA_FLAG_HT4                      DMA_ISR_HTIF4
  258. #define DMA_FLAG_TE4                      DMA_ISR_TEIF4
  259. #define DMA_FLAG_GL5                      DMA_ISR_GIF5
  260. #define DMA_FLAG_TC5                      DMA_ISR_TCIF5
  261. #define DMA_FLAG_HT5                      DMA_ISR_HTIF5
  262. #define DMA_FLAG_TE5                      DMA_ISR_TEIF5
  263. #define DMA_FLAG_GL6                      DMA_ISR_GIF6
  264. #define DMA_FLAG_TC6                      DMA_ISR_TCIF6
  265. #define DMA_FLAG_HT6                      DMA_ISR_HTIF6
  266. #define DMA_FLAG_TE6                      DMA_ISR_TEIF6
  267. #define DMA_FLAG_GL7                      DMA_ISR_GIF7
  268. #define DMA_FLAG_TC7                      DMA_ISR_TCIF7
  269. #define DMA_FLAG_HT7                      DMA_ISR_HTIF7
  270. #define DMA_FLAG_TE7                      DMA_ISR_TEIF7
  271. /**
  272.   * @}
  273.   */
  274.  
  275. /**
  276.   * @}
  277.   */
  278.  
  279. /* Exported macros -----------------------------------------------------------*/
  280. /** @defgroup DMA_Exported_Macros DMA Exported Macros
  281.   * @{
  282.   */
  283.  
  284. /** @brief  Reset DMA handle state.
  285.   * @param  __HANDLE__ DMA handle
  286.   * @retval None
  287.   */
  288. #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
  289.  
  290. /**
  291.   * @brief  Enable the specified DMA Channel.
  292.   * @param  __HANDLE__ DMA handle
  293.   * @retval None
  294.   */
  295. #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
  296.  
  297. /**
  298.   * @brief  Disable the specified DMA Channel.
  299.   * @param  __HANDLE__ DMA handle
  300.   * @retval None
  301.   */
  302. #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
  303.  
  304.  
  305. /* Interrupt & Flag management */
  306. #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
  307.     defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
  308.     defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
  309.  
  310. /**
  311.   * @brief  Return the current DMA Channel transfer complete flag.
  312.   * @param  __HANDLE__ DMA handle
  313.   * @retval The specified transfer complete flag index.
  314.   */
  315.  
  316. #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
  317. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
  318.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
  319.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
  320.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
  321.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
  322.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
  323.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
  324.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
  325.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
  326.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
  327.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
  328.    DMA_FLAG_TC7)
  329.  
  330. /**
  331.   * @brief  Return the current DMA Channel half transfer complete flag.
  332.   * @param  __HANDLE__ DMA handle
  333.   * @retval The specified half transfer complete flag index.
  334.   */
  335. #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
  336. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
  337.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
  338.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
  339.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
  340.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
  341.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
  342.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
  343.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
  344.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
  345.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
  346.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
  347.    DMA_FLAG_HT7)
  348.  
  349. /**
  350.   * @brief  Return the current DMA Channel transfer error flag.
  351.   * @param  __HANDLE__ DMA handle
  352.   * @retval The specified transfer error flag index.
  353.   */
  354. #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
  355. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
  356.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
  357.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
  358.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
  359.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
  360.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
  361.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
  362.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
  363.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
  364.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
  365.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
  366.    DMA_FLAG_TE7)
  367.  
  368. /**
  369.   * @brief  Return the current DMA Channel Global interrupt flag.
  370.   * @param  __HANDLE__ DMA handle
  371.   * @retval The specified transfer error flag index.
  372.   */
  373. #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
  374. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
  375.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
  376.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
  377.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
  378.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
  379.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
  380.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
  381.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
  382.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
  383.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
  384.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
  385.    DMA_ISR_GIF7)
  386.  
  387. /**
  388.   * @brief  Get the DMA Channel pending flags.
  389.   * @param  __HANDLE__ DMA handle
  390.   * @param  __FLAG__ Get the specified flag.
  391.   *          This parameter can be any combination of the following values:
  392.   *            @arg DMA_FLAG_TCx: Transfer complete flag
  393.   *            @arg DMA_FLAG_HTx: Half transfer complete flag
  394.   *            @arg DMA_FLAG_TEx: Transfer error flag
  395.   *            @arg DMA_FLAG_GLx: Global interrupt flag
  396.   *         Where x can be from 1 to 7 to select the DMA Channel x flag.
  397.   * @retval The state of FLAG (SET or RESET).
  398.   */
  399. #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
  400.  (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
  401.  
  402. /**
  403.   * @brief  Clear the DMA Channel pending flags.
  404.   * @param  __HANDLE__ DMA handle
  405.   * @param  __FLAG__ specifies the flag to clear.
  406.   *          This parameter can be any combination of the following values:
  407.   *            @arg DMA_FLAG_TCx:  Transfer complete flag
  408.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
  409.   *            @arg DMA_FLAG_TEx:  Transfer error flag
  410.   *            @arg DMA_FLAG_GLx: Global interrupt flag
  411.     *         Where x can be from 1 to 7 to select the DMA Channel x flag.
  412.   * @retval None
  413.   */
  414. #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
  415. (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
  416.  
  417. #else
  418. /**
  419.   * @brief  Return the current DMA Channel transfer complete flag.
  420.   * @param  __HANDLE__ DMA handle
  421.   * @retval The specified transfer complete flag index.
  422.   */
  423.  
  424. #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
  425. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
  426.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
  427.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
  428.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
  429.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
  430.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
  431.    DMA_FLAG_TC7)
  432.  
  433. /**
  434.   * @brief  Return the current DMA Channel half transfer complete flag.
  435.   * @param  __HANDLE__ DMA handle
  436.   * @retval The specified half transfer complete flag index.
  437.   */
  438. #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
  439. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
  440.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
  441.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
  442.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
  443.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
  444.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
  445.    DMA_FLAG_HT7)
  446.  
  447. /**
  448.   * @brief  Return the current DMA Channel transfer error flag.
  449.   * @param  __HANDLE__ DMA handle
  450.   * @retval The specified transfer error flag index.
  451.   */
  452. #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
  453. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
  454.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
  455.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
  456.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
  457.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
  458.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
  459.    DMA_FLAG_TE7)
  460.  
  461. /**
  462.   * @brief  Return the current DMA Channel Global interrupt flag.
  463.   * @param  __HANDLE__ DMA handle
  464.   * @retval The specified transfer error flag index.
  465.   */
  466. #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
  467. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
  468.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
  469.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
  470.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
  471.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
  472.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
  473.    DMA_ISR_GIF7)
  474.  
  475. /**
  476.   * @brief  Get the DMA Channel pending flags.
  477.   * @param  __HANDLE__ DMA handle
  478.   * @param  __FLAG__ Get the specified flag.
  479.   *          This parameter can be any combination of the following values:
  480.   *            @arg DMA_FLAG_TCIFx:  Transfer complete flag
  481.   *            @arg DMA_FLAG_HTIFx:  Half transfer complete flag
  482.   *            @arg DMA_FLAG_TEIFx:  Transfer error flag
  483.   *            @arg DMA_ISR_GIFx:    Global interrupt flag
  484.   *         Where x can be from 1 to 7 to select the DMA Channel x flag.
  485.   * @retval The state of FLAG (SET or RESET).
  486.   */
  487. #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))
  488.  
  489. /**
  490.   * @brief  Clear the DMA Channel pending flags.
  491.   * @param  __HANDLE__ DMA handle
  492.   * @param  __FLAG__ specifies the flag to clear.
  493.   *          This parameter can be any combination of the following values:
  494.   *            @arg DMA_FLAG_TCx:  Transfer complete flag
  495.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
  496.   *            @arg DMA_FLAG_TEx:  Transfer error flag
  497.   *            @arg DMA_FLAG_GLx: Global interrupt flag
  498.   *         Where x can be from 1 to 7 to select the DMA Channel x flag.
  499.   * @retval None
  500.   */
  501. #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
  502.  
  503. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  504.  
  505. /**
  506.   * @brief  Enable the specified DMA Channel interrupts.
  507.   * @param  __HANDLE__ DMA handle
  508.   * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
  509.   *          This parameter can be any combination of the following values:
  510.   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
  511.   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
  512.   *            @arg DMA_IT_TE:  Transfer error interrupt mask
  513.   * @retval None
  514.   */
  515. #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
  516.  
  517. /**
  518.   * @brief  Disable the specified DMA Channel interrupts.
  519.   * @param  __HANDLE__ DMA handle
  520.   * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
  521.   *          This parameter can be any combination of the following values:
  522.   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
  523.   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
  524.   *            @arg DMA_IT_TE:  Transfer error interrupt mask
  525.   * @retval None
  526.   */
  527. #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
  528.  
  529. /**
  530.   * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
  531.   * @param  __HANDLE__ DMA handle
  532.   * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
  533.   *          This parameter can be one of the following values:
  534.   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
  535.   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
  536.   *            @arg DMA_IT_TE:  Transfer error interrupt mask
  537.   * @retval The state of DMA_IT (SET or RESET).
  538.   */
  539. #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
  540.  
  541. /**
  542.   * @brief  Return the number of remaining data units in the current DMA Channel transfer.
  543.   * @param  __HANDLE__ DMA handle
  544.   * @retval The number of remaining data units in the current DMA Channel transfer.
  545.   */
  546. #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
  547.  
  548. /**
  549.   * @}
  550.   */
  551.  
  552. /* Exported functions --------------------------------------------------------*/
  553.  
  554. /** @addtogroup DMA_Exported_Functions
  555.   * @{
  556.   */
  557.  
  558. /** @addtogroup DMA_Exported_Functions_Group1
  559.   * @{
  560.   */
  561. /* Initialization and de-initialization functions *****************************/
  562. HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
  563. HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
  564. /**
  565.   * @}
  566.   */
  567.  
  568. /** @addtogroup DMA_Exported_Functions_Group2
  569.   * @{
  570.   */
  571. /* IO operation functions *****************************************************/
  572. HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
  573. HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
  574. HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
  575. HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
  576. HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
  577. void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
  578. HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
  579. HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
  580.  
  581. /**
  582.   * @}
  583.   */
  584.  
  585. /** @addtogroup DMA_Exported_Functions_Group3
  586.   * @{
  587.   */
  588. /* Peripheral State and Error functions ***************************************/
  589. HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
  590. uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
  591. /**
  592.   * @}
  593.   */
  594.  
  595. /**
  596.   * @}
  597.   */
  598.  
  599. /* Private macros ------------------------------------------------------------*/
  600. /** @defgroup DMA_Private_Macros DMA Private Macros
  601.   * @{
  602.   */
  603.  
  604. #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
  605.                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
  606.                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
  607.  
  608. #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
  609.  
  610. #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
  611.                                             ((STATE) == DMA_PINC_DISABLE))
  612.  
  613. #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
  614.                                         ((STATE) == DMA_MINC_DISABLE))
  615.  
  616. #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
  617.                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
  618.                                            ((SIZE) == DMA_PDATAALIGN_WORD))
  619.  
  620. #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
  621.                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
  622.                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
  623.  
  624. #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
  625.                            ((MODE) == DMA_CIRCULAR))
  626.  
  627. #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
  628.                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
  629.                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
  630.                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
  631.  
  632. /**
  633.   * @}
  634.   */
  635.  
  636. /* Private functions ---------------------------------------------------------*/
  637.  
  638. /**
  639.   * @}
  640.   */
  641.  
  642. /**
  643.   * @}
  644.   */
  645.  
  646. #ifdef __cplusplus
  647. }
  648. #endif
  649.  
  650. #endif /* STM32L1xx_HAL_DMA_H */
  651.  
  652. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  653.