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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_utils.c
  4.   * @author  MCD Application Team
  5.   * @brief   UTILS LL module driver.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10.   * All rights reserved.</center></h2>
  11.   *
  12.   * This software component is licensed by ST under BSD 3-Clause license,
  13.   * the "License"; You may not use this file except in compliance with the
  14.   * License. You may obtain a copy of the License at:
  15.   *                        opensource.org/licenses/BSD-3-Clause
  16.   *
  17.   ******************************************************************************
  18.   */
  19.  
  20. /* Includes ------------------------------------------------------------------*/
  21. #include "stm32f1xx_ll_rcc.h"
  22. #include "stm32f1xx_ll_utils.h"
  23. #include "stm32f1xx_ll_system.h"
  24. #ifdef  USE_FULL_ASSERT
  25. #include "stm32_assert.h"
  26. #else
  27. #define assert_param(expr) ((void)0U)
  28. #endif
  29.  
  30. /** @addtogroup STM32F1xx_LL_Driver
  31.   * @{
  32.   */
  33.  
  34. /** @addtogroup UTILS_LL
  35.   * @{
  36.   */
  37.  
  38. /* Private types -------------------------------------------------------------*/
  39. /* Private variables ---------------------------------------------------------*/
  40. /* Private constants ---------------------------------------------------------*/
  41. /** @addtogroup UTILS_LL_Private_Constants
  42.   * @{
  43.   */
  44.  
  45. /* Defines used for PLL range */
  46. #define UTILS_PLL_OUTPUT_MAX        RCC_MAX_FREQUENCY    /*!< Frequency max for PLL output, in Hz  */
  47.  
  48. /* Defines used for HSE range */
  49. #define UTILS_HSE_FREQUENCY_MIN     RCC_HSE_MIN       /*!< Frequency min for HSE frequency, in Hz   */
  50. #define UTILS_HSE_FREQUENCY_MAX     RCC_HSE_MAX       /*!< Frequency max for HSE frequency, in Hz   */
  51.  
  52. /* Defines used for FLASH latency according to HCLK Frequency */
  53. #if defined(FLASH_ACR_LATENCY)
  54. #define UTILS_LATENCY1_FREQ         24000000U        /*!< SYSCLK frequency to set FLASH latency 1 */
  55. #define UTILS_LATENCY2_FREQ         48000000U        /*!< SYSCLK frequency to set FLASH latency 2 */
  56. #else
  57. /*!< No Latency Configuration in this device */
  58. #endif
  59. /**
  60.   * @}
  61.   */
  62. /* Private macros ------------------------------------------------------------*/
  63. /** @addtogroup UTILS_LL_Private_Macros
  64.   * @{
  65.   */
  66. #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
  67.                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
  68.                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
  69.                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
  70.                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
  71.                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
  72.                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
  73.                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
  74.                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
  75.  
  76. #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
  77.                                       || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
  78.                                       || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
  79.                                       || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
  80.                                       || ((__VALUE__) == LL_RCC_APB1_DIV_16))
  81.  
  82. #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
  83.                                       || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
  84.                                       || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
  85.                                       || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
  86.                                       || ((__VALUE__) == LL_RCC_APB2_DIV_16))
  87.  
  88. #if defined(RCC_CFGR_PLLMULL6_5)
  89. #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \
  90.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
  91.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
  92.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
  93.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
  94.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
  95.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_6_5))
  96. #else
  97. #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
  98.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
  99.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
  100.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
  101.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
  102.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
  103.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
  104.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
  105.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
  106.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
  107.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
  108.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
  109.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
  110.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
  111.                                           || ((__VALUE__) == LL_RCC_PLL_MUL_16))
  112. #endif /* RCC_CFGR_PLLMULL6_5 */
  113.  
  114. #if defined(RCC_CFGR2_PREDIV1)
  115. #define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_2)   || \
  116.                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_3)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_4)   || \
  117.                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_5)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_6)   || \
  118.                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_7)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_8)   || \
  119.                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_9)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_10)  || \
  120.                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12)  || \
  121.                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14)  || \
  122.                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
  123. #else
  124. #define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
  125. #endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/
  126.  
  127. #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
  128.  
  129.  
  130. #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
  131.                                         || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
  132.  
  133. #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
  134. /**
  135.   * @}
  136.   */
  137. /* Private function prototypes -----------------------------------------------*/
  138. /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
  139.   * @{
  140.   */
  141. static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
  142.                                                LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
  143. static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
  144. static ErrorStatus UTILS_PLL_IsBusy(void);
  145. /**
  146.   * @}
  147.   */
  148.  
  149. /* Exported functions --------------------------------------------------------*/
  150. /** @addtogroup UTILS_LL_Exported_Functions
  151.   * @{
  152.   */
  153.  
  154. /** @addtogroup UTILS_LL_EF_DELAY
  155.   * @{
  156.   */
  157.  
  158. /**
  159.   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
  160.   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
  161.   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
  162.   * @param  HCLKFrequency HCLK frequency in Hz
  163.   * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
  164.   * @retval None
  165.   */
  166. void LL_Init1msTick(uint32_t HCLKFrequency)
  167. {
  168.   /* Use frequency provided in argument */
  169.   LL_InitTick(HCLKFrequency, 1000U);
  170. }
  171.  
  172. /**
  173.   * @brief  This function provides accurate delay (in milliseconds) based
  174.   *         on SysTick counter flag
  175.   * @note   When a RTOS is used, it is recommended to avoid using blocking delay
  176.   *         and use rather osDelay service.
  177.   * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
  178.   *         will configure Systick to 1ms
  179.   * @param  Delay specifies the delay time length, in milliseconds.
  180.   * @retval None
  181.   */
  182. void LL_mDelay(uint32_t Delay)
  183. {
  184.   __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
  185.   /* Add this code to indicate that local variable is not used */
  186.   ((void)tmp);
  187.  
  188.   /* Add a period to guaranty minimum wait */
  189.   if (Delay < LL_MAX_DELAY)
  190.   {
  191.     Delay++;
  192.   }
  193.  
  194.   while (Delay)
  195.   {
  196.     if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
  197.     {
  198.       Delay--;
  199.     }
  200.   }
  201. }
  202.  
  203. /**
  204.   * @}
  205.   */
  206.  
  207. /** @addtogroup UTILS_EF_SYSTEM
  208.   *  @brief    System Configuration functions
  209.   *
  210.   @verbatim
  211.  ===============================================================================
  212.            ##### System Configuration functions #####
  213.  ===============================================================================
  214.     [..]
  215.          System, AHB and APB buses clocks configuration
  216.  
  217.          (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.
  218.   @endverbatim
  219.   @internal
  220.              Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
  221.              (++) +-----------------------------------------------+
  222.              (++) | Latency       | SYSCLK clock frequency (MHz)  |
  223.              (++) |---------------|-------------------------------|
  224.              (++) |0WS(1CPU cycle)|       0 < SYSCLK <= 24        |
  225.              (++) |---------------|-------------------------------|
  226.              (++) |1WS(2CPU cycle)|      24 < SYSCLK <= 48        |
  227.              (++) |---------------|-------------------------------|
  228.              (++) |2WS(3CPU cycle)|      48 < SYSCLK <= 72        |
  229.              (++) +-----------------------------------------------+
  230.   @endinternal
  231.   * @{
  232.   */
  233.  
  234. /**
  235.   * @brief  This function sets directly SystemCoreClock CMSIS variable.
  236.   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
  237.   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
  238.   * @retval None
  239.   */
  240. void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
  241. {
  242.   /* HCLK clock frequency */
  243.   SystemCoreClock = HCLKFrequency;
  244. }
  245.  
  246. /**
  247.   * @brief  Update number of Flash wait states in line with new frequency and current
  248.             voltage range.
  249.   * @param  Frequency  SYSCLK frequency
  250.   * @retval An ErrorStatus enumeration value:
  251.   *          - SUCCESS: Latency has been modified
  252.   *          - ERROR: Latency cannot be modified
  253.   */
  254. #if defined(FLASH_ACR_LATENCY)
  255. ErrorStatus LL_SetFlashLatency(uint32_t Frequency)
  256. {
  257.   uint32_t timeout;
  258.   uint32_t getlatency;
  259.   uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
  260.   ErrorStatus status = SUCCESS;
  261.  
  262.   /* Frequency cannot be equal to 0 */
  263.   if (Frequency == 0U)
  264.   {
  265.     status = ERROR;
  266.   }
  267.   else
  268.   {
  269.     if (Frequency > UTILS_LATENCY2_FREQ)
  270.     {
  271.       /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
  272.       latency = LL_FLASH_LATENCY_2;
  273.     }
  274.     else
  275.     {
  276.       if (Frequency > UTILS_LATENCY1_FREQ)
  277.       {
  278.         /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
  279.         latency = LL_FLASH_LATENCY_1;
  280.       }
  281.       else
  282.       {
  283.         /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
  284.         latency = LL_FLASH_LATENCY_0;
  285.       }
  286.     }
  287.  
  288.     if (status != ERROR)
  289.     {
  290.       LL_FLASH_SetLatency(latency);
  291.  
  292.       /* Check that the new number of wait states is taken into account to access the Flash
  293.          memory by reading the FLASH_ACR register */
  294.       timeout = 2;
  295.       do
  296.       {
  297.       /* Wait for Flash latency to be updated */
  298.       getlatency = LL_FLASH_GetLatency();
  299.       timeout--;
  300.       } while ((getlatency != latency) && (timeout > 0));
  301.  
  302.       if(getlatency != latency)
  303.       {
  304.         status = ERROR;
  305.       }
  306.       else
  307.       {
  308.         status = SUCCESS;
  309.       }
  310.     }
  311.   }
  312.  
  313.   return status;
  314. }
  315. #endif /* FLASH_ACR_LATENCY */
  316.  
  317. /**
  318.   * @brief  This function configures system clock with HSI as clock source of the PLL
  319.   * @note   The application need to ensure that PLL is disabled.
  320.   * @note   Function is based on the following formula:
  321.   *         - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
  322.   *         - PREDIV: Set to 2 for few devices
  323.   *         - PLLMUL: The application software must set correctly the PLL multiplication factor to
  324.   *                   not exceed 72MHz
  325.   * @note   FLASH latency can be modified through this function.
  326.   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
  327.   *                             the configuration information for the PLL.
  328.   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
  329.   *                             the configuration information for the BUS prescalers.
  330.   * @retval An ErrorStatus enumeration value:
  331.   *          - SUCCESS: Max frequency configuration done
  332.   *          - ERROR: Max frequency configuration not done
  333.   */
  334. ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
  335.                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
  336. {
  337.   ErrorStatus status = SUCCESS;
  338.   uint32_t pllfreq = 0U;
  339.  
  340.   /* Check if one of the PLL is enabled */
  341.   if (UTILS_PLL_IsBusy() == SUCCESS)
  342.   {
  343. #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
  344.     /* Check PREDIV value */
  345.     assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
  346. #else
  347.     /* Force PREDIV value to 2 */
  348.     UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
  349. #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
  350.     /* Calculate the new PLL output frequency */
  351.     pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
  352.  
  353.     /* Enable HSI if not enabled */
  354.     if (LL_RCC_HSI_IsReady() != 1U)
  355.     {
  356.       LL_RCC_HSI_Enable();
  357.       while (LL_RCC_HSI_IsReady() != 1U)
  358.       {
  359.         /* Wait for HSI ready */
  360.       }
  361.     }
  362.  
  363.     /* Configure PLL */
  364.     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
  365.  
  366.     /* Enable PLL and switch system clock to PLL */
  367.     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
  368.   }
  369.   else
  370.   {
  371.     /* Current PLL configuration cannot be modified */
  372.     status = ERROR;
  373.   }
  374.  
  375.   return status;
  376. }
  377.  
  378. /**
  379.   * @brief  This function configures system clock with HSE as clock source of the PLL
  380.   * @note   The application need to ensure that PLL is disabled.
  381.   * @note   Function is based on the following formula:
  382.   *         - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
  383.   *         - PREDIV: Set to 2 for few devices
  384.   *         - PLLMUL: The application software must set correctly the PLL multiplication factor to
  385.   *                   not exceed @ref UTILS_PLL_OUTPUT_MAX
  386.   * @note   FLASH latency can be modified through this function.
  387.   * @param  HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
  388.   * @param  HSEBypass This parameter can be one of the following values:
  389.   *         @arg @ref LL_UTILS_HSEBYPASS_ON
  390.   *         @arg @ref LL_UTILS_HSEBYPASS_OFF
  391.   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
  392.   *                             the configuration information for the PLL.
  393.   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
  394.   *                             the configuration information for the BUS prescalers.
  395.   * @retval An ErrorStatus enumeration value:
  396.   *          - SUCCESS: Max frequency configuration done
  397.   *          - ERROR: Max frequency configuration not done
  398.   */
  399. ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
  400.                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
  401. {
  402.   ErrorStatus status = SUCCESS;
  403.   uint32_t pllfreq = 0U;
  404.  
  405.   /* Check the parameters */
  406.   assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
  407.   assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
  408.  
  409.   /* Check if one of the PLL is enabled */
  410.   if (UTILS_PLL_IsBusy() == SUCCESS)
  411.   {
  412.     assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
  413.  
  414.     /* Calculate the new PLL output frequency */
  415.     pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
  416.  
  417.     /* Enable HSE if not enabled */
  418.     if (LL_RCC_HSE_IsReady() != 1U)
  419.     {
  420.       /* Check if need to enable HSE bypass feature or not */
  421.       if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
  422.       {
  423.         LL_RCC_HSE_EnableBypass();
  424.       }
  425.       else
  426.       {
  427.         LL_RCC_HSE_DisableBypass();
  428.       }
  429.  
  430.       /* Enable HSE */
  431.       LL_RCC_HSE_Enable();
  432.       while (LL_RCC_HSE_IsReady() != 1U)
  433.       {
  434.         /* Wait for HSE ready */
  435.       }
  436.     }
  437.  
  438.     /* Configure PLL */
  439.     LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
  440.  
  441.     /* Enable PLL and switch system clock to PLL */
  442.     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
  443.   }
  444.   else
  445.   {
  446.     /* Current PLL configuration cannot be modified */
  447.     status = ERROR;
  448.   }
  449.  
  450.   return status;
  451. }
  452.  
  453. /**
  454.   * @}
  455.   */
  456.  
  457. /**
  458.   * @}
  459.   */
  460.  
  461. /** @addtogroup UTILS_LL_Private_Functions
  462.   * @{
  463.   */
  464. /**
  465.   * @brief  Function to check that PLL can be modified
  466.   * @param  PLL_InputFrequency  PLL input frequency (in Hz)
  467.   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
  468.   *                             the configuration information for the PLL.
  469.   * @retval PLL output frequency (in Hz)
  470.   */
  471. static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
  472. {
  473.   uint32_t pllfreq = 0U;
  474.  
  475.   /* Check the parameters */
  476.   assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
  477.  
  478.   /* Check different PLL parameters according to RM                          */
  479. #if defined (RCC_CFGR2_PREDIV1)
  480.   pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
  481. #else
  482.   pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
  483. #endif /*RCC_CFGR2_PREDIV1SRC*/
  484.   assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
  485.  
  486.   return pllfreq;
  487. }
  488.  
  489. /**
  490.   * @brief  Function to check that PLL can be modified
  491.   * @retval An ErrorStatus enumeration value:
  492.   *          - SUCCESS: PLL modification can be done
  493.   *          - ERROR: PLL is busy
  494.   */
  495. static ErrorStatus UTILS_PLL_IsBusy(void)
  496. {
  497.   ErrorStatus status = SUCCESS;
  498.  
  499.   /* Check if PLL is busy*/
  500.   if (LL_RCC_PLL_IsReady() != 0U)
  501.   {
  502.     /* PLL configuration cannot be modified */
  503.     status = ERROR;
  504.   }
  505. #if defined(RCC_PLL2_SUPPORT)
  506.   /* Check if PLL2 is busy*/
  507.   if (LL_RCC_PLL2_IsReady() != 0U)
  508.   {
  509.     /* PLL2 configuration cannot be modified */
  510.     status = ERROR;
  511.   }
  512. #endif /* RCC_PLL2_SUPPORT */
  513.  
  514. #if defined(RCC_PLLI2S_SUPPORT)
  515.   /* Check if PLLI2S  is busy*/
  516.   if (LL_RCC_PLLI2S_IsReady() != 0U)
  517.   {
  518.     /* PLLI2S configuration cannot be modified */
  519.     status = ERROR;
  520.   }
  521. #endif /* RCC_PLLI2S_SUPPORT */
  522.  
  523.   return status;
  524. }
  525.  
  526. /**
  527.   * @brief  Function to enable PLL and switch system clock to PLL
  528.   * @param  SYSCLK_Frequency SYSCLK frequency
  529.   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
  530.   *                             the configuration information for the BUS prescalers.
  531.   * @retval An ErrorStatus enumeration value:
  532.   *          - SUCCESS: No problem to switch system to PLL
  533.   *          - ERROR: Problem to switch system to PLL
  534.   */
  535. static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
  536. {
  537.   ErrorStatus status = SUCCESS;
  538. #if defined(FLASH_ACR_LATENCY)
  539.   uint32_t sysclk_frequency_current = 0U;
  540. #endif /* FLASH_ACR_LATENCY */
  541.  
  542.   assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
  543.   assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
  544.   assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
  545.  
  546. #if defined(FLASH_ACR_LATENCY)
  547.   /* Calculate current SYSCLK frequency */
  548.   sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]);
  549. #endif /* FLASH_ACR_LATENCY */
  550.  
  551.   /* Increasing the number of wait states because of higher CPU frequency */
  552. #if defined (FLASH_ACR_LATENCY)
  553.   if (sysclk_frequency_current < SYSCLK_Frequency)
  554.   {
  555.     /* Set FLASH latency to highest latency */
  556.     status = LL_SetFlashLatency(SYSCLK_Frequency);
  557.   }
  558. #endif /* FLASH_ACR_LATENCY */
  559.  
  560.   /* Update system clock configuration */
  561.   if (status == SUCCESS)
  562.   {
  563. #if defined(RCC_PLL2_SUPPORT)
  564.     if (LL_RCC_PLL_GetMainSource() != LL_RCC_PLLSOURCE_HSI_DIV_2)
  565.     {
  566.       /* Enable PLL2 */
  567.       LL_RCC_PLL2_Enable();
  568.       while (LL_RCC_PLL2_IsReady() != 1U)
  569.       {
  570.         /* Wait for PLL2 ready */
  571.       }
  572.     }
  573. #endif /* RCC_PLL2_SUPPORT */
  574.     /* Enable PLL */
  575.     LL_RCC_PLL_Enable();
  576.     while (LL_RCC_PLL_IsReady() != 1U)
  577.     {
  578.       /* Wait for PLL ready */
  579.     }
  580.  
  581.     /* Sysclk activation on the main PLL */
  582.     LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
  583.     LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
  584.     while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
  585.     {
  586.       /* Wait for system clock switch to PLL */
  587.     }
  588.  
  589.     /* Set APB1 & APB2 prescaler*/
  590.     LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
  591.     LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
  592.   }
  593.  
  594.   /* Decreasing the number of wait states because of lower CPU frequency */
  595. #if defined (FLASH_ACR_LATENCY)
  596.   if (sysclk_frequency_current > SYSCLK_Frequency)
  597.   {
  598.     /* Set FLASH latency to lowest latency */
  599.     status = LL_SetFlashLatency(SYSCLK_Frequency);
  600.   }
  601. #endif /* FLASH_ACR_LATENCY */
  602.  
  603.   /* Update SystemCoreClock variable */
  604.   if (status == SUCCESS)
  605.   {
  606.     LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
  607.   }
  608.  
  609.   return status;
  610. }
  611.  
  612. /**
  613.   * @}
  614.   */
  615.  
  616. /**
  617.   * @}
  618.   */
  619.  
  620. /**
  621.   * @}
  622.   */
  623.  
  624. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  625.