Subversion Repositories LedShow

Rev

Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_tim.c
  4.   * @author  MCD Application Team
  5.   * @brief   TIM LL module driver.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10.   *
  11.   * Redistribution and use in source and binary forms, with or without modification,
  12.   * are permitted provided that the following conditions are met:
  13.   *   1. Redistributions of source code must retain the above copyright notice,
  14.   *      this list of conditions and the following disclaimer.
  15.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16.   *      this list of conditions and the following disclaimer in the documentation
  17.   *      and/or other materials provided with the distribution.
  18.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19.   *      may be used to endorse or promote products derived from this software
  20.   *      without specific prior written permission.
  21.   *
  22.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32.   *
  33.   ******************************************************************************
  34.   */
  35. #if defined(USE_FULL_LL_DRIVER)
  36.  
  37. /* Includes ------------------------------------------------------------------*/
  38. #include "stm32f1xx_ll_tim.h"
  39. #include "stm32f1xx_ll_bus.h"
  40.  
  41. #ifdef  USE_FULL_ASSERT
  42. #include "stm32_assert.h"
  43. #else
  44. #define assert_param(expr) ((void)0U)
  45. #endif
  46.  
  47. /** @addtogroup STM32F1xx_LL_Driver
  48.   * @{
  49.   */
  50.  
  51. #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
  52.  
  53. /** @addtogroup TIM_LL
  54.   * @{
  55.   */
  56.  
  57. /* Private types -------------------------------------------------------------*/
  58. /* Private variables ---------------------------------------------------------*/
  59. /* Private constants ---------------------------------------------------------*/
  60. /* Private macros ------------------------------------------------------------*/
  61. /** @addtogroup TIM_LL_Private_Macros
  62.   * @{
  63.   */
  64. #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
  65.                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
  66.                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
  67.                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
  68.                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
  69.  
  70. #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
  71.                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
  72.                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
  73.  
  74. #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
  75.                                   || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
  76.                                   || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
  77.                                   || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
  78.                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
  79.                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
  80.                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
  81.                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
  82.  
  83. #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
  84.                                    || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
  85.  
  86. #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
  87.                                       || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
  88.  
  89. #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
  90.                                        || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
  91.  
  92. #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
  93.                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
  94.                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
  95.  
  96. #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
  97.                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
  98.                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
  99.                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
  100.  
  101. #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
  102.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
  103.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
  104.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
  105.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
  106.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
  107.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
  108.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
  109.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
  110.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
  111.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
  112.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
  113.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
  114.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
  115.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
  116.                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
  117.  
  118. #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
  119.                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
  120.  
  121. #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
  122.                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
  123.                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
  124.  
  125. #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
  126.                                                || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
  127.  
  128. #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
  129.                                      || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
  130.  
  131. #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
  132.                                       || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
  133.  
  134. #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
  135.                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
  136.                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
  137.                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
  138.  
  139. #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
  140.                                        || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
  141.  
  142. #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
  143.                                           || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
  144.  
  145. #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
  146.                                                   || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
  147. /**
  148.   * @}
  149.   */
  150.  
  151.  
  152. /* Private function prototypes -----------------------------------------------*/
  153. /** @defgroup TIM_LL_Private_Functions TIM Private Functions
  154.   * @{
  155.   */
  156. static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  157. static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  158. static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  159. static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  160. static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  161. static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  162. static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  163. static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  164. /**
  165.   * @}
  166.   */
  167.  
  168. /* Exported functions --------------------------------------------------------*/
  169. /** @addtogroup TIM_LL_Exported_Functions
  170.   * @{
  171.   */
  172.  
  173. /** @addtogroup TIM_LL_EF_Init
  174.   * @{
  175.   */
  176.  
  177. /**
  178.   * @brief  Set TIMx registers to their reset values.
  179.   * @param  TIMx Timer instance
  180.   * @retval An ErrorStatus enumeration value:
  181.   *          - SUCCESS: TIMx registers are de-initialized
  182.   *          - ERROR: invalid TIMx instance
  183.   */
  184. ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
  185. {
  186.   ErrorStatus result = SUCCESS;
  187.  
  188.   /* Check the parameters */
  189.   assert_param(IS_TIM_INSTANCE(TIMx));
  190.  
  191.   if (TIMx == TIM2)
  192.   {
  193.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
  194.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
  195.   }
  196. #if defined(TIM1)
  197.   else if (TIMx == TIM1)
  198.   {
  199.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
  200.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
  201.   }
  202. #endif
  203. #if defined(TIM3)
  204.   else if (TIMx == TIM3)
  205.   {
  206.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
  207.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
  208.   }
  209. #endif
  210. #if defined(TIM4)
  211.   else if (TIMx == TIM4)
  212.   {
  213.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
  214.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
  215.   }
  216. #endif
  217. #if defined(TIM5)
  218.   else if (TIMx == TIM5)
  219.   {
  220.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
  221.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
  222.   }
  223. #endif
  224. #if defined(TIM6)
  225.   else if (TIMx == TIM6)
  226.   {
  227.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
  228.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
  229.   }
  230. #endif
  231. #if defined (TIM7)
  232.   else if (TIMx == TIM7)
  233.   {
  234.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
  235.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
  236.   }
  237. #endif
  238. #if defined(TIM8)
  239.   else if (TIMx == TIM8)
  240.   {
  241.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
  242.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
  243.   }
  244. #endif
  245. #if defined(TIM9)
  246.   else if (TIMx == TIM9)
  247.   {
  248.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
  249.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
  250.   }
  251. #endif
  252. #if defined(TIM10)
  253.   else if (TIMx == TIM10)
  254.   {
  255.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
  256.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
  257.   }
  258. #endif
  259. #if defined(TIM11)
  260.   else if (TIMx == TIM11)
  261.   {
  262.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
  263.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
  264.   }
  265. #endif
  266. #if defined(TIM12)
  267.   else if (TIMx == TIM12)
  268.   {
  269.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
  270.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
  271.   }
  272. #endif
  273. #if defined(TIM13)
  274.   else if (TIMx == TIM13)
  275.   {
  276.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
  277.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
  278.   }
  279. #endif
  280. #if defined(TIM14)
  281.   else if (TIMx == TIM14)
  282.   {
  283.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
  284.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
  285.   }
  286. #endif
  287. #if defined(TIM15)
  288.   else if (TIMx == TIM15)
  289.   {
  290.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
  291.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
  292.   }
  293. #endif
  294. #if defined(TIM16)
  295.   else if (TIMx == TIM16)
  296.   {
  297.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
  298.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
  299.   }
  300. #endif
  301. #if defined(TIM17)
  302.   else if (TIMx == TIM17)
  303.   {
  304.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
  305.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
  306.   }
  307. #endif
  308.   else
  309.   {
  310.     result = ERROR;
  311.   }
  312.  
  313.   return result;
  314. }
  315.  
  316. /**
  317.   * @brief  Set the fields of the time base unit configuration data structure
  318.   *         to their default values.
  319.   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
  320.   * @retval None
  321.   */
  322. void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
  323. {
  324.   /* Set the default configuration */
  325.   TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
  326.   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
  327.   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
  328.   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
  329.   TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
  330. }
  331.  
  332. /**
  333.   * @brief  Configure the TIMx time base unit.
  334.   * @param  TIMx Timer Instance
  335.   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
  336.   * @retval An ErrorStatus enumeration value:
  337.   *          - SUCCESS: TIMx registers are de-initialized
  338.   *          - ERROR: not applicable
  339.   */
  340. ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
  341. {
  342.   uint32_t tmpcr1 = 0U;
  343.  
  344.   /* Check the parameters */
  345.   assert_param(IS_TIM_INSTANCE(TIMx));
  346.   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
  347.   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
  348.  
  349.   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
  350.  
  351.   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  352.   {
  353.     /* Select the Counter Mode */
  354.     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
  355.   }
  356.  
  357.   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  358.   {
  359.     /* Set the clock division */
  360.     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
  361.   }
  362.  
  363.   /* Write to TIMx CR1 */
  364.   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
  365.  
  366.   /* Set the Autoreload value */
  367.   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
  368.  
  369.   /* Set the Prescaler value */
  370.   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
  371.  
  372.   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  373.   {
  374.     /* Set the Repetition Counter value */
  375.     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
  376.   }
  377.  
  378.   /* Generate an update event to reload the Prescaler
  379.      and the repetition counter value (if applicable) immediately */
  380.   LL_TIM_GenerateEvent_UPDATE(TIMx);
  381.  
  382.   return SUCCESS;
  383. }
  384.  
  385. /**
  386.   * @brief  Set the fields of the TIMx output channel configuration data
  387.   *         structure to their default values.
  388.   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
  389.   * @retval None
  390.   */
  391. void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
  392. {
  393.   /* Set the default configuration */
  394.   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
  395.   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
  396.   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
  397.   TIM_OC_InitStruct->CompareValue = 0x00000000U;
  398.   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
  399.   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
  400.   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
  401.   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
  402. }
  403.  
  404. /**
  405.   * @brief  Configure the TIMx output channel.
  406.   * @param  TIMx Timer Instance
  407.   * @param  Channel This parameter can be one of the following values:
  408.   *         @arg @ref LL_TIM_CHANNEL_CH1
  409.   *         @arg @ref LL_TIM_CHANNEL_CH2
  410.   *         @arg @ref LL_TIM_CHANNEL_CH3
  411.   *         @arg @ref LL_TIM_CHANNEL_CH4
  412.   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
  413.   * @retval An ErrorStatus enumeration value:
  414.   *          - SUCCESS: TIMx output channel is initialized
  415.   *          - ERROR: TIMx output channel is not initialized
  416.   */
  417. ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
  418. {
  419.   ErrorStatus result = ERROR;
  420.  
  421.   switch (Channel)
  422.   {
  423.     case LL_TIM_CHANNEL_CH1:
  424.       result = OC1Config(TIMx, TIM_OC_InitStruct);
  425.       break;
  426.     case LL_TIM_CHANNEL_CH2:
  427.       result = OC2Config(TIMx, TIM_OC_InitStruct);
  428.       break;
  429.     case LL_TIM_CHANNEL_CH3:
  430.       result = OC3Config(TIMx, TIM_OC_InitStruct);
  431.       break;
  432.     case LL_TIM_CHANNEL_CH4:
  433.       result = OC4Config(TIMx, TIM_OC_InitStruct);
  434.       break;
  435.     default:
  436.       break;
  437.   }
  438.  
  439.   return result;
  440. }
  441.  
  442. /**
  443.   * @brief  Set the fields of the TIMx input channel configuration data
  444.   *         structure to their default values.
  445.   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
  446.   * @retval None
  447.   */
  448. void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  449. {
  450.   /* Set the default configuration */
  451.   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
  452.   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  453.   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
  454.   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
  455. }
  456.  
  457. /**
  458.   * @brief  Configure the TIMx input channel.
  459.   * @param  TIMx Timer Instance
  460.   * @param  Channel This parameter can be one of the following values:
  461.   *         @arg @ref LL_TIM_CHANNEL_CH1
  462.   *         @arg @ref LL_TIM_CHANNEL_CH2
  463.   *         @arg @ref LL_TIM_CHANNEL_CH3
  464.   *         @arg @ref LL_TIM_CHANNEL_CH4
  465.   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
  466.   * @retval An ErrorStatus enumeration value:
  467.   *          - SUCCESS: TIMx output channel is initialized
  468.   *          - ERROR: TIMx output channel is not initialized
  469.   */
  470. ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
  471. {
  472.   ErrorStatus result = ERROR;
  473.  
  474.   switch (Channel)
  475.   {
  476.     case LL_TIM_CHANNEL_CH1:
  477.       result = IC1Config(TIMx, TIM_IC_InitStruct);
  478.       break;
  479.     case LL_TIM_CHANNEL_CH2:
  480.       result = IC2Config(TIMx, TIM_IC_InitStruct);
  481.       break;
  482.     case LL_TIM_CHANNEL_CH3:
  483.       result = IC3Config(TIMx, TIM_IC_InitStruct);
  484.       break;
  485.     case LL_TIM_CHANNEL_CH4:
  486.       result = IC4Config(TIMx, TIM_IC_InitStruct);
  487.       break;
  488.     default:
  489.       break;
  490.   }
  491.  
  492.   return result;
  493. }
  494.  
  495. /**
  496.   * @brief  Fills each TIM_EncoderInitStruct field with its default value
  497.   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
  498.   * @retval None
  499.   */
  500. void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
  501. {
  502.   /* Set the default configuration */
  503.   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
  504.   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
  505.   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  506.   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
  507.   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
  508.   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
  509.   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  510.   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
  511.   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
  512. }
  513.  
  514. /**
  515.   * @brief  Configure the encoder interface of the timer instance.
  516.   * @param  TIMx Timer Instance
  517.   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
  518.   * @retval An ErrorStatus enumeration value:
  519.   *          - SUCCESS: TIMx registers are de-initialized
  520.   *          - ERROR: not applicable
  521.   */
  522. ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
  523. {
  524.   uint32_t tmpccmr1 = 0U;
  525.   uint32_t tmpccer = 0U;
  526.  
  527.   /* Check the parameters */
  528.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
  529.   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
  530.   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
  531.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
  532.   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
  533.   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
  534.   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
  535.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
  536.   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
  537.   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
  538.  
  539.   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
  540.   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
  541.  
  542.   /* Get the TIMx CCMR1 register value */
  543.   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  544.  
  545.   /* Get the TIMx CCER register value */
  546.   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  547.  
  548.   /* Configure TI1 */
  549.   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
  550.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
  551.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
  552.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
  553.  
  554.   /* Configure TI2 */
  555.   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
  556.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
  557.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
  558.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
  559.  
  560.   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
  561.   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
  562.   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
  563.   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
  564.   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
  565.  
  566.   /* Set encoder mode */
  567.   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
  568.  
  569.   /* Write to TIMx CCMR1 */
  570.   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  571.  
  572.   /* Write to TIMx CCER */
  573.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  574.  
  575.   return SUCCESS;
  576. }
  577.  
  578. /**
  579.   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
  580.   *         structure to their default values.
  581.   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
  582.   * @retval None
  583.   */
  584. void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
  585. {
  586.   /* Set the default configuration */
  587.   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
  588.   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
  589.   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
  590.   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
  591. }
  592.  
  593. /**
  594.   * @brief  Configure the Hall sensor interface of the timer instance.
  595.   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
  596.   *       to the TI1 input channel
  597.   * @note TIMx slave mode controller is configured in reset mode.
  598.           Selected internal trigger is TI1F_ED.
  599.   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
  600.   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
  601.   *       between 2 changes on the inputs. It gives information about motor speed.
  602.   * @note Channel 2 is configured in output PWM 2 mode.
  603.   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
  604.   * @note OC2REF is selected as trigger output on TRGO.
  605.   * @param  TIMx Timer Instance
  606.   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
  607.   * @retval An ErrorStatus enumeration value:
  608.   *          - SUCCESS: TIMx registers are de-initialized
  609.   *          - ERROR: not applicable
  610.   */
  611. ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
  612. {
  613.   uint32_t tmpcr2 = 0U;
  614.   uint32_t tmpccmr1 = 0U;
  615.   uint32_t tmpccer = 0U;
  616.   uint32_t tmpsmcr = 0U;
  617.  
  618.   /* Check the parameters */
  619.   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
  620.   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
  621.   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
  622.   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
  623.  
  624.   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
  625.   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
  626.  
  627.   /* Get the TIMx CR2 register value */
  628.   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  629.  
  630.   /* Get the TIMx CCMR1 register value */
  631.   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  632.  
  633.   /* Get the TIMx CCER register value */
  634.   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  635.  
  636.   /* Get the TIMx SMCR register value */
  637.   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
  638.  
  639.   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
  640.   tmpcr2 |= TIM_CR2_TI1S;
  641.  
  642.   /* OC2REF signal is used as trigger output (TRGO) */
  643.   tmpcr2 |= LL_TIM_TRGO_OC2REF;
  644.  
  645.   /* Configure the slave mode controller */
  646.   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
  647.   tmpsmcr |= LL_TIM_TS_TI1F_ED;
  648.   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
  649.  
  650.   /* Configure input channel 1 */
  651.   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
  652.   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
  653.   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
  654.   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
  655.  
  656.   /* Configure input channel 2 */
  657.   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
  658.   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
  659.  
  660.   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
  661.   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
  662.   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
  663.   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
  664.  
  665.   /* Write to TIMx CR2 */
  666.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  667.  
  668.   /* Write to TIMx SMCR */
  669.   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
  670.  
  671.   /* Write to TIMx CCMR1 */
  672.   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  673.  
  674.   /* Write to TIMx CCER */
  675.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  676.  
  677.   /* Write to TIMx CCR2 */
  678.   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
  679.  
  680.   return SUCCESS;
  681. }
  682.  
  683. /**
  684.   * @brief  Set the fields of the Break and Dead Time configuration data structure
  685.   *         to their default values.
  686.   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
  687.   * @retval None
  688.   */
  689. void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
  690. {
  691.   /* Set the default configuration */
  692.   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
  693.   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
  694.   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
  695.   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
  696.   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
  697.   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
  698.   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
  699. }
  700.  
  701. /**
  702.   * @brief  Configure the Break and Dead Time feature of the timer instance.
  703.   * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
  704.   *  depending on the LOCK configuration, it can be necessary to configure all of
  705.   *  them during the first write access to the TIMx_BDTR register.
  706.   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  707.   *       a timer instance provides a break input.
  708.   * @param  TIMx Timer Instance
  709.   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
  710.   * @retval An ErrorStatus enumeration value:
  711.   *          - SUCCESS: Break and Dead Time is initialized
  712.   *          - ERROR: not applicable
  713.   */
  714. ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
  715. {
  716.   uint32_t tmpbdtr = 0;
  717.  
  718.   /* Check the parameters */
  719.   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
  720.   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
  721.   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
  722.   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
  723.   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
  724.   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
  725.   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
  726.  
  727.   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
  728.   the OSSI State, the dead time value and the Automatic Output Enable Bit */
  729.  
  730.   /* Set the BDTR bits */
  731.   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
  732.   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
  733.   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
  734.   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
  735.   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
  736.   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
  737.   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
  738.   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
  739.  
  740.   /* Set TIMx_BDTR */
  741.   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
  742.  
  743.   return SUCCESS;
  744. }
  745. /**
  746.   * @}
  747.   */
  748.  
  749. /**
  750.   * @}
  751.   */
  752.  
  753. /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
  754.  *  @brief   Private functions
  755.   * @{
  756.   */
  757. /**
  758.   * @brief  Configure the TIMx output channel 1.
  759.   * @param  TIMx Timer Instance
  760.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
  761.   * @retval An ErrorStatus enumeration value:
  762.   *          - SUCCESS: TIMx registers are de-initialized
  763.   *          - ERROR: not applicable
  764.   */
  765. static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  766. {
  767.   uint32_t tmpccmr1 = 0U;
  768.   uint32_t tmpccer = 0U;
  769.   uint32_t tmpcr2 = 0U;
  770.  
  771.   /* Check the parameters */
  772.   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  773.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  774.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  775.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  776.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
  777.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
  778.  
  779.   /* Disable the Channel 1: Reset the CC1E Bit */
  780.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
  781.  
  782.   /* Get the TIMx CCER register value */
  783.   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  784.  
  785.   /* Get the TIMx CR2 register value */
  786.   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  787.  
  788.   /* Get the TIMx CCMR1 register value */
  789.   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  790.  
  791.   /* Reset Capture/Compare selection Bits */
  792.   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
  793.  
  794.   /* Set the Output Compare Mode */
  795.   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
  796.  
  797.   /* Set the Output Compare Polarity */
  798.   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
  799.  
  800.   /* Set the Output State */
  801.   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
  802.  
  803.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  804.   {
  805.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
  806.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
  807.  
  808.     /* Set the complementary output Polarity */
  809.     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
  810.  
  811.     /* Set the complementary output State */
  812.     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
  813.  
  814.     /* Set the Output Idle state */
  815.     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
  816.  
  817.     /* Set the complementary output Idle state */
  818.     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
  819.   }
  820.  
  821.   /* Write to TIMx CR2 */
  822.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  823.  
  824.   /* Write to TIMx CCMR1 */
  825.   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  826.  
  827.   /* Set the Capture Compare Register value */
  828.   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
  829.  
  830.   /* Write to TIMx CCER */
  831.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  832.  
  833.   return SUCCESS;
  834. }
  835.  
  836. /**
  837.   * @brief  Configure the TIMx output channel 2.
  838.   * @param  TIMx Timer Instance
  839.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
  840.   * @retval An ErrorStatus enumeration value:
  841.   *          - SUCCESS: TIMx registers are de-initialized
  842.   *          - ERROR: not applicable
  843.   */
  844. static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  845. {
  846.   uint32_t tmpccmr1 = 0U;
  847.   uint32_t tmpccer = 0U;
  848.   uint32_t tmpcr2 = 0U;
  849.  
  850.   /* Check the parameters */
  851.   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
  852.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  853.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  854.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  855.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
  856.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
  857.  
  858.   /* Disable the Channel 2: Reset the CC2E Bit */
  859.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
  860.  
  861.   /* Get the TIMx CCER register value */
  862.   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
  863.  
  864.   /* Get the TIMx CR2 register value */
  865.   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  866.  
  867.   /* Get the TIMx CCMR1 register value */
  868.   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  869.  
  870.   /* Reset Capture/Compare selection Bits */
  871.   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
  872.  
  873.   /* Select the Output Compare Mode */
  874.   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
  875.  
  876.   /* Set the Output Compare Polarity */
  877.   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
  878.  
  879.   /* Set the Output State */
  880.   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
  881.  
  882.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  883.   {
  884.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
  885.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
  886.  
  887.     /* Set the complementary output Polarity */
  888.     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
  889.  
  890.     /* Set the complementary output State */
  891.     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
  892.  
  893.     /* Set the Output Idle state */
  894.     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
  895.  
  896.     /* Set the complementary output Idle state */
  897.     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
  898.   }
  899.  
  900.   /* Write to TIMx CR2 */
  901.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  902.  
  903.   /* Write to TIMx CCMR1 */
  904.   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  905.  
  906.   /* Set the Capture Compare Register value */
  907.   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
  908.  
  909.   /* Write to TIMx CCER */
  910.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  911.  
  912.   return SUCCESS;
  913. }
  914.  
  915. /**
  916.   * @brief  Configure the TIMx output channel 3.
  917.   * @param  TIMx Timer Instance
  918.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
  919.   * @retval An ErrorStatus enumeration value:
  920.   *          - SUCCESS: TIMx registers are de-initialized
  921.   *          - ERROR: not applicable
  922.   */
  923. static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  924. {
  925.   uint32_t tmpccmr2 = 0U;
  926.   uint32_t tmpccer = 0U;
  927.   uint32_t tmpcr2 = 0U;
  928.  
  929.   /* Check the parameters */
  930.   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
  931.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  932.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  933.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  934.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
  935.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
  936.  
  937.   /* Disable the Channel 3: Reset the CC3E Bit */
  938.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
  939.  
  940.   /* Get the TIMx CCER register value */
  941.   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
  942.  
  943.   /* Get the TIMx CR2 register value */
  944.   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  945.  
  946.   /* Get the TIMx CCMR2 register value */
  947.   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
  948.  
  949.   /* Reset Capture/Compare selection Bits */
  950.   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
  951.  
  952.   /* Select the Output Compare Mode */
  953.   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
  954.  
  955.   /* Set the Output Compare Polarity */
  956.   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
  957.  
  958.   /* Set the Output State */
  959.   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
  960.  
  961.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  962.   {
  963.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
  964.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
  965.  
  966.     /* Set the complementary output Polarity */
  967.     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
  968.  
  969.     /* Set the complementary output State */
  970.     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
  971.  
  972.     /* Set the Output Idle state */
  973.     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
  974.  
  975.     /* Set the complementary output Idle state */
  976.     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
  977.   }
  978.  
  979.   /* Write to TIMx CR2 */
  980.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  981.  
  982.   /* Write to TIMx CCMR2 */
  983.   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
  984.  
  985.   /* Set the Capture Compare Register value */
  986.   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
  987.  
  988.   /* Write to TIMx CCER */
  989.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  990.  
  991.   return SUCCESS;
  992. }
  993.  
  994. /**
  995.   * @brief  Configure the TIMx output channel 4.
  996.   * @param  TIMx Timer Instance
  997.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
  998.   * @retval An ErrorStatus enumeration value:
  999.   *          - SUCCESS: TIMx registers are de-initialized
  1000.   *          - ERROR: not applicable
  1001.   */
  1002. static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  1003. {
  1004.   uint32_t tmpccmr2 = 0U;
  1005.   uint32_t tmpccer = 0U;
  1006.   uint32_t tmpcr2 = 0U;
  1007.  
  1008.   /* Check the parameters */
  1009.   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
  1010.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  1011.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  1012.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  1013.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
  1014.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
  1015.  
  1016.   /* Disable the Channel 4: Reset the CC4E Bit */
  1017.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
  1018.  
  1019.   /* Get the TIMx CCER register value */
  1020.   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  1021.  
  1022.   /* Get the TIMx CR2 register value */
  1023.   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
  1024.  
  1025.   /* Get the TIMx CCMR2 register value */
  1026.   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
  1027.  
  1028.   /* Reset Capture/Compare selection Bits */
  1029.   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
  1030.  
  1031.   /* Select the Output Compare Mode */
  1032.   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
  1033.  
  1034.   /* Set the Output Compare Polarity */
  1035.   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
  1036.  
  1037.   /* Set the Output State */
  1038.   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
  1039.  
  1040.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  1041.   {
  1042.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
  1043.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
  1044.  
  1045.     /* Set the Output Idle state */
  1046.     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
  1047.   }
  1048.  
  1049.   /* Write to TIMx CR2 */
  1050.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  1051.  
  1052.   /* Write to TIMx CCMR2 */
  1053.   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
  1054.  
  1055.   /* Set the Capture Compare Register value */
  1056.   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
  1057.  
  1058.   /* Write to TIMx CCER */
  1059.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  1060.  
  1061.   return SUCCESS;
  1062. }
  1063.  
  1064.  
  1065. /**
  1066.   * @brief  Configure the TIMx input channel 1.
  1067.   * @param  TIMx Timer Instance
  1068.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
  1069.   * @retval An ErrorStatus enumeration value:
  1070.   *          - SUCCESS: TIMx registers are de-initialized
  1071.   *          - ERROR: not applicable
  1072.   */
  1073. static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  1074. {
  1075.   /* Check the parameters */
  1076.   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  1077.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  1078.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  1079.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  1080.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  1081.  
  1082.   /* Disable the Channel 1: Reset the CC1E Bit */
  1083.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
  1084.  
  1085.   /* Select the Input and set the filter and the prescaler value */
  1086.   MODIFY_REG(TIMx->CCMR1,
  1087.              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
  1088.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
  1089.  
  1090.   /* Select the Polarity and set the CC1E Bit */
  1091.   MODIFY_REG(TIMx->CCER,
  1092.              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
  1093.              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
  1094.  
  1095.   return SUCCESS;
  1096. }
  1097.  
  1098. /**
  1099.   * @brief  Configure the TIMx input channel 2.
  1100.   * @param  TIMx Timer Instance
  1101.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
  1102.   * @retval An ErrorStatus enumeration value:
  1103.   *          - SUCCESS: TIMx registers are de-initialized
  1104.   *          - ERROR: not applicable
  1105.   */
  1106. static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  1107. {
  1108.   /* Check the parameters */
  1109.   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
  1110.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  1111.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  1112.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  1113.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  1114.  
  1115.   /* Disable the Channel 2: Reset the CC2E Bit */
  1116.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
  1117.  
  1118.   /* Select the Input and set the filter and the prescaler value */
  1119.   MODIFY_REG(TIMx->CCMR1,
  1120.              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
  1121.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
  1122.  
  1123.   /* Select the Polarity and set the CC2E Bit */
  1124.   MODIFY_REG(TIMx->CCER,
  1125.              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
  1126.              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
  1127.  
  1128.   return SUCCESS;
  1129. }
  1130.  
  1131. /**
  1132.   * @brief  Configure the TIMx input channel 3.
  1133.   * @param  TIMx Timer Instance
  1134.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
  1135.   * @retval An ErrorStatus enumeration value:
  1136.   *          - SUCCESS: TIMx registers are de-initialized
  1137.   *          - ERROR: not applicable
  1138.   */
  1139. static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  1140. {
  1141.   /* Check the parameters */
  1142.   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
  1143.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  1144.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  1145.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  1146.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  1147.  
  1148.   /* Disable the Channel 3: Reset the CC3E Bit */
  1149.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
  1150.  
  1151.   /* Select the Input and set the filter and the prescaler value */
  1152.   MODIFY_REG(TIMx->CCMR2,
  1153.              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
  1154.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
  1155.  
  1156.   /* Select the Polarity and set the CC3E Bit */
  1157.   MODIFY_REG(TIMx->CCER,
  1158.              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
  1159.              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
  1160.  
  1161.   return SUCCESS;
  1162. }
  1163.  
  1164. /**
  1165.   * @brief  Configure the TIMx input channel 4.
  1166.   * @param  TIMx Timer Instance
  1167.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
  1168.   * @retval An ErrorStatus enumeration value:
  1169.   *          - SUCCESS: TIMx registers are de-initialized
  1170.   *          - ERROR: not applicable
  1171.   */
  1172. static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  1173. {
  1174.   /* Check the parameters */
  1175.   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
  1176.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  1177.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  1178.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  1179.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  1180.  
  1181.   /* Disable the Channel 4: Reset the CC4E Bit */
  1182.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
  1183.  
  1184.   /* Select the Input and set the filter and the prescaler value */
  1185.   MODIFY_REG(TIMx->CCMR2,
  1186.              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
  1187.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
  1188.  
  1189.   /* Select the Polarity and set the CC4E Bit */
  1190.   MODIFY_REG(TIMx->CCER,
  1191.              TIM_CCER_CC4P,
  1192.              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
  1193.  
  1194.   return SUCCESS;
  1195. }
  1196.  
  1197.  
  1198. /**
  1199.   * @}
  1200.   */
  1201.  
  1202. /**
  1203.   * @}
  1204.   */
  1205.  
  1206. #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14  || TIM15 || TIM16 || TIM17 */
  1207.  
  1208. /**
  1209.   * @}
  1210.   */
  1211.  
  1212. #endif /* USE_FULL_LL_DRIVER */
  1213.  
  1214. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1215.