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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_fsmc.c
  4.   * @author  MCD Application Team
  5.   * @brief   FSMC Low Layer HAL module driver.
  6.   *
  7.   *          This file provides firmware functions to manage the following
  8.   *          functionalities of the Flexible Memory Controller (FSMC) peripheral memories:
  9.   *           + Initialization/de-initialization functions
  10.   *           + Peripheral Control functions
  11.   *           + Peripheral State functions
  12.   *
  13.   @verbatim
  14.   ==============================================================================
  15.                         ##### FSMC peripheral features #####
  16.   ==============================================================================
  17.   [..] The Flexible memory controller (FSMC) includes following memory controllers:
  18.        (+) The NOR/PSRAM memory controller
  19.        (+) The NAND/PC Card memory controller
  20.  
  21.   [..] The FSMC functional block makes the interface with synchronous and asynchronous static
  22.        memories and 16-bit PC memory cards. Its main purposes are:
  23.        (+) to translate AHB transactions into the appropriate external device protocol
  24.        (+) to meet the access time requirements of the external memory devices
  25.  
  26.   [..] All external memories share the addresses, data and control signals with the controller.
  27.        Each external device is accessed by means of a unique Chip Select. The FSMC performs
  28.        only one access at a time to an external device.
  29.        The main features of the FSMC controller are the following:
  30.         (+) Interface with static-memory mapped devices including:
  31.            (++) Static random access memory (SRAM)
  32.            (++) Read-only memory (ROM)
  33.            (++) NOR Flash memory/OneNAND Flash memory
  34.            (++) PSRAM (4 memory banks)
  35.            (++) 16-bit PC Card compatible devices
  36.            (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  37.                 data
  38.         (+) Independent Chip Select control for each memory bank
  39.         (+) Independent configuration for each memory bank
  40.  
  41.   @endverbatim
  42.   ******************************************************************************
  43.   * @attention
  44.   *
  45.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  46.   * All rights reserved.</center></h2>
  47.   *
  48.   * This software component is licensed by ST under BSD 3-Clause license,
  49.   * the "License"; You may not use this file except in compliance with the
  50.   * License. You may obtain a copy of the License at:
  51.   *                       opensource.org/licenses/BSD-3-Clause
  52.   *
  53.   ******************************************************************************
  54.   */
  55.  
  56. /* Includes ------------------------------------------------------------------*/
  57. #include "stm32f1xx_hal.h"
  58.  
  59. /** @addtogroup STM32F1xx_HAL_Driver
  60.   * @{
  61.   */
  62. #if (((defined HAL_NOR_MODULE_ENABLED || defined HAL_SRAM_MODULE_ENABLED)) || defined HAL_NAND_MODULE_ENABLED || defined HAL_PCCARD_MODULE_ENABLED )
  63.  
  64. /** @defgroup FSMC_LL  FSMC Low Layer
  65.   * @brief FSMC driver modules
  66.   * @{
  67.   */
  68.        
  69. /* Private typedef -----------------------------------------------------------*/
  70. /* Private define ------------------------------------------------------------*/
  71.  
  72. /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
  73.   * @{
  74.   */
  75.  
  76. /* ----------------------- FSMC registers bit mask --------------------------- */
  77.  
  78. #if defined FSMC_BANK1
  79. /* --- BCR Register ---*/
  80. /* BCR register clear mask */
  81.  
  82. /* --- BTR Register ---*/
  83. /* BTR register clear mask */
  84. #define BTR_CLEAR_MASK    ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD  |\
  85.                                       FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
  86.                                       FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT  |\
  87.                                       FSMC_BTRx_ACCMOD))
  88.  
  89. /* --- BWTR Register ---*/
  90. /* BWTR register clear mask */
  91. #if defined(FSMC_BWTRx_BUSTURN)
  92. #define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD  |\
  93.                                       FSMC_BWTRx_DATAST | FSMC_BWTRx_BUSTURN |\
  94.                                       FSMC_BWTRx_ACCMOD))
  95. #else
  96. #define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD  |\
  97.                                       FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD))
  98. #endif /* FSMC_BWTRx_BUSTURN */
  99. #endif /* FSMC_BANK1 */
  100. #if defined(FSMC_BANK3)
  101.  
  102. /* --- PCR Register ---*/
  103. /* PCR register clear mask */
  104. #define PCR_CLEAR_MASK    ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN  | \
  105.                                       FSMC_PCRx_PTYP    | FSMC_PCRx_PWID   | \
  106.                                       FSMC_PCRx_ECCEN   | FSMC_PCRx_TCLR   | \
  107.                                       FSMC_PCRx_TAR     | FSMC_PCRx_ECCPS))
  108. /* --- PMEM Register ---*/
  109. /* PMEM register clear mask */
  110. #define PMEM_CLEAR_MASK   ((uint32_t)(FSMC_PMEMx_MEMSETx  | FSMC_PMEMx_MEMWAITx |\
  111.                                       FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx))
  112.  
  113. /* --- PATT Register ---*/
  114. /* PATT register clear mask */
  115. #define PATT_CLEAR_MASK   ((uint32_t)(FSMC_PATTx_ATTSETx  | FSMC_PATTx_ATTWAITx |\
  116.                                       FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx))
  117.  
  118. #endif /* FSMC_BANK3 */
  119. #if defined(FSMC_BANK4)
  120. /* --- PCR Register ---*/
  121. /* PCR register clear mask */
  122. #define PCR4_CLEAR_MASK   ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN  | \
  123.                                       FSMC_PCR4_PTYP    | FSMC_PCR4_PWID   | \
  124.                                       FSMC_PCR4_ECCEN   | FSMC_PCR4_TCLR   | \
  125.                                       FSMC_PCR4_TAR     | FSMC_PCR4_ECCPS))
  126. /* --- PMEM Register ---*/
  127. /* PMEM register clear mask */
  128. #define PMEM4_CLEAR_MASK  ((uint32_t)(FSMC_PMEM4_MEMSET4  | FSMC_PMEM4_MEMWAIT4 |\
  129.                                       FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4))
  130.  
  131. /* --- PATT Register ---*/
  132. /* PATT register clear mask */
  133. #define PATT4_CLEAR_MASK  ((uint32_t)(FSMC_PATT4_ATTSET4  | FSMC_PATT4_ATTWAIT4 |\
  134.                                       FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4))
  135.  
  136. /* --- PIO4 Register ---*/
  137. /* PIO4 register clear mask */
  138. #define PIO4_CLEAR_MASK   ((uint32_t)(FSMC_PIO4_IOSET4  | FSMC_PIO4_IOWAIT4 | \
  139.                                       FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
  140.  
  141. #endif /* FSMC_BANK4 */
  142.  
  143. /**
  144.   * @}
  145.   */
  146.  
  147. /* Private macro -------------------------------------------------------------*/
  148. /* Private variables ---------------------------------------------------------*/
  149. /* Private function prototypes -----------------------------------------------*/
  150. /* Exported functions --------------------------------------------------------*/
  151.  
  152. /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
  153.   * @{
  154.   */
  155.  
  156. #if defined FSMC_BANK1
  157.  
  158. /** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions
  159.   * @brief  NORSRAM Controller functions
  160.   *
  161.   @verbatim
  162.   ==============================================================================
  163.                    ##### How to use NORSRAM device driver #####
  164.   ==============================================================================
  165.  
  166.   [..]
  167.     This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
  168.     to run the NORSRAM external devices.
  169.  
  170.     (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
  171.     (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
  172.     (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
  173.     (+) FSMC NORSRAM bank extended timing configuration using the function
  174.         FSMC_NORSRAM_Extended_Timing_Init()
  175.     (+) FSMC NORSRAM bank enable/disable write operation using the functions
  176.         FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
  177.  
  178. @endverbatim
  179.   * @{
  180.   */
  181.  
  182. /** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
  183.   * @brief    Initialization and Configuration functions
  184.   *
  185.   @verbatim
  186.   ==============================================================================
  187.               ##### Initialization and de_initialization functions #####
  188.   ==============================================================================
  189.   [..]
  190.     This section provides functions allowing to:
  191.     (+) Initialize and configure the FSMC NORSRAM interface
  192.     (+) De-initialize the FSMC NORSRAM interface
  193.     (+) Configure the FSMC clock and associated GPIOs
  194.  
  195. @endverbatim
  196.   * @{
  197.   */
  198.  
  199. /**
  200.   * @brief  Initialize the FSMC_NORSRAM device according to the specified
  201.   *         control parameters in the FSMC_NORSRAM_InitTypeDef
  202.   * @param  Device Pointer to NORSRAM device instance
  203.   * @param  Init Pointer to NORSRAM Initialization structure
  204.   * @retval HAL status
  205.   */
  206. HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init)
  207. {
  208.   uint32_t flashaccess;
  209.  
  210.   /* Check the parameters */
  211.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  212.   assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
  213.   assert_param(IS_FSMC_MUX(Init->DataAddressMux));
  214.   assert_param(IS_FSMC_MEMORY(Init->MemoryType));
  215.   assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
  216.   assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
  217.   assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
  218.   assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
  219.   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
  220.   assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
  221.   assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
  222.   assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
  223.   assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
  224.   assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
  225.   assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
  226.  
  227.   /* Disable NORSRAM Device */
  228.   __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
  229.  
  230.   /* Set NORSRAM device control parameters */
  231.   if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
  232.   {
  233.     flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
  234.   }
  235.   else
  236.   {
  237.     flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
  238.   }
  239.  
  240.   MODIFY_REG(Device->BTCR[Init->NSBank],
  241.              (FSMC_BCRx_MBKEN                |
  242.               FSMC_BCRx_MUXEN                |
  243.               FSMC_BCRx_MTYP                 |
  244.               FSMC_BCRx_MWID                 |
  245.               FSMC_BCRx_FACCEN               |
  246.               FSMC_BCRx_BURSTEN              |
  247.               FSMC_BCRx_WAITPOL              |
  248.               FSMC_BCRx_WRAPMOD              |
  249.               FSMC_BCRx_WAITCFG              |
  250.               FSMC_BCRx_WREN                 |
  251.               FSMC_BCRx_WAITEN               |
  252.               FSMC_BCRx_EXTMOD               |
  253.               FSMC_BCRx_ASYNCWAIT            |
  254.               FSMC_BCRx_CBURSTRW             |
  255.               0x00070000U), /* CPSIZE to be defined in CMSIS file */
  256.              (flashaccess                   |
  257.               Init->DataAddressMux          |
  258.               Init->MemoryType              |
  259.               Init->MemoryDataWidth         |
  260.               Init->BurstAccessMode         |
  261.               Init->WaitSignalPolarity      |
  262.               Init->WrapMode                |
  263.               Init->WaitSignalActive        |
  264.               Init->WriteOperation          |
  265.               Init->WaitSignal              |
  266.               Init->ExtendedMode            |
  267.               Init->AsynchronousWait        |
  268.               Init->WriteBurst              |
  269.               Init->PageSize));
  270.  
  271.  
  272.   return HAL_OK;
  273. }
  274.  
  275. /**
  276.   * @brief  DeInitialize the FSMC_NORSRAM peripheral
  277.   * @param  Device Pointer to NORSRAM device instance
  278.   * @param  ExDevice Pointer to NORSRAM extended mode device instance
  279.   * @param  Bank NORSRAM bank number
  280.   * @retval HAL status
  281.   */
  282. HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
  283. {
  284.   /* Check the parameters */
  285.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  286.   assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
  287.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  288.  
  289.   /* Disable the FSMC_NORSRAM device */
  290.   __FSMC_NORSRAM_DISABLE(Device, Bank);
  291.  
  292.   /* De-initialize the FSMC_NORSRAM device */
  293.   /* FSMC_NORSRAM_BANK1 */
  294.   if (Bank == FSMC_NORSRAM_BANK1)
  295.   {
  296.     Device->BTCR[Bank] = 0x000030DBU;
  297.   }
  298.   /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
  299.   else
  300.   {
  301.     Device->BTCR[Bank] = 0x000030D2U;
  302.   }
  303.  
  304.   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
  305.   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;
  306.  
  307.   return HAL_OK;
  308. }
  309.  
  310. /**
  311.   * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
  312.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  313.   * @param  Device Pointer to NORSRAM device instance
  314.   * @param  Timing Pointer to NORSRAM Timing structure
  315.   * @param  Bank NORSRAM bank number
  316.   * @retval HAL status
  317.   */
  318. HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
  319. {
  320.  
  321.   /* Check the parameters */
  322.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  323.   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  324.   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  325.   assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  326.   assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  327.   assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  328.   assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  329.   assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  330.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  331.  
  332.   /* Set FSMC_NORSRAM device timing parameters */
  333.   MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                                  |
  334.                                                       ((Timing->AddressHoldTime)        << FSMC_BTRx_ADDHLD_Pos)  |
  335.                                                       ((Timing->DataSetupTime)          << FSMC_BTRx_DATAST_Pos)  |
  336.                                                       ((Timing->BusTurnAroundDuration)  << FSMC_BTRx_BUSTURN_Pos) |
  337.                                                       (((Timing->CLKDivision) - 1U)     << FSMC_BTRx_CLKDIV_Pos)  |
  338.                                                       (((Timing->DataLatency) - 2U)     << FSMC_BTRx_DATLAT_Pos)  |
  339.                                                       (Timing->AccessMode)));
  340.  
  341.   return HAL_OK;
  342. }
  343.  
  344. /**
  345.   * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
  346.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  347.   * @param  Device Pointer to NORSRAM device instance
  348.   * @param  Timing Pointer to NORSRAM Timing structure
  349.   * @param  Bank NORSRAM bank number
  350.   * @param  ExtendedMode FSMC Extended Mode
  351.   *          This parameter can be one of the following values:
  352.   *            @arg FSMC_EXTENDED_MODE_DISABLE
  353.   *            @arg FSMC_EXTENDED_MODE_ENABLE
  354.   * @retval HAL status
  355.   */
  356. HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
  357. {
  358.   /* Check the parameters */
  359.   assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
  360.  
  361.   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  362.   if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
  363.   {
  364.     /* Check the parameters */
  365.     assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
  366.     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  367.     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  368.     assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  369. #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  370.     assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  371. #else
  372.     assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  373.     assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  374. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  375.     assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  376.     assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  377.  
  378.     /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  379. #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  380.     MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
  381.                                                      ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos)  |
  382.                                                      ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos)  |
  383.                                                      Timing->AccessMode                                          |
  384.                                                      ((Timing->BusTurnAroundDuration)  << FSMC_BWTRx_BUSTURN_Pos)));
  385. #else
  386.     MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
  387.                                                      ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos)  |
  388.                                                      ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos)  |
  389.                                                      Timing->AccessMode                                          |
  390.                                                      (((Timing->CLKDivision) - 1U)     << FSMC_BTRx_CLKDIV_Pos)   |
  391.                                                      (((Timing->DataLatency) - 2U)     << FSMC_BWTRx_DATLAT_Pos)));
  392. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  393.   }
  394.   else
  395.   {
  396.     Device->BWTR[Bank] = 0x0FFFFFFFU;
  397.   }
  398.  
  399.   return HAL_OK;
  400. }
  401. /**
  402.   * @}
  403.   */
  404.  
  405. /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
  406.  *  @brief   management functions
  407.  *
  408. @verbatim
  409.   ==============================================================================
  410.                       ##### FSMC_NORSRAM Control functions #####
  411.   ==============================================================================
  412.   [..]
  413.     This subsection provides a set of functions allowing to control dynamically
  414.     the FSMC NORSRAM interface.
  415.  
  416. @endverbatim
  417.   * @{
  418.   */
  419.  
  420. /**
  421.   * @brief  Enables dynamically FSMC_NORSRAM write operation.
  422.   * @param  Device Pointer to NORSRAM device instance
  423.   * @param  Bank NORSRAM bank number
  424.   * @retval HAL status
  425.   */
  426. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  427. {
  428.   /* Check the parameters */
  429.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  430.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  431.  
  432.   /* Enable write operation */
  433.   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  434.  
  435.   return HAL_OK;
  436. }
  437.  
  438. /**
  439.   * @brief  Disables dynamically FSMC_NORSRAM write operation.
  440.   * @param  Device Pointer to NORSRAM device instance
  441.   * @param  Bank NORSRAM bank number
  442.   * @retval HAL status
  443.   */
  444. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  445. {
  446.   /* Check the parameters */
  447.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  448.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  449.  
  450.   /* Disable write operation */
  451.   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  452.  
  453.   return HAL_OK;
  454. }
  455.  
  456. /**
  457.   * @}
  458.   */
  459.  
  460. /**
  461.   * @}
  462.   */
  463. #endif /* FSMC_BANK1 */
  464.  
  465. #if defined(FSMC_BANK3)
  466.  
  467. /** @defgroup FSMC_LL_Exported_Functions_NAND FSMC Low Layer NAND Exported Functions
  468.   * @brief    NAND Controller functions
  469.   *
  470.   @verbatim
  471.   ==============================================================================
  472.                     ##### How to use NAND device driver #####
  473.   ==============================================================================
  474.   [..]
  475.     This driver contains a set of APIs to interface with the FSMC NAND banks in order
  476.     to run the NAND external devices.
  477.  
  478.     (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
  479.     (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
  480.     (+) FSMC NAND bank common space timing configuration using the function
  481.         FSMC_NAND_CommonSpace_Timing_Init()
  482.     (+) FSMC NAND bank attribute space timing configuration using the function
  483.         FSMC_NAND_AttributeSpace_Timing_Init()
  484.     (+) FSMC NAND bank enable/disable ECC correction feature using the functions
  485.         FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
  486.     (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
  487.  
  488. @endverbatim
  489.   * @{
  490.   */
  491.  
  492. /** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
  493.  *  @brief    Initialization and Configuration functions
  494.  *
  495. @verbatim
  496.   ==============================================================================
  497.               ##### Initialization and de_initialization functions #####
  498.   ==============================================================================
  499.   [..]
  500.     This section provides functions allowing to:
  501.     (+) Initialize and configure the FSMC NAND interface
  502.     (+) De-initialize the FSMC NAND interface
  503.     (+) Configure the FSMC clock and associated GPIOs
  504.  
  505. @endverbatim
  506.   * @{
  507.   */
  508.  
  509. /**
  510.   * @brief  Initializes the FSMC_NAND device according to the specified
  511.   *         control parameters in the FSMC_NAND_HandleTypeDef
  512.   * @param  Device Pointer to NAND device instance
  513.   * @param  Init Pointer to NAND Initialization structure
  514.   * @retval HAL status
  515.   */
  516. HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
  517. {
  518.   /* Check the parameters */
  519.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  520.   assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
  521.   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
  522.   assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
  523.   assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
  524.   assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
  525.   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
  526.   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
  527.  
  528.   /* Set NAND device control parameters */
  529.   if (Init->NandBank == FSMC_NAND_BANK2)
  530.   {
  531.     /* NAND bank 2 registers configuration */
  532.     MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
  533.                                               FSMC_PCR_MEMORY_TYPE_NAND                               |
  534.                                               Init->MemoryDataWidth                                  |
  535.                                               Init->EccComputation                                   |
  536.                                               Init->ECCPageSize                                      |
  537.                                               ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos)  |
  538.                                               ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
  539.   }
  540.   else
  541.   {
  542.     /* NAND bank 3 registers configuration */
  543.     MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
  544.                                               FSMC_PCR_MEMORY_TYPE_NAND                               |
  545.                                               Init->MemoryDataWidth                                  |
  546.                                               Init->EccComputation                                   |
  547.                                               Init->ECCPageSize                                      |
  548.                                               ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos)  |
  549.                                               ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
  550.   }
  551.  
  552.   return HAL_OK;
  553. }
  554.  
  555. /**
  556.   * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
  557.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  558.   * @param  Device Pointer to NAND device instance
  559.   * @param  Timing Pointer to NAND timing structure
  560.   * @param  Bank NAND bank number
  561.   * @retval HAL status
  562.   */
  563. HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  564. {
  565.   /* Check the parameters */
  566.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  567.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  568.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  569.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  570.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  571.   assert_param(IS_FSMC_NAND_BANK(Bank));
  572.  
  573.   /* Set FSMC_NAND device timing parameters */
  574.   if (Bank == FSMC_NAND_BANK2)
  575.   {
  576.     /* NAND bank 2 registers configuration */
  577.     MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
  578.                                                 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
  579.                                                 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
  580.                                                 ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
  581.   }
  582.   else
  583.   {
  584.     /* NAND bank 3 registers configuration */
  585.     MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
  586.                                                 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
  587.                                                 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
  588.                                                 ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
  589.   }
  590.  
  591.   return HAL_OK;
  592. }
  593.  
  594. /**
  595.   * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
  596.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  597.   * @param  Device Pointer to NAND device instance
  598.   * @param  Timing Pointer to NAND timing structure
  599.   * @param  Bank NAND bank number
  600.   * @retval HAL status
  601.   */
  602. HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  603. {
  604.   /* Check the parameters */
  605.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  606.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  607.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  608.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  609.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  610.   assert_param(IS_FSMC_NAND_BANK(Bank));
  611.  
  612.   /* Set FSMC_NAND device timing parameters */
  613.   if (Bank == FSMC_NAND_BANK2)
  614.   {
  615.     /* NAND bank 2 registers configuration */
  616.     MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
  617.                                                 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
  618.                                                 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
  619.                                                 ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  620.   }
  621.   else
  622.   {
  623.     /* NAND bank 3 registers configuration */
  624.     MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
  625.                                                 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
  626.                                                 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
  627.                                                 ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  628.   }
  629.  
  630.   return HAL_OK;
  631. }
  632.  
  633. /**
  634.   * @brief  DeInitializes the FSMC_NAND device
  635.   * @param  Device Pointer to NAND device instance
  636.   * @param  Bank NAND bank number
  637.   * @retval HAL status
  638.   */
  639. HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  640. {
  641.   /* Check the parameters */
  642.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  643.   assert_param(IS_FSMC_NAND_BANK(Bank));
  644.  
  645.   /* Disable the NAND Bank */
  646.   __FSMC_NAND_DISABLE(Device, Bank);
  647.  
  648.   /* De-initialize the NAND Bank */
  649.   if (Bank == FSMC_NAND_BANK2)
  650.   {
  651.     /* Set the FSMC_NAND_BANK2 registers to their reset values */
  652.     WRITE_REG(Device->PCR2,  0x00000018U);
  653.     WRITE_REG(Device->SR2,   0x00000040U);
  654.     WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
  655.     WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
  656.   }
  657.   /* FSMC_Bank3_NAND */
  658.   else
  659.   {
  660.     /* Set the FSMC_NAND_BANK3 registers to their reset values */
  661.     WRITE_REG(Device->PCR3,  0x00000018U);
  662.     WRITE_REG(Device->SR3,   0x00000040U);
  663.     WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
  664.     WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
  665.   }
  666.  
  667.   return HAL_OK;
  668. }
  669.  
  670. /**
  671.   * @}
  672.   */
  673.  
  674. /** @defgroup HAL_FSMC_NAND_Group2 Peripheral Control functions
  675.   *  @brief   management functions
  676.   *
  677. @verbatim
  678.   ==============================================================================
  679.                        ##### FSMC_NAND Control functions #####
  680.   ==============================================================================
  681.   [..]
  682.     This subsection provides a set of functions allowing to control dynamically
  683.     the FSMC NAND interface.
  684.  
  685. @endverbatim
  686.   * @{
  687.   */
  688.  
  689.  
  690. /**
  691.   * @brief  Enables dynamically FSMC_NAND ECC feature.
  692.   * @param  Device Pointer to NAND device instance
  693.   * @param  Bank NAND bank number
  694.   * @retval HAL status
  695.   */
  696. HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  697. {
  698.   /* Check the parameters */
  699.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  700.   assert_param(IS_FSMC_NAND_BANK(Bank));
  701.  
  702.   /* Enable ECC feature */
  703.   if (Bank == FSMC_NAND_BANK2)
  704.   {
  705.     SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
  706.   }
  707.   else
  708.   {
  709.     SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
  710.   }
  711.  
  712.   return HAL_OK;
  713. }
  714.  
  715.  
  716. /**
  717.   * @brief  Disables dynamically FSMC_NAND ECC feature.
  718.   * @param  Device Pointer to NAND device instance
  719.   * @param  Bank NAND bank number
  720.   * @retval HAL status
  721.   */
  722. HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  723. {
  724.   /* Check the parameters */
  725.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  726.   assert_param(IS_FSMC_NAND_BANK(Bank));
  727.  
  728.   /* Disable ECC feature */
  729.   if (Bank == FSMC_NAND_BANK2)
  730.   {
  731.     CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
  732.   }
  733.   else
  734.   {
  735.     CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
  736.   }
  737.  
  738.   return HAL_OK;
  739. }
  740.  
  741. /**
  742.   * @brief  Disables dynamically FSMC_NAND ECC feature.
  743.   * @param  Device Pointer to NAND device instance
  744.   * @param  ECCval Pointer to ECC value
  745.   * @param  Bank NAND bank number
  746.   * @param  Timeout Timeout wait value
  747.   * @retval HAL status
  748.   */
  749. HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
  750. {
  751.   uint32_t tickstart;
  752.  
  753.   /* Check the parameters */
  754.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  755.   assert_param(IS_FSMC_NAND_BANK(Bank));
  756.  
  757.   /* Get tick */
  758.   tickstart = HAL_GetTick();
  759.  
  760.   /* Wait until FIFO is empty */
  761.   while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
  762.   {
  763.     /* Check for the Timeout */
  764.     if (Timeout != HAL_MAX_DELAY)
  765.     {
  766.       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
  767.       {
  768.         return HAL_TIMEOUT;
  769.       }
  770.     }
  771.   }
  772.  
  773.   if (Bank == FSMC_NAND_BANK2)
  774.   {
  775.     /* Get the ECCR2 register value */
  776.     *ECCval = (uint32_t)Device->ECCR2;
  777.   }
  778.   else
  779.   {
  780.     /* Get the ECCR3 register value */
  781.     *ECCval = (uint32_t)Device->ECCR3;
  782.   }
  783.  
  784.   return HAL_OK;
  785. }
  786.  
  787. /**
  788.   * @}
  789.   */
  790. #endif /* FSMC_BANK3 */
  791.  
  792. #if defined(FSMC_BANK4)
  793.  
  794. /** @addtogroup FSMC_LL_PCCARD
  795.   * @brief    PCCARD Controller functions
  796.   *
  797.   @verbatim
  798.   ==============================================================================
  799.                     ##### How to use PCCARD device driver #####
  800.   ==============================================================================
  801.   [..]
  802.     This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
  803.     to run the PCCARD/compact flash external devices.
  804.  
  805.     (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
  806.     (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
  807.     (+) FSMC PCCARD bank common space timing configuration using the function
  808.         FSMC_PCCARD_CommonSpace_Timing_Init()
  809.     (+) FSMC PCCARD bank attribute space timing configuration using the function
  810.         FSMC_PCCARD_AttributeSpace_Timing_Init()
  811.     (+) FSMC PCCARD bank IO space timing configuration using the function
  812.         FSMC_PCCARD_IOSpace_Timing_Init()
  813. @endverbatim
  814.   * @{
  815.   */
  816.  
  817. /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
  818.   *  @brief    Initialization and Configuration functions
  819.   *
  820. @verbatim
  821.   ==============================================================================
  822.               ##### Initialization and de_initialization functions #####
  823.   ==============================================================================
  824.   [..]
  825.     This section provides functions allowing to:
  826.     (+) Initialize and configure the FSMC PCCARD interface
  827.     (+) De-initialize the FSMC PCCARD interface
  828.     (+) Configure the FSMC clock and associated GPIOs
  829.  
  830. @endverbatim
  831.   * @{
  832.   */
  833.  
  834. /**
  835.   * @brief  Initializes the FSMC_PCCARD device according to the specified
  836.   *         control parameters in the FSMC_PCCARD_HandleTypeDef
  837.   * @param  Device Pointer to PCCARD device instance
  838.   * @param  Init Pointer to PCCARD Initialization structure
  839.   * @retval HAL status
  840.   */
  841. HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
  842. {
  843.   /* Check the parameters */
  844.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  845.   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
  846.   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
  847.   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
  848.  
  849.   /* Set FSMC_PCCARD device control parameters */
  850.   MODIFY_REG(Device->PCR4,
  851.              (FSMC_PCRx_PTYP                                          |
  852.               FSMC_PCRx_PWAITEN                                       |
  853.               FSMC_PCRx_PWID                                          |
  854.               FSMC_PCRx_TCLR                                          |
  855.               FSMC_PCRx_TAR),
  856.              (FSMC_PCR_MEMORY_TYPE_PCCARD                             |
  857.               Init->Waitfeature                                      |
  858.               FSMC_NAND_PCC_MEM_BUS_WIDTH_16                          |
  859.               (Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos)   |
  860.               (Init->TARSetupTime  << FSMC_PCRx_TAR_Pos)));
  861.  
  862.   return HAL_OK;
  863. }
  864.  
  865. /**
  866.   * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
  867.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  868.   * @param  Device Pointer to PCCARD device instance
  869.   * @param  Timing Pointer to PCCARD timing structure
  870.   * @retval HAL status
  871.   */
  872. HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
  873. {
  874.   /* Check the parameters */
  875.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  876.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  877.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  878.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  879.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  880.  
  881.   /* Set PCCARD timing parameters */
  882.   MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
  883.              (Timing->SetupTime                                              |
  884.               ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos)  |
  885.               ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos)  |
  886.               ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
  887.  
  888.   return HAL_OK;
  889. }
  890.  
  891. /**
  892.   * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
  893.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  894.   * @param  Device Pointer to PCCARD device instance
  895.   * @param  Timing Pointer to PCCARD timing structure
  896.   * @retval HAL status
  897.   */
  898. HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
  899. {
  900.   /* Check the parameters */
  901.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  902.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  903.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  904.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  905.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  906.  
  907.   /* Set PCCARD timing parameters */
  908.   MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK,
  909.              (Timing->SetupTime                                              |
  910.               ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos)  |
  911.               ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos)  |
  912.               ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  913.  
  914.   return HAL_OK;
  915. }
  916.  
  917. /**
  918.   * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
  919.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  920.   * @param  Device Pointer to PCCARD device instance
  921.   * @param  Timing Pointer to PCCARD timing structure
  922.   * @retval HAL status
  923.   */
  924. HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
  925. {
  926.   /* Check the parameters */
  927.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  928.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  929.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  930.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  931.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  932.  
  933.   /* Set FSMC_PCCARD device timing parameters */
  934.   MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
  935.              (Timing->SetupTime                                           |
  936.               (Timing->WaitSetupTime   << FSMC_PIO4_IOWAIT4_Pos) |
  937.               (Timing->HoldSetupTime   << FSMC_PIO4_IOHOLD4_Pos) |
  938.               (Timing->HiZSetupTime    << FSMC_PIO4_IOHIZ4_Pos)));
  939.  
  940.   return HAL_OK;
  941. }
  942.  
  943. /**
  944.   * @brief  DeInitializes the FSMC_PCCARD device
  945.   * @param  Device Pointer to PCCARD device instance
  946.   * @retval HAL status
  947.   */
  948. HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
  949. {
  950.   /* Check the parameters */
  951.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  952.  
  953.   /* Disable the FSMC_PCCARD device */
  954.   __FSMC_PCCARD_DISABLE(Device);
  955.  
  956.   /* De-initialize the FSMC_PCCARD device */
  957.   Device->PCR4    = 0x00000018U;
  958.   Device->SR4     = 0x00000040U;
  959.   Device->PMEM4   = 0xFCFCFCFCU;
  960.   Device->PATT4   = 0xFCFCFCFCU;
  961.   Device->PIO4    = 0xFCFCFCFCU;
  962.  
  963.   return HAL_OK;
  964. }
  965.  
  966. /**
  967.   * @}
  968.   */
  969. #endif /* FSMC_BANK4 */
  970.  
  971.  
  972. /**
  973.   * @}
  974.   */
  975.  
  976. /**
  977.   * @}
  978.   */
  979.  
  980. #endif /* HAL_NOR_MODULE_ENABLED */
  981. /**
  982.   * @}
  983.   */
  984.  
  985. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  986.