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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_fsmc.c
  4.   * @author  MCD Application Team
  5.   * @brief   FSMC Low Layer HAL module driver.
  6.   *
  7.   *          This file provides firmware functions to manage the following
  8.   *          functionalities of the Flexible Memory Controller (FSMC) peripheral memories:
  9.   *           + Initialization/de-initialization functions
  10.   *           + Peripheral Control functions
  11.   *           + Peripheral State functions
  12.   *
  13.   @verbatim
  14.   ==============================================================================
  15.                         ##### FSMC peripheral features #####
  16.   ==============================================================================
  17.   [..] The Flexible memory controller (FSMC) includes following memory controllers:
  18.        (+) The NOR/PSRAM memory controller
  19.        (+) The NAND/PC Card memory controller
  20.  
  21.   [..] The FSMC functional block makes the interface with synchronous and asynchronous static
  22.        memories and 16-bit PC memory cards. Its main purposes are:
  23.        (+) to translate AHB transactions into the appropriate external device protocol
  24.        (+) to meet the access time requirements of the external memory devices
  25.  
  26.   [..] All external memories share the addresses, data and control signals with the controller.
  27.        Each external device is accessed by means of a unique Chip Select. The FSMC performs
  28.        only one access at a time to an external device.
  29.        The main features of the FSMC controller are the following:
  30.         (+) Interface with static-memory mapped devices including:
  31.            (++) Static random access memory (SRAM)
  32.            (++) Read-only memory (ROM)
  33.            (++) NOR Flash memory/OneNAND Flash memory
  34.            (++) PSRAM (4 memory banks)
  35.            (++) 16-bit PC Card compatible devices
  36.            (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  37.                 data
  38.         (+) Independent Chip Select control for each memory bank
  39.         (+) Independent configuration for each memory bank
  40.  
  41.   @endverbatim
  42.   ******************************************************************************
  43.   * @attention
  44.   *
  45.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  46.   * All rights reserved.</center></h2>
  47.   *
  48.   * This software component is licensed by ST under BSD 3-Clause license,
  49.   * the "License"; You may not use this file except in compliance with the
  50.   * License. You may obtain a copy of the License at:
  51.   *                       opensource.org/licenses/BSD-3-Clause
  52.   *
  53.   ******************************************************************************
  54.   */
  55.  
  56. /* Includes ------------------------------------------------------------------*/
  57. #include "stm32f1xx_hal.h"
  58.  
  59. /** @addtogroup STM32F1xx_HAL_Driver
  60.   * @{
  61.   */
  62. #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
  63.  
  64. /** @defgroup FSMC_LL  FSMC Low Layer
  65.   * @brief FSMC driver modules
  66.   * @{
  67.   */
  68.  
  69. /* Private typedef -----------------------------------------------------------*/
  70. /* Private define ------------------------------------------------------------*/
  71.  
  72. /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
  73.   * @{
  74.   */
  75.  
  76. /* ----------------------- FSMC registers bit mask --------------------------- */
  77.  
  78. #if defined(FSMC_BANK1)
  79. /* --- BCR Register ---*/
  80. /* BCR register clear mask */
  81.  
  82. /* --- BTR Register ---*/
  83. /* BTR register clear mask */
  84. #define BTR_CLEAR_MASK    ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD  |\
  85.                                       FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
  86.                                       FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT  |\
  87.                                       FSMC_BTRx_ACCMOD))
  88.  
  89. /* --- BWTR Register ---*/
  90. /* BWTR register clear mask */
  91. #if defined(FSMC_BWTRx_BUSTURN)
  92. #define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD  |\
  93.                                       FSMC_BWTRx_DATAST | FSMC_BWTRx_BUSTURN |\
  94.                                       FSMC_BWTRx_ACCMOD))
  95. #else
  96. #define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD |\
  97.                                       FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD |\
  98.                                       FSMC_BWTRx_CLKDIV | FSMC_BWTRx_DATLAT))
  99. #endif /* FSMC_BWTRx_BUSTURN */
  100. #endif /* FSMC_BANK1 */
  101. #if defined(FSMC_BANK3)
  102.  
  103. /* --- PCR Register ---*/
  104. /* PCR register clear mask */
  105. #define PCR_CLEAR_MASK    ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN  | \
  106.                                       FSMC_PCRx_PTYP    | FSMC_PCRx_PWID   | \
  107.                                       FSMC_PCRx_ECCEN   | FSMC_PCRx_TCLR   | \
  108.                                       FSMC_PCRx_TAR     | FSMC_PCRx_ECCPS))
  109. /* --- PMEM Register ---*/
  110. /* PMEM register clear mask */
  111. #define PMEM_CLEAR_MASK   ((uint32_t)(FSMC_PMEMx_MEMSETx  | FSMC_PMEMx_MEMWAITx |\
  112.                                       FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx))
  113.  
  114. /* --- PATT Register ---*/
  115. /* PATT register clear mask */
  116. #define PATT_CLEAR_MASK   ((uint32_t)(FSMC_PATTx_ATTSETx  | FSMC_PATTx_ATTWAITx |\
  117.                                       FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx))
  118.  
  119. #endif /* FSMC_BANK3 */
  120. #if defined(FSMC_BANK4)
  121. /* --- PCR Register ---*/
  122. /* PCR register clear mask */
  123. #define PCR4_CLEAR_MASK   ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN  | \
  124.                                       FSMC_PCR4_PTYP    | FSMC_PCR4_PWID   | \
  125.                                       FSMC_PCR4_ECCEN   | FSMC_PCR4_TCLR   | \
  126.                                       FSMC_PCR4_TAR     | FSMC_PCR4_ECCPS))
  127. /* --- PMEM Register ---*/
  128. /* PMEM register clear mask */
  129. #define PMEM4_CLEAR_MASK  ((uint32_t)(FSMC_PMEM4_MEMSET4  | FSMC_PMEM4_MEMWAIT4 |\
  130.                                       FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4))
  131.  
  132. /* --- PATT Register ---*/
  133. /* PATT register clear mask */
  134. #define PATT4_CLEAR_MASK  ((uint32_t)(FSMC_PATT4_ATTSET4  | FSMC_PATT4_ATTWAIT4 |\
  135.                                       FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4))
  136.  
  137. /* --- PIO4 Register ---*/
  138. /* PIO4 register clear mask */
  139. #define PIO4_CLEAR_MASK   ((uint32_t)(FSMC_PIO4_IOSET4  | FSMC_PIO4_IOWAIT4 | \
  140.                                       FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
  141.  
  142. #endif /* FSMC_BANK4 */
  143.  
  144. /**
  145.   * @}
  146.   */
  147.  
  148. /* Private macro -------------------------------------------------------------*/
  149. /* Private variables ---------------------------------------------------------*/
  150. /* Private function prototypes -----------------------------------------------*/
  151. /* Exported functions --------------------------------------------------------*/
  152.  
  153. /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
  154.   * @{
  155.   */
  156.  
  157. #if defined(FSMC_BANK1)
  158.  
  159. /** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions
  160.   * @brief  NORSRAM Controller functions
  161.   *
  162.   @verbatim
  163.   ==============================================================================
  164.                    ##### How to use NORSRAM device driver #####
  165.   ==============================================================================
  166.  
  167.   [..]
  168.     This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
  169.     to run the NORSRAM external devices.
  170.  
  171.     (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
  172.     (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
  173.     (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
  174.     (+) FSMC NORSRAM bank extended timing configuration using the function
  175.         FSMC_NORSRAM_Extended_Timing_Init()
  176.     (+) FSMC NORSRAM bank enable/disable write operation using the functions
  177.         FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
  178.  
  179. @endverbatim
  180.   * @{
  181.   */
  182.  
  183. /** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
  184.   * @brief    Initialization and Configuration functions
  185.   *
  186.   @verbatim
  187.   ==============================================================================
  188.               ##### Initialization and de_initialization functions #####
  189.   ==============================================================================
  190.   [..]
  191.     This section provides functions allowing to:
  192.     (+) Initialize and configure the FSMC NORSRAM interface
  193.     (+) De-initialize the FSMC NORSRAM interface
  194.     (+) Configure the FSMC clock and associated GPIOs
  195.  
  196. @endverbatim
  197.   * @{
  198.   */
  199.  
  200. /**
  201.   * @brief  Initialize the FSMC_NORSRAM device according to the specified
  202.   *         control parameters in the FSMC_NORSRAM_InitTypeDef
  203.   * @param  Device Pointer to NORSRAM device instance
  204.   * @param  Init Pointer to NORSRAM Initialization structure
  205.   * @retval HAL status
  206.   */
  207. HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
  208.                                     FSMC_NORSRAM_InitTypeDef *Init)
  209. {
  210.   uint32_t flashaccess;
  211.   uint32_t btcr_reg;
  212.   uint32_t mask;
  213.  
  214.   /* Check the parameters */
  215.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  216.   assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
  217.   assert_param(IS_FSMC_MUX(Init->DataAddressMux));
  218.   assert_param(IS_FSMC_MEMORY(Init->MemoryType));
  219.   assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
  220.   assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
  221.   assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
  222.   assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
  223.   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
  224.   assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
  225.   assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
  226.   assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
  227.   assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
  228.   assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
  229.   assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
  230.  
  231.   /* Disable NORSRAM Device */
  232.   __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
  233.  
  234.   /* Set NORSRAM device control parameters */
  235.   if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
  236.   {
  237.     flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
  238.   }
  239.   else
  240.   {
  241.     flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
  242.   }
  243.  
  244.   btcr_reg = (flashaccess                   | \
  245.               Init->DataAddressMux          | \
  246.               Init->MemoryType              | \
  247.               Init->MemoryDataWidth         | \
  248.               Init->BurstAccessMode         | \
  249.               Init->WaitSignalPolarity      | \
  250.               Init->WaitSignalActive        | \
  251.               Init->WriteOperation          | \
  252.               Init->WaitSignal              | \
  253.               Init->ExtendedMode            | \
  254.               Init->AsynchronousWait        | \
  255.               Init->WriteBurst);
  256.  
  257.   btcr_reg |= Init->WrapMode;
  258.   btcr_reg |= Init->PageSize;
  259.  
  260.   mask = (FSMC_BCRx_MBKEN                |
  261.           FSMC_BCRx_MUXEN                |
  262.           FSMC_BCRx_MTYP                 |
  263.           FSMC_BCRx_MWID                 |
  264.           FSMC_BCRx_FACCEN               |
  265.           FSMC_BCRx_BURSTEN              |
  266.           FSMC_BCRx_WAITPOL              |
  267.           FSMC_BCRx_WAITCFG              |
  268.           FSMC_BCRx_WREN                 |
  269.           FSMC_BCRx_WAITEN               |
  270.           FSMC_BCRx_EXTMOD               |
  271.           FSMC_BCRx_ASYNCWAIT            |
  272.           FSMC_BCRx_CBURSTRW);
  273.  
  274.   mask |= FSMC_BCRx_WRAPMOD;
  275.   mask |= 0x00070000U; /* CPSIZE to be defined in CMSIS file */
  276.  
  277.   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
  278.  
  279.  
  280.   return HAL_OK;
  281. }
  282.  
  283. /**
  284.   * @brief  DeInitialize the FSMC_NORSRAM peripheral
  285.   * @param  Device Pointer to NORSRAM device instance
  286.   * @param  ExDevice Pointer to NORSRAM extended mode device instance
  287.   * @param  Bank NORSRAM bank number
  288.   * @retval HAL status
  289.   */
  290. HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
  291.                                      FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
  292. {
  293.   /* Check the parameters */
  294.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  295.   assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
  296.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  297.  
  298.   /* Disable the FSMC_NORSRAM device */
  299.   __FSMC_NORSRAM_DISABLE(Device, Bank);
  300.  
  301.   /* De-initialize the FSMC_NORSRAM device */
  302.   /* FSMC_NORSRAM_BANK1 */
  303.   if (Bank == FSMC_NORSRAM_BANK1)
  304.   {
  305.     Device->BTCR[Bank] = 0x000030DBU;
  306.   }
  307.   /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
  308.   else
  309.   {
  310.     Device->BTCR[Bank] = 0x000030D2U;
  311.   }
  312.  
  313.   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
  314.   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;
  315.  
  316.   return HAL_OK;
  317. }
  318.  
  319. /**
  320.   * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
  321.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  322.   * @param  Device Pointer to NORSRAM device instance
  323.   * @param  Timing Pointer to NORSRAM Timing structure
  324.   * @param  Bank NORSRAM bank number
  325.   * @retval HAL status
  326.   */
  327. HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
  328.                                           FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
  329. {
  330.  
  331.   /* Check the parameters */
  332.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  333.   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  334.   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  335.   assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  336.   assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  337.   assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  338.   assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  339.   assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  340.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  341.  
  342.   /* Set FSMC_NORSRAM device timing parameters */
  343.   MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                                  |
  344.                                                        ((Timing->AddressHoldTime)        << FSMC_BTRx_ADDHLD_Pos)  |
  345.                                                        ((Timing->DataSetupTime)          << FSMC_BTRx_DATAST_Pos)  |
  346.                                                        ((Timing->BusTurnAroundDuration)  << FSMC_BTRx_BUSTURN_Pos) |
  347.                                                        (((Timing->CLKDivision) - 1U)     << FSMC_BTRx_CLKDIV_Pos)  |
  348.                                                        (((Timing->DataLatency) - 2U)     << FSMC_BTRx_DATLAT_Pos)  |
  349.                                                        (Timing->AccessMode)));
  350.  
  351.   return HAL_OK;
  352. }
  353.  
  354. /**
  355.   * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
  356.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  357.   * @param  Device Pointer to NORSRAM device instance
  358.   * @param  Timing Pointer to NORSRAM Timing structure
  359.   * @param  Bank NORSRAM bank number
  360.   * @param  ExtendedMode FSMC Extended Mode
  361.   *          This parameter can be one of the following values:
  362.   *            @arg FSMC_EXTENDED_MODE_DISABLE
  363.   *            @arg FSMC_EXTENDED_MODE_ENABLE
  364.   * @retval HAL status
  365.   */
  366. HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
  367.                                                    FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
  368.                                                    uint32_t ExtendedMode)
  369. {
  370.   /* Check the parameters */
  371.   assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
  372.  
  373.   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  374.   if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
  375.   {
  376.     /* Check the parameters */
  377.     assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
  378.     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  379.     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  380.     assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  381. #if defined(FSMC_BWTRx_BUSTURN)
  382.     assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  383. #else
  384.     assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  385.     assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  386. #endif /* FSMC_BWTRx_BUSTURN */
  387.     assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  388.     assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  389.  
  390.     /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  391. #if defined(FSMC_BWTRx_BUSTURN)
  392.     MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
  393.                                                      ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos)  |
  394.                                                      ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos)  |
  395.                                                      Timing->AccessMode                                          |
  396.                                                      ((Timing->BusTurnAroundDuration)  << FSMC_BWTRx_BUSTURN_Pos)));
  397. #else
  398.     MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
  399.                                                      ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos)  |
  400.                                                      ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos)  |
  401.                                                      Timing->AccessMode                                          |
  402.                                                      (((Timing->CLKDivision) - 1U)     << FSMC_BWTRx_CLKDIV_Pos)  |
  403.                                                      (((Timing->DataLatency) - 2U)     << FSMC_BWTRx_DATLAT_Pos)));
  404. #endif /* FSMC_BWTRx_BUSTURN */
  405.   }
  406.   else
  407.   {
  408.     Device->BWTR[Bank] = 0x0FFFFFFFU;
  409.   }
  410.  
  411.   return HAL_OK;
  412. }
  413. /**
  414.   * @}
  415.   */
  416.  
  417. /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
  418.   *  @brief   management functions
  419.   *
  420. @verbatim
  421.   ==============================================================================
  422.                       ##### FSMC_NORSRAM Control functions #####
  423.   ==============================================================================
  424.   [..]
  425.     This subsection provides a set of functions allowing to control dynamically
  426.     the FSMC NORSRAM interface.
  427.  
  428. @endverbatim
  429.   * @{
  430.   */
  431.  
  432. /**
  433.   * @brief  Enables dynamically FSMC_NORSRAM write operation.
  434.   * @param  Device Pointer to NORSRAM device instance
  435.   * @param  Bank NORSRAM bank number
  436.   * @retval HAL status
  437.   */
  438. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  439. {
  440.   /* Check the parameters */
  441.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  442.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  443.  
  444.   /* Enable write operation */
  445.   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  446.  
  447.   return HAL_OK;
  448. }
  449.  
  450. /**
  451.   * @brief  Disables dynamically FSMC_NORSRAM write operation.
  452.   * @param  Device Pointer to NORSRAM device instance
  453.   * @param  Bank NORSRAM bank number
  454.   * @retval HAL status
  455.   */
  456. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  457. {
  458.   /* Check the parameters */
  459.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  460.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  461.  
  462.   /* Disable write operation */
  463.   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  464.  
  465.   return HAL_OK;
  466. }
  467.  
  468. /**
  469.   * @}
  470.   */
  471.  
  472. /**
  473.   * @}
  474.   */
  475. #endif /* FSMC_BANK1 */
  476.  
  477. #if defined(FSMC_BANK3)
  478.  
  479. /** @defgroup FSMC_LL_Exported_Functions_NAND FSMC Low Layer NAND Exported Functions
  480.   * @brief    NAND Controller functions
  481.   *
  482.   @verbatim
  483.   ==============================================================================
  484.                     ##### How to use NAND device driver #####
  485.   ==============================================================================
  486.   [..]
  487.     This driver contains a set of APIs to interface with the FSMC NAND banks in order
  488.     to run the NAND external devices.
  489.  
  490.     (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
  491.     (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
  492.     (+) FSMC NAND bank common space timing configuration using the function
  493.         FSMC_NAND_CommonSpace_Timing_Init()
  494.     (+) FSMC NAND bank attribute space timing configuration using the function
  495.         FSMC_NAND_AttributeSpace_Timing_Init()
  496.     (+) FSMC NAND bank enable/disable ECC correction feature using the functions
  497.         FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
  498.     (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
  499.  
  500. @endverbatim
  501.   * @{
  502.   */
  503.  
  504. /** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
  505.   *  @brief    Initialization and Configuration functions
  506.   *
  507. @verbatim
  508.   ==============================================================================
  509.               ##### Initialization and de_initialization functions #####
  510.   ==============================================================================
  511.   [..]
  512.     This section provides functions allowing to:
  513.     (+) Initialize and configure the FSMC NAND interface
  514.     (+) De-initialize the FSMC NAND interface
  515.     (+) Configure the FSMC clock and associated GPIOs
  516.  
  517. @endverbatim
  518.   * @{
  519.   */
  520.  
  521. /**
  522.   * @brief  Initializes the FSMC_NAND device according to the specified
  523.   *         control parameters in the FSMC_NAND_HandleTypeDef
  524.   * @param  Device Pointer to NAND device instance
  525.   * @param  Init Pointer to NAND Initialization structure
  526.   * @retval HAL status
  527.   */
  528. HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
  529. {
  530.   /* Check the parameters */
  531.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  532.   assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
  533.   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
  534.   assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
  535.   assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
  536.   assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
  537.   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
  538.   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
  539.  
  540.   /* Set NAND device control parameters */
  541.   if (Init->NandBank == FSMC_NAND_BANK2)
  542.   {
  543.     /* NAND bank 2 registers configuration */
  544.     MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
  545.                                               FSMC_PCR_MEMORY_TYPE_NAND                               |
  546.                                               Init->MemoryDataWidth                                  |
  547.                                               Init->EccComputation                                   |
  548.                                               Init->ECCPageSize                                      |
  549.                                               ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos)  |
  550.                                               ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
  551.   }
  552.   else
  553.   {
  554.     /* NAND bank 3 registers configuration */
  555.     MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
  556.                                               FSMC_PCR_MEMORY_TYPE_NAND                               |
  557.                                               Init->MemoryDataWidth                                  |
  558.                                               Init->EccComputation                                   |
  559.                                               Init->ECCPageSize                                      |
  560.                                               ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos)  |
  561.                                               ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
  562.   }
  563.  
  564.   return HAL_OK;
  565. }
  566.  
  567. /**
  568.   * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
  569.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  570.   * @param  Device Pointer to NAND device instance
  571.   * @param  Timing Pointer to NAND timing structure
  572.   * @param  Bank NAND bank number
  573.   * @retval HAL status
  574.   */
  575. HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
  576.                                                    FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  577. {
  578.   /* Check the parameters */
  579.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  580.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  581.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  582.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  583.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  584.   assert_param(IS_FSMC_NAND_BANK(Bank));
  585.  
  586.   /* Set FSMC_NAND device timing parameters */
  587.   if (Bank == FSMC_NAND_BANK2)
  588.   {
  589.     /* NAND bank 2 registers configuration */
  590.     MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
  591.                                                 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
  592.                                                 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
  593.                                                 ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
  594.   }
  595.   else
  596.   {
  597.     /* NAND bank 3 registers configuration */
  598.     MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
  599.                                                 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
  600.                                                 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
  601.                                                 ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
  602.   }
  603.  
  604.   return HAL_OK;
  605. }
  606.  
  607. /**
  608.   * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
  609.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  610.   * @param  Device Pointer to NAND device instance
  611.   * @param  Timing Pointer to NAND timing structure
  612.   * @param  Bank NAND bank number
  613.   * @retval HAL status
  614.   */
  615. HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
  616.                                                       FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  617. {
  618.   /* Check the parameters */
  619.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  620.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  621.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  622.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  623.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  624.   assert_param(IS_FSMC_NAND_BANK(Bank));
  625.  
  626.   /* Set FSMC_NAND device timing parameters */
  627.   if (Bank == FSMC_NAND_BANK2)
  628.   {
  629.     /* NAND bank 2 registers configuration */
  630.     MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
  631.                                                 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
  632.                                                 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
  633.                                                 ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  634.   }
  635.   else
  636.   {
  637.     /* NAND bank 3 registers configuration */
  638.     MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
  639.                                                 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
  640.                                                 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
  641.                                                 ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  642.   }
  643.  
  644.   return HAL_OK;
  645. }
  646.  
  647. /**
  648.   * @brief  DeInitializes the FSMC_NAND device
  649.   * @param  Device Pointer to NAND device instance
  650.   * @param  Bank NAND bank number
  651.   * @retval HAL status
  652.   */
  653. HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  654. {
  655.   /* Check the parameters */
  656.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  657.   assert_param(IS_FSMC_NAND_BANK(Bank));
  658.  
  659.   /* Disable the NAND Bank */
  660.   __FSMC_NAND_DISABLE(Device, Bank);
  661.  
  662.   /* De-initialize the NAND Bank */
  663.   if (Bank == FSMC_NAND_BANK2)
  664.   {
  665.     /* Set the FSMC_NAND_BANK2 registers to their reset values */
  666.     WRITE_REG(Device->PCR2,  0x00000018U);
  667.     WRITE_REG(Device->SR2,   0x00000040U);
  668.     WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
  669.     WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
  670.   }
  671.   /* FSMC_Bank3_NAND */
  672.   else
  673.   {
  674.     /* Set the FSMC_NAND_BANK3 registers to their reset values */
  675.     WRITE_REG(Device->PCR3,  0x00000018U);
  676.     WRITE_REG(Device->SR3,   0x00000040U);
  677.     WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
  678.     WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
  679.   }
  680.  
  681.   return HAL_OK;
  682. }
  683.  
  684. /**
  685.   * @}
  686.   */
  687.  
  688. /** @defgroup HAL_FSMC_NAND_Group2 Peripheral Control functions
  689.   *  @brief   management functions
  690.   *
  691. @verbatim
  692.   ==============================================================================
  693.                        ##### FSMC_NAND Control functions #####
  694.   ==============================================================================
  695.   [..]
  696.     This subsection provides a set of functions allowing to control dynamically
  697.     the FSMC NAND interface.
  698.  
  699. @endverbatim
  700.   * @{
  701.   */
  702.  
  703.  
  704. /**
  705.   * @brief  Enables dynamically FSMC_NAND ECC feature.
  706.   * @param  Device Pointer to NAND device instance
  707.   * @param  Bank NAND bank number
  708.   * @retval HAL status
  709.   */
  710. HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  711. {
  712.   /* Check the parameters */
  713.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  714.   assert_param(IS_FSMC_NAND_BANK(Bank));
  715.  
  716.   /* Enable ECC feature */
  717.   if (Bank == FSMC_NAND_BANK2)
  718.   {
  719.     SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
  720.   }
  721.   else
  722.   {
  723.     SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
  724.   }
  725.  
  726.   return HAL_OK;
  727. }
  728.  
  729.  
  730. /**
  731.   * @brief  Disables dynamically FSMC_NAND ECC feature.
  732.   * @param  Device Pointer to NAND device instance
  733.   * @param  Bank NAND bank number
  734.   * @retval HAL status
  735.   */
  736. HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  737. {
  738.   /* Check the parameters */
  739.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  740.   assert_param(IS_FSMC_NAND_BANK(Bank));
  741.  
  742.   /* Disable ECC feature */
  743.   if (Bank == FSMC_NAND_BANK2)
  744.   {
  745.     CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
  746.   }
  747.   else
  748.   {
  749.     CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
  750.   }
  751.  
  752.   return HAL_OK;
  753. }
  754.  
  755. /**
  756.   * @brief  Disables dynamically FSMC_NAND ECC feature.
  757.   * @param  Device Pointer to NAND device instance
  758.   * @param  ECCval Pointer to ECC value
  759.   * @param  Bank NAND bank number
  760.   * @param  Timeout Timeout wait value
  761.   * @retval HAL status
  762.   */
  763. HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
  764.                                   uint32_t Timeout)
  765. {
  766.   uint32_t tickstart;
  767.  
  768.   /* Check the parameters */
  769.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  770.   assert_param(IS_FSMC_NAND_BANK(Bank));
  771.  
  772.   /* Get tick */
  773.   tickstart = HAL_GetTick();
  774.  
  775.   /* Wait until FIFO is empty */
  776.   while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
  777.   {
  778.     /* Check for the Timeout */
  779.     if (Timeout != HAL_MAX_DELAY)
  780.     {
  781.       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
  782.       {
  783.         return HAL_TIMEOUT;
  784.       }
  785.     }
  786.   }
  787.  
  788.   if (Bank == FSMC_NAND_BANK2)
  789.   {
  790.     /* Get the ECCR2 register value */
  791.     *ECCval = (uint32_t)Device->ECCR2;
  792.   }
  793.   else
  794.   {
  795.     /* Get the ECCR3 register value */
  796.     *ECCval = (uint32_t)Device->ECCR3;
  797.   }
  798.  
  799.   return HAL_OK;
  800. }
  801.  
  802. /**
  803.   * @}
  804.   */
  805. #endif /* FSMC_BANK3 */
  806.  
  807. #if defined(FSMC_BANK4)
  808.  
  809. /** @addtogroup FSMC_LL_PCCARD
  810.   * @brief    PCCARD Controller functions
  811.   *
  812.   @verbatim
  813.   ==============================================================================
  814.                     ##### How to use PCCARD device driver #####
  815.   ==============================================================================
  816.   [..]
  817.     This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
  818.     to run the PCCARD/compact flash external devices.
  819.  
  820.     (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
  821.     (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
  822.     (+) FSMC PCCARD bank common space timing configuration using the function
  823.         FSMC_PCCARD_CommonSpace_Timing_Init()
  824.     (+) FSMC PCCARD bank attribute space timing configuration using the function
  825.         FSMC_PCCARD_AttributeSpace_Timing_Init()
  826.     (+) FSMC PCCARD bank IO space timing configuration using the function
  827.         FSMC_PCCARD_IOSpace_Timing_Init()
  828. @endverbatim
  829.   * @{
  830.   */
  831.  
  832. /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
  833.   *  @brief    Initialization and Configuration functions
  834.   *
  835. @verbatim
  836.   ==============================================================================
  837.               ##### Initialization and de_initialization functions #####
  838.   ==============================================================================
  839.   [..]
  840.     This section provides functions allowing to:
  841.     (+) Initialize and configure the FSMC PCCARD interface
  842.     (+) De-initialize the FSMC PCCARD interface
  843.     (+) Configure the FSMC clock and associated GPIOs
  844.  
  845. @endverbatim
  846.   * @{
  847.   */
  848.  
  849. /**
  850.   * @brief  Initializes the FSMC_PCCARD device according to the specified
  851.   *         control parameters in the FSMC_PCCARD_HandleTypeDef
  852.   * @param  Device Pointer to PCCARD device instance
  853.   * @param  Init Pointer to PCCARD Initialization structure
  854.   * @retval HAL status
  855.   */
  856. HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
  857. {
  858.   /* Check the parameters */
  859.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  860. #if defined(FSMC_BANK3)
  861.   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
  862.   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
  863.   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
  864. #endif /* FSMC_BANK3 */
  865.  
  866.   /* Set FSMC_PCCARD device control parameters */
  867.   MODIFY_REG(Device->PCR4,
  868.              (FSMC_PCRx_PTYP                                          |
  869.               FSMC_PCRx_PWAITEN                                       |
  870.               FSMC_PCRx_PWID                                          |
  871.               FSMC_PCRx_TCLR                                          |
  872.               FSMC_PCRx_TAR),
  873.              (FSMC_PCR_MEMORY_TYPE_PCCARD                             |
  874.               Init->Waitfeature                                      |
  875.               FSMC_NAND_PCC_MEM_BUS_WIDTH_16                          |
  876.               (Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos)   |
  877.               (Init->TARSetupTime  << FSMC_PCRx_TAR_Pos)));
  878.  
  879.   return HAL_OK;
  880. }
  881.  
  882. /**
  883.   * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
  884.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  885.   * @param  Device Pointer to PCCARD device instance
  886.   * @param  Timing Pointer to PCCARD timing structure
  887.   * @retval HAL status
  888.   */
  889. HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
  890.                                                               FSMC_NAND_PCC_TimingTypeDef *Timing)
  891. {
  892.   /* Check the parameters */
  893.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  894. #if defined(FSMC_BANK3)
  895.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  896.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  897.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  898.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  899. #endif /* FSMC_BANK3 */
  900.  
  901.   /* Set PCCARD timing parameters */
  902.   MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
  903.              (Timing->SetupTime                                              |
  904.               ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos)  |
  905.               ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos)  |
  906.               ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
  907.  
  908.   return HAL_OK;
  909. }
  910.  
  911. /**
  912.   * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
  913.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  914.   * @param  Device Pointer to PCCARD device instance
  915.   * @param  Timing Pointer to PCCARD timing structure
  916.   * @retval HAL status
  917.   */
  918. HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
  919.                                                                  FSMC_NAND_PCC_TimingTypeDef *Timing)
  920. {
  921.   /* Check the parameters */
  922.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  923. #if defined(FSMC_BANK3)
  924.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  925.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  926.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  927.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  928. #endif /* FSMC_BANK3 */
  929.  
  930.   /* Set PCCARD timing parameters */
  931.   MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK,
  932.              (Timing->SetupTime                                              |
  933.               ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos)  |
  934.               ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos)  |
  935.               ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  936.  
  937.   return HAL_OK;
  938. }
  939.  
  940. /**
  941.   * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
  942.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  943.   * @param  Device Pointer to PCCARD device instance
  944.   * @param  Timing Pointer to PCCARD timing structure
  945.   * @retval HAL status
  946.   */
  947. HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
  948.                                                           FSMC_NAND_PCC_TimingTypeDef *Timing)
  949. {
  950.   /* Check the parameters */
  951.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  952. #if defined(FSMC_BANK3)
  953.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  954.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  955.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  956.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  957. #endif /* FSMC_BANK3 */
  958.  
  959.   /* Set FSMC_PCCARD device timing parameters */
  960.   MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
  961.              (Timing->SetupTime                                           |
  962.               (Timing->WaitSetupTime   << FSMC_PIO4_IOWAIT4_Pos) |
  963.               (Timing->HoldSetupTime   << FSMC_PIO4_IOHOLD4_Pos) |
  964.               (Timing->HiZSetupTime    << FSMC_PIO4_IOHIZ4_Pos)));
  965.  
  966.   return HAL_OK;
  967. }
  968.  
  969. /**
  970.   * @brief  DeInitializes the FSMC_PCCARD device
  971.   * @param  Device Pointer to PCCARD device instance
  972.   * @retval HAL status
  973.   */
  974. HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
  975. {
  976.   /* Check the parameters */
  977.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  978.  
  979.   /* Disable the FSMC_PCCARD device */
  980.   __FSMC_PCCARD_DISABLE(Device);
  981.  
  982.   /* De-initialize the FSMC_PCCARD device */
  983.   Device->PCR4    = 0x00000018U;
  984.   Device->SR4     = 0x00000040U;
  985.   Device->PMEM4   = 0xFCFCFCFCU;
  986.   Device->PATT4   = 0xFCFCFCFCU;
  987.   Device->PIO4    = 0xFCFCFCFCU;
  988.  
  989.   return HAL_OK;
  990. }
  991.  
  992. /**
  993.   * @}
  994.   */
  995. #endif /* FSMC_BANK4 */
  996.  
  997.  
  998. /**
  999.   * @}
  1000.   */
  1001.  
  1002. /**
  1003.   * @}
  1004.   */
  1005.  
  1006. #endif /* HAL_NOR_MODULE_ENABLED */
  1007. /**
  1008.   * @}
  1009.   */
  1010. /**
  1011.   * @}
  1012.   */
  1013.  
  1014. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1015.