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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_fsmc.c
  4.   * @author  MCD Application Team
  5.   * @brief   FSMC Low Layer HAL module driver.
  6.   *
  7.   *          This file provides firmware functions to manage the following
  8.   *          functionalities of the Flexible Memory Controller (FSMC) peripheral memories:
  9.   *           + Initialization/de-initialization functions
  10.   *           + Peripheral Control functions
  11.   *           + Peripheral State functions
  12.   *
  13.   @verbatim
  14.   ==============================================================================
  15.                         ##### FSMC peripheral features #####
  16.   ==============================================================================
  17.   [..] The Flexible memory controller (FSMC) includes following memory controllers:
  18.        (+) The NOR/PSRAM memory controller
  19.        (+) The NAND/PC Card memory controller
  20.  
  21.   [..] The FSMC functional block makes the interface with synchronous and asynchronous static
  22.        memories and 16-bit PC memory cards. Its main purposes are:
  23.        (+) to translate AHB transactions into the appropriate external device protocol
  24.        (+) to meet the access time requirements of the external memory devices
  25.  
  26.   [..] All external memories share the addresses, data and control signals with the controller.
  27.        Each external device is accessed by means of a unique Chip Select. The FSMC performs
  28.        only one access at a time to an external device.
  29.        The main features of the FSMC controller are the following:
  30.         (+) Interface with static-memory mapped devices including:
  31.            (++) Static random access memory (SRAM)
  32.            (++) Read-only memory (ROM)
  33.            (++) NOR Flash memory/OneNAND Flash memory
  34.            (++) PSRAM (4 memory banks)
  35.            (++) 16-bit PC Card compatible devices
  36.            (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  37.                 data
  38.         (+) Independent Chip Select control for each memory bank
  39.         (+) Independent configuration for each memory bank
  40.  
  41.   @endverbatim
  42.   ******************************************************************************
  43.   * @attention
  44.   *
  45.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  46.   * All rights reserved.</center></h2>
  47.   *
  48.   * This software component is licensed by ST under BSD 3-Clause license,
  49.   * the "License"; You may not use this file except in compliance with the
  50.   * License. You may obtain a copy of the License at:
  51.   *                       opensource.org/licenses/BSD-3-Clause
  52.   *
  53.   ******************************************************************************
  54.   */
  55.  
  56. /* Includes ------------------------------------------------------------------*/
  57. #include "stm32f1xx_hal.h"
  58.  
  59. /** @addtogroup STM32F1xx_HAL_Driver
  60.   * @{
  61.   */
  62. #if (((defined HAL_NOR_MODULE_ENABLED || defined HAL_SRAM_MODULE_ENABLED)) || defined HAL_NAND_MODULE_ENABLED || defined HAL_PCCARD_MODULE_ENABLED )
  63.  
  64. /** @defgroup FSMC_LL  FSMC Low Layer
  65.   * @brief FSMC driver modules
  66.   * @{
  67.   */
  68.  
  69. /* Private typedef -----------------------------------------------------------*/
  70. /* Private define ------------------------------------------------------------*/
  71.  
  72. /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
  73.   * @{
  74.   */
  75.  
  76. /* ----------------------- FSMC registers bit mask --------------------------- */
  77.  
  78. #if defined FSMC_BANK1
  79. /* --- BCR Register ---*/
  80. /* BCR register clear mask */
  81.  
  82. /* --- BTR Register ---*/
  83. /* BTR register clear mask */
  84. #define BTR_CLEAR_MASK    ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD  |\
  85.                                       FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
  86.                                       FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT  |\
  87.                                       FSMC_BTRx_ACCMOD))
  88.  
  89. /* --- BWTR Register ---*/
  90. /* BWTR register clear mask */
  91. #if defined(FSMC_BWTRx_BUSTURN)
  92. #define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD  |\
  93.                                       FSMC_BWTRx_DATAST | FSMC_BWTRx_BUSTURN |\
  94.                                       FSMC_BWTRx_ACCMOD))
  95. #else
  96. #define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD  |\
  97.                                       FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD))
  98. #endif /* FSMC_BWTRx_BUSTURN */
  99. #endif /* FSMC_BANK1 */
  100. #if defined(FSMC_BANK3)
  101.  
  102. /* --- PCR Register ---*/
  103. /* PCR register clear mask */
  104. #define PCR_CLEAR_MASK    ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN  | \
  105.                                       FSMC_PCRx_PTYP    | FSMC_PCRx_PWID   | \
  106.                                       FSMC_PCRx_ECCEN   | FSMC_PCRx_TCLR   | \
  107.                                       FSMC_PCRx_TAR     | FSMC_PCRx_ECCPS))
  108. /* --- PMEM Register ---*/
  109. /* PMEM register clear mask */
  110. #define PMEM_CLEAR_MASK   ((uint32_t)(FSMC_PMEMx_MEMSETx  | FSMC_PMEMx_MEMWAITx |\
  111.                                       FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx))
  112.  
  113. /* --- PATT Register ---*/
  114. /* PATT register clear mask */
  115. #define PATT_CLEAR_MASK   ((uint32_t)(FSMC_PATTx_ATTSETx  | FSMC_PATTx_ATTWAITx |\
  116.                                       FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx))
  117.  
  118. #endif /* FSMC_BANK3 */
  119. #if defined(FSMC_BANK4)
  120. /* --- PCR Register ---*/
  121. /* PCR register clear mask */
  122. #define PCR4_CLEAR_MASK   ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN  | \
  123.                                       FSMC_PCR4_PTYP    | FSMC_PCR4_PWID   | \
  124.                                       FSMC_PCR4_ECCEN   | FSMC_PCR4_TCLR   | \
  125.                                       FSMC_PCR4_TAR     | FSMC_PCR4_ECCPS))
  126. /* --- PMEM Register ---*/
  127. /* PMEM register clear mask */
  128. #define PMEM4_CLEAR_MASK  ((uint32_t)(FSMC_PMEM4_MEMSET4  | FSMC_PMEM4_MEMWAIT4 |\
  129.                                       FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4))
  130.  
  131. /* --- PATT Register ---*/
  132. /* PATT register clear mask */
  133. #define PATT4_CLEAR_MASK  ((uint32_t)(FSMC_PATT4_ATTSET4  | FSMC_PATT4_ATTWAIT4 |\
  134.                                       FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4))
  135.  
  136. /* --- PIO4 Register ---*/
  137. /* PIO4 register clear mask */
  138. #define PIO4_CLEAR_MASK   ((uint32_t)(FSMC_PIO4_IOSET4  | FSMC_PIO4_IOWAIT4 | \
  139.                                       FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
  140.  
  141. #endif /* FSMC_BANK4 */
  142.  
  143. /**
  144.   * @}
  145.   */
  146.  
  147. /* Private macro -------------------------------------------------------------*/
  148. /* Private variables ---------------------------------------------------------*/
  149. /* Private function prototypes -----------------------------------------------*/
  150. /* Exported functions --------------------------------------------------------*/
  151.  
  152. /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
  153.   * @{
  154.   */
  155.  
  156. #if defined FSMC_BANK1
  157.  
  158. /** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions
  159.   * @brief  NORSRAM Controller functions
  160.   *
  161.   @verbatim
  162.   ==============================================================================
  163.                    ##### How to use NORSRAM device driver #####
  164.   ==============================================================================
  165.  
  166.   [..]
  167.     This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
  168.     to run the NORSRAM external devices.
  169.  
  170.     (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
  171.     (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
  172.     (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
  173.     (+) FSMC NORSRAM bank extended timing configuration using the function
  174.         FSMC_NORSRAM_Extended_Timing_Init()
  175.     (+) FSMC NORSRAM bank enable/disable write operation using the functions
  176.         FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
  177.  
  178. @endverbatim
  179.   * @{
  180.   */
  181.  
  182. /** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
  183.   * @brief    Initialization and Configuration functions
  184.   *
  185.   @verbatim
  186.   ==============================================================================
  187.               ##### Initialization and de_initialization functions #####
  188.   ==============================================================================
  189.   [..]
  190.     This section provides functions allowing to:
  191.     (+) Initialize and configure the FSMC NORSRAM interface
  192.     (+) De-initialize the FSMC NORSRAM interface
  193.     (+) Configure the FSMC clock and associated GPIOs
  194.  
  195. @endverbatim
  196.   * @{
  197.   */
  198.  
  199. /**
  200.   * @brief  Initialize the FSMC_NORSRAM device according to the specified
  201.   *         control parameters in the FSMC_NORSRAM_InitTypeDef
  202.   * @param  Device Pointer to NORSRAM device instance
  203.   * @param  Init Pointer to NORSRAM Initialization structure
  204.   * @retval HAL status
  205.   */
  206. HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
  207.                                     FSMC_NORSRAM_InitTypeDef *Init)
  208. {
  209.   uint32_t flashaccess;
  210.   uint32_t btcr_reg;
  211.   uint32_t mask;
  212.  
  213.   /* Check the parameters */
  214.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  215.   assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
  216.   assert_param(IS_FSMC_MUX(Init->DataAddressMux));
  217.   assert_param(IS_FSMC_MEMORY(Init->MemoryType));
  218.   assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
  219.   assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
  220.   assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
  221.   assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
  222.   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
  223.   assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
  224.   assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
  225.   assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
  226.   assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
  227.   assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
  228.   assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
  229.  
  230.   /* Disable NORSRAM Device */
  231.   __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
  232.  
  233.   /* Set NORSRAM device control parameters */
  234.   if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
  235.   {
  236.     flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
  237.   }
  238.   else
  239.   {
  240.     flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
  241.   }
  242.  
  243.   btcr_reg = (flashaccess                   | \
  244.               Init->DataAddressMux          | \
  245.               Init->MemoryType              | \
  246.               Init->MemoryDataWidth         | \
  247.               Init->BurstAccessMode         | \
  248.               Init->WaitSignalPolarity      | \
  249.               Init->WaitSignalActive        | \
  250.               Init->WriteOperation          | \
  251.               Init->WaitSignal              | \
  252.               Init->ExtendedMode            | \
  253.               Init->AsynchronousWait        | \
  254.               Init->WriteBurst);
  255.  
  256.   btcr_reg |= Init->WrapMode;
  257.   btcr_reg |= Init->PageSize;
  258.  
  259.   mask = (FSMC_BCRx_MBKEN                |
  260.           FSMC_BCRx_MUXEN                |
  261.           FSMC_BCRx_MTYP                 |
  262.           FSMC_BCRx_MWID                 |
  263.           FSMC_BCRx_FACCEN               |
  264.           FSMC_BCRx_BURSTEN              |
  265.           FSMC_BCRx_WAITPOL              |
  266.           FSMC_BCRx_WAITCFG              |
  267.           FSMC_BCRx_WREN                 |
  268.           FSMC_BCRx_WAITEN               |
  269.           FSMC_BCRx_EXTMOD               |
  270.           FSMC_BCRx_ASYNCWAIT            |
  271.           FSMC_BCRx_CBURSTRW);
  272.  
  273.   mask |= FSMC_BCRx_WRAPMOD;
  274.   mask |= 0x00070000U; /* CPSIZE to be defined in CMSIS file */
  275.  
  276.   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
  277.  
  278.  
  279.   return HAL_OK;
  280. }
  281.  
  282. /**
  283.   * @brief  DeInitialize the FSMC_NORSRAM peripheral
  284.   * @param  Device Pointer to NORSRAM device instance
  285.   * @param  ExDevice Pointer to NORSRAM extended mode device instance
  286.   * @param  Bank NORSRAM bank number
  287.   * @retval HAL status
  288.   */
  289. HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
  290.                                      FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
  291. {
  292.   /* Check the parameters */
  293.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  294.   assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
  295.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  296.  
  297.   /* Disable the FSMC_NORSRAM device */
  298.   __FSMC_NORSRAM_DISABLE(Device, Bank);
  299.  
  300.   /* De-initialize the FSMC_NORSRAM device */
  301.   /* FSMC_NORSRAM_BANK1 */
  302.   if (Bank == FSMC_NORSRAM_BANK1)
  303.   {
  304.     Device->BTCR[Bank] = 0x000030DBU;
  305.   }
  306.   /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
  307.   else
  308.   {
  309.     Device->BTCR[Bank] = 0x000030D2U;
  310.   }
  311.  
  312.   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
  313.   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;
  314.  
  315.   return HAL_OK;
  316. }
  317.  
  318. /**
  319.   * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
  320.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  321.   * @param  Device Pointer to NORSRAM device instance
  322.   * @param  Timing Pointer to NORSRAM Timing structure
  323.   * @param  Bank NORSRAM bank number
  324.   * @retval HAL status
  325.   */
  326. HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
  327.                                           FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
  328. {
  329.  
  330.   /* Check the parameters */
  331.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  332.   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  333.   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  334.   assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  335.   assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  336.   assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  337.   assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  338.   assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  339.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  340.  
  341.   /* Set FSMC_NORSRAM device timing parameters */
  342.   MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                                  |
  343.                                                        ((Timing->AddressHoldTime)        << FSMC_BTRx_ADDHLD_Pos)  |
  344.                                                        ((Timing->DataSetupTime)          << FSMC_BTRx_DATAST_Pos)  |
  345.                                                        ((Timing->BusTurnAroundDuration)  << FSMC_BTRx_BUSTURN_Pos) |
  346.                                                        (((Timing->CLKDivision) - 1U)     << FSMC_BTRx_CLKDIV_Pos)  |
  347.                                                        (((Timing->DataLatency) - 2U)     << FSMC_BTRx_DATLAT_Pos)  |
  348.                                                        (Timing->AccessMode)));
  349.  
  350.   return HAL_OK;
  351. }
  352.  
  353. /**
  354.   * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
  355.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  356.   * @param  Device Pointer to NORSRAM device instance
  357.   * @param  Timing Pointer to NORSRAM Timing structure
  358.   * @param  Bank NORSRAM bank number
  359.   * @param  ExtendedMode FSMC Extended Mode
  360.   *          This parameter can be one of the following values:
  361.   *            @arg FSMC_EXTENDED_MODE_DISABLE
  362.   *            @arg FSMC_EXTENDED_MODE_ENABLE
  363.   * @retval HAL status
  364.   */
  365. HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
  366.                                                    FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
  367. {
  368.   /* Check the parameters */
  369.   assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
  370.  
  371.   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  372.   if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
  373.   {
  374.     /* Check the parameters */
  375.     assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
  376.     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  377.     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  378.     assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  379. #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  380.     assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  381. #else
  382.     assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  383.     assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  384. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  385.     assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  386.     assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  387.  
  388.     /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  389. #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  390.     MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
  391.                                                      ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos)  |
  392.                                                      ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos)  |
  393.                                                      Timing->AccessMode                                          |
  394.                                                      ((Timing->BusTurnAroundDuration)  << FSMC_BWTRx_BUSTURN_Pos)));
  395. #else
  396.     MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
  397.                                                      ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos)  |
  398.                                                      ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos)  |
  399.                                                      Timing->AccessMode                                          |
  400.                                                      (((Timing->CLKDivision) - 1U)     << FSMC_BTRx_CLKDIV_Pos)   |
  401.                                                      (((Timing->DataLatency) - 2U)     << FSMC_BWTRx_DATLAT_Pos)));
  402. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  403.   }
  404.   else
  405.   {
  406.     Device->BWTR[Bank] = 0x0FFFFFFFU;
  407.   }
  408.  
  409.   return HAL_OK;
  410. }
  411. /**
  412.   * @}
  413.   */
  414.  
  415. /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
  416.   *  @brief   management functions
  417.   *
  418. @verbatim
  419.   ==============================================================================
  420.                       ##### FSMC_NORSRAM Control functions #####
  421.   ==============================================================================
  422.   [..]
  423.     This subsection provides a set of functions allowing to control dynamically
  424.     the FSMC NORSRAM interface.
  425.  
  426. @endverbatim
  427.   * @{
  428.   */
  429.  
  430. /**
  431.   * @brief  Enables dynamically FSMC_NORSRAM write operation.
  432.   * @param  Device Pointer to NORSRAM device instance
  433.   * @param  Bank NORSRAM bank number
  434.   * @retval HAL status
  435.   */
  436. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  437. {
  438.   /* Check the parameters */
  439.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  440.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  441.  
  442.   /* Enable write operation */
  443.   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  444.  
  445.   return HAL_OK;
  446. }
  447.  
  448. /**
  449.   * @brief  Disables dynamically FSMC_NORSRAM write operation.
  450.   * @param  Device Pointer to NORSRAM device instance
  451.   * @param  Bank NORSRAM bank number
  452.   * @retval HAL status
  453.   */
  454. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  455. {
  456.   /* Check the parameters */
  457.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  458.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  459.  
  460.   /* Disable write operation */
  461.   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  462.  
  463.   return HAL_OK;
  464. }
  465.  
  466. /**
  467.   * @}
  468.   */
  469.  
  470. /**
  471.   * @}
  472.   */
  473. #endif /* FSMC_BANK1 */
  474.  
  475. #if defined(FSMC_BANK3)
  476.  
  477. /** @defgroup FSMC_LL_Exported_Functions_NAND FSMC Low Layer NAND Exported Functions
  478.   * @brief    NAND Controller functions
  479.   *
  480.   @verbatim
  481.   ==============================================================================
  482.                     ##### How to use NAND device driver #####
  483.   ==============================================================================
  484.   [..]
  485.     This driver contains a set of APIs to interface with the FSMC NAND banks in order
  486.     to run the NAND external devices.
  487.  
  488.     (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
  489.     (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
  490.     (+) FSMC NAND bank common space timing configuration using the function
  491.         FSMC_NAND_CommonSpace_Timing_Init()
  492.     (+) FSMC NAND bank attribute space timing configuration using the function
  493.         FSMC_NAND_AttributeSpace_Timing_Init()
  494.     (+) FSMC NAND bank enable/disable ECC correction feature using the functions
  495.         FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
  496.     (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
  497.  
  498. @endverbatim
  499.   * @{
  500.   */
  501.  
  502. /** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
  503.   *  @brief    Initialization and Configuration functions
  504.   *
  505. @verbatim
  506.   ==============================================================================
  507.               ##### Initialization and de_initialization functions #####
  508.   ==============================================================================
  509.   [..]
  510.     This section provides functions allowing to:
  511.     (+) Initialize and configure the FSMC NAND interface
  512.     (+) De-initialize the FSMC NAND interface
  513.     (+) Configure the FSMC clock and associated GPIOs
  514.  
  515. @endverbatim
  516.   * @{
  517.   */
  518.  
  519. /**
  520.   * @brief  Initializes the FSMC_NAND device according to the specified
  521.   *         control parameters in the FSMC_NAND_HandleTypeDef
  522.   * @param  Device Pointer to NAND device instance
  523.   * @param  Init Pointer to NAND Initialization structure
  524.   * @retval HAL status
  525.   */
  526. HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
  527. {
  528.   /* Check the parameters */
  529.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  530.   assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
  531.   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
  532.   assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
  533.   assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
  534.   assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
  535.   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
  536.   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
  537.  
  538.   /* Set NAND device control parameters */
  539.   if (Init->NandBank == FSMC_NAND_BANK2)
  540.   {
  541.     /* NAND bank 2 registers configuration */
  542.     MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
  543.                                               FSMC_PCR_MEMORY_TYPE_NAND                               |
  544.                                               Init->MemoryDataWidth                                  |
  545.                                               Init->EccComputation                                   |
  546.                                               Init->ECCPageSize                                      |
  547.                                               ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos)  |
  548.                                               ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
  549.   }
  550.   else
  551.   {
  552.     /* NAND bank 3 registers configuration */
  553.     MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
  554.                                               FSMC_PCR_MEMORY_TYPE_NAND                               |
  555.                                               Init->MemoryDataWidth                                  |
  556.                                               Init->EccComputation                                   |
  557.                                               Init->ECCPageSize                                      |
  558.                                               ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos)  |
  559.                                               ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
  560.   }
  561.  
  562.   return HAL_OK;
  563. }
  564.  
  565. /**
  566.   * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
  567.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  568.   * @param  Device Pointer to NAND device instance
  569.   * @param  Timing Pointer to NAND timing structure
  570.   * @param  Bank NAND bank number
  571.   * @retval HAL status
  572.   */
  573. HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
  574.                                                    FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  575. {
  576.   /* Check the parameters */
  577.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  578.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  579.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  580.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  581.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  582.   assert_param(IS_FSMC_NAND_BANK(Bank));
  583.  
  584.   /* Set FSMC_NAND device timing parameters */
  585.   if (Bank == FSMC_NAND_BANK2)
  586.   {
  587.     /* NAND bank 2 registers configuration */
  588.     MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
  589.                                                 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
  590.                                                 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
  591.                                                 ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
  592.   }
  593.   else
  594.   {
  595.     /* NAND bank 3 registers configuration */
  596.     MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
  597.                                                 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
  598.                                                 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
  599.                                                 ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
  600.   }
  601.  
  602.   return HAL_OK;
  603. }
  604.  
  605. /**
  606.   * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
  607.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  608.   * @param  Device Pointer to NAND device instance
  609.   * @param  Timing Pointer to NAND timing structure
  610.   * @param  Bank NAND bank number
  611.   * @retval HAL status
  612.   */
  613. HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
  614.                                                       FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  615. {
  616.   /* Check the parameters */
  617.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  618.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  619.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  620.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  621.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  622.   assert_param(IS_FSMC_NAND_BANK(Bank));
  623.  
  624.   /* Set FSMC_NAND device timing parameters */
  625.   if (Bank == FSMC_NAND_BANK2)
  626.   {
  627.     /* NAND bank 2 registers configuration */
  628.     MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
  629.                                                 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
  630.                                                 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
  631.                                                 ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  632.   }
  633.   else
  634.   {
  635.     /* NAND bank 3 registers configuration */
  636.     MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
  637.                                                 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
  638.                                                 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
  639.                                                 ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  640.   }
  641.  
  642.   return HAL_OK;
  643. }
  644.  
  645. /**
  646.   * @brief  DeInitializes the FSMC_NAND device
  647.   * @param  Device Pointer to NAND device instance
  648.   * @param  Bank NAND bank number
  649.   * @retval HAL status
  650.   */
  651. HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  652. {
  653.   /* Check the parameters */
  654.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  655.   assert_param(IS_FSMC_NAND_BANK(Bank));
  656.  
  657.   /* Disable the NAND Bank */
  658.   __FSMC_NAND_DISABLE(Device, Bank);
  659.  
  660.   /* De-initialize the NAND Bank */
  661.   if (Bank == FSMC_NAND_BANK2)
  662.   {
  663.     /* Set the FSMC_NAND_BANK2 registers to their reset values */
  664.     WRITE_REG(Device->PCR2,  0x00000018U);
  665.     WRITE_REG(Device->SR2,   0x00000040U);
  666.     WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
  667.     WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
  668.   }
  669.   /* FSMC_Bank3_NAND */
  670.   else
  671.   {
  672.     /* Set the FSMC_NAND_BANK3 registers to their reset values */
  673.     WRITE_REG(Device->PCR3,  0x00000018U);
  674.     WRITE_REG(Device->SR3,   0x00000040U);
  675.     WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
  676.     WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
  677.   }
  678.  
  679.   return HAL_OK;
  680. }
  681.  
  682. /**
  683.   * @}
  684.   */
  685.  
  686. /** @defgroup HAL_FSMC_NAND_Group2 Peripheral Control functions
  687.   *  @brief   management functions
  688.   *
  689. @verbatim
  690.   ==============================================================================
  691.                        ##### FSMC_NAND Control functions #####
  692.   ==============================================================================
  693.   [..]
  694.     This subsection provides a set of functions allowing to control dynamically
  695.     the FSMC NAND interface.
  696.  
  697. @endverbatim
  698.   * @{
  699.   */
  700.  
  701.  
  702. /**
  703.   * @brief  Enables dynamically FSMC_NAND ECC feature.
  704.   * @param  Device Pointer to NAND device instance
  705.   * @param  Bank NAND bank number
  706.   * @retval HAL status
  707.   */
  708. HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  709. {
  710.   /* Check the parameters */
  711.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  712.   assert_param(IS_FSMC_NAND_BANK(Bank));
  713.  
  714.   /* Enable ECC feature */
  715.   if (Bank == FSMC_NAND_BANK2)
  716.   {
  717.     SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
  718.   }
  719.   else
  720.   {
  721.     SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
  722.   }
  723.  
  724.   return HAL_OK;
  725. }
  726.  
  727.  
  728. /**
  729.   * @brief  Disables dynamically FSMC_NAND ECC feature.
  730.   * @param  Device Pointer to NAND device instance
  731.   * @param  Bank NAND bank number
  732.   * @retval HAL status
  733.   */
  734. HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  735. {
  736.   /* Check the parameters */
  737.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  738.   assert_param(IS_FSMC_NAND_BANK(Bank));
  739.  
  740.   /* Disable ECC feature */
  741.   if (Bank == FSMC_NAND_BANK2)
  742.   {
  743.     CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
  744.   }
  745.   else
  746.   {
  747.     CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
  748.   }
  749.  
  750.   return HAL_OK;
  751. }
  752.  
  753. /**
  754.   * @brief  Disables dynamically FSMC_NAND ECC feature.
  755.   * @param  Device Pointer to NAND device instance
  756.   * @param  ECCval Pointer to ECC value
  757.   * @param  Bank NAND bank number
  758.   * @param  Timeout Timeout wait value
  759.   * @retval HAL status
  760.   */
  761. HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
  762.                                   uint32_t Timeout)
  763. {
  764.   uint32_t tickstart;
  765.  
  766.   /* Check the parameters */
  767.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  768.   assert_param(IS_FSMC_NAND_BANK(Bank));
  769.  
  770.   /* Get tick */
  771.   tickstart = HAL_GetTick();
  772.  
  773.   /* Wait until FIFO is empty */
  774.   while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
  775.   {
  776.     /* Check for the Timeout */
  777.     if (Timeout != HAL_MAX_DELAY)
  778.     {
  779.       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
  780.       {
  781.         return HAL_TIMEOUT;
  782.       }
  783.     }
  784.   }
  785.  
  786.   if (Bank == FSMC_NAND_BANK2)
  787.   {
  788.     /* Get the ECCR2 register value */
  789.     *ECCval = (uint32_t)Device->ECCR2;
  790.   }
  791.   else
  792.   {
  793.     /* Get the ECCR3 register value */
  794.     *ECCval = (uint32_t)Device->ECCR3;
  795.   }
  796.  
  797.   return HAL_OK;
  798. }
  799.  
  800. /**
  801.   * @}
  802.   */
  803. #endif /* FSMC_BANK3 */
  804.  
  805. #if defined(FSMC_BANK4)
  806.  
  807. /** @addtogroup FSMC_LL_PCCARD
  808.   * @brief    PCCARD Controller functions
  809.   *
  810.   @verbatim
  811.   ==============================================================================
  812.                     ##### How to use PCCARD device driver #####
  813.   ==============================================================================
  814.   [..]
  815.     This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
  816.     to run the PCCARD/compact flash external devices.
  817.  
  818.     (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
  819.     (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
  820.     (+) FSMC PCCARD bank common space timing configuration using the function
  821.         FSMC_PCCARD_CommonSpace_Timing_Init()
  822.     (+) FSMC PCCARD bank attribute space timing configuration using the function
  823.         FSMC_PCCARD_AttributeSpace_Timing_Init()
  824.     (+) FSMC PCCARD bank IO space timing configuration using the function
  825.         FSMC_PCCARD_IOSpace_Timing_Init()
  826. @endverbatim
  827.   * @{
  828.   */
  829.  
  830. /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
  831.   *  @brief    Initialization and Configuration functions
  832.   *
  833. @verbatim
  834.   ==============================================================================
  835.               ##### Initialization and de_initialization functions #####
  836.   ==============================================================================
  837.   [..]
  838.     This section provides functions allowing to:
  839.     (+) Initialize and configure the FSMC PCCARD interface
  840.     (+) De-initialize the FSMC PCCARD interface
  841.     (+) Configure the FSMC clock and associated GPIOs
  842.  
  843. @endverbatim
  844.   * @{
  845.   */
  846.  
  847. /**
  848.   * @brief  Initializes the FSMC_PCCARD device according to the specified
  849.   *         control parameters in the FSMC_PCCARD_HandleTypeDef
  850.   * @param  Device Pointer to PCCARD device instance
  851.   * @param  Init Pointer to PCCARD Initialization structure
  852.   * @retval HAL status
  853.   */
  854. HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
  855. {
  856.   /* Check the parameters */
  857.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  858.   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
  859.   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
  860.   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
  861.  
  862.   /* Set FSMC_PCCARD device control parameters */
  863.   MODIFY_REG(Device->PCR4,
  864.              (FSMC_PCRx_PTYP                                          |
  865.               FSMC_PCRx_PWAITEN                                       |
  866.               FSMC_PCRx_PWID                                          |
  867.               FSMC_PCRx_TCLR                                          |
  868.               FSMC_PCRx_TAR),
  869.              (FSMC_PCR_MEMORY_TYPE_PCCARD                             |
  870.               Init->Waitfeature                                      |
  871.               FSMC_NAND_PCC_MEM_BUS_WIDTH_16                          |
  872.               (Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos)   |
  873.               (Init->TARSetupTime  << FSMC_PCRx_TAR_Pos)));
  874.  
  875.   return HAL_OK;
  876. }
  877.  
  878. /**
  879.   * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
  880.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  881.   * @param  Device Pointer to PCCARD device instance
  882.   * @param  Timing Pointer to PCCARD timing structure
  883.   * @retval HAL status
  884.   */
  885. HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
  886.                                                               FSMC_NAND_PCC_TimingTypeDef *Timing)
  887. {
  888.   /* Check the parameters */
  889.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  890.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  891.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  892.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  893.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  894.  
  895.   /* Set PCCARD timing parameters */
  896.   MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
  897.              (Timing->SetupTime                                              |
  898.               ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos)  |
  899.               ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos)  |
  900.               ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
  901.  
  902.   return HAL_OK;
  903. }
  904.  
  905. /**
  906.   * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
  907.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  908.   * @param  Device Pointer to PCCARD device instance
  909.   * @param  Timing Pointer to PCCARD timing structure
  910.   * @retval HAL status
  911.   */
  912. HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
  913.                                                                  FSMC_NAND_PCC_TimingTypeDef *Timing)
  914. {
  915.   /* Check the parameters */
  916.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  917.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  918.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  919.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  920.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  921.  
  922.   /* Set PCCARD timing parameters */
  923.   MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK,
  924.              (Timing->SetupTime                                              |
  925.               ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos)  |
  926.               ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos)  |
  927.               ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  928.  
  929.   return HAL_OK;
  930. }
  931.  
  932. /**
  933.   * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
  934.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  935.   * @param  Device Pointer to PCCARD device instance
  936.   * @param  Timing Pointer to PCCARD timing structure
  937.   * @retval HAL status
  938.   */
  939. HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
  940.                                                           FSMC_NAND_PCC_TimingTypeDef *Timing)
  941. {
  942.   /* Check the parameters */
  943.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  944.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  945.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  946.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  947.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  948.  
  949.   /* Set FSMC_PCCARD device timing parameters */
  950.   MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
  951.              (Timing->SetupTime                                           |
  952.               (Timing->WaitSetupTime   << FSMC_PIO4_IOWAIT4_Pos) |
  953.               (Timing->HoldSetupTime   << FSMC_PIO4_IOHOLD4_Pos) |
  954.               (Timing->HiZSetupTime    << FSMC_PIO4_IOHIZ4_Pos)));
  955.  
  956.   return HAL_OK;
  957. }
  958.  
  959. /**
  960.   * @brief  DeInitializes the FSMC_PCCARD device
  961.   * @param  Device Pointer to PCCARD device instance
  962.   * @retval HAL status
  963.   */
  964. HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
  965. {
  966.   /* Check the parameters */
  967.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  968.  
  969.   /* Disable the FSMC_PCCARD device */
  970.   __FSMC_PCCARD_DISABLE(Device);
  971.  
  972.   /* De-initialize the FSMC_PCCARD device */
  973.   Device->PCR4    = 0x00000018U;
  974.   Device->SR4     = 0x00000040U;
  975.   Device->PMEM4   = 0xFCFCFCFCU;
  976.   Device->PATT4   = 0xFCFCFCFCU;
  977.   Device->PIO4    = 0xFCFCFCFCU;
  978.  
  979.   return HAL_OK;
  980. }
  981.  
  982. /**
  983.   * @}
  984.   */
  985. #endif /* FSMC_BANK4 */
  986.  
  987.  
  988. /**
  989.   * @}
  990.   */
  991.  
  992. /**
  993.   * @}
  994.   */
  995.  
  996. #endif /* HAL_NOR_MODULE_ENABLED */
  997. /**
  998.   * @}
  999.   */
  1000. /**
  1001.   * @}
  1002.   */
  1003.  
  1004. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1005.