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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_fsmc.c
  4.   * @author  MCD Application Team
  5.   * @version V1.0.4
  6.   * @date    29-April-2016
  7.   * @brief   FSMC Low Layer HAL module driver.
  8.   *
  9.   *          This file provides firmware functions to manage the following
  10.   *          functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
  11.   *           + Initialization/de-initialization functions
  12.   *           + Peripheral Control functions
  13.   *           + Peripheral State functions
  14.   *
  15.   @verbatim
  16.   =============================================================================
  17.                         ##### FSMC peripheral features #####
  18.   =============================================================================
  19.     [..] The Flexible static memory controller (FSMC) includes following memory controllers:
  20.          (+) The NOR/PSRAM memory controller
  21.          (+) The PC Card memory controller
  22.          (+) The NAND memory controller
  23.              (PC Card and NAND controllers available only on STM32F101xE, STM32F103xE, STM32F101xG and STM32F103xG)
  24.  
  25.     [..] The FSMC functional block makes the interface with synchronous and asynchronous static
  26.          memories and 16-bit PC memory cards. Its main purposes are:
  27.          (+) to translate AHB transactions into the appropriate external device protocol.
  28.          (+) to meet the access time requirements of the external memory devices.
  29.  
  30.     [..] All external memories share the addresses, data and control signals with the controller.
  31.          Each external device is accessed by means of a unique Chip Select. The FSMC performs
  32.          only one access at a time to an external device.
  33.          The main features of the FSMC controller are the following:
  34.           (+) Interface with static-memory mapped devices including:
  35.              (++) Static random access memory (SRAM).
  36.              (++) NOR Flash memory.
  37.              (++) PSRAM (4 memory banks).
  38.              (++) 16-bit PC Card compatible devices
  39.              (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  40.                 data
  41.           (+) Independent Chip Select control for each memory bank
  42.           (+) Independent configuration for each memory bank
  43.  
  44.   @endverbatim
  45.   ******************************************************************************
  46.   * @attention
  47.   *
  48.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  49.   *
  50.   * Redistribution and use in source and binary forms, with or without modification,
  51.   * are permitted provided that the following conditions are met:
  52.   *   1. Redistributions of source code must retain the above copyright notice,
  53.   *      this list of conditions and the following disclaimer.
  54.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  55.   *      this list of conditions and the following disclaimer in the documentation
  56.   *      and/or other materials provided with the distribution.
  57.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  58.   *      may be used to endorse or promote products derived from this software
  59.   *      without specific prior written permission.
  60.   *
  61.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  62.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  63.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  64.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  65.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  66.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  67.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  68.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  69.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  70.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  71.   *
  72.   ******************************************************************************
  73.   */
  74.  
  75. /* Includes ------------------------------------------------------------------*/
  76. #include "stm32f1xx_hal.h"
  77.  
  78. /** @addtogroup STM32F1xx_HAL_Driver
  79.   * @{
  80.   */
  81.  
  82. #if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
  83.  
  84. #if defined(FSMC_BANK1)
  85.  
  86. /** @defgroup FSMC_LL FSMC Low Layer
  87.   * @brief FSMC driver modules
  88.   * @{
  89.   */
  90.  
  91. /* Private typedef -----------------------------------------------------------*/
  92. /* Private define ------------------------------------------------------------*/
  93. /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
  94.   * @{
  95.   */
  96.  
  97. /* ----------------------- FSMC registers bit mask --------------------------- */
  98. /* --- PCR Register ---*/
  99. /* PCR register clear mask */
  100. #define PCR_CLEAR_MASK    ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN  | \
  101.                                       FSMC_PCRx_PTYP    | FSMC_PCRx_PWID   | \
  102.                                       FSMC_PCRx_ECCEN   | FSMC_PCRx_TCLR   | \
  103.                                       FSMC_PCRx_TAR     | FSMC_PCRx_ECCPS))
  104.  
  105. /* --- SR Register ---*/
  106. /* SR register clear mask */
  107. #define SR_CLEAR_MASK     ((uint32_t)(FSMC_SRx_IRS | FSMC_SRx_ILS | FSMC_SRx_IFS | \
  108.                                       FSMC_SRx_IREN | FSMC_SRx_ILEN | FSMC_SRx_IFEN))
  109.  
  110. /* --- PMEM Register ---*/
  111. /* PMEM register clear mask */
  112. #define PMEM_CLEAR_MASK   ((uint32_t)(FSMC_PMEMx_MEMSETx  | FSMC_PMEMx_MEMWAITx |\
  113.                                       FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx))
  114.  
  115. /* --- PATT Register ---*/
  116. /* PATT register clear mask */
  117. #define PATT_CLEAR_MASK   ((uint32_t)(FSMC_PATTx_ATTSETx  | FSMC_PATTx_ATTWAITx |\
  118.                                       FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx))
  119.  
  120. /* --- BCR Register ---*/
  121. /* BCR register clear mask */
  122. #define BCR_CLEAR_MASK                 ((uint32_t)(FSMC_BCRx_FACCEN  | FSMC_BCRx_MUXEN     | \
  123.                                                    FSMC_BCRx_MTYP    | FSMC_BCRx_MWID      | \
  124.                                                    FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL   | \
  125.                                                    FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG   | \
  126.                                                    FSMC_BCRx_WREN    | FSMC_BCRx_WAITEN    | \
  127.                                                    FSMC_BCRx_EXTMOD  | FSMC_BCRx_ASYNCWAIT | \
  128.                                                    FSMC_BCRx_CBURSTRW))
  129. /* --- BTR Register ---*/
  130. /* BTR register clear mask */
  131. #define BTR_CLEAR_MASK                 ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD  |\
  132.                                                    FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
  133.                                                    FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT  |\
  134.                                                    FSMC_BTRx_ACCMOD))
  135.  
  136. /* --- BWTR Register ---*/
  137. /* BWTR register clear mask */
  138. #if   (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
  139. #define BWTR_CLEAR_MASK                ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \
  140.                                                    FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \
  141.                                                    FSMC_BWTRx_BUSTURN))
  142. #else
  143. #define BWTR_CLEAR_MASK                ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \
  144.                                                    FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \
  145.                                                    FSMC_BWTRx_CLKDIV  | FSMC_BWTRx_DATLAT))
  146. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  147.  
  148. /* --- PIO4 Register ---*/
  149. /* PIO4 register clear mask */
  150. #define PIO4_CLEAR_MASK   ((uint32_t)(FSMC_PIO4_IOSET4    | FSMC_PIO4_IOWAIT4   | \
  151.                                       FSMC_PIO4_IOHOLD4   | FSMC_PIO4_IOHIZ4))
  152. /**
  153.   * @}
  154.   */
  155.  
  156. /* Private macro -------------------------------------------------------------*/
  157. /** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros
  158.   * @{
  159.   */
  160.  
  161. /**
  162.   * @}
  163.   */
  164.  
  165. /* Private variables ---------------------------------------------------------*/
  166. /* Private function prototypes -----------------------------------------------*/
  167. /* Exported functions --------------------------------------------------------*/
  168.  
  169. /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
  170.   * @{
  171.   */
  172.  
  173. /** @defgroup FSMC_NORSRAM FSMC NORSRAM Controller functions
  174.   * @brief    NORSRAM Controller functions
  175.   *
  176.   @verbatim
  177.   ==============================================================================
  178.                    ##### How to use NORSRAM device driver #####
  179.   ==============================================================================
  180.  
  181.   [..]
  182.     This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
  183.     to run the NORSRAM external devices.
  184.  
  185.     (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
  186.     (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
  187.     (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
  188.     (+) FSMC NORSRAM bank extended timing configuration using the function
  189.         FSMC_NORSRAM_Extended_Timing_Init()
  190.     (+) FSMC NORSRAM bank enable/disable write operation using the functions
  191.         FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
  192.  
  193.  
  194. @endverbatim
  195.   * @{
  196.   */
  197.  
  198. /** @defgroup FSMC_NORSRAM_Group1 Initialization/de-initialization functions
  199.   * @brief    Initialization and Configuration functions
  200.   *
  201.   @verbatim
  202.   ==============================================================================
  203.               ##### Initialization and de_initialization functions #####
  204.   ==============================================================================
  205.   [..]
  206.     This section provides functions allowing to:
  207.     (+) Initialize and configure the FSMC NORSRAM interface
  208.     (+) De-initialize the FSMC NORSRAM interface
  209.     (+) Configure the FSMC clock and associated GPIOs
  210.  
  211. @endverbatim
  212.   * @{
  213.   */
  214.  
  215. /**
  216.   * @brief  Initialize the FSMC_NORSRAM device according to the specified
  217.   *         control parameters in the FSMC_NORSRAM_InitTypeDef
  218.   * @param  Device: Pointer to NORSRAM device instance
  219.   * @param  Init: Pointer to NORSRAM Initialization structure
  220.   * @retval HAL status
  221.   */
  222. HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init)
  223. {
  224.   /* Check the parameters */
  225.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  226.   assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
  227.   assert_param(IS_FSMC_MUX(Init->DataAddressMux));
  228.   assert_param(IS_FSMC_MEMORY(Init->MemoryType));
  229.   assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
  230.   assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
  231.   assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
  232.   assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
  233.   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
  234.   assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
  235.   assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
  236.   assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
  237.   assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
  238.   assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
  239.  
  240.   /* Disable NORSRAM Device */
  241.   __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
  242.  
  243.   /* Set NORSRAM device control parameters */
  244.   if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
  245.   {
  246.     MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_ENABLE
  247.                | Init->DataAddressMux
  248.                | Init->MemoryType
  249.                | Init->MemoryDataWidth
  250.                | Init->BurstAccessMode
  251.                | Init->WaitSignalPolarity
  252.                | Init->WrapMode
  253.                | Init->WaitSignalActive
  254.                | Init->WriteOperation
  255.                | Init->WaitSignal
  256.                | Init->ExtendedMode
  257.                | Init->AsynchronousWait
  258.                | Init->WriteBurst
  259.                                                                      )
  260.               );
  261.   }
  262.   else
  263.   {
  264.     MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_DISABLE
  265.                | Init->DataAddressMux
  266.                | Init->MemoryType
  267.                | Init->MemoryDataWidth
  268.                | Init->BurstAccessMode
  269.                | Init->WaitSignalPolarity
  270.                | Init->WrapMode
  271.                | Init->WaitSignalActive
  272.                | Init->WriteOperation
  273.                | Init->WaitSignal
  274.                | Init->ExtendedMode
  275.                | Init->AsynchronousWait
  276.                | Init->WriteBurst
  277.                                                                      )
  278.               );
  279.   }
  280.  
  281.   return HAL_OK;
  282. }
  283.  
  284.  
  285. /**
  286.   * @brief  DeInitialize the FSMC_NORSRAM peripheral
  287.   * @param  Device: Pointer to NORSRAM device instance
  288.   * @param  ExDevice: Pointer to NORSRAM extended mode device instance
  289.   * @param  Bank: NORSRAM bank number
  290.   * @retval HAL status
  291.   */
  292. HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
  293. {
  294.   /* Check the parameters */
  295.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  296.   assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
  297.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  298.  
  299.   /* Disable the FSMC_NORSRAM device */
  300.   __FSMC_NORSRAM_DISABLE(Device, Bank);
  301.  
  302.   /* De-initialize the FSMC_NORSRAM device */
  303.   /* FSMC_NORSRAM_BANK1 */
  304.   if (Bank == FSMC_NORSRAM_BANK1)
  305.   {
  306.     Device->BTCR[Bank] = 0x000030DB;
  307.   }
  308.   /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
  309.   else
  310.   {
  311.     Device->BTCR[Bank] = 0x000030D2;
  312.   }
  313.  
  314.   Device->BTCR[Bank + 1] = 0x0FFFFFFF;
  315.   ExDevice->BWTR[Bank]   = 0x0FFFFFFF;
  316.  
  317.   return HAL_OK;
  318. }
  319.  
  320.  
  321. /**
  322.   * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
  323.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  324.   * @param  Device: Pointer to NORSRAM device instance
  325.   * @param  Timing: Pointer to NORSRAM Timing structure
  326.   * @param  Bank: NORSRAM bank number
  327.   * @retval HAL status
  328.   */
  329. HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
  330. {
  331.   /* Check the parameters */
  332.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  333.   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  334.   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  335.   assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  336.   assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  337.   assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  338.   assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  339.   assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  340.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  341.  
  342.   /* Set FSMC_NORSRAM device timing parameters */
  343.   MODIFY_REG(Device->BTCR[Bank + 1],                                                    \
  344.              BTR_CLEAR_MASK,                                                                     \
  345.              (uint32_t)(Timing->AddressSetupTime                                               | \
  346.                         ((Timing->AddressHoldTime)        << POSITION_VAL(FSMC_BTRx_ADDHLD))        | \
  347.                         ((Timing->DataSetupTime)          << POSITION_VAL(FSMC_BTRx_DATAST))        | \
  348.                         ((Timing->BusTurnAroundDuration)  << POSITION_VAL(FSMC_BTRx_BUSTURN))       | \
  349.                         (((Timing->CLKDivision) - 1)        << POSITION_VAL(FSMC_BTRx_CLKDIV))        | \
  350.                         (((Timing->DataLatency) - 2)        << POSITION_VAL(FSMC_BTRx_DATLAT))        | \
  351.                         (Timing->AccessMode)));
  352.  
  353.   return HAL_OK;
  354. }
  355.  
  356. /**
  357.   * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
  358.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  359.   * @param  Device: Pointer to NORSRAM device instance
  360.   * @param  Timing: Pointer to NORSRAM Timing structure
  361.   * @param  Bank: NORSRAM bank number
  362.   * @param  ExtendedMode: FSMC Extended Mode
  363.   *          This parameter can be one of the following values:
  364.   *            @arg FSMC_EXTENDED_MODE_DISABLE
  365.   *            @arg FSMC_EXTENDED_MODE_ENABLE
  366.   * @retval HAL status
  367.   */
  368. HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
  369. {
  370.   /* Check the parameters */
  371.   assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
  372.  
  373.   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  374.   if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
  375.   {
  376.     /* Check the parameters */
  377.     assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
  378.     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  379.     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  380.     assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  381. #if   (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
  382.     assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  383. #else
  384.     assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  385.     assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  386. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  387.     assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  388.     assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  389.  
  390.     /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  391. #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
  392.     MODIFY_REG(Device->BWTR[Bank],                                                  \
  393.                BWTR_CLEAR_MASK,                                                              \
  394.                (uint32_t)(Timing->AddressSetupTime                                         | \
  395.                           ((Timing->AddressHoldTime)        << POSITION_VAL(FSMC_BWTRx_ADDHLD)) | \
  396.                           ((Timing->DataSetupTime)          << POSITION_VAL(FSMC_BWTRx_DATAST)) | \
  397.                           Timing->AccessMode                                                          | \
  398.                           ((Timing->BusTurnAroundDuration)  << POSITION_VAL(FSMC_BWTRx_BUSTURN))));
  399. #else
  400.     MODIFY_REG(Device->BWTR[Bank],                                                  \
  401.                BWTR_CLEAR_MASK,                                                              \
  402.                (uint32_t)(Timing->AddressSetupTime                                         | \
  403.                           ((Timing->AddressHoldTime)  << POSITION_VAL(FSMC_BWTRx_ADDHLD))       | \
  404.                           ((Timing->DataSetupTime)    << POSITION_VAL(FSMC_BWTRx_DATAST))       | \
  405.                           Timing->AccessMode                                                          | \
  406.                           (((Timing->CLKDivision) - 1)  << POSITION_VAL(FSMC_BTRx_CLKDIV))        | \
  407.                           (((Timing->DataLatency) - 2)  << POSITION_VAL(FSMC_BWTRx_DATLAT))));
  408. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  409.   }
  410.   else
  411.   {
  412.     Device->BWTR[Bank] = 0x0FFFFFFF;
  413.   }
  414.  
  415.   return HAL_OK;
  416. }
  417.  
  418.  
  419. /**
  420.   * @}
  421.   */
  422.  
  423.  
  424. /** @defgroup FSMC_NORSRAM_Group2 Control functions
  425.  *  @brief   management functions
  426.  *
  427. @verbatim
  428.   ==============================================================================
  429.                       ##### FSMC_NORSRAM Control functions #####
  430.   ==============================================================================
  431.   [..]
  432.     This subsection provides a set of functions allowing to control dynamically
  433.     the FSMC NORSRAM interface.
  434.  
  435. @endverbatim
  436.   * @{
  437.   */
  438.  
  439. /**
  440.   * @brief  Enables dynamically FSMC_NORSRAM write operation.
  441.   * @param  Device: Pointer to NORSRAM device instance
  442.   * @param  Bank: NORSRAM bank number
  443.   * @retval HAL status
  444.   */
  445. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  446. {
  447.   /* Check the parameters */
  448.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  449.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  450.  
  451.   /* Enable write operation */
  452.   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  453.  
  454.   return HAL_OK;
  455. }
  456.  
  457. /**
  458.   * @brief  Disables dynamically FSMC_NORSRAM write operation.
  459.   * @param  Device: Pointer to NORSRAM device instance
  460.   * @param  Bank: NORSRAM bank number
  461.   * @retval HAL status
  462.   */
  463. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  464. {
  465.   /* Check the parameters */
  466.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  467.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  468.  
  469.   /* Disable write operation */
  470.   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  471.  
  472.   return HAL_OK;
  473. }
  474.  
  475. /**
  476.   * @}
  477.   */
  478.  
  479. /**
  480.   * @}
  481.   */
  482. #if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
  483. /** @defgroup FSMC_NAND FSMC NAND Controller functions
  484.   * @brief    NAND Controller functions
  485.   *
  486.   @verbatim
  487.   ==============================================================================
  488.                     ##### How to use NAND device driver #####
  489.   ==============================================================================
  490.   [..]
  491.     This driver contains a set of APIs to interface with the FSMC NAND banks in order
  492.     to run the NAND external devices.
  493.  
  494.     (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
  495.     (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
  496.     (+) FSMC NAND bank common space timing configuration using the function
  497.         FSMC_NAND_CommonSpace_Timing_Init()
  498.     (+) FSMC NAND bank attribute space timing configuration using the function
  499.         FSMC_NAND_AttributeSpace_Timing_Init()
  500.     (+) FSMC NAND bank enable/disable ECC correction feature using the functions
  501.         FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
  502.     (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
  503.  
  504. @endverbatim
  505.   * @{
  506.   */
  507.  
  508. /** @defgroup FSMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
  509.  *  @brief    Initialization and Configuration functions
  510.  *
  511. @verbatim
  512.   ==============================================================================
  513.               ##### Initialization and de_initialization functions #####
  514.   ==============================================================================
  515.   [..]
  516.     This section provides functions allowing to:
  517.     (+) Initialize and configure the FSMC NAND interface
  518.     (+) De-initialize the FSMC NAND interface
  519.     (+) Configure the FSMC clock and associated GPIOs
  520.  
  521. @endverbatim
  522.   * @{
  523.   */
  524.  
  525. /**
  526.   * @brief  Initializes the FSMC_NAND device according to the specified
  527.   *         control parameters in the FSMC_NAND_HandleTypeDef
  528.   * @param  Device: Pointer to NAND device instance
  529.   * @param  Init: Pointer to NAND Initialization structure
  530.   * @retval HAL status
  531.   */
  532. HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
  533. {
  534.   /* Check the parameters */
  535.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  536.   assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
  537.   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
  538.   assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
  539.   assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
  540.   assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
  541.   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
  542.   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
  543.  
  544.   /* Set NAND device control parameters */
  545.   if (Init->NandBank == FSMC_NAND_BANK2)
  546.   {
  547.     /* NAND bank 2 registers configuration */
  548.     MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                  | \
  549.                                               FSMC_PCR_MEMORY_TYPE_NAND                                     | \
  550.                                               Init->MemoryDataWidth                                         | \
  551.                                               Init->EccComputation                                          | \
  552.                                               Init->ECCPageSize                                             | \
  553.                                               ((Init->TCLRSetupTime) << POSITION_VAL(FSMC_PCRx_TCLR))       | \
  554.                                               ((Init->TARSetupTime) << POSITION_VAL(FSMC_PCRx_TAR))));
  555.   }
  556.   else
  557.   {
  558.     /* NAND bank 3 registers configuration */
  559.     MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                  | \
  560.                                               FSMC_PCR_MEMORY_TYPE_NAND                                     | \
  561.                                               Init->MemoryDataWidth                                         | \
  562.                                               Init->EccComputation                                          | \
  563.                                               Init->ECCPageSize                                             | \
  564.                                               ((Init->TCLRSetupTime) << POSITION_VAL(FSMC_PCRx_TCLR))       | \
  565.                                               ((Init->TARSetupTime) << POSITION_VAL(FSMC_PCRx_TAR))));
  566.   }
  567.  
  568.   return HAL_OK;
  569.  
  570. }
  571.  
  572. /**
  573.   * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
  574.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  575.   * @param  Device: Pointer to NAND device instance
  576.   * @param  Timing: Pointer to NAND timing structure
  577.   * @param  Bank: NAND bank number
  578.   * @retval HAL status
  579.   */
  580. HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  581. {
  582.   /* Check the parameters */
  583.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  584.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  585.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  586.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  587.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  588.   assert_param(IS_FSMC_NAND_BANK(Bank));
  589.  
  590.   /* Set FMC_NAND device timing parameters */
  591.   if (Bank == FSMC_NAND_BANK2)
  592.   {
  593.     /* NAND bank 2 registers configuration */
  594.     MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                      | \
  595.                                                 ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx))      | \
  596.                                                 ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx))      | \
  597.                                                 ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx))));
  598.   }
  599.   else
  600.   {
  601.     /* NAND bank 3 registers configuration */
  602.     MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                      | \
  603.                                                 ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx))      | \
  604.                                                 ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx))      | \
  605.                                                 ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx))));
  606.   }
  607.  
  608.   return HAL_OK;
  609. }
  610.  
  611. /**
  612.   * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
  613.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  614.   * @param  Device: Pointer to NAND device instance
  615.   * @param  Timing: Pointer to NAND timing structure
  616.   * @param  Bank: NAND bank number
  617.   * @retval HAL status
  618.   */
  619. HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  620. {
  621.   /* Check the parameters */
  622.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  623.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  624.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  625.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  626.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  627.   assert_param(IS_FSMC_NAND_BANK(Bank));
  628.  
  629.   /* Set FMC_NAND device timing parameters */
  630.   if (Bank == FSMC_NAND_BANK2)
  631.   {
  632.     /* NAND bank 2 registers configuration */
  633.     MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                       | \
  634.                                                 ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx))       | \
  635.                                                 ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx))       | \
  636.                                                 ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx))));
  637.   }
  638.   else
  639.   {
  640.     /* NAND bank 3 registers configuration */
  641.     MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                       | \
  642.                                                 ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx))       | \
  643.                                                 ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx))       | \
  644.                                                 ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx))));
  645.   }
  646.  
  647.   return HAL_OK;
  648. }
  649.  
  650.  
  651. /**
  652.   * @brief  DeInitializes the FSMC_NAND device
  653.   * @param  Device: Pointer to NAND device instance
  654.   * @param  Bank: NAND bank number
  655.   * @retval HAL status
  656.   */
  657. HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  658. {
  659.   /* Check the parameters */
  660.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  661.   assert_param(IS_FSMC_NAND_BANK(Bank));
  662.  
  663.   /* Disable the NAND Bank */
  664.   __FSMC_NAND_DISABLE(Device, Bank);
  665.  
  666.   /* De-initialize the NAND Bank */
  667.   if (Bank == FSMC_NAND_BANK2)
  668.   {
  669.     /* Set the FSMC_NAND_BANK2 registers to their reset values */
  670.     WRITE_REG(Device->PCR2,  0x00000018);
  671.     WRITE_REG(Device->SR2,   0x00000040);
  672.     WRITE_REG(Device->PMEM2, 0xFCFCFCFC);
  673.     WRITE_REG(Device->PATT2, 0xFCFCFCFC);
  674.   }
  675.   /* FSMC_Bank3_NAND */
  676.   else
  677.   {
  678.     /* Set the FSMC_NAND_BANK3 registers to their reset values */
  679.     WRITE_REG(Device->PCR3,  0x00000018);
  680.     WRITE_REG(Device->SR3,   0x00000040);
  681.     WRITE_REG(Device->PMEM3, 0xFCFCFCFC);
  682.     WRITE_REG(Device->PATT3, 0xFCFCFCFC);
  683.   }
  684.  
  685.   return HAL_OK;
  686. }
  687.  
  688. /**
  689.   * @}
  690.   */
  691.  
  692.  
  693. /** @defgroup FSMC_NAND_Exported_Functions_Group2 Peripheral Control functions
  694.  *  @brief   management functions
  695.  *
  696. @verbatim
  697.   ==============================================================================
  698.                        ##### FSMC_NAND Control functions #####
  699.   ==============================================================================
  700.   [..]
  701.     This subsection provides a set of functions allowing to control dynamically
  702.     the FSMC NAND interface.
  703.  
  704. @endverbatim
  705.   * @{
  706.   */
  707.  
  708.  
  709. /**
  710.   * @brief  Enables dynamically FSMC_NAND ECC feature.
  711.   * @param  Device: Pointer to NAND device instance
  712.   * @param  Bank: NAND bank number
  713.   * @retval HAL status
  714.   */
  715. HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  716. {
  717.   /* Check the parameters */
  718.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  719.   assert_param(IS_FSMC_NAND_BANK(Bank));
  720.  
  721.   /* Enable ECC feature */
  722.   if (Bank == FSMC_NAND_BANK2)
  723.   {
  724.     SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
  725.   }
  726.   else
  727.   {
  728.     SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
  729.   }
  730.  
  731.   return HAL_OK;
  732. }
  733.  
  734.  
  735. /**
  736.   * @brief  Disables dynamically FSMC_NAND ECC feature.
  737.   * @param  Device: Pointer to NAND device instance
  738.   * @param  Bank: NAND bank number
  739.   * @retval HAL status
  740.   */
  741. HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  742. {
  743.   /* Check the parameters */
  744.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  745.   assert_param(IS_FSMC_NAND_BANK(Bank));
  746.  
  747.   /* Disable ECC feature */
  748.   if (Bank == FSMC_NAND_BANK2)
  749.   {
  750.     CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
  751.   }
  752.   else
  753.   {
  754.     CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
  755.   }
  756.  
  757.   return HAL_OK;
  758. }
  759.  
  760. /**
  761.   * @brief  Disables dynamically FSMC_NAND ECC feature.
  762.   * @param  Device: Pointer to NAND device instance
  763.   * @param  ECCval: Pointer to ECC value
  764.   * @param  Bank: NAND bank number
  765.   * @param  Timeout: Timeout wait value
  766.   * @retval HAL status
  767.   */
  768. HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
  769. {
  770.   uint32_t tickstart = 0;
  771.  
  772.   /* Check the parameters */
  773.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  774.   assert_param(IS_FSMC_NAND_BANK(Bank));
  775.  
  776.   /* Get tick */
  777.   tickstart = HAL_GetTick();
  778.  
  779.   /* Wait untill FIFO is empty */
  780.   while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
  781.   {
  782.     /* Check for the Timeout */
  783.     if (Timeout != HAL_MAX_DELAY)
  784.     {
  785.       if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
  786.       {
  787.         return HAL_TIMEOUT;
  788.       }
  789.     }
  790.   }
  791.  
  792.   if (Bank == FSMC_NAND_BANK2)
  793.   {
  794.     /* Get the ECCR2 register value */
  795.     *ECCval = (uint32_t)Device->ECCR2;
  796.   }
  797.   else
  798.   {
  799.     /* Get the ECCR3 register value */
  800.     *ECCval = (uint32_t)Device->ECCR3;
  801.   }
  802.  
  803.   return HAL_OK;
  804. }
  805.  
  806. /**
  807.   * @}
  808.   */
  809.  
  810. /**
  811.   * @}
  812.   */
  813.  
  814. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  815. #if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
  816. /** @defgroup FSMC_PCCARD FSMC PCCARD Controller functions
  817.   * @brief    PCCARD Controller functions
  818.   *
  819.   @verbatim
  820.   ==============================================================================
  821.                     ##### How to use PCCARD device driver #####
  822.   ==============================================================================
  823.   [..]
  824.     This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
  825.     to run the PCCARD/compact flash external devices.
  826.  
  827.     (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
  828.     (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
  829.     (+) FSMC PCCARD bank common space timing configuration using the function
  830.         FSMC_PCCARD_CommonSpace_Timing_Init()
  831.     (+) FSMC PCCARD bank attribute space timing configuration using the function
  832.         FSMC_PCCARD_AttributeSpace_Timing_Init()
  833.     (+) FSMC PCCARD bank IO space timing configuration using the function
  834.         FSMC_PCCARD_IOSpace_Timing_Init()
  835.  
  836.  
  837. @endverbatim
  838.   * @{
  839.   */
  840.  
  841. /** @defgroup FSMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
  842.  *  @brief    Initialization and Configuration functions
  843.  *
  844. @verbatim
  845.   ==============================================================================
  846.               ##### Initialization and de_initialization functions #####
  847.   ==============================================================================
  848.   [..]
  849.     This section provides functions allowing to:
  850.     (+) Initialize and configure the FSMC PCCARD interface
  851.     (+) De-initialize the FSMC PCCARD interface
  852.     (+) Configure the FSMC clock and associated GPIOs
  853.  
  854. @endverbatim
  855.   * @{
  856.   */
  857.  
  858. /**
  859.   * @brief  Initializes the FSMC_PCCARD device according to the specified
  860.   *         control parameters in the FSMC_PCCARD_HandleTypeDef
  861.   * @param  Device: Pointer to PCCARD device instance
  862.   * @param  Init: Pointer to PCCARD Initialization structure
  863.   * @retval HAL status
  864.   */
  865. HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
  866. {
  867.   /* Check the parameters */
  868.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  869.   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
  870.   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
  871.   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
  872.  
  873.   /* Set FSMC_PCCARD device control parameters */
  874.   MODIFY_REG(Device->PCR4,                                  \
  875.              (FSMC_PCRx_PTYP | FSMC_PCRx_PWAITEN |  FSMC_PCRx_PWID  |
  876.               FSMC_PCRx_TCLR | FSMC_PCRx_TAR), \
  877.              (FSMC_PCR_MEMORY_TYPE_PCCARD                          | \
  878.               Init->Waitfeature                                     | \
  879.               FSMC_NAND_PCC_MEM_BUS_WIDTH_16                        | \
  880.               (Init->TCLRSetupTime << POSITION_VAL(FSMC_PCRx_TCLR)) | \
  881.               (Init->TARSetupTime << POSITION_VAL(FSMC_PCRx_TAR))));
  882.  
  883.   return HAL_OK;
  884.  
  885. }
  886.  
  887. /**
  888.   * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
  889.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  890.   * @param  Device: Pointer to PCCARD device instance
  891.   * @param  Timing: Pointer to PCCARD timing structure
  892.   * @retval HAL status
  893.   */
  894. HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
  895. {
  896.   /* Check the parameters */
  897.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  898.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  899.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  900.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  901.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  902.  
  903.   /* Set PCCARD timing parameters */
  904.   MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,                            \
  905.              (Timing->SetupTime                                              | \
  906.               ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx))  | \
  907.               ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx))  | \
  908.               ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx))));
  909.  
  910.   return HAL_OK;
  911. }
  912.  
  913. /**
  914.   * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
  915.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  916.   * @param  Device: Pointer to PCCARD device instance
  917.   * @param  Timing: Pointer to PCCARD timing structure
  918.   * @retval HAL status
  919.   */
  920. HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
  921. {
  922.   /* Check the parameters */
  923.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  924.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  925.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  926.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  927.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  928.  
  929.   /* Set PCCARD timing parameters */
  930.   MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK,                          \
  931.              (Timing->SetupTime                                              | \
  932.               ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx))  | \
  933.               ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx))   | \
  934.               ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx))));
  935.  
  936.   return HAL_OK;
  937. }
  938.  
  939. /**
  940.   * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
  941.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  942.   * @param  Device: Pointer to PCCARD device instance
  943.   * @param  Timing: Pointer to PCCARD timing structure
  944.   * @retval HAL status
  945.   */
  946. HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
  947. {
  948.   /* Check the parameters */
  949.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  950.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  951.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  952.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  953.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  954.  
  955.   /* Set FSMC_PCCARD device timing parameters */
  956.   MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,                         \
  957.              (Timing->SetupTime                                            | \
  958.               (Timing->WaitSetupTime   << POSITION_VAL(FSMC_PIO4_IOWAIT4)) | \
  959.               (Timing->HoldSetupTime   << POSITION_VAL(FSMC_PIO4_IOHOLD4)) | \
  960.               (Timing->HiZSetupTime    << POSITION_VAL(FSMC_PIO4_IOHIZ4))));
  961.  
  962.   return HAL_OK;
  963. }
  964.  
  965. /**
  966.   * @brief  DeInitializes the FSMC_PCCARD device
  967.   * @param  Device: Pointer to PCCARD device instance
  968.   * @retval HAL status
  969.   */
  970. HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
  971. {
  972.   /* Check the parameters */
  973.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  974.  
  975.   /* Disable the FSMC_PCCARD device */
  976.   __FSMC_PCCARD_DISABLE(Device);
  977.  
  978.   /* De-initialize the FSMC_PCCARD device */
  979.   WRITE_REG(Device->PCR4,  0x00000018);
  980.   WRITE_REG(Device->SR4,   0x00000040);
  981.   WRITE_REG(Device->PMEM4, 0xFCFCFCFC);
  982.   WRITE_REG(Device->PATT4, 0xFCFCFCFC);
  983.   WRITE_REG(Device->PIO4,  0xFCFCFCFC);
  984.  
  985.   return HAL_OK;
  986. }
  987.  
  988. /**
  989.   * @}
  990.   */
  991.  
  992. /**
  993.   * @}
  994.   */
  995. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  996.  
  997. /**
  998.   * @}
  999.   */
  1000.  
  1001. /**
  1002.   * @}
  1003.   */
  1004.  
  1005. #endif /* FSMC_BANK1 */
  1006.  
  1007. #endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) */
  1008.  
  1009. /**
  1010.   * @}
  1011.   */
  1012.  
  1013. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1014.