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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_fsmc.c
  4.   * @author  MCD Application Team
  5.   * @brief   FSMC Low Layer HAL module driver.
  6.   *
  7.   *          This file provides firmware functions to manage the following
  8.   *          functionalities of the Flexible Memory Controller (FSMC) peripheral memories:
  9.   *           + Initialization/de-initialization functions
  10.   *           + Peripheral Control functions
  11.   *           + Peripheral State functions
  12.   *
  13.   ******************************************************************************
  14.   * @attention
  15.   *
  16.   * Copyright (c) 2016 STMicroelectronics.
  17.   * All rights reserved.
  18.   *
  19.   * This software is licensed under terms that can be found in the LICENSE file
  20.   * in the root directory of this software component.
  21.   * If no LICENSE file comes with this software, it is provided AS-IS.
  22.   *
  23.   ******************************************************************************
  24.   @verbatim
  25.   ==============================================================================
  26.                         ##### FSMC peripheral features #####
  27.   ==============================================================================
  28.   [..] The Flexible memory controller (FSMC) includes following memory controllers:
  29.        (+) The NOR/PSRAM memory controller
  30.        (+) The NAND/PC Card memory controller
  31.  
  32.   [..] The FSMC functional block makes the interface with synchronous and asynchronous static
  33.        memories and 16-bit PC memory cards. Its main purposes are:
  34.        (+) to translate AHB transactions into the appropriate external device protocol
  35.        (+) to meet the access time requirements of the external memory devices
  36.  
  37.   [..] All external memories share the addresses, data and control signals with the controller.
  38.        Each external device is accessed by means of a unique Chip Select. The FSMC performs
  39.        only one access at a time to an external device.
  40.        The main features of the FSMC controller are the following:
  41.         (+) Interface with static-memory mapped devices including:
  42.            (++) Static random access memory (SRAM)
  43.            (++) Read-only memory (ROM)
  44.            (++) NOR Flash memory/OneNAND Flash memory
  45.            (++) PSRAM (4 memory banks)
  46.            (++) 16-bit PC Card compatible devices
  47.            (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  48.                 data
  49.         (+) Independent Chip Select control for each memory bank
  50.         (+) Independent configuration for each memory bank
  51.  
  52.   @endverbatim
  53.   ******************************************************************************
  54.   */
  55.  
  56. /* Includes ------------------------------------------------------------------*/
  57. #include "stm32f1xx_hal.h"
  58.  
  59. /** @addtogroup STM32F1xx_HAL_Driver
  60.   * @{
  61.   */
  62. #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) \
  63.  || defined(HAL_SRAM_MODULE_ENABLED)
  64.  
  65. /** @defgroup FSMC_LL  FSMC Low Layer
  66.   * @brief FSMC driver modules
  67.   * @{
  68.   */
  69.  
  70. /* Private typedef -----------------------------------------------------------*/
  71. /* Private define ------------------------------------------------------------*/
  72.  
  73. /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
  74.   * @{
  75.   */
  76.  
  77. /* ----------------------- FSMC registers bit mask --------------------------- */
  78.  
  79. #if defined(FSMC_BANK1)
  80. /* --- BCR Register ---*/
  81. /* BCR register clear mask */
  82.  
  83. /* --- BTR Register ---*/
  84. /* BTR register clear mask */
  85. #define BTR_CLEAR_MASK    ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD  |\
  86.                                       FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
  87.                                       FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT  |\
  88.                                       FSMC_BTRx_ACCMOD))
  89.  
  90. /* --- BWTR Register ---*/
  91. /* BWTR register clear mask */
  92. #if defined(FSMC_BWTRx_BUSTURN)
  93. #define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD  |\
  94.                                       FSMC_BWTRx_DATAST | FSMC_BWTRx_BUSTURN |\
  95.                                       FSMC_BWTRx_ACCMOD))
  96. #else
  97. #define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD |\
  98.                                       FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD |\
  99.                                       FSMC_BWTRx_CLKDIV | FSMC_BWTRx_DATLAT))
  100. #endif /* FSMC_BWTRx_BUSTURN */
  101. #endif /* FSMC_BANK1 */
  102. #if defined(FSMC_BANK3)
  103.  
  104. /* --- PCR Register ---*/
  105. /* PCR register clear mask */
  106. #define PCR_CLEAR_MASK    ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN  | \
  107.                                       FSMC_PCRx_PTYP    | FSMC_PCRx_PWID   | \
  108.                                       FSMC_PCRx_ECCEN   | FSMC_PCRx_TCLR   | \
  109.                                       FSMC_PCRx_TAR     | FSMC_PCRx_ECCPS))
  110. /* --- PMEM Register ---*/
  111. /* PMEM register clear mask */
  112. #define PMEM_CLEAR_MASK   ((uint32_t)(FSMC_PMEMx_MEMSETx  | FSMC_PMEMx_MEMWAITx |\
  113.                                       FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx))
  114.  
  115. /* --- PATT Register ---*/
  116. /* PATT register clear mask */
  117. #define PATT_CLEAR_MASK   ((uint32_t)(FSMC_PATTx_ATTSETx  | FSMC_PATTx_ATTWAITx |\
  118.                                       FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx))
  119.  
  120. #endif /* FSMC_BANK3 */
  121. #if defined(FSMC_BANK4)
  122. /* --- PCR Register ---*/
  123. /* PCR register clear mask */
  124. #define PCR4_CLEAR_MASK   ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN  | \
  125.                                       FSMC_PCR4_PTYP    | FSMC_PCR4_PWID   | \
  126.                                       FSMC_PCR4_ECCEN   | FSMC_PCR4_TCLR   | \
  127.                                       FSMC_PCR4_TAR     | FSMC_PCR4_ECCPS))
  128. /* --- PMEM Register ---*/
  129. /* PMEM register clear mask */
  130. #define PMEM4_CLEAR_MASK  ((uint32_t)(FSMC_PMEM4_MEMSET4  | FSMC_PMEM4_MEMWAIT4 |\
  131.                                       FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4))
  132.  
  133. /* --- PATT Register ---*/
  134. /* PATT register clear mask */
  135. #define PATT4_CLEAR_MASK  ((uint32_t)(FSMC_PATT4_ATTSET4  | FSMC_PATT4_ATTWAIT4 |\
  136.                                       FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4))
  137.  
  138. /* --- PIO4 Register ---*/
  139. /* PIO4 register clear mask */
  140. #define PIO4_CLEAR_MASK   ((uint32_t)(FSMC_PIO4_IOSET4  | FSMC_PIO4_IOWAIT4 | \
  141.                                       FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
  142.  
  143. #endif /* FSMC_BANK4 */
  144.  
  145. /**
  146.   * @}
  147.   */
  148.  
  149. /* Private macro -------------------------------------------------------------*/
  150. /* Private variables ---------------------------------------------------------*/
  151. /* Private function prototypes -----------------------------------------------*/
  152. /* Exported functions --------------------------------------------------------*/
  153.  
  154. /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
  155.   * @{
  156.   */
  157.  
  158. #if defined(FSMC_BANK1)
  159.  
  160. /** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions
  161.   * @brief  NORSRAM Controller functions
  162.   *
  163.   @verbatim
  164.   ==============================================================================
  165.                    ##### How to use NORSRAM device driver #####
  166.   ==============================================================================
  167.  
  168.   [..]
  169.     This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
  170.     to run the NORSRAM external devices.
  171.  
  172.     (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
  173.     (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
  174.     (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
  175.     (+) FSMC NORSRAM bank extended timing configuration using the function
  176.         FSMC_NORSRAM_Extended_Timing_Init()
  177.     (+) FSMC NORSRAM bank enable/disable write operation using the functions
  178.         FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
  179.  
  180. @endverbatim
  181.   * @{
  182.   */
  183.  
  184. /** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
  185.   * @brief    Initialization and Configuration functions
  186.   *
  187.   @verbatim
  188.   ==============================================================================
  189.               ##### Initialization and de_initialization functions #####
  190.   ==============================================================================
  191.   [..]
  192.     This section provides functions allowing to:
  193.     (+) Initialize and configure the FSMC NORSRAM interface
  194.     (+) De-initialize the FSMC NORSRAM interface
  195.     (+) Configure the FSMC clock and associated GPIOs
  196.  
  197. @endverbatim
  198.   * @{
  199.   */
  200.  
  201. /**
  202.   * @brief  Initialize the FSMC_NORSRAM device according to the specified
  203.   *         control parameters in the FSMC_NORSRAM_InitTypeDef
  204.   * @param  Device Pointer to NORSRAM device instance
  205.   * @param  Init Pointer to NORSRAM Initialization structure
  206.   * @retval HAL status
  207.   */
  208. HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
  209.                                     FSMC_NORSRAM_InitTypeDef *Init)
  210. {
  211.   uint32_t flashaccess;
  212.   uint32_t btcr_reg;
  213.   uint32_t mask;
  214.  
  215.   /* Check the parameters */
  216.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  217.   assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
  218.   assert_param(IS_FSMC_MUX(Init->DataAddressMux));
  219.   assert_param(IS_FSMC_MEMORY(Init->MemoryType));
  220.   assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
  221.   assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
  222.   assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
  223.   assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
  224.   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
  225.   assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
  226.   assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
  227.   assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
  228.   assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
  229.   assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
  230.   assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
  231.  
  232.   /* Disable NORSRAM Device */
  233.   __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
  234.  
  235.   /* Set NORSRAM device control parameters */
  236.   if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
  237.   {
  238.     flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
  239.   }
  240.   else
  241.   {
  242.     flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
  243.   }
  244.  
  245.   btcr_reg = (flashaccess                   | \
  246.               Init->DataAddressMux          | \
  247.               Init->MemoryType              | \
  248.               Init->MemoryDataWidth         | \
  249.               Init->BurstAccessMode         | \
  250.               Init->WaitSignalPolarity      | \
  251.               Init->WaitSignalActive        | \
  252.               Init->WriteOperation          | \
  253.               Init->WaitSignal              | \
  254.               Init->ExtendedMode            | \
  255.               Init->AsynchronousWait        | \
  256.               Init->WriteBurst);
  257.  
  258.   btcr_reg |= Init->WrapMode;
  259.   btcr_reg |= Init->PageSize;
  260.  
  261.   mask = (FSMC_BCRx_MBKEN                |
  262.           FSMC_BCRx_MUXEN                |
  263.           FSMC_BCRx_MTYP                 |
  264.           FSMC_BCRx_MWID                 |
  265.           FSMC_BCRx_FACCEN               |
  266.           FSMC_BCRx_BURSTEN              |
  267.           FSMC_BCRx_WAITPOL              |
  268.           FSMC_BCRx_WAITCFG              |
  269.           FSMC_BCRx_WREN                 |
  270.           FSMC_BCRx_WAITEN               |
  271.           FSMC_BCRx_EXTMOD               |
  272.           FSMC_BCRx_ASYNCWAIT            |
  273.           FSMC_BCRx_CBURSTRW);
  274.  
  275.   mask |= FSMC_BCRx_WRAPMOD;
  276.   mask |= 0x00070000U; /* CPSIZE to be defined in CMSIS file */
  277.  
  278.   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
  279.  
  280.  
  281.   return HAL_OK;
  282. }
  283.  
  284. /**
  285.   * @brief  DeInitialize the FSMC_NORSRAM peripheral
  286.   * @param  Device Pointer to NORSRAM device instance
  287.   * @param  ExDevice Pointer to NORSRAM extended mode device instance
  288.   * @param  Bank NORSRAM bank number
  289.   * @retval HAL status
  290.   */
  291. HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
  292.                                      FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
  293. {
  294.   /* Check the parameters */
  295.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  296.   assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
  297.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  298.  
  299.   /* Disable the FSMC_NORSRAM device */
  300.   __FSMC_NORSRAM_DISABLE(Device, Bank);
  301.  
  302.   /* De-initialize the FSMC_NORSRAM device */
  303.   /* FSMC_NORSRAM_BANK1 */
  304.   if (Bank == FSMC_NORSRAM_BANK1)
  305.   {
  306.     Device->BTCR[Bank] = 0x000030DBU;
  307.   }
  308.   /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
  309.   else
  310.   {
  311.     Device->BTCR[Bank] = 0x000030D2U;
  312.   }
  313.  
  314.   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
  315.   ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;
  316.  
  317.   return HAL_OK;
  318. }
  319.  
  320. /**
  321.   * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
  322.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  323.   * @param  Device Pointer to NORSRAM device instance
  324.   * @param  Timing Pointer to NORSRAM Timing structure
  325.   * @param  Bank NORSRAM bank number
  326.   * @retval HAL status
  327.   */
  328. HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
  329.                                           FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
  330. {
  331.  
  332.   /* Check the parameters */
  333.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  334.   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  335.   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  336.   assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  337.   assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  338.   assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  339.   assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  340.   assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  341.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  342.  
  343.   /* Set FSMC_NORSRAM device timing parameters */
  344.   MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                                  |
  345.                                                        ((Timing->AddressHoldTime)        << FSMC_BTRx_ADDHLD_Pos)  |
  346.                                                        ((Timing->DataSetupTime)          << FSMC_BTRx_DATAST_Pos)  |
  347.                                                        ((Timing->BusTurnAroundDuration)  << FSMC_BTRx_BUSTURN_Pos) |
  348.                                                        (((Timing->CLKDivision) - 1U)     << FSMC_BTRx_CLKDIV_Pos)  |
  349.                                                        (((Timing->DataLatency) - 2U)     << FSMC_BTRx_DATLAT_Pos)  |
  350.                                                        (Timing->AccessMode)));
  351.  
  352.   return HAL_OK;
  353. }
  354.  
  355. /**
  356.   * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
  357.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  358.   * @param  Device Pointer to NORSRAM device instance
  359.   * @param  Timing Pointer to NORSRAM Timing structure
  360.   * @param  Bank NORSRAM bank number
  361.   * @param  ExtendedMode FSMC Extended Mode
  362.   *          This parameter can be one of the following values:
  363.   *            @arg FSMC_EXTENDED_MODE_DISABLE
  364.   *            @arg FSMC_EXTENDED_MODE_ENABLE
  365.   * @retval HAL status
  366.   */
  367. HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
  368.                                                    FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
  369.                                                    uint32_t ExtendedMode)
  370. {
  371.   /* Check the parameters */
  372.   assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
  373.  
  374.   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  375.   if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
  376.   {
  377.     /* Check the parameters */
  378.     assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
  379.     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  380.     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  381.     assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  382. #if defined(FSMC_BWTRx_BUSTURN)
  383.     assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  384. #else
  385.     assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  386.     assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  387. #endif /* FSMC_BWTRx_BUSTURN */
  388.     assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  389.     assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  390.  
  391.     /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  392. #if defined(FSMC_BWTRx_BUSTURN)
  393.     MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
  394.                                                      ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos)  |
  395.                                                      ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos)  |
  396.                                                      Timing->AccessMode                                          |
  397.                                                      ((Timing->BusTurnAroundDuration)  << FSMC_BWTRx_BUSTURN_Pos)));
  398. #else
  399.     MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
  400.                                                      ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos)  |
  401.                                                      ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos)  |
  402.                                                      Timing->AccessMode                                          |
  403.                                                      (((Timing->CLKDivision) - 1U)     << FSMC_BWTRx_CLKDIV_Pos)  |
  404.                                                      (((Timing->DataLatency) - 2U)     << FSMC_BWTRx_DATLAT_Pos)));
  405. #endif /* FSMC_BWTRx_BUSTURN */
  406.   }
  407.   else
  408.   {
  409.     Device->BWTR[Bank] = 0x0FFFFFFFU;
  410.   }
  411.  
  412.   return HAL_OK;
  413. }
  414. /**
  415.   * @}
  416.   */
  417.  
  418. /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
  419.   *  @brief   management functions
  420.   *
  421. @verbatim
  422.   ==============================================================================
  423.                       ##### FSMC_NORSRAM Control functions #####
  424.   ==============================================================================
  425.   [..]
  426.     This subsection provides a set of functions allowing to control dynamically
  427.     the FSMC NORSRAM interface.
  428.  
  429. @endverbatim
  430.   * @{
  431.   */
  432.  
  433. /**
  434.   * @brief  Enables dynamically FSMC_NORSRAM write operation.
  435.   * @param  Device Pointer to NORSRAM device instance
  436.   * @param  Bank NORSRAM bank number
  437.   * @retval HAL status
  438.   */
  439. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  440. {
  441.   /* Check the parameters */
  442.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  443.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  444.  
  445.   /* Enable write operation */
  446.   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  447.  
  448.   return HAL_OK;
  449. }
  450.  
  451. /**
  452.   * @brief  Disables dynamically FSMC_NORSRAM write operation.
  453.   * @param  Device Pointer to NORSRAM device instance
  454.   * @param  Bank NORSRAM bank number
  455.   * @retval HAL status
  456.   */
  457. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  458. {
  459.   /* Check the parameters */
  460.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  461.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  462.  
  463.   /* Disable write operation */
  464.   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  465.  
  466.   return HAL_OK;
  467. }
  468.  
  469. /**
  470.   * @}
  471.   */
  472.  
  473. /**
  474.   * @}
  475.   */
  476. #endif /* FSMC_BANK1 */
  477.  
  478. #if defined(FSMC_BANK3)
  479.  
  480. /** @defgroup FSMC_LL_Exported_Functions_NAND FSMC Low Layer NAND Exported Functions
  481.   * @brief    NAND Controller functions
  482.   *
  483.   @verbatim
  484.   ==============================================================================
  485.                     ##### How to use NAND device driver #####
  486.   ==============================================================================
  487.   [..]
  488.     This driver contains a set of APIs to interface with the FSMC NAND banks in order
  489.     to run the NAND external devices.
  490.  
  491.     (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
  492.     (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
  493.     (+) FSMC NAND bank common space timing configuration using the function
  494.         FSMC_NAND_CommonSpace_Timing_Init()
  495.     (+) FSMC NAND bank attribute space timing configuration using the function
  496.         FSMC_NAND_AttributeSpace_Timing_Init()
  497.     (+) FSMC NAND bank enable/disable ECC correction feature using the functions
  498.         FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
  499.     (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
  500.  
  501. @endverbatim
  502.   * @{
  503.   */
  504.  
  505. /** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
  506.   *  @brief    Initialization and Configuration functions
  507.   *
  508. @verbatim
  509.   ==============================================================================
  510.               ##### Initialization and de_initialization functions #####
  511.   ==============================================================================
  512.   [..]
  513.     This section provides functions allowing to:
  514.     (+) Initialize and configure the FSMC NAND interface
  515.     (+) De-initialize the FSMC NAND interface
  516.     (+) Configure the FSMC clock and associated GPIOs
  517.  
  518. @endverbatim
  519.   * @{
  520.   */
  521.  
  522. /**
  523.   * @brief  Initializes the FSMC_NAND device according to the specified
  524.   *         control parameters in the FSMC_NAND_HandleTypeDef
  525.   * @param  Device Pointer to NAND device instance
  526.   * @param  Init Pointer to NAND Initialization structure
  527.   * @retval HAL status
  528.   */
  529. HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
  530. {
  531.   /* Check the parameters */
  532.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  533.   assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
  534.   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
  535.   assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
  536.   assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
  537.   assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
  538.   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
  539.   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
  540.  
  541.   /* Set NAND device control parameters */
  542.   if (Init->NandBank == FSMC_NAND_BANK2)
  543.   {
  544.     /* NAND bank 2 registers configuration */
  545.     MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
  546.                                               FSMC_PCR_MEMORY_TYPE_NAND                               |
  547.                                               Init->MemoryDataWidth                                  |
  548.                                               Init->EccComputation                                   |
  549.                                               Init->ECCPageSize                                      |
  550.                                               ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos)  |
  551.                                               ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
  552.   }
  553.   else
  554.   {
  555.     /* NAND bank 3 registers configuration */
  556.     MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
  557.                                               FSMC_PCR_MEMORY_TYPE_NAND                               |
  558.                                               Init->MemoryDataWidth                                  |
  559.                                               Init->EccComputation                                   |
  560.                                               Init->ECCPageSize                                      |
  561.                                               ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos)  |
  562.                                               ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
  563.   }
  564.  
  565.   return HAL_OK;
  566. }
  567.  
  568. /**
  569.   * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
  570.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  571.   * @param  Device Pointer to NAND device instance
  572.   * @param  Timing Pointer to NAND timing structure
  573.   * @param  Bank NAND bank number
  574.   * @retval HAL status
  575.   */
  576. HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
  577.                                                    FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  578. {
  579.   /* Check the parameters */
  580.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  581.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  582.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  583.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  584.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  585.   assert_param(IS_FSMC_NAND_BANK(Bank));
  586.  
  587.   /* Set FSMC_NAND device timing parameters */
  588.   if (Bank == FSMC_NAND_BANK2)
  589.   {
  590.     /* NAND bank 2 registers configuration */
  591.     MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
  592.                                                 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
  593.                                                 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
  594.                                                 ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
  595.   }
  596.   else
  597.   {
  598.     /* NAND bank 3 registers configuration */
  599.     MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
  600.                                                 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
  601.                                                 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
  602.                                                 ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
  603.   }
  604.  
  605.   return HAL_OK;
  606. }
  607.  
  608. /**
  609.   * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
  610.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  611.   * @param  Device Pointer to NAND device instance
  612.   * @param  Timing Pointer to NAND timing structure
  613.   * @param  Bank NAND bank number
  614.   * @retval HAL status
  615.   */
  616. HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
  617.                                                       FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  618. {
  619.   /* Check the parameters */
  620.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  621.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  622.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  623.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  624.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  625.   assert_param(IS_FSMC_NAND_BANK(Bank));
  626.  
  627.   /* Set FSMC_NAND device timing parameters */
  628.   if (Bank == FSMC_NAND_BANK2)
  629.   {
  630.     /* NAND bank 2 registers configuration */
  631.     MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
  632.                                                 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
  633.                                                 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
  634.                                                 ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  635.   }
  636.   else
  637.   {
  638.     /* NAND bank 3 registers configuration */
  639.     MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
  640.                                                 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
  641.                                                 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
  642.                                                 ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  643.   }
  644.  
  645.   return HAL_OK;
  646. }
  647.  
  648. /**
  649.   * @brief  DeInitializes the FSMC_NAND device
  650.   * @param  Device Pointer to NAND device instance
  651.   * @param  Bank NAND bank number
  652.   * @retval HAL status
  653.   */
  654. HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  655. {
  656.   /* Check the parameters */
  657.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  658.   assert_param(IS_FSMC_NAND_BANK(Bank));
  659.  
  660.   /* Disable the NAND Bank */
  661.   __FSMC_NAND_DISABLE(Device, Bank);
  662.  
  663.   /* De-initialize the NAND Bank */
  664.   if (Bank == FSMC_NAND_BANK2)
  665.   {
  666.     /* Set the FSMC_NAND_BANK2 registers to their reset values */
  667.     WRITE_REG(Device->PCR2,  0x00000018U);
  668.     WRITE_REG(Device->SR2,   0x00000040U);
  669.     WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
  670.     WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
  671.   }
  672.   /* FSMC_Bank3_NAND */
  673.   else
  674.   {
  675.     /* Set the FSMC_NAND_BANK3 registers to their reset values */
  676.     WRITE_REG(Device->PCR3,  0x00000018U);
  677.     WRITE_REG(Device->SR3,   0x00000040U);
  678.     WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
  679.     WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
  680.   }
  681.  
  682.   return HAL_OK;
  683. }
  684.  
  685. /**
  686.   * @}
  687.   */
  688.  
  689. /** @defgroup HAL_FSMC_NAND_Group2 Peripheral Control functions
  690.   *  @brief   management functions
  691.   *
  692. @verbatim
  693.   ==============================================================================
  694.                        ##### FSMC_NAND Control functions #####
  695.   ==============================================================================
  696.   [..]
  697.     This subsection provides a set of functions allowing to control dynamically
  698.     the FSMC NAND interface.
  699.  
  700. @endverbatim
  701.   * @{
  702.   */
  703.  
  704.  
  705. /**
  706.   * @brief  Enables dynamically FSMC_NAND ECC feature.
  707.   * @param  Device Pointer to NAND device instance
  708.   * @param  Bank NAND bank number
  709.   * @retval HAL status
  710.   */
  711. HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  712. {
  713.   /* Check the parameters */
  714.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  715.   assert_param(IS_FSMC_NAND_BANK(Bank));
  716.  
  717.   /* Enable ECC feature */
  718.   if (Bank == FSMC_NAND_BANK2)
  719.   {
  720.     SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
  721.   }
  722.   else
  723.   {
  724.     SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
  725.   }
  726.  
  727.   return HAL_OK;
  728. }
  729.  
  730.  
  731. /**
  732.   * @brief  Disables dynamically FSMC_NAND ECC feature.
  733.   * @param  Device Pointer to NAND device instance
  734.   * @param  Bank NAND bank number
  735.   * @retval HAL status
  736.   */
  737. HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  738. {
  739.   /* Check the parameters */
  740.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  741.   assert_param(IS_FSMC_NAND_BANK(Bank));
  742.  
  743.   /* Disable ECC feature */
  744.   if (Bank == FSMC_NAND_BANK2)
  745.   {
  746.     CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
  747.   }
  748.   else
  749.   {
  750.     CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
  751.   }
  752.  
  753.   return HAL_OK;
  754. }
  755.  
  756. /**
  757.   * @brief  Disables dynamically FSMC_NAND ECC feature.
  758.   * @param  Device Pointer to NAND device instance
  759.   * @param  ECCval Pointer to ECC value
  760.   * @param  Bank NAND bank number
  761.   * @param  Timeout Timeout wait value
  762.   * @retval HAL status
  763.   */
  764. HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
  765.                                   uint32_t Timeout)
  766. {
  767.   uint32_t tickstart;
  768.  
  769.   /* Check the parameters */
  770.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  771.   assert_param(IS_FSMC_NAND_BANK(Bank));
  772.  
  773.   /* Get tick */
  774.   tickstart = HAL_GetTick();
  775.  
  776.   /* Wait until FIFO is empty */
  777.   while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
  778.   {
  779.     /* Check for the Timeout */
  780.     if (Timeout != HAL_MAX_DELAY)
  781.     {
  782.       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
  783.       {
  784.         return HAL_TIMEOUT;
  785.       }
  786.     }
  787.   }
  788.  
  789.   if (Bank == FSMC_NAND_BANK2)
  790.   {
  791.     /* Get the ECCR2 register value */
  792.     *ECCval = (uint32_t)Device->ECCR2;
  793.   }
  794.   else
  795.   {
  796.     /* Get the ECCR3 register value */
  797.     *ECCval = (uint32_t)Device->ECCR3;
  798.   }
  799.  
  800.   return HAL_OK;
  801. }
  802.  
  803. /**
  804.   * @}
  805.   */
  806. #endif /* FSMC_BANK3 */
  807.  
  808. #if defined(FSMC_BANK4)
  809.  
  810. /** @addtogroup FSMC_LL_PCCARD
  811.   * @brief    PCCARD Controller functions
  812.   *
  813.   @verbatim
  814.   ==============================================================================
  815.                     ##### How to use PCCARD device driver #####
  816.   ==============================================================================
  817.   [..]
  818.     This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
  819.     to run the PCCARD/compact flash external devices.
  820.  
  821.     (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
  822.     (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
  823.     (+) FSMC PCCARD bank common space timing configuration using the function
  824.         FSMC_PCCARD_CommonSpace_Timing_Init()
  825.     (+) FSMC PCCARD bank attribute space timing configuration using the function
  826.         FSMC_PCCARD_AttributeSpace_Timing_Init()
  827.     (+) FSMC PCCARD bank IO space timing configuration using the function
  828.         FSMC_PCCARD_IOSpace_Timing_Init()
  829. @endverbatim
  830.   * @{
  831.   */
  832.  
  833. /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
  834.   *  @brief    Initialization and Configuration functions
  835.   *
  836. @verbatim
  837.   ==============================================================================
  838.               ##### Initialization and de_initialization functions #####
  839.   ==============================================================================
  840.   [..]
  841.     This section provides functions allowing to:
  842.     (+) Initialize and configure the FSMC PCCARD interface
  843.     (+) De-initialize the FSMC PCCARD interface
  844.     (+) Configure the FSMC clock and associated GPIOs
  845.  
  846. @endverbatim
  847.   * @{
  848.   */
  849.  
  850. /**
  851.   * @brief  Initializes the FSMC_PCCARD device according to the specified
  852.   *         control parameters in the FSMC_PCCARD_HandleTypeDef
  853.   * @param  Device Pointer to PCCARD device instance
  854.   * @param  Init Pointer to PCCARD Initialization structure
  855.   * @retval HAL status
  856.   */
  857. HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
  858. {
  859.   /* Check the parameters */
  860.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  861. #if defined(FSMC_BANK3)
  862.   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
  863.   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
  864.   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
  865. #endif /* FSMC_BANK3 */
  866.  
  867.   /* Set FSMC_PCCARD device control parameters */
  868.   MODIFY_REG(Device->PCR4,
  869.              (FSMC_PCRx_PTYP                                          |
  870.               FSMC_PCRx_PWAITEN                                       |
  871.               FSMC_PCRx_PWID                                          |
  872.               FSMC_PCRx_TCLR                                          |
  873.               FSMC_PCRx_TAR),
  874.              (FSMC_PCR_MEMORY_TYPE_PCCARD                             |
  875.               Init->Waitfeature                                      |
  876.               FSMC_NAND_PCC_MEM_BUS_WIDTH_16                          |
  877.               (Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos)   |
  878.               (Init->TARSetupTime  << FSMC_PCRx_TAR_Pos)));
  879.  
  880.   return HAL_OK;
  881. }
  882.  
  883. /**
  884.   * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
  885.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  886.   * @param  Device Pointer to PCCARD device instance
  887.   * @param  Timing Pointer to PCCARD timing structure
  888.   * @retval HAL status
  889.   */
  890. HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
  891.                                                               FSMC_NAND_PCC_TimingTypeDef *Timing)
  892. {
  893.   /* Check the parameters */
  894.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  895. #if defined(FSMC_BANK3)
  896.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  897.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  898.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  899.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  900. #endif /* FSMC_BANK3 */
  901.  
  902.   /* Set PCCARD timing parameters */
  903.   MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
  904.              (Timing->SetupTime                                              |
  905.               ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos)  |
  906.               ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos)  |
  907.               ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
  908.  
  909.   return HAL_OK;
  910. }
  911.  
  912. /**
  913.   * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
  914.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  915.   * @param  Device Pointer to PCCARD device instance
  916.   * @param  Timing Pointer to PCCARD timing structure
  917.   * @retval HAL status
  918.   */
  919. HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
  920.                                                                  FSMC_NAND_PCC_TimingTypeDef *Timing)
  921. {
  922.   /* Check the parameters */
  923.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  924. #if defined(FSMC_BANK3)
  925.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  926.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  927.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  928.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  929. #endif /* FSMC_BANK3 */
  930.  
  931.   /* Set PCCARD timing parameters */
  932.   MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK,
  933.              (Timing->SetupTime                                              |
  934.               ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos)  |
  935.               ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos)  |
  936.               ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  937.  
  938.   return HAL_OK;
  939. }
  940.  
  941. /**
  942.   * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
  943.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  944.   * @param  Device Pointer to PCCARD device instance
  945.   * @param  Timing Pointer to PCCARD timing structure
  946.   * @retval HAL status
  947.   */
  948. HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
  949.                                                           FSMC_NAND_PCC_TimingTypeDef *Timing)
  950. {
  951.   /* Check the parameters */
  952.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  953. #if defined(FSMC_BANK3)
  954.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  955.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  956.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  957.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  958. #endif /* FSMC_BANK3 */
  959.  
  960.   /* Set FSMC_PCCARD device timing parameters */
  961.   MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
  962.              (Timing->SetupTime                                           |
  963.               (Timing->WaitSetupTime   << FSMC_PIO4_IOWAIT4_Pos) |
  964.               (Timing->HoldSetupTime   << FSMC_PIO4_IOHOLD4_Pos) |
  965.               (Timing->HiZSetupTime    << FSMC_PIO4_IOHIZ4_Pos)));
  966.  
  967.   return HAL_OK;
  968. }
  969.  
  970. /**
  971.   * @brief  DeInitializes the FSMC_PCCARD device
  972.   * @param  Device Pointer to PCCARD device instance
  973.   * @retval HAL status
  974.   */
  975. HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
  976. {
  977.   /* Check the parameters */
  978.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  979.  
  980.   /* Disable the FSMC_PCCARD device */
  981.   __FSMC_PCCARD_DISABLE(Device);
  982.  
  983.   /* De-initialize the FSMC_PCCARD device */
  984.   Device->PCR4    = 0x00000018U;
  985.   Device->SR4     = 0x00000040U;
  986.   Device->PMEM4   = 0xFCFCFCFCU;
  987.   Device->PATT4   = 0xFCFCFCFCU;
  988.   Device->PIO4    = 0xFCFCFCFCU;
  989.  
  990.   return HAL_OK;
  991. }
  992.  
  993. /**
  994.   * @}
  995.   */
  996. #endif /* FSMC_BANK4 */
  997.  
  998.  
  999. /**
  1000.   * @}
  1001.   */
  1002.  
  1003. /**
  1004.   * @}
  1005.   */
  1006.  
  1007. #endif /* HAL_NOR_MODULE_ENABLED */
  1008. /**
  1009.   * @}
  1010.   */
  1011. /**
  1012.   * @}
  1013.   */
  1014.