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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_fsmc.c
  4.   * @author  MCD Application Team
  5.   * @brief   FSMC Low Layer HAL module driver.
  6.   *
  7.   *          This file provides firmware functions to manage the following
  8.   *          functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
  9.   *           + Initialization/de-initialization functions
  10.   *           + Peripheral Control functions
  11.   *           + Peripheral State functions
  12.   *
  13.   @verbatim
  14.   =============================================================================
  15.                         ##### FSMC peripheral features #####
  16.   =============================================================================
  17.     [..] The Flexible static memory controller (FSMC) includes following memory controllers:
  18.          (+) The NOR/PSRAM memory controller
  19.          (+) The PC Card memory controller
  20.          (+) The NAND memory controller
  21.              (PC Card and NAND controllers available only on STM32F101xE, STM32F103xE, STM32F101xG and STM32F103xG)
  22.  
  23.     [..] The FSMC functional block makes the interface with synchronous and asynchronous static
  24.          memories and 16-bit PC memory cards. Its main purposes are:
  25.          (+) to translate AHB transactions into the appropriate external device protocol.
  26.          (+) to meet the access time requirements of the external memory devices.
  27.  
  28.     [..] All external memories share the addresses, data and control signals with the controller.
  29.          Each external device is accessed by means of a unique Chip Select. The FSMC performs
  30.          only one access at a time to an external device.
  31.          The main features of the FSMC controller are the following:
  32.           (+) Interface with static-memory mapped devices including:
  33.              (++) Static random access memory (SRAM).
  34.              (++) NOR Flash memory.
  35.              (++) PSRAM (4 memory banks).
  36.              (++) 16-bit PC Card compatible devices.
  37.              (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  38.                   data.
  39.           (+) Independent Chip Select control for each memory bank.
  40.           (+) Independent configuration for each memory bank.
  41.        
  42.   @endverbatim
  43.   ******************************************************************************
  44.   * @attention
  45.   *
  46.   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  47.   *
  48.   * Redistribution and use in source and binary forms, with or without modification,
  49.   * are permitted provided that the following conditions are met:
  50.   *   1. Redistributions of source code must retain the above copyright notice,
  51.   *      this list of conditions and the following disclaimer.
  52.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  53.   *      this list of conditions and the following disclaimer in the documentation
  54.   *      and/or other materials provided with the distribution.
  55.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  56.   *      may be used to endorse or promote products derived from this software
  57.   *      without specific prior written permission.
  58.   *
  59.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  60.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  61.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  62.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  63.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  64.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  65.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  66.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  67.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  68.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  69.   *
  70.   ******************************************************************************
  71.   */
  72.  
  73. /* Includes ------------------------------------------------------------------*/
  74. #include "stm32f1xx_hal.h"
  75.  
  76. /** @addtogroup STM32F1xx_HAL_Driver
  77.   * @{
  78.   */
  79.  
  80. #if defined(FSMC_BANK1)
  81.  
  82. #if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
  83.  
  84. /** @defgroup FSMC_LL FSMC Low Layer
  85.   * @brief FSMC driver modules
  86.   * @{
  87.   */
  88.  
  89. /* Private typedef -----------------------------------------------------------*/
  90. /* Private define ------------------------------------------------------------*/
  91. /* Private macro -------------------------------------------------------------*/
  92. /* Private variables ---------------------------------------------------------*/
  93. /* Private function prototypes -----------------------------------------------*/
  94. /* Exported functions --------------------------------------------------------*/
  95.  
  96. /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
  97.   * @{
  98.   */
  99.  
  100. /** @defgroup FSMC_NORSRAM FSMC NORSRAM Controller functions
  101.   * @brief    NORSRAM Controller functions
  102.   *
  103.   @verbatim
  104.   ==============================================================================
  105.                    ##### How to use NORSRAM device driver #####
  106.   ==============================================================================
  107.  
  108.   [..]
  109.     This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
  110.     to run the NORSRAM external devices.
  111.  
  112.     (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
  113.     (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
  114.     (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
  115.     (+) FSMC NORSRAM bank extended timing configuration using the function
  116.         FSMC_NORSRAM_Extended_Timing_Init()
  117.     (+) FSMC NORSRAM bank enable/disable write operation using the functions
  118.         FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
  119.  
  120. @endverbatim
  121.   * @{
  122.   */
  123.        
  124. /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
  125.   * @brief    Initialization and Configuration functions
  126.   *
  127.   @verbatim
  128.   ==============================================================================
  129.               ##### Initialization and de_initialization functions #####
  130.   ==============================================================================
  131.   [..]
  132.     This section provides functions allowing to:
  133.     (+) Initialize and configure the FSMC NORSRAM interface
  134.     (+) De-initialize the FSMC NORSRAM interface
  135.     (+) Configure the FSMC clock and associated GPIOs
  136.  
  137. @endverbatim
  138.   * @{
  139.   */
  140.  
  141. /**
  142.   * @brief  Initialize the FSMC_NORSRAM device according to the specified
  143.   *         control parameters in the FSMC_NORSRAM_InitTypeDef
  144.   * @param  Device: Pointer to NORSRAM device instance
  145.   * @param  Init: Pointer to NORSRAM Initialization structure
  146.   * @retval HAL status
  147.   */
  148. HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init)
  149. {
  150.   /* Check the parameters */
  151.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  152.   assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
  153.   assert_param(IS_FSMC_MUX(Init->DataAddressMux));
  154.   assert_param(IS_FSMC_MEMORY(Init->MemoryType));
  155.   assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
  156.   assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
  157.   assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
  158.   assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
  159.   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
  160.   assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
  161.   assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
  162.   assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
  163.   assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
  164.   assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
  165.  
  166.   /* Disable NORSRAM Device */
  167.   __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
  168.  
  169.   /* Set NORSRAM device control parameters */
  170.   if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
  171.   {
  172.     MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_ENABLE
  173.                | Init->DataAddressMux
  174.                | Init->MemoryType
  175.                | Init->MemoryDataWidth
  176.                | Init->BurstAccessMode
  177.                | Init->WaitSignalPolarity
  178.                | Init->WrapMode
  179.                | Init->WaitSignalActive
  180.                | Init->WriteOperation
  181.                | Init->WaitSignal
  182.                | Init->ExtendedMode
  183.                | Init->AsynchronousWait
  184.                | Init->WriteBurst
  185.                                                                      )
  186.               );
  187.   }
  188.   else
  189.   {
  190.     MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_DISABLE
  191.                | Init->DataAddressMux
  192.                | Init->MemoryType
  193.                | Init->MemoryDataWidth
  194.                | Init->BurstAccessMode
  195.                | Init->WaitSignalPolarity
  196.                | Init->WrapMode
  197.                | Init->WaitSignalActive
  198.                | Init->WriteOperation
  199.                | Init->WaitSignal
  200.                | Init->ExtendedMode
  201.                | Init->AsynchronousWait
  202.                | Init->WriteBurst
  203.                                                                      )
  204.               );
  205.   }
  206.  
  207.   return HAL_OK;
  208. }
  209.  
  210. /**
  211.   * @brief  DeInitialize the FSMC_NORSRAM peripheral
  212.   * @param  Device: Pointer to NORSRAM device instance
  213.   * @param  ExDevice: Pointer to NORSRAM extended mode device instance
  214.   * @param  Bank: NORSRAM bank number  
  215.   * @retval HAL status
  216.   */
  217. HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
  218. {
  219.   /* Check the parameters */
  220.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  221.   assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
  222.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  223.  
  224.   /* Disable the FSMC_NORSRAM device */
  225.   __FSMC_NORSRAM_DISABLE(Device, Bank);
  226.  
  227.   /* De-initialize the FSMC_NORSRAM device */
  228.   /* FSMC_NORSRAM_BANK1 */
  229.   if(Bank == FSMC_NORSRAM_BANK1)
  230.   {
  231.     Device->BTCR[Bank] = 0x000030DBU;
  232.   }
  233.   /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
  234.   else
  235.   {  
  236.     Device->BTCR[Bank] = 0x000030D2U;
  237.   }
  238.  
  239.   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
  240.   ExDevice->BWTR[Bank]    = 0x0FFFFFFFU;
  241.    
  242.   return HAL_OK;
  243. }
  244.  
  245.  
  246. /**
  247.   * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
  248.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  249.   * @param  Device: Pointer to NORSRAM device instance
  250.   * @param  Timing: Pointer to NORSRAM Timing structure
  251.   * @param  Bank: NORSRAM bank number
  252.   * @retval HAL status
  253.   */
  254. HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
  255. {
  256.   /* Check the parameters */
  257.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  258.   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  259.   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  260.   assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  261.   assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  262.   assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  263.   assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  264.   assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  265.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  266.  
  267.   /* Set FSMC_NORSRAM device timing parameters */
  268.   MODIFY_REG(Device->BTCR[Bank + 1U],                                                        \
  269.              BTR_CLEAR_MASK,                                                                \
  270.              (uint32_t)(Timing->AddressSetupTime                                          | \
  271.                         ((Timing->AddressHoldTime)        << FSMC_BTRx_ADDHLD_Pos)        | \
  272.                         ((Timing->DataSetupTime)          << FSMC_BTRx_DATAST_Pos)        | \
  273.                         ((Timing->BusTurnAroundDuration)  << FSMC_BTRx_BUSTURN_Pos)       | \
  274.                         (((Timing->CLKDivision) - 1U)     << FSMC_BTRx_CLKDIV_Pos)        | \
  275.                         (((Timing->DataLatency) - 2U)     << FSMC_BTRx_DATLAT_Pos)        | \
  276.                         (Timing->AccessMode)));
  277.  
  278.   return HAL_OK;
  279. }
  280.  
  281. /**
  282.   * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
  283.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  284.   * @param  Device: Pointer to NORSRAM device instance
  285.   * @param  Timing: Pointer to NORSRAM Timing structure
  286.   * @param  Bank: NORSRAM bank number
  287.   * @param  ExtendedMode FSMC Extended Mode
  288.   *          This parameter can be one of the following values:
  289.   *            @arg FSMC_EXTENDED_MODE_DISABLE
  290.   *            @arg FSMC_EXTENDED_MODE_ENABLE
  291.   * @retval HAL status
  292.   */
  293. HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
  294. {
  295.   /* Check the parameters */
  296.   assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
  297.  
  298.   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  299.   if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
  300.   {
  301.     /* Check the parameters */
  302.     assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
  303.     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  304.     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  305.     assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  306. #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  307.     assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  308. #else
  309.     assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  310.     assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  311. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  312.     assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  313.     assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  314.  
  315.     /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  316. #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  317.     MODIFY_REG(Device->BWTR[Bank],                                                      \
  318.                BWTR_CLEAR_MASK,                                                         \
  319.                (uint32_t)(Timing->AddressSetupTime                                    | \
  320.                           ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos) | \
  321.                           ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos) | \
  322.                           Timing->AccessMode                                          | \
  323.                           ((Timing->BusTurnAroundDuration)  << FSMC_BWTRx_BUSTURN_Pos)));
  324. #else
  325.     MODIFY_REG(Device->BWTR[Bank],                                                      \
  326.                BWTR_CLEAR_MASK,                                                         \
  327.                (uint32_t)(Timing->AddressSetupTime                                    | \
  328.                           ((Timing->AddressHoldTime)  << FSMC_BWTRx_ADDHLD_Pos)       | \
  329.                           ((Timing->DataSetupTime)    << FSMC_BWTRx_DATAST_Pos)       | \
  330.                           Timing->AccessMode                                          | \
  331.                           (((Timing->CLKDivision) - 1U)  << FSMC_BTRx_CLKDIV_Pos)     | \
  332.                           (((Timing->DataLatency) - 2U)  << FSMC_BWTRx_DATLAT_Pos)));
  333. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  334.   }
  335.   else
  336.   {
  337.     Device->BWTR[Bank] = 0x0FFFFFFFU;
  338.   }
  339.  
  340.   return HAL_OK;
  341. }
  342. /**
  343.   * @}
  344.   */
  345.  
  346. /** @defgroup FSMC_NORSRAM_Group2 Control functions
  347.   *  @brief   management functions
  348.   *
  349. @verbatim
  350.   ==============================================================================
  351.                       ##### FSMC_NORSRAM Control functions #####
  352.   ==============================================================================
  353.   [..]
  354.     This subsection provides a set of functions allowing to control dynamically
  355.     the FSMC NORSRAM interface.
  356.  
  357. @endverbatim
  358.   * @{
  359.   */
  360.  
  361. /**
  362.   * @brief  Enables dynamically FSMC_NORSRAM write operation.
  363.   * @param  Device: Pointer to NORSRAM device instance
  364.   * @param  Bank: NORSRAM bank number
  365.   * @retval HAL status
  366.   */
  367. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  368. {
  369.   /* Check the parameters */
  370.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  371.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  372.  
  373.   /* Enable write operation */
  374.   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  375.  
  376.   return HAL_OK;
  377. }
  378.  
  379. /**
  380.   * @brief  Disables dynamically FSMC_NORSRAM write operation.
  381.   * @param  Device: Pointer to NORSRAM device instance
  382.   * @param  Bank: NORSRAM bank number
  383.   * @retval HAL status
  384.   */
  385. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  386. {
  387.   /* Check the parameters */
  388.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  389.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  390.  
  391.   /* Disable write operation */
  392.   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  393.  
  394.   return HAL_OK;
  395. }
  396. /**
  397.   * @}
  398.   */
  399.  
  400. /**
  401.   * @}
  402.   */
  403.  
  404. #if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
  405. /** @defgroup FSMC_NAND FSMC NAND Controller functions
  406.   * @brief    NAND Controller functions
  407.   *
  408.   @verbatim
  409.   ==============================================================================
  410.                     ##### How to use NAND device driver #####
  411.   ==============================================================================
  412.   [..]
  413.     This driver contains a set of APIs to interface with the FSMC NAND banks in order
  414.     to run the NAND external devices.
  415.  
  416.     (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
  417.     (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
  418.     (+) FSMC NAND bank common space timing configuration using the function
  419.         FSMC_NAND_CommonSpace_Timing_Init()
  420.     (+) FSMC NAND bank attribute space timing configuration using the function
  421.         FSMC_NAND_AttributeSpace_Timing_Init()
  422.     (+) FSMC NAND bank enable/disable ECC correction feature using the functions
  423.         FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
  424.     (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
  425.  
  426. @endverbatim
  427.   * @{
  428.   */
  429.  
  430. /** @defgroup FSMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
  431.   *  @brief    Initialization and Configuration functions
  432.   *
  433. @verbatim
  434.   ==============================================================================
  435.               ##### Initialization and de_initialization functions #####
  436.   ==============================================================================
  437.   [..]
  438.     This section provides functions allowing to:
  439.     (+) Initialize and configure the FSMC NAND interface
  440.     (+) De-initialize the FSMC NAND interface
  441.     (+) Configure the FSMC clock and associated GPIOs
  442.  
  443. @endverbatim
  444.   * @{
  445.   */
  446.  
  447. /**
  448.   * @brief  Initializes the FSMC_NAND device according to the specified
  449.   *         control parameters in the FSMC_NAND_HandleTypeDef
  450.   * @param  Device: Pointer to NAND device instance
  451.   * @param  Init: Pointer to NAND Initialization structure
  452.   * @retval HAL status
  453.   */
  454. HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
  455. {
  456.   /* Check the parameters */
  457.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  458.   assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
  459.   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
  460.   assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
  461.   assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
  462.   assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
  463.   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
  464.   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
  465.  
  466.   /* Set NAND device control parameters */
  467.   if (Init->NandBank == FSMC_NAND_BANK2)
  468.   {
  469.     /* NAND bank 2 registers configuration */
  470.     MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                             |
  471.                                               FSMC_PCR_MEMORY_TYPE_NAND                     |
  472.                                               Init->MemoryDataWidth                         |
  473.                                               Init->EccComputation                          |
  474.                                               Init->ECCPageSize                             |
  475.                                               ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) |
  476.                                               ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
  477.   }
  478.   else
  479.   {
  480.     /* NAND bank 3 registers configuration */
  481.     MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                             |
  482.                                               FSMC_PCR_MEMORY_TYPE_NAND                     |
  483.                                               Init->MemoryDataWidth                         |
  484.                                               Init->EccComputation                          |
  485.                                               Init->ECCPageSize                             |
  486.                                               ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) |
  487.                                               ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
  488.   }
  489.  
  490.   return HAL_OK;
  491. }
  492.  
  493. /**
  494.   * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
  495.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  496.   * @param  Device: Pointer to NAND device instance
  497.   * @param  Timing: Pointer to NAND timing structure
  498.   * @param  Bank: NAND bank number
  499.   * @retval HAL status
  500.   */
  501. HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  502. {
  503.   /* Check the parameters */
  504.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  505.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  506.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  507.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  508.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  509.   assert_param(IS_FSMC_NAND_BANK(Bank));
  510.  
  511.   /* Set FMC_NAND device timing parameters */
  512.   if(Bank == FSMC_NAND_BANK2)
  513.   {
  514.     /* NAND bank 2 registers configuration */
  515.     MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                         | \
  516.                                                 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos)      | \
  517.                                                 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos)      | \
  518.                                                 ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
  519.   }
  520.   else
  521.   {
  522.     /* NAND bank 3 registers configuration */
  523.     MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                         | \
  524.                                                 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos)      | \
  525.                                                 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos)      | \
  526.                                                 ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
  527.   }
  528.  
  529.   return HAL_OK;
  530. }
  531.  
  532. /**
  533.   * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
  534.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  535.   * @param  Device: Pointer to NAND device instance
  536.   * @param  Timing: Pointer to NAND timing structure
  537.   * @param  Bank: NAND bank number
  538.   * @retval HAL status
  539.   */
  540. HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  541. {
  542.   /* Check the parameters */
  543.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  544.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  545.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  546.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  547.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  548.   assert_param(IS_FSMC_NAND_BANK(Bank));
  549.  
  550.   /* Set FMC_NAND device timing parameters */
  551.   if(Bank == FSMC_NAND_BANK2)
  552.   {
  553.     /* NAND bank 2 registers configuration */
  554.     MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                         | \
  555.                                                 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos)      | \
  556.                                                 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos)      | \
  557.                                                 ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  558.   }
  559.   else
  560.   {
  561.     /* NAND bank 3 registers configuration */
  562.     MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                         | \
  563.                                                 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos)      | \
  564.                                                 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos)      | \
  565.                                                 ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  566.   }
  567.  
  568.   return HAL_OK;
  569. }
  570.  
  571.  
  572. /**
  573.   * @brief  DeInitializes the FSMC_NAND device
  574.   * @param  Device: Pointer to NAND device instance
  575.   * @param  Bank: NAND bank number
  576.   * @retval HAL status
  577.   */
  578. HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  579. {
  580.   /* Check the parameters */
  581.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  582.   assert_param(IS_FSMC_NAND_BANK(Bank));
  583.  
  584.   /* Disable the NAND Bank */
  585.   __FSMC_NAND_DISABLE(Device, Bank);
  586.  
  587.   /* De-initialize the NAND Bank */
  588.   if(Bank == FSMC_NAND_BANK2)
  589.   {
  590.     /* Set the FSMC_NAND_BANK2 registers to their reset values */
  591.     WRITE_REG(Device->PCR2,  0x00000018U);
  592.     WRITE_REG(Device->SR2,   0x00000040U);
  593.     WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
  594.     WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
  595.   }
  596.   /* FSMC_Bank3_NAND */
  597.   else
  598.   {
  599.     /* Set the FSMC_NAND_BANK3 registers to their reset values */
  600.     WRITE_REG(Device->PCR3,  0x00000018U);
  601.     WRITE_REG(Device->SR3,   0x00000040U);
  602.     WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
  603.     WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
  604.   }
  605.  
  606.   return HAL_OK;
  607. }
  608.  
  609. /**
  610.   * @}
  611.   */
  612.  
  613.  
  614. /** @defgroup FSMC_NAND_Exported_Functions_Group2 Peripheral Control functions
  615.   *  @brief   management functions
  616.   *
  617. @verbatim
  618.   ==============================================================================
  619.                        ##### FSMC_NAND Control functions #####
  620.   ==============================================================================
  621.   [..]
  622.     This subsection provides a set of functions allowing to control dynamically
  623.     the FSMC NAND interface.
  624.  
  625. @endverbatim
  626.   * @{
  627.   */
  628.  
  629. /**
  630.   * @brief  Enables dynamically FSMC_NAND ECC feature.
  631.   * @param  Device: Pointer to NAND device instance
  632.   * @param  Bank: NAND bank number
  633.   * @retval HAL status
  634.   */
  635. HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  636. {
  637.   /* Check the parameters */
  638.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  639.   assert_param(IS_FSMC_NAND_BANK(Bank));
  640.  
  641.   /* Enable ECC feature */
  642.   if(Bank == FSMC_NAND_BANK2)
  643.   {
  644.     SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
  645.   }
  646.   else
  647.   {
  648.     SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
  649.   }
  650.  
  651.   return HAL_OK;
  652. }
  653.  
  654. /**
  655.   * @brief  Disables dynamically FSMC_NAND ECC feature.
  656.   * @param  Device: Pointer to NAND device instance
  657.   * @param  Bank: NAND bank number
  658.   * @retval HAL status
  659.   */
  660. HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  661. {
  662.   /* Check the parameters */
  663.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  664.   assert_param(IS_FSMC_NAND_BANK(Bank));
  665.  
  666.   /* Disable ECC feature */
  667.   if(Bank == FSMC_NAND_BANK2)
  668.   {
  669.     CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
  670.   }
  671.   else
  672.   {
  673.     CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
  674.   }
  675.  
  676.   return HAL_OK;
  677. }
  678.  
  679. /**
  680.   * @brief  Disables dynamically FSMC_NAND ECC feature.
  681.   * @param  Device: Pointer to NAND device instance
  682.   * @param  ECCval: Pointer to ECC value
  683.   * @param  Bank: NAND bank number
  684.   * @param  Timeout: Timeout wait value  
  685.   * @retval HAL status
  686.   */
  687. HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
  688. {
  689.   uint32_t tickstart = 0U;
  690.  
  691.   /* Check the parameters */
  692.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  693.   assert_param(IS_FSMC_NAND_BANK(Bank));
  694.  
  695.   /* Get tick */
  696.   tickstart = HAL_GetTick();
  697.  
  698.   /* Wait until FIFO is empty */
  699.   while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
  700.   {
  701.     /* Check for the Timeout */
  702.     if(Timeout != HAL_MAX_DELAY)
  703.     {
  704.       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
  705.       {
  706.         return HAL_TIMEOUT;
  707.       }
  708.     }
  709.   }
  710.  
  711.   if(Bank == FSMC_NAND_BANK2)
  712.   {
  713.     /* Get the ECCR2 register value */
  714.     *ECCval = (uint32_t)Device->ECCR2;
  715.   }
  716.   else
  717.   {
  718.     /* Get the ECCR3 register value */
  719.     *ECCval = (uint32_t)Device->ECCR3;
  720.   }
  721.  
  722.   return HAL_OK;
  723. }
  724.  
  725. /**
  726.   * @}
  727.   */
  728.  
  729. /**
  730.   * @}
  731.   */
  732.  
  733. /** @defgroup FSMC_PCCARD FSMC PCCARD Controller functions
  734.   * @brief    PCCARD Controller functions
  735.   *
  736.   @verbatim
  737.   ==============================================================================
  738.                     ##### How to use PCCARD device driver #####
  739.   ==============================================================================
  740.   [..]
  741.     This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
  742.     to run the PCCARD/compact flash external devices.
  743.  
  744.     (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
  745.     (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
  746.     (+) FSMC PCCARD bank common space timing configuration using the function
  747.         FSMC_PCCARD_CommonSpace_Timing_Init()
  748.     (+) FSMC PCCARD bank attribute space timing configuration using the function
  749.         FSMC_PCCARD_AttributeSpace_Timing_Init()
  750.     (+) FSMC PCCARD bank IO space timing configuration using the function
  751.         FSMC_PCCARD_IOSpace_Timing_Init()
  752.  
  753. @endverbatim
  754.   * @{
  755.   */
  756.  
  757. /** @defgroup FSMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
  758.   *  @brief    Initialization and Configuration functions
  759.   *
  760. @verbatim
  761.   ==============================================================================
  762.               ##### Initialization and de_initialization functions #####
  763.   ==============================================================================
  764.   [..]
  765.     This section provides functions allowing to:
  766.     (+) Initialize and configure the FSMC PCCARD interface
  767.     (+) De-initialize the FSMC PCCARD interface
  768.     (+) Configure the FSMC clock and associated GPIOs
  769.  
  770. @endverbatim
  771.   * @{
  772.   */
  773.  
  774. /**
  775.   * @brief  Initializes the FSMC_PCCARD device according to the specified
  776.   *         control parameters in the FSMC_PCCARD_HandleTypeDef
  777.   * @param  Device: Pointer to PCCARD device instance
  778.   * @param  Init: Pointer to PCCARD Initialization structure
  779.   * @retval HAL status
  780.   */
  781. HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
  782. {
  783.   /* Check the parameters */
  784.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  785.   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
  786.   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
  787.   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
  788.  
  789.   /* Set FSMC_PCCARD device control parameters */
  790.   MODIFY_REG(Device->PCR4,
  791.              (FSMC_PCRx_PTYP | FSMC_PCRx_PWAITEN |  FSMC_PCRx_PWID  |
  792.               FSMC_PCRx_TCLR | FSMC_PCRx_TAR),
  793.              (FSMC_PCR_MEMORY_TYPE_PCCARD                           |
  794.               Init->Waitfeature                                     |
  795.               FSMC_NAND_PCC_MEM_BUS_WIDTH_16                        |
  796.               (Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos)           |
  797.               (Init->TARSetupTime << FSMC_PCRx_TAR_Pos)));
  798.  
  799.   return HAL_OK;
  800.  
  801. }
  802.  
  803. /**
  804.   * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
  805.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  806.   * @param  Device: Pointer to PCCARD device instance
  807.   * @param  Timing: Pointer to PCCARD timing structure
  808.   * @retval HAL status
  809.   */
  810. HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
  811. {
  812.   /* Check the parameters */
  813.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  814.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  815.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  816.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  817.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  818.  
  819.   /* Set PCCARD timing parameters */
  820.   MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
  821.              (Timing->SetupTime                                     |
  822.               ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos)  |
  823.               ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos)  |
  824.               ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
  825.  
  826.   return HAL_OK;
  827. }
  828.  
  829. /**
  830.   * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
  831.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  832.   * @param  Device: Pointer to PCCARD device instance
  833.   * @param  Timing: Pointer to PCCARD timing structure
  834.   * @retval HAL status
  835.   */
  836. HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
  837. {
  838.   /* Check the parameters */
  839.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  840.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  841.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  842.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  843.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  844.  
  845.   /* Set PCCARD timing parameters */
  846.   MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK,                          \
  847.              (Timing->SetupTime                                     | \
  848.               ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos)  | \
  849.               ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos)  | \
  850.               ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
  851.  
  852.   return HAL_OK;
  853. }
  854.  
  855. /**
  856.   * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
  857.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  858.   * @param  Device: Pointer to PCCARD device instance
  859.   * @param  Timing: Pointer to PCCARD timing structure
  860.   * @retval HAL status
  861.   */
  862. HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
  863. {
  864.   /* Check the parameters */
  865.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  866.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  867.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  868.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  869.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  870.  
  871.   /* Set FSMC_PCCARD device timing parameters */
  872.   MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,                        \
  873.              (Timing->SetupTime                                  | \
  874.               (Timing->WaitSetupTime   << FSMC_PIO4_IOWAIT4_Pos) | \
  875.               (Timing->HoldSetupTime   << FSMC_PIO4_IOHOLD4_Pos) | \
  876.               (Timing->HiZSetupTime    << FSMC_PIO4_IOHIZ4_Pos)));
  877.  
  878.   return HAL_OK;
  879. }
  880.  
  881. /**
  882.   * @brief  DeInitializes the FSMC_PCCARD device
  883.   * @param  Device: Pointer to PCCARD device instance
  884.   * @retval HAL status
  885.   */
  886. HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
  887. {
  888.   /* Check the parameters */
  889.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  890.  
  891.   /* Disable the FSMC_PCCARD device */
  892.   __FSMC_PCCARD_DISABLE(Device);
  893.  
  894.   /* De-initialize the FSMC_PCCARD device */
  895.   WRITE_REG(Device->PCR4,  0x00000018U);
  896.   WRITE_REG(Device->SR4,   0x00000040U);
  897.   WRITE_REG(Device->PMEM4, 0xFCFCFCFCU);
  898.   WRITE_REG(Device->PATT4, 0xFCFCFCFCU);
  899.   WRITE_REG(Device->PIO4,  0xFCFCFCFCU);
  900.  
  901.   return HAL_OK;
  902. }
  903.  
  904. /**
  905.   * @}
  906.   */
  907.  
  908. /**
  909.   * @}
  910.   */
  911. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  912.  
  913. /**
  914.   * @}
  915.   */
  916.  
  917. /**
  918.   * @}
  919.   */
  920.  
  921. #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
  922.  
  923. #endif /* FSMC_BANK1 */
  924.  
  925. /**
  926.   * @}
  927.   */
  928.  
  929. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  930.