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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_fsmc.c
  4.   * @author  MCD Application Team
  5.   * @version V1.0.1
  6.   * @date    31-July-2015
  7.   * @brief   FSMC Low Layer HAL module driver.
  8.   *    
  9.   *          This file provides firmware functions to manage the following
  10.   *          functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
  11.   *           + Initialization/de-initialization functions
  12.   *           + Peripheral Control functions
  13.   *           + Peripheral State functions
  14.   *        
  15.   @verbatim
  16.   =============================================================================
  17.                         ##### FSMC peripheral features #####
  18.   =============================================================================
  19.     [..] The Flexible static memory controller (FSMC) includes following memory controllers:
  20.          (+) The NOR/PSRAM memory controller
  21.          (+) The NAND/PC Card memory controller (except STM32F100xE devices)
  22.        
  23.     [..] The FSMC functional block makes the interface with synchronous and asynchronous static
  24.          memories and 16-bit PC memory cards. Its main purposes are:
  25.          (+) to translate AHB transactions into the appropriate external device protocol.
  26.          (+) to meet the access time requirements of the external memory devices.
  27.    
  28.     [..] All external memories share the addresses, data and control signals with the controller.
  29.          Each external device is accessed by means of a unique Chip Select. The FSMC performs
  30.          only one access at a time to an external device.
  31.          The main features of the FSMC controller are the following:
  32.           (+) Interface with static-memory mapped devices including:
  33.              (++) Static random access memory (SRAM).
  34.              (++) NOR Flash memory.
  35.              (++) PSRAM (4 memory banks).
  36.              (++) 16-bit PC Card compatible devices
  37.              (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  38.                 data
  39.           (+) Independent Chip Select control for each memory bank
  40.           (+) Independent configuration for each memory bank
  41.        
  42.   @endverbatim
  43.   ******************************************************************************
  44.   * @attention
  45.   *
  46.   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  47.   *
  48.   * Redistribution and use in source and binary forms, with or without modification,
  49.   * are permitted provided that the following conditions are met:
  50.   *   1. Redistributions of source code must retain the above copyright notice,
  51.   *      this list of conditions and the following disclaimer.
  52.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  53.   *      this list of conditions and the following disclaimer in the documentation
  54.   *      and/or other materials provided with the distribution.
  55.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  56.   *      may be used to endorse or promote products derived from this software
  57.   *      without specific prior written permission.
  58.   *
  59.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  60.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  61.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  62.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  63.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  64.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  65.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  66.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  67.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  68.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  69.   *
  70.   ******************************************************************************
  71.   */
  72.  
  73. /* Includes ------------------------------------------------------------------*/
  74. #include "stm32f1xx_hal.h"
  75.  
  76. /** @addtogroup STM32F1xx_HAL_Driver
  77.   * @{
  78.   */
  79.  
  80. #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
  81.  
  82. #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
  83.  
  84. /** @defgroup FSMC_LL FSMC_LL
  85.   * @brief FSMC driver modules
  86.   * @{
  87.   */
  88.  
  89. /* Private typedef -----------------------------------------------------------*/
  90. /* Private define ------------------------------------------------------------*/
  91. /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
  92.   * @{
  93.   */
  94.  
  95. /* ----------------------- FMC registers bit mask --------------------------- */
  96. /* --- PCR Register ---*/
  97. /* PCR register clear mask */
  98. #define PCR_CLEAR_MASK    ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PTYP    | FSMC_PCRx_PWID  | \
  99.                                       FSMC_PCRx_ECCEN   | FSMC_PCRx_TCLR    |                   \
  100.                                       FSMC_PCRx_TAR     | FSMC_PCRx_ECCPS))
  101.  
  102. /* --- SR Register ---*/
  103. /* SR register clear mask */
  104. #define SR_CLEAR_MASK     ((uint32_t)(FSMC_SRx_IRS | FSMC_SRx_ILS | FSMC_SRx_IFS | \
  105.                                       FSMC_SRx_IREN | FSMC_SRx_ILEN | FSMC_SRx_IFEN))
  106.  
  107. /* --- PMEM Register ---*/
  108. /* PMEM register clear mask */
  109. #define PMEM_CLEAR_MASK   ((uint32_t)(FSMC_PMEMx_MEMSETx  | FSMC_PMEMx_MEMWAITx |\
  110.                                       FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx))
  111.  
  112. /* --- PATT Register ---*/
  113. /* PATT register clear mask */
  114. #define PATT_CLEAR_MASK   ((uint32_t)(FSMC_PATTx_ATTSETx  | FSMC_PATTx_ATTWAITx |\
  115.                                       FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx))
  116.  
  117. /* --- PIO4 Register ---*/
  118. /* PIO4 register clear mask */
  119. #define PIO4_CLEAR_MASK   ((uint32_t)(FSMC_PIO4_IOSET4    | FSMC_PIO4_IOWAIT4   | \
  120.                                       FSMC_PIO4_IOHOLD4   | FSMC_PIO4_IOHIZ4))
  121. /**
  122.   * @}
  123.   */
  124.  
  125. /* Private macro -------------------------------------------------------------*/    
  126. /** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros
  127.   * @{
  128.   */
  129.  
  130. /**
  131.   * @}
  132.   */
  133.  
  134. /* Private variables ---------------------------------------------------------*/
  135. /* Private function prototypes -----------------------------------------------*/
  136. /* Exported functions --------------------------------------------------------*/
  137.  
  138. /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
  139.   * @{
  140.   */
  141.  
  142. /** @defgroup FSMC_NORSRAM FSMC NORSRAM Controller functions
  143.   * @brief    NORSRAM Controller functions
  144.   *
  145.   @verbatim
  146.   ==============================================================================  
  147.                    ##### How to use NORSRAM device driver #####
  148.   ==============================================================================
  149.  
  150.   [..]
  151.     This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
  152.     to run the NORSRAM external devices.
  153.      
  154.     (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
  155.     (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
  156.     (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
  157.     (+) FSMC NORSRAM bank extended timing configuration using the function
  158.         FSMC_NORSRAM_Extended_Timing_Init()
  159.     (+) FSMC NORSRAM bank enable/disable write operation using the functions
  160.         FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
  161.        
  162.  
  163. @endverbatim
  164.   * @{
  165.   */
  166.  
  167. /** @defgroup FSMC_NORSRAM_Group1 Initialization/de-initialization functions
  168.   * @brief    Initialization and Configuration functions
  169.   *
  170.   @verbatim    
  171.   ==============================================================================
  172.               ##### Initialization and de_initialization functions #####
  173.   ==============================================================================
  174.   [..]  
  175.     This section provides functions allowing to:
  176.     (+) Initialize and configure the FSMC NORSRAM interface
  177.     (+) De-initialize the FSMC NORSRAM interface
  178.     (+) Configure the FSMC clock and associated GPIOs    
  179.  
  180. @endverbatim
  181.   * @{
  182.   */
  183.  
  184. /**
  185.   * @brief  Initialize the FSMC_NORSRAM device according to the specified
  186.   *         control parameters in the FSMC_NORSRAM_InitTypeDef
  187.   * @param  Device: Pointer to NORSRAM device instance
  188.   * @param  Init: Pointer to NORSRAM Initialization structure  
  189.   * @retval HAL status
  190.   */
  191. HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
  192. {
  193.   /* Check the parameters */
  194.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  195.   assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
  196.   assert_param(IS_FSMC_MUX(Init->DataAddressMux));
  197.   assert_param(IS_FSMC_MEMORY(Init->MemoryType));
  198.   assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
  199.   assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
  200.   assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
  201.   assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
  202.   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
  203.   assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
  204.   assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
  205.   assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
  206.   assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
  207.   assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
  208.  
  209.   /* Disable NORSRAM Device */
  210.   __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);  
  211.  
  212.   /* Set NORSRAM device control parameters */
  213.   if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
  214.   {
  215.     MODIFY_REG(Device->BTCR[Init->NSBank], \
  216.       (FSMC_BCRx_FACCEN                 | FSMC_BCRx_MUXEN       | FSMC_BCRx_MTYP                                        | \
  217.       FSMC_BCRx_MWID        | FSMC_BCRx_BURSTEN     | FSMC_BCRx_WAITPOL         | FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \
  218.       FSMC_BCRx_WREN        | FSMC_BCRx_WAITEN  | FSMC_BCRx_EXTMOD    | FSMC_BCRx_ASYNCWAIT     | FSMC_BCRx_CBURSTRW),    \
  219.       (FSMC_NORSRAM_FLASH_ACCESS_ENABLE | Init->DataAddressMux  | Init->MemoryType                                      | \
  220.       Init->MemoryDataWidth | Init->BurstAccessMode | Init->WaitSignalPolarity  | Init->WrapMode    | Init->WaitSignalActive |\
  221.       Init->WriteOperation  | Init->WaitSignal  | Init->ExtendedMode  | Init->AsynchronousWait  | Init->WriteBurst )      \
  222.       );
  223.   }
  224.   else
  225.   {
  226.     MODIFY_REG(Device->BTCR[Init->NSBank], \
  227.       (FSMC_BCRx_FACCEN                  | FSMC_BCRx_MUXEN      | FSMC_BCRx_MTYP                                        | \
  228.       FSMC_BCRx_MWID        | FSMC_BCRx_BURSTEN     | FSMC_BCRx_WAITPOL         | FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \
  229.       FSMC_BCRx_WREN        | FSMC_BCRx_WAITEN  | FSMC_BCRx_EXTMOD    | FSMC_BCRx_ASYNCWAIT     | FSMC_BCRx_CBURSTRW),    \
  230.       (FSMC_NORSRAM_FLASH_ACCESS_DISABLE | Init->DataAddressMux | Init->MemoryType                                      | \
  231.       Init->MemoryDataWidth | Init->BurstAccessMode | Init->WaitSignalPolarity  | Init->WrapMode    | Init->WaitSignalActive |\
  232.       Init->WriteOperation  | Init->WaitSignal  | Init->ExtendedMode  | Init->AsynchronousWait  | Init->WriteBurst )      \
  233.       );
  234.   }
  235.  
  236.   return HAL_OK;
  237. }
  238.  
  239.  
  240. /**
  241.   * @brief  DeInitialize the FSMC_NORSRAM peripheral
  242.   * @param  Device: Pointer to NORSRAM device instance
  243.   * @param  ExDevice: Pointer to NORSRAM extended mode device instance  
  244.   * @param  Bank: NORSRAM bank number  
  245.   * @retval HAL status
  246.   */
  247. HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
  248. {
  249.   /* Check the parameters */
  250.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  251.   assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
  252.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  253.  
  254.   /* Disable the FSMC_NORSRAM device */
  255.   __FSMC_NORSRAM_DISABLE(Device, Bank);
  256.  
  257.   /* De-initialize the FSMC_NORSRAM device */
  258.   /* FSMC_NORSRAM_BANK1 */
  259.   if(Bank == FSMC_NORSRAM_BANK1)
  260.   {
  261.     Device->BTCR[Bank] = 0x000030DB;    
  262.   }
  263.   /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
  264.   else
  265.   {  
  266.     Device->BTCR[Bank] = 0x000030D2;
  267.   }
  268.  
  269.   Device->BTCR[Bank + 1] = 0x0FFFFFFF;
  270.   ExDevice->BWTR[Bank]   = 0x0FFFFFFF;
  271.    
  272.   return HAL_OK;
  273. }
  274.  
  275.  
  276. /**
  277.   * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
  278.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  279.   * @param  Device: Pointer to NORSRAM device instance
  280.   * @param  Timing: Pointer to NORSRAM Timing structure
  281.   * @param  Bank: NORSRAM bank number  
  282.   * @retval HAL status
  283.   */
  284. HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
  285. {
  286.   /* Check the parameters */
  287.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  288.   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  289.   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  290.   assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  291.   assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  292.   assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  293.   assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  294.   assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  295.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  296.  
  297.   /* Set FSMC_NORSRAM device timing parameters */  
  298.   MODIFY_REG(Device->BTCR[Bank + 1],                                              \
  299.     (FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD | FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN | \
  300.     FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT | FSMC_BTRx_ACCMOD),                      \
  301.     ( Timing->AddressSetupTime                                                  | \
  302.     ((Timing->AddressHoldTime)        << POSITION_VAL(FSMC_BTRx_ADDHLD))        | \
  303.     ((Timing->DataSetupTime)          << POSITION_VAL(FSMC_BTRx_DATAST))        | \
  304.     ((Timing->BusTurnAroundDuration)  << POSITION_VAL(FSMC_BTRx_BUSTURN))       | \
  305.     (((Timing->CLKDivision)-1)        << POSITION_VAL(FSMC_BTRx_CLKDIV))        | \
  306.     (((Timing->DataLatency)-2)        << POSITION_VAL(FSMC_BTRx_DATLAT))        | \
  307.     (Timing->AccessMode)));
  308.  
  309.   return HAL_OK;  
  310. }
  311.  
  312. /**
  313.   * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
  314.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  315.   * @param  Device: Pointer to NORSRAM device instance
  316.   * @param  Timing: Pointer to NORSRAM Timing structure
  317.   * @param  Bank: NORSRAM bank number  
  318.   * @param  ExtendedMode: FSMC Extended Mode
  319.   *          This parameter can be one of the following values:
  320.   *            @arg FSMC_EXTENDED_MODE_DISABLE
  321.   *            @arg FSMC_EXTENDED_MODE_ENABLE
  322.   * @retval HAL status
  323.   */
  324. HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
  325. {
  326.   /* Check the parameters */
  327.   assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
  328.  
  329.   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  330.   if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
  331.   {
  332.     /* Check the parameters */  
  333.     assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));  
  334.     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  335.     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  336.     assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  337. #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  338.     assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  339. #else
  340.     assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  341.     assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  342. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  343.     assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  344.     assert_param(IS_FSMC_NORSRAM_BANK(Bank));  
  345.  
  346. #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  347.     MODIFY_REG(Device->BWTR[Bank],                                                \
  348.       (FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | FSMC_BWTRx_BUSTURN), \
  349.       (Timing->AddressSetupTime                                                 | \
  350.       ((Timing->AddressHoldTime)        << POSITION_VAL(FSMC_BWTRx_ADDHLD))     | \
  351.       ((Timing->DataSetupTime)          << POSITION_VAL(FSMC_BWTRx_DATAST))     | \
  352.       Timing->AccessMode                                                        | \
  353.       ((Timing->BusTurnAroundDuration)  << POSITION_VAL(FSMC_BWTRx_BUSTURN))));
  354. #else
  355.     MODIFY_REG(Device->BWTR[Bank],                                                \
  356.       (FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | FSMC_BWTRx_CLKDIV | FSMC_BWTRx_DATLAT), \
  357.       (Timing->AddressSetupTime                 | \
  358.       ((Timing->AddressHoldTime)  << POSITION_VAL(FSMC_BWTRx_ADDHLD))           | \
  359.       ((Timing->DataSetupTime)    << POSITION_VAL(FSMC_BWTRx_DATAST))           | \
  360.       Timing->AccessMode                                                        | \
  361.       (((Timing->CLKDivision)-1)  << POSITION_VAL(FSMC_BTRx_CLKDIV))            | \
  362.       (((Timing->DataLatency)-2)  << POSITION_VAL(FSMC_BWTRx_DATLAT))));
  363. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  364.   }
  365.   else                                        
  366.   {
  367.     Device->BWTR[Bank] = 0x0FFFFFFF;
  368.   }  
  369.  
  370.   return HAL_OK;  
  371. }
  372.  
  373.  
  374. /**
  375.   * @}
  376.   */
  377.  
  378.  
  379. /** @defgroup FSMC_NORSRAM_Group2 Control functions
  380.  *  @brief   management functions
  381.  *
  382. @verbatim  
  383.   ==============================================================================
  384.                       ##### FSMC_NORSRAM Control functions #####
  385.   ==============================================================================
  386.   [..]
  387.     This subsection provides a set of functions allowing to control dynamically
  388.     the FSMC NORSRAM interface.
  389.  
  390. @endverbatim
  391.   * @{
  392.   */
  393.    
  394. /**
  395.   * @brief  Enables dynamically FSMC_NORSRAM write operation.
  396.   * @param  Device: Pointer to NORSRAM device instance
  397.   * @param  Bank: NORSRAM bank number  
  398.   * @retval HAL status
  399.   */
  400. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  401. {
  402.   /* Check the parameters */
  403.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  404.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  405.  
  406.   /* Enable write operation */
  407.   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  408.  
  409.   return HAL_OK;  
  410. }
  411.  
  412. /**
  413.   * @brief  Disables dynamically FSMC_NORSRAM write operation.
  414.   * @param  Device: Pointer to NORSRAM device instance
  415.   * @param  Bank: NORSRAM bank number  
  416.   * @retval HAL status
  417.   */
  418. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  419. {
  420.   /* Check the parameters */
  421.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  422.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  423.    
  424.   /* Disable write operation */
  425.   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  426.  
  427.   return HAL_OK;  
  428. }
  429.  
  430. /**
  431.   * @}
  432.   */
  433.  
  434. /**
  435.   * @}
  436.   */
  437. #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  438. /** @defgroup FSMC_NAND FSMC NAND Controller functions
  439.   * @brief    NAND Controller functions
  440.   *
  441.   @verbatim
  442.   ==============================================================================
  443.                     ##### How to use NAND device driver #####
  444.   ==============================================================================
  445.   [..]
  446.     This driver contains a set of APIs to interface with the FSMC NAND banks in order
  447.     to run the NAND external devices.
  448.  
  449.     (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
  450.     (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
  451.     (+) FSMC NAND bank common space timing configuration using the function
  452.         FSMC_NAND_CommonSpace_Timing_Init()
  453.     (+) FSMC NAND bank attribute space timing configuration using the function
  454.         FSMC_NAND_AttributeSpace_Timing_Init()
  455.     (+) FSMC NAND bank enable/disable ECC correction feature using the functions
  456.         FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
  457.     (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()    
  458.  
  459. @endverbatim
  460.   * @{
  461.   */
  462.    
  463. /** @defgroup FSMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
  464.  *  @brief    Initialization and Configuration functions
  465.  *
  466. @verbatim    
  467.   ==============================================================================
  468.               ##### Initialization and de_initialization functions #####
  469.   ==============================================================================
  470.   [..]  
  471.     This section provides functions allowing to:
  472.     (+) Initialize and configure the FSMC NAND interface
  473.     (+) De-initialize the FSMC NAND interface
  474.     (+) Configure the FSMC clock and associated GPIOs
  475.        
  476. @endverbatim
  477.   * @{
  478.   */
  479.  
  480. /**
  481.   * @brief  Initializes the FSMC_NAND device according to the specified
  482.   *         control parameters in the FSMC_NAND_HandleTypeDef
  483.   * @param  Device: Pointer to NAND device instance
  484.   * @param  Init: Pointer to NAND Initialization structure
  485.   * @retval HAL status
  486.   */
  487. HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
  488. {
  489.   /* Check the parameters */
  490.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  491.   assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
  492.   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
  493.   assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
  494.   assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
  495.   assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
  496.   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
  497.   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));  
  498.  
  499.   if(Init->NandBank == FSMC_NAND_BANK2)
  500.   {
  501.     /* NAND bank 2 registers configuration */
  502.     MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                  |\
  503.                    FSMC_PCR_MEMORY_TYPE_NAND                                     |\
  504.                    Init->MemoryDataWidth                                         |\
  505.                    Init->EccComputation                                          |\
  506.                    Init->ECCPageSize                                             |\
  507.                    ((Init->TCLRSetupTime) << POSITION_VAL(FSMC_PCRx_TCLR))       |\
  508.                    ((Init->TARSetupTime) << POSITION_VAL(FSMC_PCRx_TAR))));  
  509.   }
  510.   else
  511.   {
  512.     /* NAND bank 3 registers configuration */
  513.     MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                  |\
  514.                    FSMC_PCR_MEMORY_TYPE_NAND                                     |\
  515.                    Init->MemoryDataWidth                                         |\
  516.                    Init->EccComputation                                          |\
  517.                    Init->ECCPageSize                                             |\
  518.                    ((Init->TCLRSetupTime) << POSITION_VAL(FSMC_PCRx_TCLR))       |\
  519.                    ((Init->TARSetupTime) << POSITION_VAL(FSMC_PCRx_TAR))));  
  520.   }
  521.  
  522.   return HAL_OK;
  523.  
  524. }
  525.  
  526. /**
  527.   * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
  528.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  529.   * @param  Device: Pointer to NAND device instance
  530.   * @param  Timing: Pointer to NAND timing structure
  531.   * @param  Bank: NAND bank number  
  532.   * @retval HAL status
  533.   */
  534. HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  535. {
  536.   /* Check the parameters */
  537.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  538.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  539.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  540.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  541.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  542.   assert_param(IS_FSMC_NAND_BANK(Bank));
  543.  
  544.   if(Bank == FSMC_NAND_BANK2)
  545.   {
  546.     /* NAND bank 2 registers configuration */
  547.     MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                      |\
  548.                    ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx))      |\
  549.                    ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx))      |\
  550.                    ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx))));
  551.  
  552.   }
  553.   else
  554.   {
  555.     /* NAND bank 3 registers configuration */
  556.     MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                      |\
  557.                    ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx))      |\
  558.                    ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx))      |\
  559.                    ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx))));
  560.   }  
  561.  
  562.   return HAL_OK;  
  563. }
  564.  
  565. /**
  566.   * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
  567.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  568.   * @param  Device: Pointer to NAND device instance
  569.   * @param  Timing: Pointer to NAND timing structure
  570.   * @param  Bank: NAND bank number
  571.   * @retval HAL status
  572.   */
  573. HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  574. {
  575.   /* Check the parameters */
  576.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  577.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  578.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  579.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  580.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  581.   assert_param(IS_FSMC_NAND_BANK(Bank));
  582.  
  583.   if(Bank == FSMC_NAND_BANK2)
  584.   {
  585.     /* NAND bank 2 registers configuration */
  586.     MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                       |\
  587.                    ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx))       |\
  588.                    ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx))       |\
  589.                    ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx))));
  590.   }
  591.   else
  592.   {
  593.     /* NAND bank 3 registers configuration */
  594.     MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                       |\
  595.                    ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx))       |\
  596.                    ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx))       |\
  597.                    ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx))));
  598.   }  
  599.  
  600.   return HAL_OK;
  601. }
  602.  
  603.  
  604. /**
  605.   * @brief  DeInitializes the FSMC_NAND device
  606.   * @param  Device: Pointer to NAND device instance
  607.   * @param  Bank: NAND bank number
  608.   * @retval HAL status
  609.   */
  610. HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  611. {
  612.   /* Check the parameters */
  613.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  614.   assert_param(IS_FSMC_NAND_BANK(Bank));
  615.      
  616.   /* Disable the NAND Bank */
  617.   __FSMC_NAND_DISABLE(Device, Bank);
  618.  
  619.   /* De-initialize the NAND Bank */
  620.   if(Bank == FSMC_NAND_BANK2)
  621.   {
  622.     /* Set the FSMC_NAND_BANK2 registers to their reset values */
  623.     WRITE_REG(Device->PCR2,  0x00000018);
  624.     WRITE_REG(Device->SR2,   0x00000040);
  625.     WRITE_REG(Device->PMEM2, 0xFCFCFCFC);
  626.     WRITE_REG(Device->PATT2, 0xFCFCFCFC);
  627.   }
  628.   /* FSMC_Bank3_NAND */  
  629.   else
  630.   {
  631.     /* Set the FSMC_NAND_BANK3 registers to their reset values */
  632.     WRITE_REG(Device->PCR3,  0x00000018);
  633.     WRITE_REG(Device->SR3,   0x00000040);
  634.     WRITE_REG(Device->PMEM3, 0xFCFCFCFC);
  635.     WRITE_REG(Device->PATT3, 0xFCFCFCFC);
  636.   }
  637.  
  638.   return HAL_OK;
  639. }
  640.  
  641. /**
  642.   * @}
  643.   */
  644.  
  645.  
  646. /** @defgroup FSMC_NAND_Exported_Functions_Group2 Peripheral Control functions
  647.  *  @brief   management functions
  648.  *
  649. @verbatim  
  650.   ==============================================================================
  651.                        ##### FSMC_NAND Control functions #####
  652.   ==============================================================================  
  653.   [..]
  654.     This subsection provides a set of functions allowing to control dynamically
  655.     the FSMC NAND interface.
  656.  
  657. @endverbatim
  658.   * @{
  659.   */
  660.  
  661.    
  662. /**
  663.   * @brief  Enables dynamically FSMC_NAND ECC feature.
  664.   * @param  Device: Pointer to NAND device instance
  665.   * @param  Bank: NAND bank number
  666.   * @retval HAL status
  667.   */    
  668. HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
  669. {
  670.   /* Check the parameters */
  671.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  672.   assert_param(IS_FSMC_NAND_BANK(Bank));
  673.    
  674.   /* Enable ECC feature */
  675.   if(Bank == FSMC_NAND_BANK2)
  676.   {
  677.     SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
  678.   }
  679.   else
  680.   {
  681.     SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
  682.   }
  683.  
  684.   return HAL_OK;  
  685. }
  686.  
  687.  
  688. /**
  689.   * @brief  Disables dynamically FSMC_NAND ECC feature.
  690.   * @param  Device: Pointer to NAND device instance
  691.   * @param  Bank: NAND bank number
  692.   * @retval HAL status
  693.   */  
  694. HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  
  695. {  
  696.   /* Check the parameters */
  697.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  698.   assert_param(IS_FSMC_NAND_BANK(Bank));
  699.    
  700.   /* Disable ECC feature */
  701.   if(Bank == FSMC_NAND_BANK2)
  702.   {
  703.     CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
  704.   }
  705.   else
  706.   {
  707.     CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
  708.   }
  709.  
  710.   return HAL_OK;  
  711. }
  712.  
  713. /**
  714.   * @brief  Disables dynamically FSMC_NAND ECC feature.
  715.   * @param  Device: Pointer to NAND device instance
  716.   * @param  ECCval: Pointer to ECC value
  717.   * @param  Bank: NAND bank number
  718.   * @param  Timeout: Timeout wait value  
  719.   * @retval HAL status
  720.   */
  721. HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
  722. {
  723.   uint32_t tickstart = 0;
  724.  
  725.   /* Check the parameters */
  726.   assert_param(IS_FSMC_NAND_DEVICE(Device));
  727.   assert_param(IS_FSMC_NAND_BANK(Bank));
  728.      
  729.   /* Get tick */
  730.   tickstart = HAL_GetTick();
  731.  
  732.   /* Wait untill FIFO is empty */
  733.   while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
  734.   {
  735.     /* Check for the Timeout */
  736.     if(Timeout != HAL_MAX_DELAY)
  737.     {
  738.       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
  739.       {
  740.         return HAL_TIMEOUT;
  741.       }
  742.     }  
  743.   }
  744.      
  745.   if(Bank == FSMC_NAND_BANK2)
  746.   {    
  747.     /* Get the ECCR2 register value */
  748.     *ECCval = (uint32_t)Device->ECCR2;
  749.   }
  750.   else
  751.   {    
  752.     /* Get the ECCR3 register value */
  753.     *ECCval = (uint32_t)Device->ECCR3;
  754.   }
  755.  
  756.   return HAL_OK;  
  757. }
  758.  
  759. /**
  760.   * @}
  761.   */
  762.  
  763. /**
  764.   * @}
  765.   */
  766.    
  767. /** @defgroup FSMC_PCCARD FSMC PCCARD Controller functions
  768.   * @brief    PCCARD Controller functions
  769.   *
  770.   @verbatim
  771.   ==============================================================================  
  772.                     ##### How to use PCCARD device driver #####
  773.   ==============================================================================
  774.   [..]
  775.     This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
  776.     to run the PCCARD/compact flash external devices.
  777.  
  778.     (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
  779.     (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
  780.     (+) FSMC PCCARD bank common space timing configuration using the function
  781.         FSMC_PCCARD_CommonSpace_Timing_Init()
  782.     (+) FSMC PCCARD bank attribute space timing configuration using the function
  783.         FSMC_PCCARD_AttributeSpace_Timing_Init()
  784.     (+) FSMC PCCARD bank IO space timing configuration using the function
  785.         FSMC_PCCARD_IOSpace_Timing_Init()
  786.  
  787.        
  788. @endverbatim
  789.   * @{
  790.   */
  791.  
  792. /** @defgroup FSMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
  793.  *  @brief    Initialization and Configuration functions
  794.  *
  795. @verbatim    
  796.   ==============================================================================
  797.               ##### Initialization and de_initialization functions #####
  798.   ==============================================================================
  799.   [..]  
  800.     This section provides functions allowing to:
  801.     (+) Initialize and configure the FSMC PCCARD interface
  802.     (+) De-initialize the FSMC PCCARD interface
  803.     (+) Configure the FSMC clock and associated GPIOs
  804.        
  805. @endverbatim
  806.   * @{
  807.   */
  808.  
  809. /**
  810.   * @brief  Initializes the FSMC_PCCARD device according to the specified
  811.   *         control parameters in the FSMC_PCCARD_HandleTypeDef
  812.   * @param  Device: Pointer to PCCARD device instance
  813.   * @param  Init: Pointer to PCCARD Initialization structure  
  814.   * @retval HAL status
  815.   */
  816. HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
  817. {
  818.   /* Check the parameters */
  819.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  820.   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
  821.   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
  822.   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));    
  823.  
  824.   /* Set FSMC_PCCARD device control parameters */
  825.   MODIFY_REG(Device->PCR4,                                  \
  826.     (FSMC_PCRx_PTYP | FSMC_PCRx_PWAITEN |  FSMC_PCRx_PWID  | FSMC_PCRx_TCLR | FSMC_PCRx_TAR), \
  827.     (FSMC_PCR_MEMORY_TYPE_PCCARD                          | \
  828.     Init->Waitfeature                                     | \
  829.     FSMC_NAND_PCC_MEM_BUS_WIDTH_16                        | \
  830.     (Init->TCLRSetupTime << POSITION_VAL(FSMC_PCRx_TCLR)) | \
  831.     (Init->TARSetupTime << POSITION_VAL(FSMC_PCRx_TAR))));
  832.  
  833.   return HAL_OK;
  834.  
  835. }
  836.  
  837. /**
  838.   * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
  839.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  840.   * @param  Device: Pointer to PCCARD device instance
  841.   * @param  Timing: Pointer to PCCARD timing structure
  842.   * @retval HAL status
  843.   */
  844. HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
  845. {
  846.   /* Check the parameters */
  847.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  848.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  849.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  850.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  851.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  852.  
  853.   /* Set PCCARD timing parameters */
  854.   MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,                            \
  855.       (Timing->SetupTime                                              | \
  856.       ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx))  | \
  857.       ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx))  | \
  858.       ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx))));
  859.  
  860.   return HAL_OK;  
  861. }
  862.  
  863. /**
  864.   * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
  865.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  866.   * @param  Device: Pointer to PCCARD device instance
  867.   * @param  Timing: Pointer to PCCARD timing structure  
  868.   * @retval HAL status
  869.   */
  870. HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
  871. {
  872.   /* Check the parameters */
  873.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  874.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  875.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  876.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  877.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  878.  
  879.   /* Set PCCARD timing parameters */
  880.   MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK,                          \
  881.     (Timing->SetupTime                                              | \
  882.     ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx))  | \
  883.     ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx))   | \
  884.     ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx))));
  885.  
  886.   return HAL_OK;
  887. }
  888.  
  889. /**
  890.   * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
  891.   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
  892.   * @param  Device: Pointer to PCCARD device instance
  893.   * @param  Timing: Pointer to PCCARD timing structure  
  894.   * @retval HAL status
  895.   */
  896. HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
  897. {
  898.   /* Check the parameters */  
  899.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  900.   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
  901.   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
  902.   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
  903.   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
  904.  
  905.   /* Set FSMC_PCCARD device timing parameters */
  906.   MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,                         \
  907.     (Timing->SetupTime                                            | \
  908.     (Timing->WaitSetupTime   << POSITION_VAL(FSMC_PIO4_IOWAIT4)) | \
  909.     (Timing->HoldSetupTime   << POSITION_VAL(FSMC_PIO4_IOHOLD4)) | \
  910.     (Timing->HiZSetupTime    << POSITION_VAL(FSMC_PIO4_IOHIZ4))));
  911.  
  912.   return HAL_OK;
  913. }
  914.                                            
  915. /**
  916.   * @brief  DeInitializes the FSMC_PCCARD device
  917.   * @param  Device: Pointer to PCCARD device instance
  918.   * @retval HAL status
  919.   */
  920. HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
  921. {
  922.   /* Check the parameters */  
  923.   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
  924.    
  925.   /* Disable the FSMC_PCCARD device */
  926.   __FSMC_PCCARD_DISABLE(Device);
  927.  
  928.   /* De-initialize the FSMC_PCCARD device */
  929.   WRITE_REG(Device->PCR4,  0x00000018);
  930.   WRITE_REG(Device->SR4,   0x00000040);
  931.   WRITE_REG(Device->PMEM4, 0xFCFCFCFC);
  932.   WRITE_REG(Device->PATT4, 0xFCFCFCFC);
  933.   WRITE_REG(Device->PIO4,  0xFCFCFCFC);
  934.  
  935.   return HAL_OK;
  936. }
  937.  
  938. /**
  939.   * @}
  940.   */
  941.  
  942. /**
  943.   * @}
  944.   */
  945.  
  946. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  947.  
  948. /**
  949.   * @}
  950.   */
  951.  
  952. /**
  953.   * @}
  954.   */
  955.  
  956. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
  957.  
  958. #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED */
  959.  
  960. /**
  961.   * @}
  962.   */
  963.  
  964. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  965.