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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_tim.c
  4.   * @author  MCD Application Team
  5.   * @brief   TIM HAL module driver.
  6.   *          This file provides firmware functions to manage the following
  7.   *          functionalities of the Timer (TIM) peripheral:
  8.   *           + TIM Time Base Initialization
  9.   *           + TIM Time Base Start
  10.   *           + TIM Time Base Start Interruption
  11.   *           + TIM Time Base Start DMA
  12.   *           + TIM Output Compare/PWM Initialization
  13.   *           + TIM Output Compare/PWM Channel Configuration
  14.   *           + TIM Output Compare/PWM  Start
  15.   *           + TIM Output Compare/PWM  Start Interruption
  16.   *           + TIM Output Compare/PWM Start DMA
  17.   *           + TIM Input Capture Initialization
  18.   *           + TIM Input Capture Channel Configuration
  19.   *           + TIM Input Capture Start
  20.   *           + TIM Input Capture Start Interruption
  21.   *           + TIM Input Capture Start DMA
  22.   *           + TIM One Pulse Initialization
  23.   *           + TIM One Pulse Channel Configuration
  24.   *           + TIM One Pulse Start
  25.   *           + TIM Encoder Interface Initialization
  26.   *           + TIM Encoder Interface Start
  27.   *           + TIM Encoder Interface Start Interruption
  28.   *           + TIM Encoder Interface Start DMA
  29.   *           + Commutation Event configuration with Interruption and DMA
  30.   *           + TIM OCRef clear configuration
  31.   *           + TIM External Clock configuration
  32.   @verbatim
  33.   ==============================================================================
  34.                       ##### TIMER Generic features #####
  35.   ==============================================================================
  36.   [..] The Timer features include:
  37.        (#) 16-bit up, down, up/down auto-reload counter.
  38.        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
  39.            counter clock frequency either by any factor between 1 and 65536.
  40.        (#) Up to 4 independent channels for:
  41.            (++) Input Capture
  42.            (++) Output Compare
  43.            (++) PWM generation (Edge and Center-aligned Mode)
  44.            (++) One-pulse mode output
  45.        (#) Synchronization circuit to control the timer with external signals and to interconnect
  46.             several timers together.
  47.        (#) Supports incremental encoder for positioning purposes
  48.  
  49.             ##### How to use this driver #####
  50.   ==============================================================================
  51.     [..]
  52.      (#) Initialize the TIM low level resources by implementing the following functions
  53.          depending on the selected feature:
  54.            (++) Time Base : HAL_TIM_Base_MspInit()
  55.            (++) Input Capture : HAL_TIM_IC_MspInit()
  56.            (++) Output Compare : HAL_TIM_OC_MspInit()
  57.            (++) PWM generation : HAL_TIM_PWM_MspInit()
  58.            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
  59.            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
  60.  
  61.      (#) Initialize the TIM low level resources :
  62.         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
  63.         (##) TIM pins configuration
  64.             (+++) Enable the clock for the TIM GPIOs using the following function:
  65.              __HAL_RCC_GPIOx_CLK_ENABLE();
  66.             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
  67.  
  68.      (#) The external Clock can be configured, if needed (the default clock is the
  69.          internal clock from the APBx), using the following function:
  70.          HAL_TIM_ConfigClockSource, the clock configuration should be done before
  71.          any start function.
  72.  
  73.      (#) Configure the TIM in the desired functioning mode using one of the
  74.        Initialization function of this driver:
  75.        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
  76.        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
  77.             Output Compare signal.
  78.        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
  79.             PWM signal.
  80.        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
  81.             external signal.
  82.        (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
  83.             in One Pulse Mode.
  84.        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
  85.  
  86.      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
  87.            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
  88.            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
  89.            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
  90.            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
  91.            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
  92.            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
  93.  
  94.      (#) The DMA Burst is managed with the two following functions:
  95.          HAL_TIM_DMABurst_WriteStart()
  96.          HAL_TIM_DMABurst_ReadStart()
  97.  
  98.     *** Callback registration ***
  99.   =============================================
  100.  
  101.   [..]
  102.   The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
  103.   allows the user to configure dynamically the driver callbacks.
  104.  
  105.   [..]
  106.   Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
  107.   @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
  108.   the Callback ID and a pointer to the user callback function.
  109.  
  110.   [..]
  111.   Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
  112.   weak function.
  113.   @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
  114.   and the Callback ID.
  115.  
  116.   [..]
  117.   These functions allow to register/unregister following callbacks:
  118.     (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
  119.     (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
  120.     (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
  121.     (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
  122.     (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
  123.     (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
  124.     (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
  125.     (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
  126.     (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
  127.     (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
  128.     (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
  129.     (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
  130.     (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
  131.     (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
  132.     (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
  133.     (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
  134.     (+) TriggerCallback                   : TIM Trigger Callback.
  135.     (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
  136.     (+) IC_CaptureCallback                : TIM Input Capture Callback.
  137.     (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
  138.     (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
  139.     (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
  140.     (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
  141.     (+) ErrorCallback                     : TIM Error Callback.
  142.     (+) CommutationCallback               : TIM Commutation Callback.
  143.     (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
  144.     (+) BreakCallback                     : TIM Break Callback.
  145.  
  146.   [..]
  147. By default, after the Init and when the state is HAL_TIM_STATE_RESET
  148. all interrupt callbacks are set to the corresponding weak functions:
  149.   examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
  150.  
  151.   [..]
  152.   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
  153.   functionalities in the Init / DeInit only when these callbacks are null
  154.   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
  155.     keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
  156.  
  157.   [..]
  158.     Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
  159.     Exception done MspInit / MspDeInit that can be registered / unregistered
  160.     in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
  161.     thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
  162.   In that case first register the MspInit/MspDeInit user callbacks
  163.       using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
  164.  
  165.   [..]
  166.       When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
  167.       not defined, the callback registration feature is not available and all callbacks
  168.       are set to the corresponding weak functions.
  169.  
  170.   @endverbatim
  171.   ******************************************************************************
  172.   * @attention
  173.   *
  174.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  175.   * All rights reserved.</center></h2>
  176.   *
  177.   * This software component is licensed by ST under BSD 3-Clause license,
  178.   * the "License"; You may not use this file except in compliance with the
  179.   * License. You may obtain a copy of the License at:
  180.   *                        opensource.org/licenses/BSD-3-Clause
  181.   *
  182.   ******************************************************************************
  183.   */
  184.  
  185. /* Includes ------------------------------------------------------------------*/
  186. #include "stm32f1xx_hal.h"
  187.  
  188. /** @addtogroup STM32F1xx_HAL_Driver
  189.   * @{
  190.   */
  191.  
  192. /** @defgroup TIM TIM
  193.   * @brief TIM HAL module driver
  194.   * @{
  195.   */
  196.  
  197. #ifdef HAL_TIM_MODULE_ENABLED
  198.  
  199. /* Private typedef -----------------------------------------------------------*/
  200. /* Private define ------------------------------------------------------------*/
  201. /* Private macros ------------------------------------------------------------*/
  202. /* Private variables ---------------------------------------------------------*/
  203. /* Private function prototypes -----------------------------------------------*/
  204. /** @addtogroup TIM_Private_Functions
  205.   * @{
  206.   */
  207. static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  208. static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  209. static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  210. static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
  211. static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  212.                               uint32_t TIM_ICFilter);
  213. static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
  214. static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  215.                               uint32_t TIM_ICFilter);
  216. static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  217.                               uint32_t TIM_ICFilter);
  218. static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
  219. static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
  220. static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
  221. static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
  222. static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
  223. static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
  224. static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
  225.                                                   TIM_SlaveConfigTypeDef *sSlaveConfig);
  226. /**
  227.   * @}
  228.   */
  229. /* Exported functions --------------------------------------------------------*/
  230.  
  231. /** @defgroup TIM_Exported_Functions TIM Exported Functions
  232.   * @{
  233.   */
  234.  
  235. /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
  236.   *  @brief    Time Base functions
  237.   *
  238. @verbatim
  239.   ==============================================================================
  240.               ##### Time Base functions #####
  241.   ==============================================================================
  242.   [..]
  243.     This section provides functions allowing to:
  244.     (+) Initialize and configure the TIM base.
  245.     (+) De-initialize the TIM base.
  246.     (+) Start the Time Base.
  247.     (+) Stop the Time Base.
  248.     (+) Start the Time Base and enable interrupt.
  249.     (+) Stop the Time Base and disable interrupt.
  250.     (+) Start the Time Base and enable DMA transfer.
  251.     (+) Stop the Time Base and disable DMA transfer.
  252.  
  253. @endverbatim
  254.   * @{
  255.   */
  256. /**
  257.   * @brief  Initializes the TIM Time base Unit according to the specified
  258.   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
  259.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  260.   *         requires a timer reset to avoid unexpected direction
  261.   *         due to DIR bit readonly in center aligned mode.
  262.   *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  263.   * @param  htim TIM Base handle
  264.   * @retval HAL status
  265.   */
  266. HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
  267. {
  268.   /* Check the TIM handle allocation */
  269.   if (htim == NULL)
  270.   {
  271.     return HAL_ERROR;
  272.   }
  273.  
  274.   /* Check the parameters */
  275.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  276.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  277.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  278.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  279.  
  280.   if (htim->State == HAL_TIM_STATE_RESET)
  281.   {
  282.     /* Allocate lock resource and initialize it */
  283.     htim->Lock = HAL_UNLOCKED;
  284.  
  285. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  286.     /* Reset interrupt callbacks to legacy weak callbacks */
  287.     TIM_ResetCallback(htim);
  288.  
  289.     if (htim->Base_MspInitCallback == NULL)
  290.     {
  291.       htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
  292.     }
  293.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  294.     htim->Base_MspInitCallback(htim);
  295. #else
  296.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  297.     HAL_TIM_Base_MspInit(htim);
  298. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  299.   }
  300.  
  301.   /* Set the TIM state */
  302.   htim->State = HAL_TIM_STATE_BUSY;
  303.  
  304.   /* Set the Time Base configuration */
  305.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  306.  
  307.   /* Initialize the DMA burst operation state */
  308.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  309.  
  310.   /* Initialize the TIM channels state */
  311.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  312.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  313.  
  314.   /* Initialize the TIM state*/
  315.   htim->State = HAL_TIM_STATE_READY;
  316.  
  317.   return HAL_OK;
  318. }
  319.  
  320. /**
  321.   * @brief  DeInitializes the TIM Base peripheral
  322.   * @param  htim TIM Base handle
  323.   * @retval HAL status
  324.   */
  325. HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
  326. {
  327.   /* Check the parameters */
  328.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  329.  
  330.   htim->State = HAL_TIM_STATE_BUSY;
  331.  
  332.   /* Disable the TIM Peripheral Clock */
  333.   __HAL_TIM_DISABLE(htim);
  334.  
  335. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  336.   if (htim->Base_MspDeInitCallback == NULL)
  337.   {
  338.     htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
  339.   }
  340.   /* DeInit the low level hardware */
  341.   htim->Base_MspDeInitCallback(htim);
  342. #else
  343.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  344.   HAL_TIM_Base_MspDeInit(htim);
  345. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  346.  
  347.   /* Change the DMA burst operation state */
  348.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  349.  
  350.   /* Change the TIM channels state */
  351.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  352.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  353.  
  354.   /* Change TIM state */
  355.   htim->State = HAL_TIM_STATE_RESET;
  356.  
  357.   /* Release Lock */
  358.   __HAL_UNLOCK(htim);
  359.  
  360.   return HAL_OK;
  361. }
  362.  
  363. /**
  364.   * @brief  Initializes the TIM Base MSP.
  365.   * @param  htim TIM Base handle
  366.   * @retval None
  367.   */
  368. __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
  369. {
  370.   /* Prevent unused argument(s) compilation warning */
  371.   UNUSED(htim);
  372.  
  373.   /* NOTE : This function should not be modified, when the callback is needed,
  374.             the HAL_TIM_Base_MspInit could be implemented in the user file
  375.    */
  376. }
  377.  
  378. /**
  379.   * @brief  DeInitializes TIM Base MSP.
  380.   * @param  htim TIM Base handle
  381.   * @retval None
  382.   */
  383. __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
  384. {
  385.   /* Prevent unused argument(s) compilation warning */
  386.   UNUSED(htim);
  387.  
  388.   /* NOTE : This function should not be modified, when the callback is needed,
  389.             the HAL_TIM_Base_MspDeInit could be implemented in the user file
  390.    */
  391. }
  392.  
  393.  
  394. /**
  395.   * @brief  Starts the TIM Base generation.
  396.   * @param  htim TIM Base handle
  397.   * @retval HAL status
  398.   */
  399. HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
  400. {
  401.   uint32_t tmpsmcr;
  402.  
  403.   /* Check the parameters */
  404.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  405.  
  406.   /* Check the TIM state */
  407.   if (htim->State != HAL_TIM_STATE_READY)
  408.   {
  409.     return HAL_ERROR;
  410.   }
  411.  
  412.   /* Set the TIM state */
  413.   htim->State = HAL_TIM_STATE_BUSY;
  414.  
  415.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  416.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  417.   {
  418.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  419.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  420.     {
  421.       __HAL_TIM_ENABLE(htim);
  422.     }
  423.   }
  424.   else
  425.   {
  426.     __HAL_TIM_ENABLE(htim);
  427.   }
  428.  
  429.   /* Return function status */
  430.   return HAL_OK;
  431. }
  432.  
  433. /**
  434.   * @brief  Stops the TIM Base generation.
  435.   * @param  htim TIM Base handle
  436.   * @retval HAL status
  437.   */
  438. HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
  439. {
  440.   /* Check the parameters */
  441.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  442.  
  443.   /* Disable the Peripheral */
  444.   __HAL_TIM_DISABLE(htim);
  445.  
  446.   /* Set the TIM state */
  447.   htim->State = HAL_TIM_STATE_READY;
  448.  
  449.   /* Return function status */
  450.   return HAL_OK;
  451. }
  452.  
  453. /**
  454.   * @brief  Starts the TIM Base generation in interrupt mode.
  455.   * @param  htim TIM Base handle
  456.   * @retval HAL status
  457.   */
  458. HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
  459. {
  460.   uint32_t tmpsmcr;
  461.  
  462.   /* Check the parameters */
  463.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  464.  
  465.   /* Check the TIM state */
  466.   if (htim->State != HAL_TIM_STATE_READY)
  467.   {
  468.     return HAL_ERROR;
  469.   }
  470.  
  471.   /* Set the TIM state */
  472.   htim->State = HAL_TIM_STATE_BUSY;
  473.  
  474.   /* Enable the TIM Update interrupt */
  475.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
  476.  
  477.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  478.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  479.   {
  480.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  481.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  482.     {
  483.       __HAL_TIM_ENABLE(htim);
  484.     }
  485.   }
  486.   else
  487.   {
  488.     __HAL_TIM_ENABLE(htim);
  489.   }
  490.  
  491.   /* Return function status */
  492.   return HAL_OK;
  493. }
  494.  
  495. /**
  496.   * @brief  Stops the TIM Base generation in interrupt mode.
  497.   * @param  htim TIM Base handle
  498.   * @retval HAL status
  499.   */
  500. HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
  501. {
  502.   /* Check the parameters */
  503.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  504.  
  505.   /* Disable the TIM Update interrupt */
  506.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
  507.  
  508.   /* Disable the Peripheral */
  509.   __HAL_TIM_DISABLE(htim);
  510.  
  511.   /* Set the TIM state */
  512.   htim->State = HAL_TIM_STATE_READY;
  513.  
  514.   /* Return function status */
  515.   return HAL_OK;
  516. }
  517.  
  518. /**
  519.   * @brief  Starts the TIM Base generation in DMA mode.
  520.   * @param  htim TIM Base handle
  521.   * @param  pData The source Buffer address.
  522.   * @param  Length The length of data to be transferred from memory to peripheral.
  523.   * @retval HAL status
  524.   */
  525. HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
  526. {
  527.   uint32_t tmpsmcr;
  528.  
  529.   /* Check the parameters */
  530.   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
  531.  
  532.   /* Set the TIM state */
  533.   if (htim->State == HAL_TIM_STATE_BUSY)
  534.   {
  535.     return HAL_BUSY;
  536.   }
  537.   else if (htim->State == HAL_TIM_STATE_READY)
  538.   {
  539.     if ((pData == NULL) && (Length > 0U))
  540.     {
  541.       return HAL_ERROR;
  542.     }
  543.     else
  544.     {
  545.       htim->State = HAL_TIM_STATE_BUSY;
  546.     }
  547.   }
  548.   else
  549.   {
  550.     return HAL_ERROR;
  551.   }
  552.  
  553.   /* Set the DMA Period elapsed callbacks */
  554.   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  555.   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  556.  
  557.   /* Set the DMA error callback */
  558.   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  559.  
  560.   /* Enable the DMA channel */
  561.   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
  562.   {
  563.     /* Return error status */
  564.     return HAL_ERROR;
  565.   }
  566.  
  567.   /* Enable the TIM Update DMA request */
  568.   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
  569.  
  570.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  571.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  572.   {
  573.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  574.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  575.     {
  576.       __HAL_TIM_ENABLE(htim);
  577.     }
  578.   }
  579.   else
  580.   {
  581.     __HAL_TIM_ENABLE(htim);
  582.   }
  583.  
  584.   /* Return function status */
  585.   return HAL_OK;
  586. }
  587.  
  588. /**
  589.   * @brief  Stops the TIM Base generation in DMA mode.
  590.   * @param  htim TIM Base handle
  591.   * @retval HAL status
  592.   */
  593. HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
  594. {
  595.   /* Check the parameters */
  596.   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
  597.  
  598.   /* Disable the TIM Update DMA request */
  599.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
  600.  
  601.   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  602.  
  603.   /* Disable the Peripheral */
  604.   __HAL_TIM_DISABLE(htim);
  605.  
  606.   /* Set the TIM state */
  607.   htim->State = HAL_TIM_STATE_READY;
  608.  
  609.   /* Return function status */
  610.   return HAL_OK;
  611. }
  612.  
  613. /**
  614.   * @}
  615.   */
  616.  
  617. /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
  618.   *  @brief    TIM Output Compare functions
  619.   *
  620. @verbatim
  621.   ==============================================================================
  622.                   ##### TIM Output Compare functions #####
  623.   ==============================================================================
  624.   [..]
  625.     This section provides functions allowing to:
  626.     (+) Initialize and configure the TIM Output Compare.
  627.     (+) De-initialize the TIM Output Compare.
  628.     (+) Start the TIM Output Compare.
  629.     (+) Stop the TIM Output Compare.
  630.     (+) Start the TIM Output Compare and enable interrupt.
  631.     (+) Stop the TIM Output Compare and disable interrupt.
  632.     (+) Start the TIM Output Compare and enable DMA transfer.
  633.     (+) Stop the TIM Output Compare and disable DMA transfer.
  634.  
  635. @endverbatim
  636.   * @{
  637.   */
  638. /**
  639.   * @brief  Initializes the TIM Output Compare according to the specified
  640.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  641.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  642.   *         requires a timer reset to avoid unexpected direction
  643.   *         due to DIR bit readonly in center aligned mode.
  644.   *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
  645.   * @param  htim TIM Output Compare handle
  646.   * @retval HAL status
  647.   */
  648. HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
  649. {
  650.   /* Check the TIM handle allocation */
  651.   if (htim == NULL)
  652.   {
  653.     return HAL_ERROR;
  654.   }
  655.  
  656.   /* Check the parameters */
  657.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  658.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  659.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  660.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  661.  
  662.   if (htim->State == HAL_TIM_STATE_RESET)
  663.   {
  664.     /* Allocate lock resource and initialize it */
  665.     htim->Lock = HAL_UNLOCKED;
  666.  
  667. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  668.     /* Reset interrupt callbacks to legacy weak callbacks */
  669.     TIM_ResetCallback(htim);
  670.  
  671.     if (htim->OC_MspInitCallback == NULL)
  672.     {
  673.       htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
  674.     }
  675.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  676.     htim->OC_MspInitCallback(htim);
  677. #else
  678.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  679.     HAL_TIM_OC_MspInit(htim);
  680. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  681.   }
  682.  
  683.   /* Set the TIM state */
  684.   htim->State = HAL_TIM_STATE_BUSY;
  685.  
  686.   /* Init the base time for the Output Compare */
  687.   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
  688.  
  689.   /* Initialize the DMA burst operation state */
  690.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  691.  
  692.   /* Initialize the TIM channels state */
  693.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  694.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  695.  
  696.   /* Initialize the TIM state*/
  697.   htim->State = HAL_TIM_STATE_READY;
  698.  
  699.   return HAL_OK;
  700. }
  701.  
  702. /**
  703.   * @brief  DeInitializes the TIM peripheral
  704.   * @param  htim TIM Output Compare handle
  705.   * @retval HAL status
  706.   */
  707. HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
  708. {
  709.   /* Check the parameters */
  710.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  711.  
  712.   htim->State = HAL_TIM_STATE_BUSY;
  713.  
  714.   /* Disable the TIM Peripheral Clock */
  715.   __HAL_TIM_DISABLE(htim);
  716.  
  717. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  718.   if (htim->OC_MspDeInitCallback == NULL)
  719.   {
  720.     htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
  721.   }
  722.   /* DeInit the low level hardware */
  723.   htim->OC_MspDeInitCallback(htim);
  724. #else
  725.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  726.   HAL_TIM_OC_MspDeInit(htim);
  727. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  728.  
  729.   /* Change the DMA burst operation state */
  730.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  731.  
  732.   /* Change the TIM channels state */
  733.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  734.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  735.  
  736.   /* Change TIM state */
  737.   htim->State = HAL_TIM_STATE_RESET;
  738.  
  739.   /* Release Lock */
  740.   __HAL_UNLOCK(htim);
  741.  
  742.   return HAL_OK;
  743. }
  744.  
  745. /**
  746.   * @brief  Initializes the TIM Output Compare MSP.
  747.   * @param  htim TIM Output Compare handle
  748.   * @retval None
  749.   */
  750. __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
  751. {
  752.   /* Prevent unused argument(s) compilation warning */
  753.   UNUSED(htim);
  754.  
  755.   /* NOTE : This function should not be modified, when the callback is needed,
  756.             the HAL_TIM_OC_MspInit could be implemented in the user file
  757.    */
  758. }
  759.  
  760. /**
  761.   * @brief  DeInitializes TIM Output Compare MSP.
  762.   * @param  htim TIM Output Compare handle
  763.   * @retval None
  764.   */
  765. __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
  766. {
  767.   /* Prevent unused argument(s) compilation warning */
  768.   UNUSED(htim);
  769.  
  770.   /* NOTE : This function should not be modified, when the callback is needed,
  771.             the HAL_TIM_OC_MspDeInit could be implemented in the user file
  772.    */
  773. }
  774.  
  775. /**
  776.   * @brief  Starts the TIM Output Compare signal generation.
  777.   * @param  htim TIM Output Compare handle
  778.   * @param  Channel TIM Channel to be enabled
  779.   *          This parameter can be one of the following values:
  780.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  781.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  782.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  783.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  784.   * @retval HAL status
  785.   */
  786. HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  787. {
  788.   uint32_t tmpsmcr;
  789.  
  790.   /* Check the parameters */
  791.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  792.  
  793.   /* Check the TIM channel state */
  794.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  795.   {
  796.     return HAL_ERROR;
  797.   }
  798.  
  799.   /* Set the TIM channel state */
  800.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  801.  
  802.   /* Enable the Output compare channel */
  803.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  804.  
  805.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  806.   {
  807.     /* Enable the main output */
  808.     __HAL_TIM_MOE_ENABLE(htim);
  809.   }
  810.  
  811.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  812.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  813.   {
  814.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  815.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  816.     {
  817.       __HAL_TIM_ENABLE(htim);
  818.     }
  819.   }
  820.   else
  821.   {
  822.     __HAL_TIM_ENABLE(htim);
  823.   }
  824.  
  825.   /* Return function status */
  826.   return HAL_OK;
  827. }
  828.  
  829. /**
  830.   * @brief  Stops the TIM Output Compare signal generation.
  831.   * @param  htim TIM Output Compare handle
  832.   * @param  Channel TIM Channel to be disabled
  833.   *          This parameter can be one of the following values:
  834.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  835.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  836.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  837.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  838.   * @retval HAL status
  839.   */
  840. HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  841. {
  842.   /* Check the parameters */
  843.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  844.  
  845.   /* Disable the Output compare channel */
  846.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  847.  
  848.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  849.   {
  850.     /* Disable the Main Output */
  851.     __HAL_TIM_MOE_DISABLE(htim);
  852.   }
  853.  
  854.   /* Disable the Peripheral */
  855.   __HAL_TIM_DISABLE(htim);
  856.  
  857.   /* Set the TIM channel state */
  858.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  859.  
  860.   /* Return function status */
  861.   return HAL_OK;
  862. }
  863.  
  864. /**
  865.   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
  866.   * @param  htim TIM Output Compare handle
  867.   * @param  Channel TIM Channel to be enabled
  868.   *          This parameter can be one of the following values:
  869.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  870.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  871.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  872.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  873.   * @retval HAL status
  874.   */
  875. HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  876. {
  877.   uint32_t tmpsmcr;
  878.  
  879.   /* Check the parameters */
  880.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  881.  
  882.   /* Check the TIM channel state */
  883.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  884.   {
  885.     return HAL_ERROR;
  886.   }
  887.  
  888.   /* Set the TIM channel state */
  889.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  890.  
  891.   switch (Channel)
  892.   {
  893.     case TIM_CHANNEL_1:
  894.     {
  895.       /* Enable the TIM Capture/Compare 1 interrupt */
  896.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  897.       break;
  898.     }
  899.  
  900.     case TIM_CHANNEL_2:
  901.     {
  902.       /* Enable the TIM Capture/Compare 2 interrupt */
  903.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  904.       break;
  905.     }
  906.  
  907.     case TIM_CHANNEL_3:
  908.     {
  909.       /* Enable the TIM Capture/Compare 3 interrupt */
  910.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  911.       break;
  912.     }
  913.  
  914.     case TIM_CHANNEL_4:
  915.     {
  916.       /* Enable the TIM Capture/Compare 4 interrupt */
  917.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  918.       break;
  919.     }
  920.  
  921.     default:
  922.       break;
  923.   }
  924.  
  925.   /* Enable the Output compare channel */
  926.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  927.  
  928.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  929.   {
  930.     /* Enable the main output */
  931.     __HAL_TIM_MOE_ENABLE(htim);
  932.   }
  933.  
  934.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  935.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  936.   {
  937.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  938.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  939.     {
  940.       __HAL_TIM_ENABLE(htim);
  941.     }
  942.   }
  943.   else
  944.   {
  945.     __HAL_TIM_ENABLE(htim);
  946.   }
  947.  
  948.   /* Return function status */
  949.   return HAL_OK;
  950. }
  951.  
  952. /**
  953.   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
  954.   * @param  htim TIM Output Compare handle
  955.   * @param  Channel TIM Channel to be disabled
  956.   *          This parameter can be one of the following values:
  957.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  958.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  959.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  960.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  961.   * @retval HAL status
  962.   */
  963. HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  964. {
  965.   /* Check the parameters */
  966.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  967.  
  968.   switch (Channel)
  969.   {
  970.     case TIM_CHANNEL_1:
  971.     {
  972.       /* Disable the TIM Capture/Compare 1 interrupt */
  973.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  974.       break;
  975.     }
  976.  
  977.     case TIM_CHANNEL_2:
  978.     {
  979.       /* Disable the TIM Capture/Compare 2 interrupt */
  980.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  981.       break;
  982.     }
  983.  
  984.     case TIM_CHANNEL_3:
  985.     {
  986.       /* Disable the TIM Capture/Compare 3 interrupt */
  987.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  988.       break;
  989.     }
  990.  
  991.     case TIM_CHANNEL_4:
  992.     {
  993.       /* Disable the TIM Capture/Compare 4 interrupt */
  994.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  995.       break;
  996.     }
  997.  
  998.     default:
  999.       break;
  1000.   }
  1001.  
  1002.   /* Disable the Output compare channel */
  1003.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1004.  
  1005.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1006.   {
  1007.     /* Disable the Main Output */
  1008.     __HAL_TIM_MOE_DISABLE(htim);
  1009.   }
  1010.  
  1011.   /* Disable the Peripheral */
  1012.   __HAL_TIM_DISABLE(htim);
  1013.  
  1014.   /* Set the TIM channel state */
  1015.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1016.  
  1017.   /* Return function status */
  1018.   return HAL_OK;
  1019. }
  1020.  
  1021. /**
  1022.   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
  1023.   * @param  htim TIM Output Compare handle
  1024.   * @param  Channel TIM Channel to be enabled
  1025.   *          This parameter can be one of the following values:
  1026.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1027.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1028.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1029.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1030.   * @param  pData The source Buffer address.
  1031.   * @param  Length The length of data to be transferred from memory to TIM peripheral
  1032.   * @retval HAL status
  1033.   */
  1034. HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
  1035. {
  1036.   uint32_t tmpsmcr;
  1037.  
  1038.   /* Check the parameters */
  1039.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1040.  
  1041.   /* Set the TIM channel state */
  1042.   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
  1043.   {
  1044.     return HAL_BUSY;
  1045.   }
  1046.   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
  1047.   {
  1048.     if ((pData == NULL) && (Length > 0U))
  1049.     {
  1050.       return HAL_ERROR;
  1051.     }
  1052.     else
  1053.     {
  1054.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1055.     }
  1056.   }
  1057.   else
  1058.   {
  1059.     return HAL_ERROR;
  1060.   }
  1061.  
  1062.   switch (Channel)
  1063.   {
  1064.     case TIM_CHANNEL_1:
  1065.     {
  1066.       /* Set the DMA compare callbacks */
  1067.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1068.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1069.  
  1070.       /* Set the DMA error callback */
  1071.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  1072.  
  1073.       /* Enable the DMA channel */
  1074.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
  1075.       {
  1076.         /* Return error status */
  1077.         return HAL_ERROR;
  1078.       }
  1079.  
  1080.       /* Enable the TIM Capture/Compare 1 DMA request */
  1081.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  1082.       break;
  1083.     }
  1084.  
  1085.     case TIM_CHANNEL_2:
  1086.     {
  1087.       /* Set the DMA compare callbacks */
  1088.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1089.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1090.  
  1091.       /* Set the DMA error callback */
  1092.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  1093.  
  1094.       /* Enable the DMA channel */
  1095.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
  1096.       {
  1097.         /* Return error status */
  1098.         return HAL_ERROR;
  1099.       }
  1100.  
  1101.       /* Enable the TIM Capture/Compare 2 DMA request */
  1102.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  1103.       break;
  1104.     }
  1105.  
  1106.     case TIM_CHANNEL_3:
  1107.     {
  1108.       /* Set the DMA compare callbacks */
  1109.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1110.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1111.  
  1112.       /* Set the DMA error callback */
  1113.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  1114.  
  1115.       /* Enable the DMA channel */
  1116.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
  1117.       {
  1118.         /* Return error status */
  1119.         return HAL_ERROR;
  1120.       }
  1121.       /* Enable the TIM Capture/Compare 3 DMA request */
  1122.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  1123.       break;
  1124.     }
  1125.  
  1126.     case TIM_CHANNEL_4:
  1127.     {
  1128.       /* Set the DMA compare callbacks */
  1129.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1130.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1131.  
  1132.       /* Set the DMA error callback */
  1133.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  1134.  
  1135.       /* Enable the DMA channel */
  1136.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
  1137.       {
  1138.         /* Return error status */
  1139.         return HAL_ERROR;
  1140.       }
  1141.       /* Enable the TIM Capture/Compare 4 DMA request */
  1142.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  1143.       break;
  1144.     }
  1145.  
  1146.     default:
  1147.       break;
  1148.   }
  1149.  
  1150.   /* Enable the Output compare channel */
  1151.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1152.  
  1153.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1154.   {
  1155.     /* Enable the main output */
  1156.     __HAL_TIM_MOE_ENABLE(htim);
  1157.   }
  1158.  
  1159.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1160.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1161.   {
  1162.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1163.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1164.     {
  1165.       __HAL_TIM_ENABLE(htim);
  1166.     }
  1167.   }
  1168.   else
  1169.   {
  1170.     __HAL_TIM_ENABLE(htim);
  1171.   }
  1172.  
  1173.   /* Return function status */
  1174.   return HAL_OK;
  1175. }
  1176.  
  1177. /**
  1178.   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
  1179.   * @param  htim TIM Output Compare handle
  1180.   * @param  Channel TIM Channel to be disabled
  1181.   *          This parameter can be one of the following values:
  1182.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1183.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1184.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1185.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1186.   * @retval HAL status
  1187.   */
  1188. HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  1189. {
  1190.   /* Check the parameters */
  1191.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1192.  
  1193.   switch (Channel)
  1194.   {
  1195.     case TIM_CHANNEL_1:
  1196.     {
  1197.       /* Disable the TIM Capture/Compare 1 DMA request */
  1198.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  1199.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  1200.       break;
  1201.     }
  1202.  
  1203.     case TIM_CHANNEL_2:
  1204.     {
  1205.       /* Disable the TIM Capture/Compare 2 DMA request */
  1206.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  1207.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  1208.       break;
  1209.     }
  1210.  
  1211.     case TIM_CHANNEL_3:
  1212.     {
  1213.       /* Disable the TIM Capture/Compare 3 DMA request */
  1214.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  1215.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  1216.       break;
  1217.     }
  1218.  
  1219.     case TIM_CHANNEL_4:
  1220.     {
  1221.       /* Disable the TIM Capture/Compare 4 interrupt */
  1222.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  1223.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  1224.       break;
  1225.     }
  1226.  
  1227.     default:
  1228.       break;
  1229.   }
  1230.  
  1231.   /* Disable the Output compare channel */
  1232.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1233.  
  1234.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1235.   {
  1236.     /* Disable the Main Output */
  1237.     __HAL_TIM_MOE_DISABLE(htim);
  1238.   }
  1239.  
  1240.   /* Disable the Peripheral */
  1241.   __HAL_TIM_DISABLE(htim);
  1242.  
  1243.   /* Set the TIM channel state */
  1244.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1245.  
  1246.   /* Return function status */
  1247.   return HAL_OK;
  1248. }
  1249.  
  1250. /**
  1251.   * @}
  1252.   */
  1253.  
  1254. /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
  1255.   *  @brief    TIM PWM functions
  1256.   *
  1257. @verbatim
  1258.   ==============================================================================
  1259.                           ##### TIM PWM functions #####
  1260.   ==============================================================================
  1261.   [..]
  1262.     This section provides functions allowing to:
  1263.     (+) Initialize and configure the TIM PWM.
  1264.     (+) De-initialize the TIM PWM.
  1265.     (+) Start the TIM PWM.
  1266.     (+) Stop the TIM PWM.
  1267.     (+) Start the TIM PWM and enable interrupt.
  1268.     (+) Stop the TIM PWM and disable interrupt.
  1269.     (+) Start the TIM PWM and enable DMA transfer.
  1270.     (+) Stop the TIM PWM and disable DMA transfer.
  1271.  
  1272. @endverbatim
  1273.   * @{
  1274.   */
  1275. /**
  1276.   * @brief  Initializes the TIM PWM Time Base according to the specified
  1277.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  1278.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  1279.   *         requires a timer reset to avoid unexpected direction
  1280.   *         due to DIR bit readonly in center aligned mode.
  1281.   *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
  1282.   * @param  htim TIM PWM handle
  1283.   * @retval HAL status
  1284.   */
  1285. HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
  1286. {
  1287.   /* Check the TIM handle allocation */
  1288.   if (htim == NULL)
  1289.   {
  1290.     return HAL_ERROR;
  1291.   }
  1292.  
  1293.   /* Check the parameters */
  1294.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1295.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  1296.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  1297.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  1298.  
  1299.   if (htim->State == HAL_TIM_STATE_RESET)
  1300.   {
  1301.     /* Allocate lock resource and initialize it */
  1302.     htim->Lock = HAL_UNLOCKED;
  1303.  
  1304. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1305.     /* Reset interrupt callbacks to legacy weak callbacks */
  1306.     TIM_ResetCallback(htim);
  1307.  
  1308.     if (htim->PWM_MspInitCallback == NULL)
  1309.     {
  1310.       htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
  1311.     }
  1312.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  1313.     htim->PWM_MspInitCallback(htim);
  1314. #else
  1315.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  1316.     HAL_TIM_PWM_MspInit(htim);
  1317. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1318.   }
  1319.  
  1320.   /* Set the TIM state */
  1321.   htim->State = HAL_TIM_STATE_BUSY;
  1322.  
  1323.   /* Init the base time for the PWM */
  1324.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  1325.  
  1326.   /* Initialize the DMA burst operation state */
  1327.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  1328.  
  1329.   /* Initialize the TIM channels state */
  1330.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  1331.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  1332.  
  1333.   /* Initialize the TIM state*/
  1334.   htim->State = HAL_TIM_STATE_READY;
  1335.  
  1336.   return HAL_OK;
  1337. }
  1338.  
  1339. /**
  1340.   * @brief  DeInitializes the TIM peripheral
  1341.   * @param  htim TIM PWM handle
  1342.   * @retval HAL status
  1343.   */
  1344. HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
  1345. {
  1346.   /* Check the parameters */
  1347.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1348.  
  1349.   htim->State = HAL_TIM_STATE_BUSY;
  1350.  
  1351.   /* Disable the TIM Peripheral Clock */
  1352.   __HAL_TIM_DISABLE(htim);
  1353.  
  1354. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1355.   if (htim->PWM_MspDeInitCallback == NULL)
  1356.   {
  1357.     htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
  1358.   }
  1359.   /* DeInit the low level hardware */
  1360.   htim->PWM_MspDeInitCallback(htim);
  1361. #else
  1362.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  1363.   HAL_TIM_PWM_MspDeInit(htim);
  1364. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1365.  
  1366.   /* Change the DMA burst operation state */
  1367.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  1368.  
  1369.   /* Change the TIM channels state */
  1370.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  1371.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  1372.  
  1373.   /* Change TIM state */
  1374.   htim->State = HAL_TIM_STATE_RESET;
  1375.  
  1376.   /* Release Lock */
  1377.   __HAL_UNLOCK(htim);
  1378.  
  1379.   return HAL_OK;
  1380. }
  1381.  
  1382. /**
  1383.   * @brief  Initializes the TIM PWM MSP.
  1384.   * @param  htim TIM PWM handle
  1385.   * @retval None
  1386.   */
  1387. __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
  1388. {
  1389.   /* Prevent unused argument(s) compilation warning */
  1390.   UNUSED(htim);
  1391.  
  1392.   /* NOTE : This function should not be modified, when the callback is needed,
  1393.             the HAL_TIM_PWM_MspInit could be implemented in the user file
  1394.    */
  1395. }
  1396.  
  1397. /**
  1398.   * @brief  DeInitializes TIM PWM MSP.
  1399.   * @param  htim TIM PWM handle
  1400.   * @retval None
  1401.   */
  1402. __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
  1403. {
  1404.   /* Prevent unused argument(s) compilation warning */
  1405.   UNUSED(htim);
  1406.  
  1407.   /* NOTE : This function should not be modified, when the callback is needed,
  1408.             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
  1409.    */
  1410. }
  1411.  
  1412. /**
  1413.   * @brief  Starts the PWM signal generation.
  1414.   * @param  htim TIM handle
  1415.   * @param  Channel TIM Channels to be enabled
  1416.   *          This parameter can be one of the following values:
  1417.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1418.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1419.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1420.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1421.   * @retval HAL status
  1422.   */
  1423. HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  1424. {
  1425.   uint32_t tmpsmcr;
  1426.  
  1427.   /* Check the parameters */
  1428.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1429.  
  1430.   /* Check the TIM channel state */
  1431.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  1432.   {
  1433.     return HAL_ERROR;
  1434.   }
  1435.  
  1436.   /* Set the TIM channel state */
  1437.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1438.  
  1439.   /* Enable the Capture compare channel */
  1440.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1441.  
  1442.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1443.   {
  1444.     /* Enable the main output */
  1445.     __HAL_TIM_MOE_ENABLE(htim);
  1446.   }
  1447.  
  1448.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1449.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1450.   {
  1451.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1452.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1453.     {
  1454.       __HAL_TIM_ENABLE(htim);
  1455.     }
  1456.   }
  1457.   else
  1458.   {
  1459.     __HAL_TIM_ENABLE(htim);
  1460.   }
  1461.  
  1462.   /* Return function status */
  1463.   return HAL_OK;
  1464. }
  1465.  
  1466. /**
  1467.   * @brief  Stops the PWM signal generation.
  1468.   * @param  htim TIM PWM handle
  1469.   * @param  Channel TIM Channels to be disabled
  1470.   *          This parameter can be one of the following values:
  1471.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1472.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1473.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1474.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1475.   * @retval HAL status
  1476.   */
  1477. HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  1478. {
  1479.   /* Check the parameters */
  1480.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1481.  
  1482.   /* Disable the Capture compare channel */
  1483.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1484.  
  1485.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1486.   {
  1487.     /* Disable the Main Output */
  1488.     __HAL_TIM_MOE_DISABLE(htim);
  1489.   }
  1490.  
  1491.   /* Disable the Peripheral */
  1492.   __HAL_TIM_DISABLE(htim);
  1493.  
  1494.   /* Set the TIM channel state */
  1495.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1496.  
  1497.   /* Return function status */
  1498.   return HAL_OK;
  1499. }
  1500.  
  1501. /**
  1502.   * @brief  Starts the PWM signal generation in interrupt mode.
  1503.   * @param  htim TIM PWM handle
  1504.   * @param  Channel TIM Channel to be enabled
  1505.   *          This parameter can be one of the following values:
  1506.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1507.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1508.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1509.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1510.   * @retval HAL status
  1511.   */
  1512. HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  1513. {
  1514.   uint32_t tmpsmcr;
  1515.   /* Check the parameters */
  1516.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1517.  
  1518.   /* Check the TIM channel state */
  1519.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  1520.   {
  1521.     return HAL_ERROR;
  1522.   }
  1523.  
  1524.   /* Set the TIM channel state */
  1525.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1526.  
  1527.   switch (Channel)
  1528.   {
  1529.     case TIM_CHANNEL_1:
  1530.     {
  1531.       /* Enable the TIM Capture/Compare 1 interrupt */
  1532.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  1533.       break;
  1534.     }
  1535.  
  1536.     case TIM_CHANNEL_2:
  1537.     {
  1538.       /* Enable the TIM Capture/Compare 2 interrupt */
  1539.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  1540.       break;
  1541.     }
  1542.  
  1543.     case TIM_CHANNEL_3:
  1544.     {
  1545.       /* Enable the TIM Capture/Compare 3 interrupt */
  1546.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  1547.       break;
  1548.     }
  1549.  
  1550.     case TIM_CHANNEL_4:
  1551.     {
  1552.       /* Enable the TIM Capture/Compare 4 interrupt */
  1553.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  1554.       break;
  1555.     }
  1556.  
  1557.     default:
  1558.       break;
  1559.   }
  1560.  
  1561.   /* Enable the Capture compare channel */
  1562.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1563.  
  1564.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1565.   {
  1566.     /* Enable the main output */
  1567.     __HAL_TIM_MOE_ENABLE(htim);
  1568.   }
  1569.  
  1570.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1571.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1572.   {
  1573.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1574.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1575.     {
  1576.       __HAL_TIM_ENABLE(htim);
  1577.     }
  1578.   }
  1579.   else
  1580.   {
  1581.     __HAL_TIM_ENABLE(htim);
  1582.   }
  1583.  
  1584.   /* Return function status */
  1585.   return HAL_OK;
  1586. }
  1587.  
  1588. /**
  1589.   * @brief  Stops the PWM signal generation in interrupt mode.
  1590.   * @param  htim TIM PWM handle
  1591.   * @param  Channel TIM Channels to be disabled
  1592.   *          This parameter can be one of the following values:
  1593.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1594.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1595.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1596.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1597.   * @retval HAL status
  1598.   */
  1599. HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  1600. {
  1601.   /* Check the parameters */
  1602.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1603.  
  1604.   switch (Channel)
  1605.   {
  1606.     case TIM_CHANNEL_1:
  1607.     {
  1608.       /* Disable the TIM Capture/Compare 1 interrupt */
  1609.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  1610.       break;
  1611.     }
  1612.  
  1613.     case TIM_CHANNEL_2:
  1614.     {
  1615.       /* Disable the TIM Capture/Compare 2 interrupt */
  1616.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  1617.       break;
  1618.     }
  1619.  
  1620.     case TIM_CHANNEL_3:
  1621.     {
  1622.       /* Disable the TIM Capture/Compare 3 interrupt */
  1623.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  1624.       break;
  1625.     }
  1626.  
  1627.     case TIM_CHANNEL_4:
  1628.     {
  1629.       /* Disable the TIM Capture/Compare 4 interrupt */
  1630.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  1631.       break;
  1632.     }
  1633.  
  1634.     default:
  1635.       break;
  1636.   }
  1637.  
  1638.   /* Disable the Capture compare channel */
  1639.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1640.  
  1641.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1642.   {
  1643.     /* Disable the Main Output */
  1644.     __HAL_TIM_MOE_DISABLE(htim);
  1645.   }
  1646.  
  1647.   /* Disable the Peripheral */
  1648.   __HAL_TIM_DISABLE(htim);
  1649.  
  1650.   /* Set the TIM channel state */
  1651.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1652.  
  1653.   /* Return function status */
  1654.   return HAL_OK;
  1655. }
  1656.  
  1657. /**
  1658.   * @brief  Starts the TIM PWM signal generation in DMA mode.
  1659.   * @param  htim TIM PWM handle
  1660.   * @param  Channel TIM Channels to be enabled
  1661.   *          This parameter can be one of the following values:
  1662.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1663.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1664.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1665.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1666.   * @param  pData The source Buffer address.
  1667.   * @param  Length The length of data to be transferred from memory to TIM peripheral
  1668.   * @retval HAL status
  1669.   */
  1670. HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
  1671. {
  1672.   uint32_t tmpsmcr;
  1673.  
  1674.   /* Check the parameters */
  1675.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1676.  
  1677.   /* Set the TIM channel state */
  1678.   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
  1679.   {
  1680.     return HAL_BUSY;
  1681.   }
  1682.   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
  1683.   {
  1684.     if ((pData == NULL) && (Length > 0U))
  1685.     {
  1686.       return HAL_ERROR;
  1687.     }
  1688.     else
  1689.     {
  1690.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1691.     }
  1692.   }
  1693.   else
  1694.   {
  1695.     return HAL_ERROR;
  1696.   }
  1697.  
  1698.   switch (Channel)
  1699.   {
  1700.     case TIM_CHANNEL_1:
  1701.     {
  1702.       /* Set the DMA compare callbacks */
  1703.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1704.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1705.  
  1706.       /* Set the DMA error callback */
  1707.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  1708.  
  1709.       /* Enable the DMA channel */
  1710.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
  1711.       {
  1712.         /* Return error status */
  1713.         return HAL_ERROR;
  1714.       }
  1715.  
  1716.       /* Enable the TIM Capture/Compare 1 DMA request */
  1717.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  1718.       break;
  1719.     }
  1720.  
  1721.     case TIM_CHANNEL_2:
  1722.     {
  1723.       /* Set the DMA compare callbacks */
  1724.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1725.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1726.  
  1727.       /* Set the DMA error callback */
  1728.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  1729.  
  1730.       /* Enable the DMA channel */
  1731.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
  1732.       {
  1733.         /* Return error status */
  1734.         return HAL_ERROR;
  1735.       }
  1736.       /* Enable the TIM Capture/Compare 2 DMA request */
  1737.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  1738.       break;
  1739.     }
  1740.  
  1741.     case TIM_CHANNEL_3:
  1742.     {
  1743.       /* Set the DMA compare callbacks */
  1744.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1745.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1746.  
  1747.       /* Set the DMA error callback */
  1748.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  1749.  
  1750.       /* Enable the DMA channel */
  1751.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
  1752.       {
  1753.         /* Return error status */
  1754.         return HAL_ERROR;
  1755.       }
  1756.       /* Enable the TIM Output Capture/Compare 3 request */
  1757.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  1758.       break;
  1759.     }
  1760.  
  1761.     case TIM_CHANNEL_4:
  1762.     {
  1763.       /* Set the DMA compare callbacks */
  1764.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1765.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1766.  
  1767.       /* Set the DMA error callback */
  1768.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  1769.  
  1770.       /* Enable the DMA channel */
  1771.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
  1772.       {
  1773.         /* Return error status */
  1774.         return HAL_ERROR;
  1775.       }
  1776.       /* Enable the TIM Capture/Compare 4 DMA request */
  1777.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  1778.       break;
  1779.     }
  1780.  
  1781.     default:
  1782.       break;
  1783.   }
  1784.  
  1785.   /* Enable the Capture compare channel */
  1786.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1787.  
  1788.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1789.   {
  1790.     /* Enable the main output */
  1791.     __HAL_TIM_MOE_ENABLE(htim);
  1792.   }
  1793.  
  1794.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1795.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1796.   {
  1797.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1798.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1799.     {
  1800.       __HAL_TIM_ENABLE(htim);
  1801.     }
  1802.   }
  1803.   else
  1804.   {
  1805.     __HAL_TIM_ENABLE(htim);
  1806.   }
  1807.  
  1808.   /* Return function status */
  1809.   return HAL_OK;
  1810. }
  1811.  
  1812. /**
  1813.   * @brief  Stops the TIM PWM signal generation in DMA mode.
  1814.   * @param  htim TIM PWM handle
  1815.   * @param  Channel TIM Channels to be disabled
  1816.   *          This parameter can be one of the following values:
  1817.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1818.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1819.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1820.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1821.   * @retval HAL status
  1822.   */
  1823. HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  1824. {
  1825.   /* Check the parameters */
  1826.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1827.  
  1828.   switch (Channel)
  1829.   {
  1830.     case TIM_CHANNEL_1:
  1831.     {
  1832.       /* Disable the TIM Capture/Compare 1 DMA request */
  1833.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  1834.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  1835.       break;
  1836.     }
  1837.  
  1838.     case TIM_CHANNEL_2:
  1839.     {
  1840.       /* Disable the TIM Capture/Compare 2 DMA request */
  1841.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  1842.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  1843.       break;
  1844.     }
  1845.  
  1846.     case TIM_CHANNEL_3:
  1847.     {
  1848.       /* Disable the TIM Capture/Compare 3 DMA request */
  1849.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  1850.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  1851.       break;
  1852.     }
  1853.  
  1854.     case TIM_CHANNEL_4:
  1855.     {
  1856.       /* Disable the TIM Capture/Compare 4 interrupt */
  1857.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  1858.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  1859.       break;
  1860.     }
  1861.  
  1862.     default:
  1863.       break;
  1864.   }
  1865.  
  1866.   /* Disable the Capture compare channel */
  1867.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1868.  
  1869.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1870.   {
  1871.     /* Disable the Main Output */
  1872.     __HAL_TIM_MOE_DISABLE(htim);
  1873.   }
  1874.  
  1875.   /* Disable the Peripheral */
  1876.   __HAL_TIM_DISABLE(htim);
  1877.  
  1878.   /* Set the TIM channel state */
  1879.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1880.  
  1881.   /* Return function status */
  1882.   return HAL_OK;
  1883. }
  1884.  
  1885. /**
  1886.   * @}
  1887.   */
  1888.  
  1889. /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
  1890.   *  @brief    TIM Input Capture functions
  1891.   *
  1892. @verbatim
  1893.   ==============================================================================
  1894.               ##### TIM Input Capture functions #####
  1895.   ==============================================================================
  1896.  [..]
  1897.    This section provides functions allowing to:
  1898.    (+) Initialize and configure the TIM Input Capture.
  1899.    (+) De-initialize the TIM Input Capture.
  1900.    (+) Start the TIM Input Capture.
  1901.    (+) Stop the TIM Input Capture.
  1902.    (+) Start the TIM Input Capture and enable interrupt.
  1903.    (+) Stop the TIM Input Capture and disable interrupt.
  1904.    (+) Start the TIM Input Capture and enable DMA transfer.
  1905.    (+) Stop the TIM Input Capture and disable DMA transfer.
  1906.  
  1907. @endverbatim
  1908.   * @{
  1909.   */
  1910. /**
  1911.   * @brief  Initializes the TIM Input Capture Time base according to the specified
  1912.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  1913.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  1914.   *         requires a timer reset to avoid unexpected direction
  1915.   *         due to DIR bit readonly in center aligned mode.
  1916.   *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
  1917.   * @param  htim TIM Input Capture handle
  1918.   * @retval HAL status
  1919.   */
  1920. HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
  1921. {
  1922.   /* Check the TIM handle allocation */
  1923.   if (htim == NULL)
  1924.   {
  1925.     return HAL_ERROR;
  1926.   }
  1927.  
  1928.   /* Check the parameters */
  1929.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1930.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  1931.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  1932.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  1933.  
  1934.   if (htim->State == HAL_TIM_STATE_RESET)
  1935.   {
  1936.     /* Allocate lock resource and initialize it */
  1937.     htim->Lock = HAL_UNLOCKED;
  1938.  
  1939. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1940.     /* Reset interrupt callbacks to legacy weak callbacks */
  1941.     TIM_ResetCallback(htim);
  1942.  
  1943.     if (htim->IC_MspInitCallback == NULL)
  1944.     {
  1945.       htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
  1946.     }
  1947.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  1948.     htim->IC_MspInitCallback(htim);
  1949. #else
  1950.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  1951.     HAL_TIM_IC_MspInit(htim);
  1952. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1953.   }
  1954.  
  1955.   /* Set the TIM state */
  1956.   htim->State = HAL_TIM_STATE_BUSY;
  1957.  
  1958.   /* Init the base time for the input capture */
  1959.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  1960.  
  1961.   /* Initialize the DMA burst operation state */
  1962.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  1963.  
  1964.   /* Initialize the TIM channels state */
  1965.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  1966.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  1967.  
  1968.   /* Initialize the TIM state*/
  1969.   htim->State = HAL_TIM_STATE_READY;
  1970.  
  1971.   return HAL_OK;
  1972. }
  1973.  
  1974. /**
  1975.   * @brief  DeInitializes the TIM peripheral
  1976.   * @param  htim TIM Input Capture handle
  1977.   * @retval HAL status
  1978.   */
  1979. HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
  1980. {
  1981.   /* Check the parameters */
  1982.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1983.  
  1984.   htim->State = HAL_TIM_STATE_BUSY;
  1985.  
  1986.   /* Disable the TIM Peripheral Clock */
  1987.   __HAL_TIM_DISABLE(htim);
  1988.  
  1989. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1990.   if (htim->IC_MspDeInitCallback == NULL)
  1991.   {
  1992.     htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
  1993.   }
  1994.   /* DeInit the low level hardware */
  1995.   htim->IC_MspDeInitCallback(htim);
  1996. #else
  1997.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  1998.   HAL_TIM_IC_MspDeInit(htim);
  1999. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2000.  
  2001.   /* Change the DMA burst operation state */
  2002.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  2003.  
  2004.   /* Change the TIM channels state */
  2005.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  2006.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  2007.  
  2008.   /* Change TIM state */
  2009.   htim->State = HAL_TIM_STATE_RESET;
  2010.  
  2011.   /* Release Lock */
  2012.   __HAL_UNLOCK(htim);
  2013.  
  2014.   return HAL_OK;
  2015. }
  2016.  
  2017. /**
  2018.   * @brief  Initializes the TIM Input Capture MSP.
  2019.   * @param  htim TIM Input Capture handle
  2020.   * @retval None
  2021.   */
  2022. __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
  2023. {
  2024.   /* Prevent unused argument(s) compilation warning */
  2025.   UNUSED(htim);
  2026.  
  2027.   /* NOTE : This function should not be modified, when the callback is needed,
  2028.             the HAL_TIM_IC_MspInit could be implemented in the user file
  2029.    */
  2030. }
  2031.  
  2032. /**
  2033.   * @brief  DeInitializes TIM Input Capture MSP.
  2034.   * @param  htim TIM handle
  2035.   * @retval None
  2036.   */
  2037. __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
  2038. {
  2039.   /* Prevent unused argument(s) compilation warning */
  2040.   UNUSED(htim);
  2041.  
  2042.   /* NOTE : This function should not be modified, when the callback is needed,
  2043.             the HAL_TIM_IC_MspDeInit could be implemented in the user file
  2044.    */
  2045. }
  2046.  
  2047. /**
  2048.   * @brief  Starts the TIM Input Capture measurement.
  2049.   * @param  htim TIM Input Capture handle
  2050.   * @param  Channel TIM Channels to be enabled
  2051.   *          This parameter can be one of the following values:
  2052.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2053.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2054.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2055.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2056.   * @retval HAL status
  2057.   */
  2058. HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  2059. {
  2060.   uint32_t tmpsmcr;
  2061.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  2062.   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
  2063.  
  2064.   /* Check the parameters */
  2065.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2066.  
  2067.   /* Check the TIM channel state */
  2068.   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
  2069.       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
  2070.   {
  2071.     return HAL_ERROR;
  2072.   }
  2073.  
  2074.   /* Set the TIM channel state */
  2075.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2076.   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2077.  
  2078.   /* Enable the Input Capture channel */
  2079.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  2080.  
  2081.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  2082.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  2083.   {
  2084.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  2085.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  2086.     {
  2087.       __HAL_TIM_ENABLE(htim);
  2088.     }
  2089.   }
  2090.   else
  2091.   {
  2092.     __HAL_TIM_ENABLE(htim);
  2093.   }
  2094.  
  2095.   /* Return function status */
  2096.   return HAL_OK;
  2097. }
  2098.  
  2099. /**
  2100.   * @brief  Stops the TIM Input Capture measurement.
  2101.   * @param  htim TIM Input Capture handle
  2102.   * @param  Channel TIM Channels to be disabled
  2103.   *          This parameter can be one of the following values:
  2104.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2105.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2106.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2107.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2108.   * @retval HAL status
  2109.   */
  2110. HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  2111. {
  2112.   /* Check the parameters */
  2113.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2114.  
  2115.   /* Disable the Input Capture channel */
  2116.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2117.  
  2118.   /* Disable the Peripheral */
  2119.   __HAL_TIM_DISABLE(htim);
  2120.  
  2121.   /* Set the TIM channel state */
  2122.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2123.   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2124.  
  2125.   /* Return function status */
  2126.   return HAL_OK;
  2127. }
  2128.  
  2129. /**
  2130.   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
  2131.   * @param  htim TIM Input Capture handle
  2132.   * @param  Channel TIM Channels to be enabled
  2133.   *          This parameter can be one of the following values:
  2134.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2135.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2136.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2137.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2138.   * @retval HAL status
  2139.   */
  2140. HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  2141. {
  2142.   uint32_t tmpsmcr;
  2143.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  2144.   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
  2145.  
  2146.   /* Check the parameters */
  2147.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2148.  
  2149.   /* Check the TIM channel state */
  2150.   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
  2151.       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
  2152.   {
  2153.     return HAL_ERROR;
  2154.   }
  2155.  
  2156.   /* Set the TIM channel state */
  2157.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2158.   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2159.  
  2160.   switch (Channel)
  2161.   {
  2162.     case TIM_CHANNEL_1:
  2163.     {
  2164.       /* Enable the TIM Capture/Compare 1 interrupt */
  2165.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  2166.       break;
  2167.     }
  2168.  
  2169.     case TIM_CHANNEL_2:
  2170.     {
  2171.       /* Enable the TIM Capture/Compare 2 interrupt */
  2172.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  2173.       break;
  2174.     }
  2175.  
  2176.     case TIM_CHANNEL_3:
  2177.     {
  2178.       /* Enable the TIM Capture/Compare 3 interrupt */
  2179.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  2180.       break;
  2181.     }
  2182.  
  2183.     case TIM_CHANNEL_4:
  2184.     {
  2185.       /* Enable the TIM Capture/Compare 4 interrupt */
  2186.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  2187.       break;
  2188.     }
  2189.  
  2190.     default:
  2191.       break;
  2192.   }
  2193.   /* Enable the Input Capture channel */
  2194.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  2195.  
  2196.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  2197.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  2198.   {
  2199.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  2200.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  2201.     {
  2202.       __HAL_TIM_ENABLE(htim);
  2203.     }
  2204.   }
  2205.   else
  2206.   {
  2207.     __HAL_TIM_ENABLE(htim);
  2208.   }
  2209.  
  2210.   /* Return function status */
  2211.   return HAL_OK;
  2212. }
  2213.  
  2214. /**
  2215.   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
  2216.   * @param  htim TIM Input Capture handle
  2217.   * @param  Channel TIM Channels to be disabled
  2218.   *          This parameter can be one of the following values:
  2219.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2220.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2221.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2222.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2223.   * @retval HAL status
  2224.   */
  2225. HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  2226. {
  2227.   /* Check the parameters */
  2228.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2229.  
  2230.   switch (Channel)
  2231.   {
  2232.     case TIM_CHANNEL_1:
  2233.     {
  2234.       /* Disable the TIM Capture/Compare 1 interrupt */
  2235.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  2236.       break;
  2237.     }
  2238.  
  2239.     case TIM_CHANNEL_2:
  2240.     {
  2241.       /* Disable the TIM Capture/Compare 2 interrupt */
  2242.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  2243.       break;
  2244.     }
  2245.  
  2246.     case TIM_CHANNEL_3:
  2247.     {
  2248.       /* Disable the TIM Capture/Compare 3 interrupt */
  2249.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  2250.       break;
  2251.     }
  2252.  
  2253.     case TIM_CHANNEL_4:
  2254.     {
  2255.       /* Disable the TIM Capture/Compare 4 interrupt */
  2256.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  2257.       break;
  2258.     }
  2259.  
  2260.     default:
  2261.       break;
  2262.   }
  2263.  
  2264.   /* Disable the Input Capture channel */
  2265.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2266.  
  2267.   /* Disable the Peripheral */
  2268.   __HAL_TIM_DISABLE(htim);
  2269.  
  2270.   /* Set the TIM channel state */
  2271.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2272.   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2273.  
  2274.   /* Return function status */
  2275.   return HAL_OK;
  2276. }
  2277.  
  2278. /**
  2279.   * @brief  Starts the TIM Input Capture measurement in DMA mode.
  2280.   * @param  htim TIM Input Capture handle
  2281.   * @param  Channel TIM Channels to be enabled
  2282.   *          This parameter can be one of the following values:
  2283.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2284.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2285.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2286.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2287.   * @param  pData The destination Buffer address.
  2288.   * @param  Length The length of data to be transferred from TIM peripheral to memory.
  2289.   * @retval HAL status
  2290.   */
  2291. HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
  2292. {
  2293.   uint32_t tmpsmcr;
  2294.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  2295.   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
  2296.  
  2297.   /* Check the parameters */
  2298.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2299.   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
  2300.  
  2301.   /* Set the TIM channel state */
  2302.   if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
  2303.       || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
  2304.   {
  2305.     return HAL_BUSY;
  2306.   }
  2307.   else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
  2308.            && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
  2309.   {
  2310.     if ((pData == NULL) && (Length > 0U))
  2311.     {
  2312.       return HAL_ERROR;
  2313.     }
  2314.     else
  2315.     {
  2316.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2317.       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2318.     }
  2319.   }
  2320.   else
  2321.   {
  2322.     return HAL_ERROR;
  2323.   }
  2324.  
  2325.   switch (Channel)
  2326.   {
  2327.     case TIM_CHANNEL_1:
  2328.     {
  2329.       /* Set the DMA capture callbacks */
  2330.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  2331.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2332.  
  2333.       /* Set the DMA error callback */
  2334.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  2335.  
  2336.       /* Enable the DMA channel */
  2337.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
  2338.       {
  2339.         /* Return error status */
  2340.         return HAL_ERROR;
  2341.       }
  2342.       /* Enable the TIM Capture/Compare 1 DMA request */
  2343.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  2344.       break;
  2345.     }
  2346.  
  2347.     case TIM_CHANNEL_2:
  2348.     {
  2349.       /* Set the DMA capture callbacks */
  2350.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  2351.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2352.  
  2353.       /* Set the DMA error callback */
  2354.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  2355.  
  2356.       /* Enable the DMA channel */
  2357.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
  2358.       {
  2359.         /* Return error status */
  2360.         return HAL_ERROR;
  2361.       }
  2362.       /* Enable the TIM Capture/Compare 2  DMA request */
  2363.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  2364.       break;
  2365.     }
  2366.  
  2367.     case TIM_CHANNEL_3:
  2368.     {
  2369.       /* Set the DMA capture callbacks */
  2370.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
  2371.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2372.  
  2373.       /* Set the DMA error callback */
  2374.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  2375.  
  2376.       /* Enable the DMA channel */
  2377.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
  2378.       {
  2379.         /* Return error status */
  2380.         return HAL_ERROR;
  2381.       }
  2382.       /* Enable the TIM Capture/Compare 3  DMA request */
  2383.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  2384.       break;
  2385.     }
  2386.  
  2387.     case TIM_CHANNEL_4:
  2388.     {
  2389.       /* Set the DMA capture callbacks */
  2390.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
  2391.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2392.  
  2393.       /* Set the DMA error callback */
  2394.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  2395.  
  2396.       /* Enable the DMA channel */
  2397.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
  2398.       {
  2399.         /* Return error status */
  2400.         return HAL_ERROR;
  2401.       }
  2402.       /* Enable the TIM Capture/Compare 4  DMA request */
  2403.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  2404.       break;
  2405.     }
  2406.  
  2407.     default:
  2408.       break;
  2409.   }
  2410.  
  2411.   /* Enable the Input Capture channel */
  2412.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  2413.  
  2414.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  2415.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  2416.   {
  2417.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  2418.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  2419.     {
  2420.       __HAL_TIM_ENABLE(htim);
  2421.     }
  2422.   }
  2423.   else
  2424.   {
  2425.     __HAL_TIM_ENABLE(htim);
  2426.   }
  2427.  
  2428.   /* Return function status */
  2429.   return HAL_OK;
  2430. }
  2431.  
  2432. /**
  2433.   * @brief  Stops the TIM Input Capture measurement in DMA mode.
  2434.   * @param  htim TIM Input Capture handle
  2435.   * @param  Channel TIM Channels to be disabled
  2436.   *          This parameter can be one of the following values:
  2437.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2438.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2439.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2440.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2441.   * @retval HAL status
  2442.   */
  2443. HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  2444. {
  2445.   /* Check the parameters */
  2446.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2447.   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
  2448.  
  2449.   /* Disable the Input Capture channel */
  2450.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2451.  
  2452.   switch (Channel)
  2453.   {
  2454.     case TIM_CHANNEL_1:
  2455.     {
  2456.       /* Disable the TIM Capture/Compare 1 DMA request */
  2457.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  2458.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  2459.       break;
  2460.     }
  2461.  
  2462.     case TIM_CHANNEL_2:
  2463.     {
  2464.       /* Disable the TIM Capture/Compare 2 DMA request */
  2465.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  2466.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  2467.       break;
  2468.     }
  2469.  
  2470.     case TIM_CHANNEL_3:
  2471.     {
  2472.       /* Disable the TIM Capture/Compare 3  DMA request */
  2473.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  2474.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  2475.       break;
  2476.     }
  2477.  
  2478.     case TIM_CHANNEL_4:
  2479.     {
  2480.       /* Disable the TIM Capture/Compare 4  DMA request */
  2481.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  2482.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  2483.       break;
  2484.     }
  2485.  
  2486.     default:
  2487.       break;
  2488.   }
  2489.  
  2490.   /* Disable the Peripheral */
  2491.   __HAL_TIM_DISABLE(htim);
  2492.  
  2493.   /* Set the TIM channel state */
  2494.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2495.   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2496.  
  2497.   /* Return function status */
  2498.   return HAL_OK;
  2499. }
  2500. /**
  2501.   * @}
  2502.   */
  2503.  
  2504. /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
  2505.   *  @brief    TIM One Pulse functions
  2506.   *
  2507. @verbatim
  2508.   ==============================================================================
  2509.                         ##### TIM One Pulse functions #####
  2510.   ==============================================================================
  2511.   [..]
  2512.     This section provides functions allowing to:
  2513.     (+) Initialize and configure the TIM One Pulse.
  2514.     (+) De-initialize the TIM One Pulse.
  2515.     (+) Start the TIM One Pulse.
  2516.     (+) Stop the TIM One Pulse.
  2517.     (+) Start the TIM One Pulse and enable interrupt.
  2518.     (+) Stop the TIM One Pulse and disable interrupt.
  2519.     (+) Start the TIM One Pulse and enable DMA transfer.
  2520.     (+) Stop the TIM One Pulse and disable DMA transfer.
  2521.  
  2522. @endverbatim
  2523.   * @{
  2524.   */
  2525. /**
  2526.   * @brief  Initializes the TIM One Pulse Time Base according to the specified
  2527.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  2528.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  2529.   *         requires a timer reset to avoid unexpected direction
  2530.   *         due to DIR bit readonly in center aligned mode.
  2531.   *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
  2532.   * @note   When the timer instance is initialized in One Pulse mode, timer
  2533.   *         channels 1 and channel 2 are reserved and cannot be used for other
  2534.   *         purpose.
  2535.   * @param  htim TIM One Pulse handle
  2536.   * @param  OnePulseMode Select the One pulse mode.
  2537.   *         This parameter can be one of the following values:
  2538.   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
  2539.   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
  2540.   * @retval HAL status
  2541.   */
  2542. HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
  2543. {
  2544.   /* Check the TIM handle allocation */
  2545.   if (htim == NULL)
  2546.   {
  2547.     return HAL_ERROR;
  2548.   }
  2549.  
  2550.   /* Check the parameters */
  2551.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  2552.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  2553.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  2554.   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
  2555.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  2556.  
  2557.   if (htim->State == HAL_TIM_STATE_RESET)
  2558.   {
  2559.     /* Allocate lock resource and initialize it */
  2560.     htim->Lock = HAL_UNLOCKED;
  2561.  
  2562. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2563.     /* Reset interrupt callbacks to legacy weak callbacks */
  2564.     TIM_ResetCallback(htim);
  2565.  
  2566.     if (htim->OnePulse_MspInitCallback == NULL)
  2567.     {
  2568.       htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
  2569.     }
  2570.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  2571.     htim->OnePulse_MspInitCallback(htim);
  2572. #else
  2573.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  2574.     HAL_TIM_OnePulse_MspInit(htim);
  2575. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2576.   }
  2577.  
  2578.   /* Set the TIM state */
  2579.   htim->State = HAL_TIM_STATE_BUSY;
  2580.  
  2581.   /* Configure the Time base in the One Pulse Mode */
  2582.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  2583.  
  2584.   /* Reset the OPM Bit */
  2585.   htim->Instance->CR1 &= ~TIM_CR1_OPM;
  2586.  
  2587.   /* Configure the OPM Mode */
  2588.   htim->Instance->CR1 |= OnePulseMode;
  2589.  
  2590.   /* Initialize the DMA burst operation state */
  2591.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  2592.  
  2593.   /* Initialize the TIM channels state */
  2594.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2595.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2596.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2597.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2598.  
  2599.   /* Initialize the TIM state*/
  2600.   htim->State = HAL_TIM_STATE_READY;
  2601.  
  2602.   return HAL_OK;
  2603. }
  2604.  
  2605. /**
  2606.   * @brief  DeInitializes the TIM One Pulse
  2607.   * @param  htim TIM One Pulse handle
  2608.   * @retval HAL status
  2609.   */
  2610. HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
  2611. {
  2612.   /* Check the parameters */
  2613.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  2614.  
  2615.   htim->State = HAL_TIM_STATE_BUSY;
  2616.  
  2617.   /* Disable the TIM Peripheral Clock */
  2618.   __HAL_TIM_DISABLE(htim);
  2619.  
  2620. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2621.   if (htim->OnePulse_MspDeInitCallback == NULL)
  2622.   {
  2623.     htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
  2624.   }
  2625.   /* DeInit the low level hardware */
  2626.   htim->OnePulse_MspDeInitCallback(htim);
  2627. #else
  2628.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  2629.   HAL_TIM_OnePulse_MspDeInit(htim);
  2630. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2631.  
  2632.   /* Change the DMA burst operation state */
  2633.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  2634.  
  2635.   /* Set the TIM channel state */
  2636.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  2637.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  2638.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  2639.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  2640.  
  2641.   /* Change TIM state */
  2642.   htim->State = HAL_TIM_STATE_RESET;
  2643.  
  2644.   /* Release Lock */
  2645.   __HAL_UNLOCK(htim);
  2646.  
  2647.   return HAL_OK;
  2648. }
  2649.  
  2650. /**
  2651.   * @brief  Initializes the TIM One Pulse MSP.
  2652.   * @param  htim TIM One Pulse handle
  2653.   * @retval None
  2654.   */
  2655. __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
  2656. {
  2657.   /* Prevent unused argument(s) compilation warning */
  2658.   UNUSED(htim);
  2659.  
  2660.   /* NOTE : This function should not be modified, when the callback is needed,
  2661.             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
  2662.    */
  2663. }
  2664.  
  2665. /**
  2666.   * @brief  DeInitializes TIM One Pulse MSP.
  2667.   * @param  htim TIM One Pulse handle
  2668.   * @retval None
  2669.   */
  2670. __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
  2671. {
  2672.   /* Prevent unused argument(s) compilation warning */
  2673.   UNUSED(htim);
  2674.  
  2675.   /* NOTE : This function should not be modified, when the callback is needed,
  2676.             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
  2677.    */
  2678. }
  2679.  
  2680. /**
  2681.   * @brief  Starts the TIM One Pulse signal generation.
  2682.   * @param  htim TIM One Pulse handle
  2683.   * @param  OutputChannel TIM Channels to be enabled
  2684.   *          This parameter can be one of the following values:
  2685.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2686.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2687.   * @retval HAL status
  2688.   */
  2689. HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2690. {
  2691.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  2692.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  2693.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  2694.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  2695.  
  2696.   /* Prevent unused argument(s) compilation warning */
  2697.   UNUSED(OutputChannel);
  2698.  
  2699.   /* Check the TIM channels state */
  2700.   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2701.       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  2702.       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2703.       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  2704.   {
  2705.     return HAL_ERROR;
  2706.   }
  2707.  
  2708.   /* Set the TIM channels state */
  2709.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2710.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2711.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2712.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2713.  
  2714.   /* Enable the Capture compare and the Input Capture channels
  2715.     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2716.     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2717.     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2718.     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
  2719.  
  2720.     No need to enable the counter, it's enabled automatically by hardware
  2721.     (the counter starts in response to a stimulus and generate a pulse */
  2722.  
  2723.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  2724.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  2725.  
  2726.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  2727.   {
  2728.     /* Enable the main output */
  2729.     __HAL_TIM_MOE_ENABLE(htim);
  2730.   }
  2731.  
  2732.   /* Return function status */
  2733.   return HAL_OK;
  2734. }
  2735.  
  2736. /**
  2737.   * @brief  Stops the TIM One Pulse signal generation.
  2738.   * @param  htim TIM One Pulse handle
  2739.   * @param  OutputChannel TIM Channels to be disable
  2740.   *          This parameter can be one of the following values:
  2741.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2742.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2743.   * @retval HAL status
  2744.   */
  2745. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2746. {
  2747.   /* Prevent unused argument(s) compilation warning */
  2748.   UNUSED(OutputChannel);
  2749.  
  2750.   /* Disable the Capture compare and the Input Capture channels
  2751.   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2752.   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2753.   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2754.   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
  2755.  
  2756.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  2757.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  2758.  
  2759.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  2760.   {
  2761.     /* Disable the Main Output */
  2762.     __HAL_TIM_MOE_DISABLE(htim);
  2763.   }
  2764.  
  2765.   /* Disable the Peripheral */
  2766.   __HAL_TIM_DISABLE(htim);
  2767.  
  2768.   /* Set the TIM channels state */
  2769.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2770.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2771.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2772.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2773.  
  2774.   /* Return function status */
  2775.   return HAL_OK;
  2776. }
  2777.  
  2778. /**
  2779.   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
  2780.   * @param  htim TIM One Pulse handle
  2781.   * @param  OutputChannel TIM Channels to be enabled
  2782.   *          This parameter can be one of the following values:
  2783.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2784.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2785.   * @retval HAL status
  2786.   */
  2787. HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2788. {
  2789.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  2790.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  2791.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  2792.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  2793.  
  2794.   /* Prevent unused argument(s) compilation warning */
  2795.   UNUSED(OutputChannel);
  2796.  
  2797.   /* Check the TIM channels state */
  2798.   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2799.       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  2800.       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2801.       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  2802.   {
  2803.     return HAL_ERROR;
  2804.   }
  2805.  
  2806.   /* Set the TIM channels state */
  2807.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2808.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2809.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2810.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2811.  
  2812.   /* Enable the Capture compare and the Input Capture channels
  2813.     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2814.     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2815.     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2816.     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
  2817.  
  2818.     No need to enable the counter, it's enabled automatically by hardware
  2819.     (the counter starts in response to a stimulus and generate a pulse */
  2820.  
  2821.   /* Enable the TIM Capture/Compare 1 interrupt */
  2822.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  2823.  
  2824.   /* Enable the TIM Capture/Compare 2 interrupt */
  2825.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  2826.  
  2827.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  2828.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  2829.  
  2830.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  2831.   {
  2832.     /* Enable the main output */
  2833.     __HAL_TIM_MOE_ENABLE(htim);
  2834.   }
  2835.  
  2836.   /* Return function status */
  2837.   return HAL_OK;
  2838. }
  2839.  
  2840. /**
  2841.   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
  2842.   * @param  htim TIM One Pulse handle
  2843.   * @param  OutputChannel TIM Channels to be enabled
  2844.   *          This parameter can be one of the following values:
  2845.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2846.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2847.   * @retval HAL status
  2848.   */
  2849. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2850. {
  2851.   /* Prevent unused argument(s) compilation warning */
  2852.   UNUSED(OutputChannel);
  2853.  
  2854.   /* Disable the TIM Capture/Compare 1 interrupt */
  2855.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  2856.  
  2857.   /* Disable the TIM Capture/Compare 2 interrupt */
  2858.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  2859.  
  2860.   /* Disable the Capture compare and the Input Capture channels
  2861.   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2862.   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2863.   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2864.   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
  2865.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  2866.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  2867.  
  2868.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  2869.   {
  2870.     /* Disable the Main Output */
  2871.     __HAL_TIM_MOE_DISABLE(htim);
  2872.   }
  2873.  
  2874.   /* Disable the Peripheral */
  2875.   __HAL_TIM_DISABLE(htim);
  2876.  
  2877.   /* Set the TIM channels state */
  2878.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2879.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2880.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2881.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2882.  
  2883.   /* Return function status */
  2884.   return HAL_OK;
  2885. }
  2886.  
  2887. /**
  2888.   * @}
  2889.   */
  2890.  
  2891. /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
  2892.   *  @brief    TIM Encoder functions
  2893.   *
  2894. @verbatim
  2895.   ==============================================================================
  2896.                           ##### TIM Encoder functions #####
  2897.   ==============================================================================
  2898.   [..]
  2899.     This section provides functions allowing to:
  2900.     (+) Initialize and configure the TIM Encoder.
  2901.     (+) De-initialize the TIM Encoder.
  2902.     (+) Start the TIM Encoder.
  2903.     (+) Stop the TIM Encoder.
  2904.     (+) Start the TIM Encoder and enable interrupt.
  2905.     (+) Stop the TIM Encoder and disable interrupt.
  2906.     (+) Start the TIM Encoder and enable DMA transfer.
  2907.     (+) Stop the TIM Encoder and disable DMA transfer.
  2908.  
  2909. @endverbatim
  2910.   * @{
  2911.   */
  2912. /**
  2913.   * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
  2914.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  2915.   *         requires a timer reset to avoid unexpected direction
  2916.   *         due to DIR bit readonly in center aligned mode.
  2917.   *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
  2918.   * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
  2919.   *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
  2920.   *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
  2921.   * @note   When the timer instance is initialized in Encoder mode, timer
  2922.   *         channels 1 and channel 2 are reserved and cannot be used for other
  2923.   *         purpose.
  2924.   * @param  htim TIM Encoder Interface handle
  2925.   * @param  sConfig TIM Encoder Interface configuration structure
  2926.   * @retval HAL status
  2927.   */
  2928. HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
  2929. {
  2930.   uint32_t tmpsmcr;
  2931.   uint32_t tmpccmr1;
  2932.   uint32_t tmpccer;
  2933.  
  2934.   /* Check the TIM handle allocation */
  2935.   if (htim == NULL)
  2936.   {
  2937.     return HAL_ERROR;
  2938.   }
  2939.  
  2940.   /* Check the parameters */
  2941.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  2942.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  2943.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  2944.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  2945.   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
  2946.   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
  2947.   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
  2948.   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
  2949.   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
  2950.   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
  2951.   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
  2952.   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
  2953.   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
  2954.  
  2955.   if (htim->State == HAL_TIM_STATE_RESET)
  2956.   {
  2957.     /* Allocate lock resource and initialize it */
  2958.     htim->Lock = HAL_UNLOCKED;
  2959.  
  2960. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2961.     /* Reset interrupt callbacks to legacy weak callbacks */
  2962.     TIM_ResetCallback(htim);
  2963.  
  2964.     if (htim->Encoder_MspInitCallback == NULL)
  2965.     {
  2966.       htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
  2967.     }
  2968.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  2969.     htim->Encoder_MspInitCallback(htim);
  2970. #else
  2971.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  2972.     HAL_TIM_Encoder_MspInit(htim);
  2973. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2974.   }
  2975.  
  2976.   /* Set the TIM state */
  2977.   htim->State = HAL_TIM_STATE_BUSY;
  2978.  
  2979.   /* Reset the SMS and ECE bits */
  2980.   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
  2981.  
  2982.   /* Configure the Time base in the Encoder Mode */
  2983.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  2984.  
  2985.   /* Get the TIMx SMCR register value */
  2986.   tmpsmcr = htim->Instance->SMCR;
  2987.  
  2988.   /* Get the TIMx CCMR1 register value */
  2989.   tmpccmr1 = htim->Instance->CCMR1;
  2990.  
  2991.   /* Get the TIMx CCER register value */
  2992.   tmpccer = htim->Instance->CCER;
  2993.  
  2994.   /* Set the encoder Mode */
  2995.   tmpsmcr |= sConfig->EncoderMode;
  2996.  
  2997.   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
  2998.   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
  2999.   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
  3000.  
  3001.   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
  3002.   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
  3003.   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
  3004.   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
  3005.   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
  3006.  
  3007.   /* Set the TI1 and the TI2 Polarities */
  3008.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
  3009.   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
  3010.  
  3011.   /* Write to TIMx SMCR */
  3012.   htim->Instance->SMCR = tmpsmcr;
  3013.  
  3014.   /* Write to TIMx CCMR1 */
  3015.   htim->Instance->CCMR1 = tmpccmr1;
  3016.  
  3017.   /* Write to TIMx CCER */
  3018.   htim->Instance->CCER = tmpccer;
  3019.  
  3020.   /* Initialize the DMA burst operation state */
  3021.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  3022.  
  3023.   /* Set the TIM channels state */
  3024.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3025.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3026.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3027.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3028.  
  3029.   /* Initialize the TIM state*/
  3030.   htim->State = HAL_TIM_STATE_READY;
  3031.  
  3032.   return HAL_OK;
  3033. }
  3034.  
  3035.  
  3036. /**
  3037.   * @brief  DeInitializes the TIM Encoder interface
  3038.   * @param  htim TIM Encoder Interface handle
  3039.   * @retval HAL status
  3040.   */
  3041. HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
  3042. {
  3043.   /* Check the parameters */
  3044.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  3045.  
  3046.   htim->State = HAL_TIM_STATE_BUSY;
  3047.  
  3048.   /* Disable the TIM Peripheral Clock */
  3049.   __HAL_TIM_DISABLE(htim);
  3050.  
  3051. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3052.   if (htim->Encoder_MspDeInitCallback == NULL)
  3053.   {
  3054.     htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
  3055.   }
  3056.   /* DeInit the low level hardware */
  3057.   htim->Encoder_MspDeInitCallback(htim);
  3058. #else
  3059.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  3060.   HAL_TIM_Encoder_MspDeInit(htim);
  3061. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3062.  
  3063.   /* Change the DMA burst operation state */
  3064.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  3065.  
  3066.   /* Set the TIM channels state */
  3067.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  3068.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  3069.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  3070.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  3071.  
  3072.   /* Change TIM state */
  3073.   htim->State = HAL_TIM_STATE_RESET;
  3074.  
  3075.   /* Release Lock */
  3076.   __HAL_UNLOCK(htim);
  3077.  
  3078.   return HAL_OK;
  3079. }
  3080.  
  3081. /**
  3082.   * @brief  Initializes the TIM Encoder Interface MSP.
  3083.   * @param  htim TIM Encoder Interface handle
  3084.   * @retval None
  3085.   */
  3086. __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
  3087. {
  3088.   /* Prevent unused argument(s) compilation warning */
  3089.   UNUSED(htim);
  3090.  
  3091.   /* NOTE : This function should not be modified, when the callback is needed,
  3092.             the HAL_TIM_Encoder_MspInit could be implemented in the user file
  3093.    */
  3094. }
  3095.  
  3096. /**
  3097.   * @brief  DeInitializes TIM Encoder Interface MSP.
  3098.   * @param  htim TIM Encoder Interface handle
  3099.   * @retval None
  3100.   */
  3101. __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
  3102. {
  3103.   /* Prevent unused argument(s) compilation warning */
  3104.   UNUSED(htim);
  3105.  
  3106.   /* NOTE : This function should not be modified, when the callback is needed,
  3107.             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
  3108.    */
  3109. }
  3110.  
  3111. /**
  3112.   * @brief  Starts the TIM Encoder Interface.
  3113.   * @param  htim TIM Encoder Interface handle
  3114.   * @param  Channel TIM Channels to be enabled
  3115.   *          This parameter can be one of the following values:
  3116.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3117.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3118.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3119.   * @retval HAL status
  3120.   */
  3121. HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  3122. {
  3123.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  3124.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  3125.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  3126.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  3127.  
  3128.   /* Check the parameters */
  3129.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3130.  
  3131.   /* Set the TIM channel(s) state */
  3132.   if (Channel == TIM_CHANNEL_1)
  3133.   {
  3134.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3135.         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
  3136.     {
  3137.       return HAL_ERROR;
  3138.     }
  3139.     else
  3140.     {
  3141.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3142.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3143.     }
  3144.   }
  3145.   else if (Channel == TIM_CHANNEL_2)
  3146.   {
  3147.     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3148.         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3149.     {
  3150.       return HAL_ERROR;
  3151.     }
  3152.     else
  3153.     {
  3154.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3155.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3156.     }
  3157.   }
  3158.   else
  3159.   {
  3160.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3161.         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3162.         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3163.         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3164.     {
  3165.       return HAL_ERROR;
  3166.     }
  3167.     else
  3168.     {
  3169.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3170.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3171.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3172.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3173.     }
  3174.   }
  3175.  
  3176.   /* Enable the encoder interface channels */
  3177.   switch (Channel)
  3178.   {
  3179.     case TIM_CHANNEL_1:
  3180.     {
  3181.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3182.       break;
  3183.     }
  3184.  
  3185.     case TIM_CHANNEL_2:
  3186.     {
  3187.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3188.       break;
  3189.     }
  3190.  
  3191.     default :
  3192.     {
  3193.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3194.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3195.       break;
  3196.     }
  3197.   }
  3198.   /* Enable the Peripheral */
  3199.   __HAL_TIM_ENABLE(htim);
  3200.  
  3201.   /* Return function status */
  3202.   return HAL_OK;
  3203. }
  3204.  
  3205. /**
  3206.   * @brief  Stops the TIM Encoder Interface.
  3207.   * @param  htim TIM Encoder Interface handle
  3208.   * @param  Channel TIM Channels to be disabled
  3209.   *          This parameter can be one of the following values:
  3210.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3211.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3212.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3213.   * @retval HAL status
  3214.   */
  3215. HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  3216. {
  3217.   /* Check the parameters */
  3218.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3219.  
  3220.   /* Disable the Input Capture channels 1 and 2
  3221.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3222.   switch (Channel)
  3223.   {
  3224.     case TIM_CHANNEL_1:
  3225.     {
  3226.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3227.       break;
  3228.     }
  3229.  
  3230.     case TIM_CHANNEL_2:
  3231.     {
  3232.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3233.       break;
  3234.     }
  3235.  
  3236.     default :
  3237.     {
  3238.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3239.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3240.       break;
  3241.     }
  3242.   }
  3243.  
  3244.   /* Disable the Peripheral */
  3245.   __HAL_TIM_DISABLE(htim);
  3246.  
  3247.   /* Set the TIM channel(s) state */
  3248.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3249.   {
  3250.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3251.     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3252.   }
  3253.   else
  3254.   {
  3255.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3256.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3257.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3258.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3259.   }
  3260.  
  3261.   /* Return function status */
  3262.   return HAL_OK;
  3263. }
  3264.  
  3265. /**
  3266.   * @brief  Starts the TIM Encoder Interface in interrupt mode.
  3267.   * @param  htim TIM Encoder Interface handle
  3268.   * @param  Channel TIM Channels to be enabled
  3269.   *          This parameter can be one of the following values:
  3270.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3271.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3272.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3273.   * @retval HAL status
  3274.   */
  3275. HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  3276. {
  3277.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  3278.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  3279.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  3280.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  3281.  
  3282.   /* Check the parameters */
  3283.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3284.  
  3285.   /* Set the TIM channel(s) state */
  3286.   if (Channel == TIM_CHANNEL_1)
  3287.   {
  3288.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3289.         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
  3290.     {
  3291.       return HAL_ERROR;
  3292.     }
  3293.     else
  3294.     {
  3295.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3296.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3297.     }
  3298.   }
  3299.   else if (Channel == TIM_CHANNEL_2)
  3300.   {
  3301.     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3302.         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3303.     {
  3304.       return HAL_ERROR;
  3305.     }
  3306.     else
  3307.     {
  3308.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3309.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3310.     }
  3311.   }
  3312.   else
  3313.   {
  3314.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3315.         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3316.         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3317.         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3318.     {
  3319.       return HAL_ERROR;
  3320.     }
  3321.     else
  3322.     {
  3323.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3324.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3325.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3326.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3327.     }
  3328.   }
  3329.  
  3330.   /* Enable the encoder interface channels */
  3331.   /* Enable the capture compare Interrupts 1 and/or 2 */
  3332.   switch (Channel)
  3333.   {
  3334.     case TIM_CHANNEL_1:
  3335.     {
  3336.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3337.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  3338.       break;
  3339.     }
  3340.  
  3341.     case TIM_CHANNEL_2:
  3342.     {
  3343.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3344.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  3345.       break;
  3346.     }
  3347.  
  3348.     default :
  3349.     {
  3350.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3351.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3352.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  3353.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  3354.       break;
  3355.     }
  3356.   }
  3357.  
  3358.   /* Enable the Peripheral */
  3359.   __HAL_TIM_ENABLE(htim);
  3360.  
  3361.   /* Return function status */
  3362.   return HAL_OK;
  3363. }
  3364.  
  3365. /**
  3366.   * @brief  Stops the TIM Encoder Interface in interrupt mode.
  3367.   * @param  htim TIM Encoder Interface handle
  3368.   * @param  Channel TIM Channels to be disabled
  3369.   *          This parameter can be one of the following values:
  3370.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3371.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3372.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3373.   * @retval HAL status
  3374.   */
  3375. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  3376. {
  3377.   /* Check the parameters */
  3378.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3379.  
  3380.   /* Disable the Input Capture channels 1 and 2
  3381.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3382.   if (Channel == TIM_CHANNEL_1)
  3383.   {
  3384.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3385.  
  3386.     /* Disable the capture compare Interrupts 1 */
  3387.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  3388.   }
  3389.   else if (Channel == TIM_CHANNEL_2)
  3390.   {
  3391.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3392.  
  3393.     /* Disable the capture compare Interrupts 2 */
  3394.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  3395.   }
  3396.   else
  3397.   {
  3398.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3399.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3400.  
  3401.     /* Disable the capture compare Interrupts 1 and 2 */
  3402.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  3403.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  3404.   }
  3405.  
  3406.   /* Disable the Peripheral */
  3407.   __HAL_TIM_DISABLE(htim);
  3408.  
  3409.   /* Set the TIM channel(s) state */
  3410.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3411.   {
  3412.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3413.     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3414.   }
  3415.   else
  3416.   {
  3417.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3418.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3419.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3420.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3421.   }
  3422.  
  3423.   /* Return function status */
  3424.   return HAL_OK;
  3425. }
  3426.  
  3427. /**
  3428.   * @brief  Starts the TIM Encoder Interface in DMA mode.
  3429.   * @param  htim TIM Encoder Interface handle
  3430.   * @param  Channel TIM Channels to be enabled
  3431.   *          This parameter can be one of the following values:
  3432.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3433.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3434.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3435.   * @param  pData1 The destination Buffer address for IC1.
  3436.   * @param  pData2 The destination Buffer address for IC2.
  3437.   * @param  Length The length of data to be transferred from TIM peripheral to memory.
  3438.   * @retval HAL status
  3439.   */
  3440. HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
  3441.                                             uint32_t *pData2, uint16_t Length)
  3442. {
  3443.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  3444.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  3445.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  3446.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  3447.  
  3448.   /* Check the parameters */
  3449.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3450.  
  3451.   /* Set the TIM channel(s) state */
  3452.   if (Channel == TIM_CHANNEL_1)
  3453.   {
  3454.     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3455.         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
  3456.     {
  3457.       return HAL_BUSY;
  3458.     }
  3459.     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
  3460.              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
  3461.     {
  3462.       if ((pData1 == NULL) && (Length > 0U))
  3463.       {
  3464.         return HAL_ERROR;
  3465.       }
  3466.       else
  3467.       {
  3468.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3469.         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3470.       }
  3471.     }
  3472.     else
  3473.     {
  3474.       return HAL_ERROR;
  3475.     }
  3476.   }
  3477.   else if (Channel == TIM_CHANNEL_2)
  3478.   {
  3479.     if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3480.         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
  3481.     {
  3482.       return HAL_BUSY;
  3483.     }
  3484.     else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
  3485.              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
  3486.     {
  3487.       if ((pData2 == NULL) && (Length > 0U))
  3488.       {
  3489.         return HAL_ERROR;
  3490.       }
  3491.       else
  3492.       {
  3493.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3494.         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3495.       }
  3496.     }
  3497.     else
  3498.     {
  3499.       return HAL_ERROR;
  3500.     }
  3501.   }
  3502.   else
  3503.   {
  3504.     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3505.         || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3506.         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3507.         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
  3508.     {
  3509.       return HAL_BUSY;
  3510.     }
  3511.     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
  3512.              && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
  3513.              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
  3514.              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
  3515.     {
  3516.       if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
  3517.       {
  3518.         return HAL_ERROR;
  3519.       }
  3520.       else
  3521.       {
  3522.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3523.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3524.         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3525.         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3526.       }
  3527.     }
  3528.     else
  3529.     {
  3530.       return HAL_ERROR;
  3531.     }
  3532.   }
  3533.  
  3534.   switch (Channel)
  3535.   {
  3536.     case TIM_CHANNEL_1:
  3537.     {
  3538.       /* Set the DMA capture callbacks */
  3539.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  3540.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3541.  
  3542.       /* Set the DMA error callback */
  3543.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  3544.  
  3545.       /* Enable the DMA channel */
  3546.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
  3547.       {
  3548.         /* Return error status */
  3549.         return HAL_ERROR;
  3550.       }
  3551.       /* Enable the TIM Input Capture DMA request */
  3552.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  3553.  
  3554.       /* Enable the Peripheral */
  3555.       __HAL_TIM_ENABLE(htim);
  3556.  
  3557.       /* Enable the Capture compare channel */
  3558.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3559.       break;
  3560.     }
  3561.  
  3562.     case TIM_CHANNEL_2:
  3563.     {
  3564.       /* Set the DMA capture callbacks */
  3565.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  3566.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3567.  
  3568.       /* Set the DMA error callback */
  3569.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
  3570.       /* Enable the DMA channel */
  3571.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
  3572.       {
  3573.         /* Return error status */
  3574.         return HAL_ERROR;
  3575.       }
  3576.       /* Enable the TIM Input Capture  DMA request */
  3577.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  3578.  
  3579.       /* Enable the Peripheral */
  3580.       __HAL_TIM_ENABLE(htim);
  3581.  
  3582.       /* Enable the Capture compare channel */
  3583.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3584.       break;
  3585.     }
  3586.  
  3587.     case TIM_CHANNEL_ALL:
  3588.     {
  3589.       /* Set the DMA capture callbacks */
  3590.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  3591.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3592.  
  3593.       /* Set the DMA error callback */
  3594.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  3595.  
  3596.       /* Enable the DMA channel */
  3597.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
  3598.       {
  3599.         /* Return error status */
  3600.         return HAL_ERROR;
  3601.       }
  3602.  
  3603.       /* Set the DMA capture callbacks */
  3604.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  3605.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3606.  
  3607.       /* Set the DMA error callback */
  3608.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  3609.  
  3610.       /* Enable the DMA channel */
  3611.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
  3612.       {
  3613.         /* Return error status */
  3614.         return HAL_ERROR;
  3615.       }
  3616.       /* Enable the Peripheral */
  3617.       __HAL_TIM_ENABLE(htim);
  3618.  
  3619.       /* Enable the Capture compare channel */
  3620.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3621.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3622.  
  3623.       /* Enable the TIM Input Capture  DMA request */
  3624.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  3625.       /* Enable the TIM Input Capture  DMA request */
  3626.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  3627.       break;
  3628.     }
  3629.  
  3630.     default:
  3631.       break;
  3632.   }
  3633.  
  3634.   /* Return function status */
  3635.   return HAL_OK;
  3636. }
  3637.  
  3638. /**
  3639.   * @brief  Stops the TIM Encoder Interface in DMA mode.
  3640.   * @param  htim TIM Encoder Interface handle
  3641.   * @param  Channel TIM Channels to be enabled
  3642.   *          This parameter can be one of the following values:
  3643.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3644.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3645.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3646.   * @retval HAL status
  3647.   */
  3648. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  3649. {
  3650.   /* Check the parameters */
  3651.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3652.  
  3653.   /* Disable the Input Capture channels 1 and 2
  3654.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3655.   if (Channel == TIM_CHANNEL_1)
  3656.   {
  3657.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3658.  
  3659.     /* Disable the capture compare DMA Request 1 */
  3660.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  3661.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  3662.   }
  3663.   else if (Channel == TIM_CHANNEL_2)
  3664.   {
  3665.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3666.  
  3667.     /* Disable the capture compare DMA Request 2 */
  3668.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  3669.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  3670.   }
  3671.   else
  3672.   {
  3673.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3674.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3675.  
  3676.     /* Disable the capture compare DMA Request 1 and 2 */
  3677.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  3678.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  3679.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  3680.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  3681.   }
  3682.  
  3683.   /* Disable the Peripheral */
  3684.   __HAL_TIM_DISABLE(htim);
  3685.  
  3686.   /* Set the TIM channel(s) state */
  3687.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3688.   {
  3689.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3690.     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3691.   }
  3692.   else
  3693.   {
  3694.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3695.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3696.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3697.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3698.   }
  3699.  
  3700.   /* Return function status */
  3701.   return HAL_OK;
  3702. }
  3703.  
  3704. /**
  3705.   * @}
  3706.   */
  3707. /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
  3708.   *  @brief    TIM IRQ handler management
  3709.   *
  3710. @verbatim
  3711.   ==============================================================================
  3712.                         ##### IRQ handler management #####
  3713.   ==============================================================================
  3714.   [..]
  3715.     This section provides Timer IRQ handler function.
  3716.  
  3717. @endverbatim
  3718.   * @{
  3719.   */
  3720. /**
  3721.   * @brief  This function handles TIM interrupts requests.
  3722.   * @param  htim TIM  handle
  3723.   * @retval None
  3724.   */
  3725. void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
  3726. {
  3727.   /* Capture compare 1 event */
  3728.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
  3729.   {
  3730.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
  3731.     {
  3732.       {
  3733.         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
  3734.         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  3735.  
  3736.         /* Input capture event */
  3737.         if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
  3738.         {
  3739. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3740.           htim->IC_CaptureCallback(htim);
  3741. #else
  3742.           HAL_TIM_IC_CaptureCallback(htim);
  3743. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3744.         }
  3745.         /* Output compare event */
  3746.         else
  3747.         {
  3748. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3749.           htim->OC_DelayElapsedCallback(htim);
  3750.           htim->PWM_PulseFinishedCallback(htim);
  3751. #else
  3752.           HAL_TIM_OC_DelayElapsedCallback(htim);
  3753.           HAL_TIM_PWM_PulseFinishedCallback(htim);
  3754. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3755.         }
  3756.         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3757.       }
  3758.     }
  3759.   }
  3760.   /* Capture compare 2 event */
  3761.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
  3762.   {
  3763.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
  3764.     {
  3765.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
  3766.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  3767.       /* Input capture event */
  3768.       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
  3769.       {
  3770. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3771.         htim->IC_CaptureCallback(htim);
  3772. #else
  3773.         HAL_TIM_IC_CaptureCallback(htim);
  3774. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3775.       }
  3776.       /* Output compare event */
  3777.       else
  3778.       {
  3779. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3780.         htim->OC_DelayElapsedCallback(htim);
  3781.         htim->PWM_PulseFinishedCallback(htim);
  3782. #else
  3783.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3784.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3785. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3786.       }
  3787.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3788.     }
  3789.   }
  3790.   /* Capture compare 3 event */
  3791.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
  3792.   {
  3793.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
  3794.     {
  3795.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
  3796.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  3797.       /* Input capture event */
  3798.       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
  3799.       {
  3800. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3801.         htim->IC_CaptureCallback(htim);
  3802. #else
  3803.         HAL_TIM_IC_CaptureCallback(htim);
  3804. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3805.       }
  3806.       /* Output compare event */
  3807.       else
  3808.       {
  3809. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3810.         htim->OC_DelayElapsedCallback(htim);
  3811.         htim->PWM_PulseFinishedCallback(htim);
  3812. #else
  3813.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3814.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3815. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3816.       }
  3817.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3818.     }
  3819.   }
  3820.   /* Capture compare 4 event */
  3821.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
  3822.   {
  3823.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
  3824.     {
  3825.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
  3826.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  3827.       /* Input capture event */
  3828.       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
  3829.       {
  3830. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3831.         htim->IC_CaptureCallback(htim);
  3832. #else
  3833.         HAL_TIM_IC_CaptureCallback(htim);
  3834. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3835.       }
  3836.       /* Output compare event */
  3837.       else
  3838.       {
  3839. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3840.         htim->OC_DelayElapsedCallback(htim);
  3841.         htim->PWM_PulseFinishedCallback(htim);
  3842. #else
  3843.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3844.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3845. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3846.       }
  3847.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3848.     }
  3849.   }
  3850.   /* TIM Update event */
  3851.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
  3852.   {
  3853.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
  3854.     {
  3855.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
  3856. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3857.       htim->PeriodElapsedCallback(htim);
  3858. #else
  3859.       HAL_TIM_PeriodElapsedCallback(htim);
  3860. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3861.     }
  3862.   }
  3863.   /* TIM Break input event */
  3864.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
  3865.   {
  3866.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
  3867.     {
  3868.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
  3869. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3870.       htim->BreakCallback(htim);
  3871. #else
  3872.       HAL_TIMEx_BreakCallback(htim);
  3873. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3874.     }
  3875.   }
  3876.   /* TIM Trigger detection event */
  3877.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
  3878.   {
  3879.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
  3880.     {
  3881.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
  3882. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3883.       htim->TriggerCallback(htim);
  3884. #else
  3885.       HAL_TIM_TriggerCallback(htim);
  3886. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3887.     }
  3888.   }
  3889.   /* TIM commutation event */
  3890.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
  3891.   {
  3892.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
  3893.     {
  3894.       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
  3895. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3896.       htim->CommutationCallback(htim);
  3897. #else
  3898.       HAL_TIMEx_CommutCallback(htim);
  3899. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3900.     }
  3901.   }
  3902. }
  3903.  
  3904. /**
  3905.   * @}
  3906.   */
  3907.  
  3908. /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
  3909.   *  @brief    TIM Peripheral Control functions
  3910.   *
  3911. @verbatim
  3912.   ==============================================================================
  3913.                    ##### Peripheral Control functions #####
  3914.   ==============================================================================
  3915.  [..]
  3916.    This section provides functions allowing to:
  3917.       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
  3918.       (+) Configure External Clock source.
  3919.       (+) Configure Complementary channels, break features and dead time.
  3920.       (+) Configure Master and the Slave synchronization.
  3921.       (+) Configure the DMA Burst Mode.
  3922.  
  3923. @endverbatim
  3924.   * @{
  3925.   */
  3926.  
  3927. /**
  3928.   * @brief  Initializes the TIM Output Compare Channels according to the specified
  3929.   *         parameters in the TIM_OC_InitTypeDef.
  3930.   * @param  htim TIM Output Compare handle
  3931.   * @param  sConfig TIM Output Compare configuration structure
  3932.   * @param  Channel TIM Channels to configure
  3933.   *          This parameter can be one of the following values:
  3934.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3935.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3936.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  3937.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  3938.   * @retval HAL status
  3939.   */
  3940. HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
  3941.                                            TIM_OC_InitTypeDef *sConfig,
  3942.                                            uint32_t Channel)
  3943. {
  3944.   /* Check the parameters */
  3945.   assert_param(IS_TIM_CHANNELS(Channel));
  3946.   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
  3947.   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
  3948.  
  3949.   /* Process Locked */
  3950.   __HAL_LOCK(htim);
  3951.  
  3952.   switch (Channel)
  3953.   {
  3954.     case TIM_CHANNEL_1:
  3955.     {
  3956.       /* Check the parameters */
  3957.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  3958.  
  3959.       /* Configure the TIM Channel 1 in Output Compare */
  3960.       TIM_OC1_SetConfig(htim->Instance, sConfig);
  3961.       break;
  3962.     }
  3963.  
  3964.     case TIM_CHANNEL_2:
  3965.     {
  3966.       /* Check the parameters */
  3967.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  3968.  
  3969.       /* Configure the TIM Channel 2 in Output Compare */
  3970.       TIM_OC2_SetConfig(htim->Instance, sConfig);
  3971.       break;
  3972.     }
  3973.  
  3974.     case TIM_CHANNEL_3:
  3975.     {
  3976.       /* Check the parameters */
  3977.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  3978.  
  3979.       /* Configure the TIM Channel 3 in Output Compare */
  3980.       TIM_OC3_SetConfig(htim->Instance, sConfig);
  3981.       break;
  3982.     }
  3983.  
  3984.     case TIM_CHANNEL_4:
  3985.     {
  3986.       /* Check the parameters */
  3987.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  3988.  
  3989.       /* Configure the TIM Channel 4 in Output Compare */
  3990.       TIM_OC4_SetConfig(htim->Instance, sConfig);
  3991.       break;
  3992.     }
  3993.  
  3994.     default:
  3995.       break;
  3996.   }
  3997.  
  3998.   __HAL_UNLOCK(htim);
  3999.  
  4000.   return HAL_OK;
  4001. }
  4002.  
  4003. /**
  4004.   * @brief  Initializes the TIM Input Capture Channels according to the specified
  4005.   *         parameters in the TIM_IC_InitTypeDef.
  4006.   * @param  htim TIM IC handle
  4007.   * @param  sConfig TIM Input Capture configuration structure
  4008.   * @param  Channel TIM Channel to configure
  4009.   *          This parameter can be one of the following values:
  4010.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4011.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4012.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  4013.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  4014.   * @retval HAL status
  4015.   */
  4016. HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
  4017. {
  4018.   /* Check the parameters */
  4019.   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4020.   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
  4021.   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
  4022.   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
  4023.   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
  4024.  
  4025.   /* Process Locked */
  4026.   __HAL_LOCK(htim);
  4027.  
  4028.   if (Channel == TIM_CHANNEL_1)
  4029.   {
  4030.     /* TI1 Configuration */
  4031.     TIM_TI1_SetConfig(htim->Instance,
  4032.                       sConfig->ICPolarity,
  4033.                       sConfig->ICSelection,
  4034.                       sConfig->ICFilter);
  4035.  
  4036.     /* Reset the IC1PSC Bits */
  4037.     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
  4038.  
  4039.     /* Set the IC1PSC value */
  4040.     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
  4041.   }
  4042.   else if (Channel == TIM_CHANNEL_2)
  4043.   {
  4044.     /* TI2 Configuration */
  4045.     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4046.  
  4047.     TIM_TI2_SetConfig(htim->Instance,
  4048.                       sConfig->ICPolarity,
  4049.                       sConfig->ICSelection,
  4050.                       sConfig->ICFilter);
  4051.  
  4052.     /* Reset the IC2PSC Bits */
  4053.     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
  4054.  
  4055.     /* Set the IC2PSC value */
  4056.     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
  4057.   }
  4058.   else if (Channel == TIM_CHANNEL_3)
  4059.   {
  4060.     /* TI3 Configuration */
  4061.     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  4062.  
  4063.     TIM_TI3_SetConfig(htim->Instance,
  4064.                       sConfig->ICPolarity,
  4065.                       sConfig->ICSelection,
  4066.                       sConfig->ICFilter);
  4067.  
  4068.     /* Reset the IC3PSC Bits */
  4069.     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
  4070.  
  4071.     /* Set the IC3PSC value */
  4072.     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
  4073.   }
  4074.   else
  4075.   {
  4076.     /* TI4 Configuration */
  4077.     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  4078.  
  4079.     TIM_TI4_SetConfig(htim->Instance,
  4080.                       sConfig->ICPolarity,
  4081.                       sConfig->ICSelection,
  4082.                       sConfig->ICFilter);
  4083.  
  4084.     /* Reset the IC4PSC Bits */
  4085.     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
  4086.  
  4087.     /* Set the IC4PSC value */
  4088.     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
  4089.   }
  4090.  
  4091.   __HAL_UNLOCK(htim);
  4092.  
  4093.   return HAL_OK;
  4094. }
  4095.  
  4096. /**
  4097.   * @brief  Initializes the TIM PWM  channels according to the specified
  4098.   *         parameters in the TIM_OC_InitTypeDef.
  4099.   * @param  htim TIM PWM handle
  4100.   * @param  sConfig TIM PWM configuration structure
  4101.   * @param  Channel TIM Channels to be configured
  4102.   *          This parameter can be one of the following values:
  4103.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4104.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4105.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  4106.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  4107.   * @retval HAL status
  4108.   */
  4109. HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
  4110.                                             TIM_OC_InitTypeDef *sConfig,
  4111.                                             uint32_t Channel)
  4112. {
  4113.   /* Check the parameters */
  4114.   assert_param(IS_TIM_CHANNELS(Channel));
  4115.   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
  4116.   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
  4117.   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
  4118.  
  4119.   /* Process Locked */
  4120.   __HAL_LOCK(htim);
  4121.  
  4122.   switch (Channel)
  4123.   {
  4124.     case TIM_CHANNEL_1:
  4125.     {
  4126.       /* Check the parameters */
  4127.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4128.  
  4129.       /* Configure the Channel 1 in PWM mode */
  4130.       TIM_OC1_SetConfig(htim->Instance, sConfig);
  4131.  
  4132.       /* Set the Preload enable bit for channel1 */
  4133.       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
  4134.  
  4135.       /* Configure the Output Fast mode */
  4136.       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
  4137.       htim->Instance->CCMR1 |= sConfig->OCFastMode;
  4138.       break;
  4139.     }
  4140.  
  4141.     case TIM_CHANNEL_2:
  4142.     {
  4143.       /* Check the parameters */
  4144.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4145.  
  4146.       /* Configure the Channel 2 in PWM mode */
  4147.       TIM_OC2_SetConfig(htim->Instance, sConfig);
  4148.  
  4149.       /* Set the Preload enable bit for channel2 */
  4150.       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
  4151.  
  4152.       /* Configure the Output Fast mode */
  4153.       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
  4154.       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
  4155.       break;
  4156.     }
  4157.  
  4158.     case TIM_CHANNEL_3:
  4159.     {
  4160.       /* Check the parameters */
  4161.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  4162.  
  4163.       /* Configure the Channel 3 in PWM mode */
  4164.       TIM_OC3_SetConfig(htim->Instance, sConfig);
  4165.  
  4166.       /* Set the Preload enable bit for channel3 */
  4167.       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
  4168.  
  4169.       /* Configure the Output Fast mode */
  4170.       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
  4171.       htim->Instance->CCMR2 |= sConfig->OCFastMode;
  4172.       break;
  4173.     }
  4174.  
  4175.     case TIM_CHANNEL_4:
  4176.     {
  4177.       /* Check the parameters */
  4178.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  4179.  
  4180.       /* Configure the Channel 4 in PWM mode */
  4181.       TIM_OC4_SetConfig(htim->Instance, sConfig);
  4182.  
  4183.       /* Set the Preload enable bit for channel4 */
  4184.       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
  4185.  
  4186.       /* Configure the Output Fast mode */
  4187.       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
  4188.       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
  4189.       break;
  4190.     }
  4191.  
  4192.     default:
  4193.       break;
  4194.   }
  4195.  
  4196.   __HAL_UNLOCK(htim);
  4197.  
  4198.   return HAL_OK;
  4199. }
  4200.  
  4201. /**
  4202.   * @brief  Initializes the TIM One Pulse Channels according to the specified
  4203.   *         parameters in the TIM_OnePulse_InitTypeDef.
  4204.   * @param  htim TIM One Pulse handle
  4205.   * @param  sConfig TIM One Pulse configuration structure
  4206.   * @param  OutputChannel TIM output channel to configure
  4207.   *          This parameter can be one of the following values:
  4208.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4209.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4210.   * @param  InputChannel TIM input Channel to configure
  4211.   *          This parameter can be one of the following values:
  4212.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4213.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4214.   * @note  To output a waveform with a minimum delay user can enable the fast
  4215.   *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
  4216.   *        output is forced in response to the edge detection on TIx input,
  4217.   *        without taking in account the comparison.
  4218.   * @retval HAL status
  4219.   */
  4220. HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
  4221.                                                  uint32_t OutputChannel,  uint32_t InputChannel)
  4222. {
  4223.   TIM_OC_InitTypeDef temp1;
  4224.  
  4225.   /* Check the parameters */
  4226.   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
  4227.   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
  4228.  
  4229.   if (OutputChannel != InputChannel)
  4230.   {
  4231.     /* Process Locked */
  4232.     __HAL_LOCK(htim);
  4233.  
  4234.     htim->State = HAL_TIM_STATE_BUSY;
  4235.  
  4236.     /* Extract the Output compare configuration from sConfig structure */
  4237.     temp1.OCMode = sConfig->OCMode;
  4238.     temp1.Pulse = sConfig->Pulse;
  4239.     temp1.OCPolarity = sConfig->OCPolarity;
  4240.     temp1.OCNPolarity = sConfig->OCNPolarity;
  4241.     temp1.OCIdleState = sConfig->OCIdleState;
  4242.     temp1.OCNIdleState = sConfig->OCNIdleState;
  4243.  
  4244.     switch (OutputChannel)
  4245.     {
  4246.       case TIM_CHANNEL_1:
  4247.       {
  4248.         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4249.  
  4250.         TIM_OC1_SetConfig(htim->Instance, &temp1);
  4251.         break;
  4252.       }
  4253.       case TIM_CHANNEL_2:
  4254.       {
  4255.         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4256.  
  4257.         TIM_OC2_SetConfig(htim->Instance, &temp1);
  4258.         break;
  4259.       }
  4260.       default:
  4261.         break;
  4262.     }
  4263.  
  4264.     switch (InputChannel)
  4265.     {
  4266.       case TIM_CHANNEL_1:
  4267.       {
  4268.         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4269.  
  4270.         TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
  4271.                           sConfig->ICSelection, sConfig->ICFilter);
  4272.  
  4273.         /* Reset the IC1PSC Bits */
  4274.         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
  4275.  
  4276.         /* Select the Trigger source */
  4277.         htim->Instance->SMCR &= ~TIM_SMCR_TS;
  4278.         htim->Instance->SMCR |= TIM_TS_TI1FP1;
  4279.  
  4280.         /* Select the Slave Mode */
  4281.         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
  4282.         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
  4283.         break;
  4284.       }
  4285.       case TIM_CHANNEL_2:
  4286.       {
  4287.         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4288.  
  4289.         TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
  4290.                           sConfig->ICSelection, sConfig->ICFilter);
  4291.  
  4292.         /* Reset the IC2PSC Bits */
  4293.         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
  4294.  
  4295.         /* Select the Trigger source */
  4296.         htim->Instance->SMCR &= ~TIM_SMCR_TS;
  4297.         htim->Instance->SMCR |= TIM_TS_TI2FP2;
  4298.  
  4299.         /* Select the Slave Mode */
  4300.         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
  4301.         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
  4302.         break;
  4303.       }
  4304.  
  4305.       default:
  4306.         break;
  4307.     }
  4308.  
  4309.     htim->State = HAL_TIM_STATE_READY;
  4310.  
  4311.     __HAL_UNLOCK(htim);
  4312.  
  4313.     return HAL_OK;
  4314.   }
  4315.   else
  4316.   {
  4317.     return HAL_ERROR;
  4318.   }
  4319. }
  4320.  
  4321. /**
  4322.   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
  4323.   * @param  htim TIM handle
  4324.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
  4325.   *         This parameter can be one of the following values:
  4326.   *            @arg TIM_DMABASE_CR1
  4327.   *            @arg TIM_DMABASE_CR2
  4328.   *            @arg TIM_DMABASE_SMCR
  4329.   *            @arg TIM_DMABASE_DIER
  4330.   *            @arg TIM_DMABASE_SR
  4331.   *            @arg TIM_DMABASE_EGR
  4332.   *            @arg TIM_DMABASE_CCMR1
  4333.   *            @arg TIM_DMABASE_CCMR2
  4334.   *            @arg TIM_DMABASE_CCER
  4335.   *            @arg TIM_DMABASE_CNT
  4336.   *            @arg TIM_DMABASE_PSC
  4337.   *            @arg TIM_DMABASE_ARR
  4338.   *            @arg TIM_DMABASE_RCR
  4339.   *            @arg TIM_DMABASE_CCR1
  4340.   *            @arg TIM_DMABASE_CCR2
  4341.   *            @arg TIM_DMABASE_CCR3
  4342.   *            @arg TIM_DMABASE_CCR4
  4343.   *            @arg TIM_DMABASE_BDTR
  4344.   * @param  BurstRequestSrc TIM DMA Request sources
  4345.   *         This parameter can be one of the following values:
  4346.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4347.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4348.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4349.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4350.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4351.   *            @arg TIM_DMA_COM: TIM Commutation DMA source
  4352.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4353.   * @param  BurstBuffer The Buffer address.
  4354.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4355.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4356.   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
  4357.   * @retval HAL status
  4358.   */
  4359. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4360.                                               uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)
  4361. {
  4362.   return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
  4363.                                           ((BurstLength) >> 8U) + 1U);
  4364. }
  4365.  
  4366. /**
  4367.   * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
  4368.   * @param  htim TIM handle
  4369.   * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
  4370.   *         This parameter can be one of the following values:
  4371.   *            @arg TIM_DMABASE_CR1
  4372.   *            @arg TIM_DMABASE_CR2
  4373.   *            @arg TIM_DMABASE_SMCR
  4374.   *            @arg TIM_DMABASE_DIER
  4375.   *            @arg TIM_DMABASE_SR
  4376.   *            @arg TIM_DMABASE_EGR
  4377.   *            @arg TIM_DMABASE_CCMR1
  4378.   *            @arg TIM_DMABASE_CCMR2
  4379.   *            @arg TIM_DMABASE_CCER
  4380.   *            @arg TIM_DMABASE_CNT
  4381.   *            @arg TIM_DMABASE_PSC
  4382.   *            @arg TIM_DMABASE_ARR
  4383.   *            @arg TIM_DMABASE_RCR
  4384.   *            @arg TIM_DMABASE_CCR1
  4385.   *            @arg TIM_DMABASE_CCR2
  4386.   *            @arg TIM_DMABASE_CCR3
  4387.   *            @arg TIM_DMABASE_CCR4
  4388.   *            @arg TIM_DMABASE_BDTR
  4389.   * @param  BurstRequestSrc TIM DMA Request sources
  4390.   *         This parameter can be one of the following values:
  4391.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4392.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4393.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4394.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4395.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4396.   *            @arg TIM_DMA_COM: TIM Commutation DMA source
  4397.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4398.   * @param  BurstBuffer The Buffer address.
  4399.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4400.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4401.   * @param  DataLength Data length. This parameter can be one value
  4402.   *         between 1 and 0xFFFF.
  4403.   * @retval HAL status
  4404.   */
  4405. HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4406.                                                    uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
  4407.                                                    uint32_t  BurstLength,  uint32_t  DataLength)
  4408. {
  4409.   /* Check the parameters */
  4410.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  4411.   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
  4412.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4413.   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
  4414.   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
  4415.  
  4416.   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
  4417.   {
  4418.     return HAL_BUSY;
  4419.   }
  4420.   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
  4421.   {
  4422.     if ((BurstBuffer == NULL) && (BurstLength > 0U))
  4423.     {
  4424.       return HAL_ERROR;
  4425.     }
  4426.     else
  4427.     {
  4428.       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
  4429.     }
  4430.   }
  4431.   else
  4432.   {
  4433.     /* nothing to do */
  4434.   }
  4435.   switch (BurstRequestSrc)
  4436.   {
  4437.     case TIM_DMA_UPDATE:
  4438.     {
  4439.       /* Set the DMA Period elapsed callbacks */
  4440.       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  4441.       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  4442.  
  4443.       /* Set the DMA error callback */
  4444.       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  4445.  
  4446.       /* Enable the DMA channel */
  4447.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
  4448.                          (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4449.       {
  4450.         /* Return error status */
  4451.         return HAL_ERROR;
  4452.       }
  4453.       break;
  4454.     }
  4455.     case TIM_DMA_CC1:
  4456.     {
  4457.       /* Set the DMA compare callbacks */
  4458.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4459.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4460.  
  4461.       /* Set the DMA error callback */
  4462.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  4463.  
  4464.       /* Enable the DMA channel */
  4465.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
  4466.                          (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4467.       {
  4468.         /* Return error status */
  4469.         return HAL_ERROR;
  4470.       }
  4471.       break;
  4472.     }
  4473.     case TIM_DMA_CC2:
  4474.     {
  4475.       /* Set the DMA compare callbacks */
  4476.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4477.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4478.  
  4479.       /* Set the DMA error callback */
  4480.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  4481.  
  4482.       /* Enable the DMA channel */
  4483.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
  4484.                          (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4485.       {
  4486.         /* Return error status */
  4487.         return HAL_ERROR;
  4488.       }
  4489.       break;
  4490.     }
  4491.     case TIM_DMA_CC3:
  4492.     {
  4493.       /* Set the DMA compare callbacks */
  4494.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4495.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4496.  
  4497.       /* Set the DMA error callback */
  4498.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  4499.  
  4500.       /* Enable the DMA channel */
  4501.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
  4502.                          (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4503.       {
  4504.         /* Return error status */
  4505.         return HAL_ERROR;
  4506.       }
  4507.       break;
  4508.     }
  4509.     case TIM_DMA_CC4:
  4510.     {
  4511.       /* Set the DMA compare callbacks */
  4512.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4513.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4514.  
  4515.       /* Set the DMA error callback */
  4516.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  4517.  
  4518.       /* Enable the DMA channel */
  4519.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
  4520.                          (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4521.       {
  4522.         /* Return error status */
  4523.         return HAL_ERROR;
  4524.       }
  4525.       break;
  4526.     }
  4527.     case TIM_DMA_COM:
  4528.     {
  4529.       /* Set the DMA commutation callbacks */
  4530.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
  4531.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
  4532.  
  4533.       /* Set the DMA error callback */
  4534.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
  4535.  
  4536.       /* Enable the DMA channel */
  4537.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
  4538.                          (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4539.       {
  4540.         /* Return error status */
  4541.         return HAL_ERROR;
  4542.       }
  4543.       break;
  4544.     }
  4545.     case TIM_DMA_TRIGGER:
  4546.     {
  4547.       /* Set the DMA trigger callbacks */
  4548.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
  4549.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
  4550.  
  4551.       /* Set the DMA error callback */
  4552.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
  4553.  
  4554.       /* Enable the DMA channel */
  4555.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
  4556.                          (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4557.       {
  4558.         /* Return error status */
  4559.         return HAL_ERROR;
  4560.       }
  4561.       break;
  4562.     }
  4563.     default:
  4564.       break;
  4565.   }
  4566.  
  4567.   /* Configure the DMA Burst Mode */
  4568.   htim->Instance->DCR = (BurstBaseAddress | BurstLength);
  4569.   /* Enable the TIM DMA Request */
  4570.   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
  4571.  
  4572.   /* Return function status */
  4573.   return HAL_OK;
  4574. }
  4575.  
  4576. /**
  4577.   * @brief  Stops the TIM DMA Burst mode
  4578.   * @param  htim TIM handle
  4579.   * @param  BurstRequestSrc TIM DMA Request sources to disable
  4580.   * @retval HAL status
  4581.   */
  4582. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
  4583. {
  4584.   /* Check the parameters */
  4585.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4586.  
  4587.   /* Abort the DMA transfer (at least disable the DMA channel) */
  4588.   switch (BurstRequestSrc)
  4589.   {
  4590.     case TIM_DMA_UPDATE:
  4591.     {
  4592.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  4593.       break;
  4594.     }
  4595.     case TIM_DMA_CC1:
  4596.     {
  4597.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  4598.       break;
  4599.     }
  4600.     case TIM_DMA_CC2:
  4601.     {
  4602.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  4603.       break;
  4604.     }
  4605.     case TIM_DMA_CC3:
  4606.     {
  4607.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  4608.       break;
  4609.     }
  4610.     case TIM_DMA_CC4:
  4611.     {
  4612.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  4613.       break;
  4614.     }
  4615.     case TIM_DMA_COM:
  4616.     {
  4617.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
  4618.       break;
  4619.     }
  4620.     case TIM_DMA_TRIGGER:
  4621.     {
  4622.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
  4623.       break;
  4624.     }
  4625.     default:
  4626.       break;
  4627.   }
  4628.  
  4629.   /* Disable the TIM Update DMA request */
  4630.   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
  4631.  
  4632.   /* Change the DMA burst operation state */
  4633.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  4634.  
  4635.   /* Return function status */
  4636.   return HAL_OK;
  4637. }
  4638.  
  4639. /**
  4640.   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
  4641.   * @param  htim TIM handle
  4642.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
  4643.   *         This parameter can be one of the following values:
  4644.   *            @arg TIM_DMABASE_CR1
  4645.   *            @arg TIM_DMABASE_CR2
  4646.   *            @arg TIM_DMABASE_SMCR
  4647.   *            @arg TIM_DMABASE_DIER
  4648.   *            @arg TIM_DMABASE_SR
  4649.   *            @arg TIM_DMABASE_EGR
  4650.   *            @arg TIM_DMABASE_CCMR1
  4651.   *            @arg TIM_DMABASE_CCMR2
  4652.   *            @arg TIM_DMABASE_CCER
  4653.   *            @arg TIM_DMABASE_CNT
  4654.   *            @arg TIM_DMABASE_PSC
  4655.   *            @arg TIM_DMABASE_ARR
  4656.   *            @arg TIM_DMABASE_RCR
  4657.   *            @arg TIM_DMABASE_CCR1
  4658.   *            @arg TIM_DMABASE_CCR2
  4659.   *            @arg TIM_DMABASE_CCR3
  4660.   *            @arg TIM_DMABASE_CCR4
  4661.   *            @arg TIM_DMABASE_BDTR
  4662.   * @param  BurstRequestSrc TIM DMA Request sources
  4663.   *         This parameter can be one of the following values:
  4664.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4665.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4666.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4667.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4668.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4669.   *            @arg TIM_DMA_COM: TIM Commutation DMA source
  4670.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4671.   * @param  BurstBuffer The Buffer address.
  4672.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4673.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4674.   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
  4675.   * @retval HAL status
  4676.   */
  4677. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4678.                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
  4679. {
  4680.   return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
  4681.                                          ((BurstLength) >> 8U) + 1U);
  4682. }
  4683.  
  4684. /**
  4685.   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
  4686.   * @param  htim TIM handle
  4687.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
  4688.   *         This parameter can be one of the following values:
  4689.   *            @arg TIM_DMABASE_CR1
  4690.   *            @arg TIM_DMABASE_CR2
  4691.   *            @arg TIM_DMABASE_SMCR
  4692.   *            @arg TIM_DMABASE_DIER
  4693.   *            @arg TIM_DMABASE_SR
  4694.   *            @arg TIM_DMABASE_EGR
  4695.   *            @arg TIM_DMABASE_CCMR1
  4696.   *            @arg TIM_DMABASE_CCMR2
  4697.   *            @arg TIM_DMABASE_CCER
  4698.   *            @arg TIM_DMABASE_CNT
  4699.   *            @arg TIM_DMABASE_PSC
  4700.   *            @arg TIM_DMABASE_ARR
  4701.   *            @arg TIM_DMABASE_RCR
  4702.   *            @arg TIM_DMABASE_CCR1
  4703.   *            @arg TIM_DMABASE_CCR2
  4704.   *            @arg TIM_DMABASE_CCR3
  4705.   *            @arg TIM_DMABASE_CCR4
  4706.   *            @arg TIM_DMABASE_BDTR
  4707.   * @param  BurstRequestSrc TIM DMA Request sources
  4708.   *         This parameter can be one of the following values:
  4709.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4710.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4711.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4712.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4713.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4714.   *            @arg TIM_DMA_COM: TIM Commutation DMA source
  4715.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4716.   * @param  BurstBuffer The Buffer address.
  4717.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4718.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4719.   * @param  DataLength Data length. This parameter can be one value
  4720.   *         between 1 and 0xFFFF.
  4721.   * @retval HAL status
  4722.   */
  4723. HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4724.                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
  4725.                                                   uint32_t  BurstLength, uint32_t  DataLength)
  4726. {
  4727.   /* Check the parameters */
  4728.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  4729.   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
  4730.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4731.   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
  4732.   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
  4733.  
  4734.   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
  4735.   {
  4736.     return HAL_BUSY;
  4737.   }
  4738.   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
  4739.   {
  4740.     if ((BurstBuffer == NULL) && (BurstLength > 0U))
  4741.     {
  4742.       return HAL_ERROR;
  4743.     }
  4744.     else
  4745.     {
  4746.       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
  4747.     }
  4748.   }
  4749.   else
  4750.   {
  4751.     /* nothing to do */
  4752.   }
  4753.   switch (BurstRequestSrc)
  4754.   {
  4755.     case TIM_DMA_UPDATE:
  4756.     {
  4757.       /* Set the DMA Period elapsed callbacks */
  4758.       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  4759.       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  4760.  
  4761.       /* Set the DMA error callback */
  4762.       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  4763.  
  4764.       /* Enable the DMA channel */
  4765.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4766.                          DataLength) != HAL_OK)
  4767.       {
  4768.         /* Return error status */
  4769.         return HAL_ERROR;
  4770.       }
  4771.       break;
  4772.     }
  4773.     case TIM_DMA_CC1:
  4774.     {
  4775.       /* Set the DMA capture callbacks */
  4776.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  4777.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4778.  
  4779.       /* Set the DMA error callback */
  4780.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  4781.  
  4782.       /* Enable the DMA channel */
  4783.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4784.                          DataLength) != HAL_OK)
  4785.       {
  4786.         /* Return error status */
  4787.         return HAL_ERROR;
  4788.       }
  4789.       break;
  4790.     }
  4791.     case TIM_DMA_CC2:
  4792.     {
  4793.       /* Set the DMA capture callbacks */
  4794.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  4795.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4796.  
  4797.       /* Set the DMA error callback */
  4798.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  4799.  
  4800.       /* Enable the DMA channel */
  4801.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4802.                          DataLength) != HAL_OK)
  4803.       {
  4804.         /* Return error status */
  4805.         return HAL_ERROR;
  4806.       }
  4807.       break;
  4808.     }
  4809.     case TIM_DMA_CC3:
  4810.     {
  4811.       /* Set the DMA capture callbacks */
  4812.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
  4813.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4814.  
  4815.       /* Set the DMA error callback */
  4816.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  4817.  
  4818.       /* Enable the DMA channel */
  4819.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4820.                          DataLength) != HAL_OK)
  4821.       {
  4822.         /* Return error status */
  4823.         return HAL_ERROR;
  4824.       }
  4825.       break;
  4826.     }
  4827.     case TIM_DMA_CC4:
  4828.     {
  4829.       /* Set the DMA capture callbacks */
  4830.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
  4831.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4832.  
  4833.       /* Set the DMA error callback */
  4834.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  4835.  
  4836.       /* Enable the DMA channel */
  4837.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4838.                          DataLength) != HAL_OK)
  4839.       {
  4840.         /* Return error status */
  4841.         return HAL_ERROR;
  4842.       }
  4843.       break;
  4844.     }
  4845.     case TIM_DMA_COM:
  4846.     {
  4847.       /* Set the DMA commutation callbacks */
  4848.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
  4849.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
  4850.  
  4851.       /* Set the DMA error callback */
  4852.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
  4853.  
  4854.       /* Enable the DMA channel */
  4855.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4856.                          DataLength) != HAL_OK)
  4857.       {
  4858.         /* Return error status */
  4859.         return HAL_ERROR;
  4860.       }
  4861.       break;
  4862.     }
  4863.     case TIM_DMA_TRIGGER:
  4864.     {
  4865.       /* Set the DMA trigger callbacks */
  4866.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
  4867.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
  4868.  
  4869.       /* Set the DMA error callback */
  4870.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
  4871.  
  4872.       /* Enable the DMA channel */
  4873.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4874.                          DataLength) != HAL_OK)
  4875.       {
  4876.         /* Return error status */
  4877.         return HAL_ERROR;
  4878.       }
  4879.       break;
  4880.     }
  4881.     default:
  4882.       break;
  4883.   }
  4884.  
  4885.   /* Configure the DMA Burst Mode */
  4886.   htim->Instance->DCR = (BurstBaseAddress | BurstLength);
  4887.  
  4888.   /* Enable the TIM DMA Request */
  4889.   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
  4890.  
  4891.   /* Return function status */
  4892.   return HAL_OK;
  4893. }
  4894.  
  4895. /**
  4896.   * @brief  Stop the DMA burst reading
  4897.   * @param  htim TIM handle
  4898.   * @param  BurstRequestSrc TIM DMA Request sources to disable.
  4899.   * @retval HAL status
  4900.   */
  4901. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
  4902. {
  4903.   /* Check the parameters */
  4904.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4905.  
  4906.   /* Abort the DMA transfer (at least disable the DMA channel) */
  4907.   switch (BurstRequestSrc)
  4908.   {
  4909.     case TIM_DMA_UPDATE:
  4910.     {
  4911.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  4912.       break;
  4913.     }
  4914.     case TIM_DMA_CC1:
  4915.     {
  4916.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  4917.       break;
  4918.     }
  4919.     case TIM_DMA_CC2:
  4920.     {
  4921.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  4922.       break;
  4923.     }
  4924.     case TIM_DMA_CC3:
  4925.     {
  4926.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  4927.       break;
  4928.     }
  4929.     case TIM_DMA_CC4:
  4930.     {
  4931.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  4932.       break;
  4933.     }
  4934.     case TIM_DMA_COM:
  4935.     {
  4936.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
  4937.       break;
  4938.     }
  4939.     case TIM_DMA_TRIGGER:
  4940.     {
  4941.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
  4942.       break;
  4943.     }
  4944.     default:
  4945.       break;
  4946.   }
  4947.  
  4948.   /* Disable the TIM Update DMA request */
  4949.   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
  4950.  
  4951.   /* Change the DMA burst operation state */
  4952.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  4953.  
  4954.   /* Return function status */
  4955.   return HAL_OK;
  4956. }
  4957.  
  4958. /**
  4959.   * @brief  Generate a software event
  4960.   * @param  htim TIM handle
  4961.   * @param  EventSource specifies the event source.
  4962.   *          This parameter can be one of the following values:
  4963.   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
  4964.   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
  4965.   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
  4966.   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
  4967.   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
  4968.   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
  4969.   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
  4970.   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
  4971.   * @note   Basic timers can only generate an update event.
  4972.   * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
  4973.   * @note   TIM_EVENTSOURCE_BREAK are relevant only for timer instances
  4974.   *         supporting a break input.
  4975.   * @retval HAL status
  4976.   */
  4977.  
  4978. HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
  4979. {
  4980.   /* Check the parameters */
  4981.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  4982.   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
  4983.  
  4984.   /* Process Locked */
  4985.   __HAL_LOCK(htim);
  4986.  
  4987.   /* Change the TIM state */
  4988.   htim->State = HAL_TIM_STATE_BUSY;
  4989.  
  4990.   /* Set the event sources */
  4991.   htim->Instance->EGR = EventSource;
  4992.  
  4993.   /* Change the TIM state */
  4994.   htim->State = HAL_TIM_STATE_READY;
  4995.  
  4996.   __HAL_UNLOCK(htim);
  4997.  
  4998.   /* Return function status */
  4999.   return HAL_OK;
  5000. }
  5001.  
  5002. /**
  5003.   * @brief  Configures the OCRef clear feature
  5004.   * @param  htim TIM handle
  5005.   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
  5006.   *         contains the OCREF clear feature and parameters for the TIM peripheral.
  5007.   * @param  Channel specifies the TIM Channel
  5008.   *          This parameter can be one of the following values:
  5009.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  5010.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  5011.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  5012.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  5013.   * @retval HAL status
  5014.   */
  5015. HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
  5016.                                            TIM_ClearInputConfigTypeDef *sClearInputConfig,
  5017.                                            uint32_t Channel)
  5018. {
  5019.   /* Check the parameters */
  5020.   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
  5021.   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
  5022.  
  5023.   /* Process Locked */
  5024.   __HAL_LOCK(htim);
  5025.  
  5026.   htim->State = HAL_TIM_STATE_BUSY;
  5027.  
  5028.   switch (sClearInputConfig->ClearInputSource)
  5029.   {
  5030.     case TIM_CLEARINPUTSOURCE_NONE:
  5031.     {
  5032.       /* Clear the OCREF clear selection bit and the the ETR Bits */
  5033.       CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
  5034.       break;
  5035.     }
  5036.  
  5037.     case TIM_CLEARINPUTSOURCE_ETR:
  5038.     {
  5039.       /* Check the parameters */
  5040.       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
  5041.       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
  5042.       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
  5043.  
  5044.       /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
  5045.       if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
  5046.       {
  5047.         htim->State = HAL_TIM_STATE_READY;
  5048.         __HAL_UNLOCK(htim);
  5049.         return HAL_ERROR;
  5050.       }
  5051.  
  5052.       TIM_ETR_SetConfig(htim->Instance,
  5053.                         sClearInputConfig->ClearInputPrescaler,
  5054.                         sClearInputConfig->ClearInputPolarity,
  5055.                         sClearInputConfig->ClearInputFilter);
  5056.       break;
  5057.     }
  5058.  
  5059.     default:
  5060.       break;
  5061.   }
  5062.  
  5063.   switch (Channel)
  5064.   {
  5065.     case TIM_CHANNEL_1:
  5066.     {
  5067.       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  5068.       {
  5069.         /* Enable the OCREF clear feature for Channel 1 */
  5070.         SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
  5071.       }
  5072.       else
  5073.       {
  5074.         /* Disable the OCREF clear feature for Channel 1 */
  5075.         CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
  5076.       }
  5077.       break;
  5078.     }
  5079.     case TIM_CHANNEL_2:
  5080.     {
  5081.       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  5082.       {
  5083.         /* Enable the OCREF clear feature for Channel 2 */
  5084.         SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
  5085.       }
  5086.       else
  5087.       {
  5088.         /* Disable the OCREF clear feature for Channel 2 */
  5089.         CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
  5090.       }
  5091.       break;
  5092.     }
  5093.     case TIM_CHANNEL_3:
  5094.     {
  5095.       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  5096.       {
  5097.         /* Enable the OCREF clear feature for Channel 3 */
  5098.         SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
  5099.       }
  5100.       else
  5101.       {
  5102.         /* Disable the OCREF clear feature for Channel 3 */
  5103.         CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
  5104.       }
  5105.       break;
  5106.     }
  5107.     case TIM_CHANNEL_4:
  5108.     {
  5109.       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  5110.       {
  5111.         /* Enable the OCREF clear feature for Channel 4 */
  5112.         SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
  5113.       }
  5114.       else
  5115.       {
  5116.         /* Disable the OCREF clear feature for Channel 4 */
  5117.         CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
  5118.       }
  5119.       break;
  5120.     }
  5121.     default:
  5122.       break;
  5123.   }
  5124.  
  5125.   htim->State = HAL_TIM_STATE_READY;
  5126.  
  5127.   __HAL_UNLOCK(htim);
  5128.  
  5129.   return HAL_OK;
  5130. }
  5131.  
  5132. /**
  5133.   * @brief   Configures the clock source to be used
  5134.   * @param  htim TIM handle
  5135.   * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
  5136.   *         contains the clock source information for the TIM peripheral.
  5137.   * @retval HAL status
  5138.   */
  5139. HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
  5140. {
  5141.   uint32_t tmpsmcr;
  5142.  
  5143.   /* Process Locked */
  5144.   __HAL_LOCK(htim);
  5145.  
  5146.   htim->State = HAL_TIM_STATE_BUSY;
  5147.  
  5148.   /* Check the parameters */
  5149.   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
  5150.  
  5151.   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
  5152.   tmpsmcr = htim->Instance->SMCR;
  5153.   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
  5154.   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  5155.   htim->Instance->SMCR = tmpsmcr;
  5156.  
  5157.   switch (sClockSourceConfig->ClockSource)
  5158.   {
  5159.     case TIM_CLOCKSOURCE_INTERNAL:
  5160.     {
  5161.       assert_param(IS_TIM_INSTANCE(htim->Instance));
  5162.       break;
  5163.     }
  5164.  
  5165.     case TIM_CLOCKSOURCE_ETRMODE1:
  5166.     {
  5167.       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
  5168.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
  5169.  
  5170.       /* Check ETR input conditioning related parameters */
  5171.       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
  5172.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5173.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5174.  
  5175.       /* Configure the ETR Clock source */
  5176.       TIM_ETR_SetConfig(htim->Instance,
  5177.                         sClockSourceConfig->ClockPrescaler,
  5178.                         sClockSourceConfig->ClockPolarity,
  5179.                         sClockSourceConfig->ClockFilter);
  5180.  
  5181.       /* Select the External clock mode1 and the ETRF trigger */
  5182.       tmpsmcr = htim->Instance->SMCR;
  5183.       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
  5184.       /* Write to TIMx SMCR */
  5185.       htim->Instance->SMCR = tmpsmcr;
  5186.       break;
  5187.     }
  5188.  
  5189.     case TIM_CLOCKSOURCE_ETRMODE2:
  5190.     {
  5191.       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
  5192.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
  5193.  
  5194.       /* Check ETR input conditioning related parameters */
  5195.       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
  5196.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5197.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5198.  
  5199.       /* Configure the ETR Clock source */
  5200.       TIM_ETR_SetConfig(htim->Instance,
  5201.                         sClockSourceConfig->ClockPrescaler,
  5202.                         sClockSourceConfig->ClockPolarity,
  5203.                         sClockSourceConfig->ClockFilter);
  5204.       /* Enable the External clock mode2 */
  5205.       htim->Instance->SMCR |= TIM_SMCR_ECE;
  5206.       break;
  5207.     }
  5208.  
  5209.     case TIM_CLOCKSOURCE_TI1:
  5210.     {
  5211.       /* Check whether or not the timer instance supports external clock mode 1 */
  5212.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  5213.  
  5214.       /* Check TI1 input conditioning related parameters */
  5215.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5216.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5217.  
  5218.       TIM_TI1_ConfigInputStage(htim->Instance,
  5219.                                sClockSourceConfig->ClockPolarity,
  5220.                                sClockSourceConfig->ClockFilter);
  5221.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
  5222.       break;
  5223.     }
  5224.  
  5225.     case TIM_CLOCKSOURCE_TI2:
  5226.     {
  5227.       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
  5228.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  5229.  
  5230.       /* Check TI2 input conditioning related parameters */
  5231.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5232.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5233.  
  5234.       TIM_TI2_ConfigInputStage(htim->Instance,
  5235.                                sClockSourceConfig->ClockPolarity,
  5236.                                sClockSourceConfig->ClockFilter);
  5237.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
  5238.       break;
  5239.     }
  5240.  
  5241.     case TIM_CLOCKSOURCE_TI1ED:
  5242.     {
  5243.       /* Check whether or not the timer instance supports external clock mode 1 */
  5244.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  5245.  
  5246.       /* Check TI1 input conditioning related parameters */
  5247.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5248.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5249.  
  5250.       TIM_TI1_ConfigInputStage(htim->Instance,
  5251.                                sClockSourceConfig->ClockPolarity,
  5252.                                sClockSourceConfig->ClockFilter);
  5253.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
  5254.       break;
  5255.     }
  5256.  
  5257.     case TIM_CLOCKSOURCE_ITR0:
  5258.     case TIM_CLOCKSOURCE_ITR1:
  5259.     case TIM_CLOCKSOURCE_ITR2:
  5260.     case TIM_CLOCKSOURCE_ITR3:
  5261.       {
  5262.         /* Check whether or not the timer instance supports internal trigger input */
  5263.         assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
  5264.  
  5265.         TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
  5266.         break;
  5267.       }
  5268.  
  5269.     default:
  5270.       break;
  5271.   }
  5272.   htim->State = HAL_TIM_STATE_READY;
  5273.  
  5274.   __HAL_UNLOCK(htim);
  5275.  
  5276.   return HAL_OK;
  5277. }
  5278.  
  5279. /**
  5280.   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
  5281.   *         or a XOR combination between CH1_input, CH2_input & CH3_input
  5282.   * @param  htim TIM handle.
  5283.   * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
  5284.   *         output of a XOR gate.
  5285.   *          This parameter can be one of the following values:
  5286.   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  5287.   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
  5288.   *            pins are connected to the TI1 input (XOR combination)
  5289.   * @retval HAL status
  5290.   */
  5291. HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
  5292. {
  5293.   uint32_t tmpcr2;
  5294.  
  5295.   /* Check the parameters */
  5296.   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
  5297.   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
  5298.  
  5299.   /* Get the TIMx CR2 register value */
  5300.   tmpcr2 = htim->Instance->CR2;
  5301.  
  5302.   /* Reset the TI1 selection */
  5303.   tmpcr2 &= ~TIM_CR2_TI1S;
  5304.  
  5305.   /* Set the TI1 selection */
  5306.   tmpcr2 |= TI1_Selection;
  5307.  
  5308.   /* Write to TIMxCR2 */
  5309.   htim->Instance->CR2 = tmpcr2;
  5310.  
  5311.   return HAL_OK;
  5312. }
  5313.  
  5314. /**
  5315.   * @brief  Configures the TIM in Slave mode
  5316.   * @param  htim TIM handle.
  5317.   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
  5318.   *         contains the selected trigger (internal trigger input, filtered
  5319.   *         timer input or external trigger input) and the Slave mode
  5320.   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
  5321.   * @retval HAL status
  5322.   */
  5323. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
  5324. {
  5325.   /* Check the parameters */
  5326.   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
  5327.   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
  5328.   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
  5329.  
  5330.   __HAL_LOCK(htim);
  5331.  
  5332.   htim->State = HAL_TIM_STATE_BUSY;
  5333.  
  5334.   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
  5335.   {
  5336.     htim->State = HAL_TIM_STATE_READY;
  5337.     __HAL_UNLOCK(htim);
  5338.     return HAL_ERROR;
  5339.   }
  5340.  
  5341.   /* Disable Trigger Interrupt */
  5342.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
  5343.  
  5344.   /* Disable Trigger DMA request */
  5345.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
  5346.  
  5347.   htim->State = HAL_TIM_STATE_READY;
  5348.  
  5349.   __HAL_UNLOCK(htim);
  5350.  
  5351.   return HAL_OK;
  5352. }
  5353.  
  5354. /**
  5355.   * @brief  Configures the TIM in Slave mode in interrupt mode
  5356.   * @param  htim TIM handle.
  5357.   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
  5358.   *         contains the selected trigger (internal trigger input, filtered
  5359.   *         timer input or external trigger input) and the Slave mode
  5360.   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
  5361.   * @retval HAL status
  5362.   */
  5363. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
  5364.                                                 TIM_SlaveConfigTypeDef *sSlaveConfig)
  5365. {
  5366.   /* Check the parameters */
  5367.   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
  5368.   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
  5369.   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
  5370.  
  5371.   __HAL_LOCK(htim);
  5372.  
  5373.   htim->State = HAL_TIM_STATE_BUSY;
  5374.  
  5375.   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
  5376.   {
  5377.     htim->State = HAL_TIM_STATE_READY;
  5378.     __HAL_UNLOCK(htim);
  5379.     return HAL_ERROR;
  5380.   }
  5381.  
  5382.   /* Enable Trigger Interrupt */
  5383.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
  5384.  
  5385.   /* Disable Trigger DMA request */
  5386.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
  5387.  
  5388.   htim->State = HAL_TIM_STATE_READY;
  5389.  
  5390.   __HAL_UNLOCK(htim);
  5391.  
  5392.   return HAL_OK;
  5393. }
  5394.  
  5395. /**
  5396.   * @brief  Read the captured value from Capture Compare unit
  5397.   * @param  htim TIM handle.
  5398.   * @param  Channel TIM Channels to be enabled
  5399.   *          This parameter can be one of the following values:
  5400.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  5401.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  5402.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  5403.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  5404.   * @retval Captured value
  5405.   */
  5406. uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
  5407. {
  5408.   uint32_t tmpreg = 0U;
  5409.  
  5410.   switch (Channel)
  5411.   {
  5412.     case TIM_CHANNEL_1:
  5413.     {
  5414.       /* Check the parameters */
  5415.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  5416.  
  5417.       /* Return the capture 1 value */
  5418.       tmpreg =  htim->Instance->CCR1;
  5419.  
  5420.       break;
  5421.     }
  5422.     case TIM_CHANNEL_2:
  5423.     {
  5424.       /* Check the parameters */
  5425.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  5426.  
  5427.       /* Return the capture 2 value */
  5428.       tmpreg =   htim->Instance->CCR2;
  5429.  
  5430.       break;
  5431.     }
  5432.  
  5433.     case TIM_CHANNEL_3:
  5434.     {
  5435.       /* Check the parameters */
  5436.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  5437.  
  5438.       /* Return the capture 3 value */
  5439.       tmpreg =   htim->Instance->CCR3;
  5440.  
  5441.       break;
  5442.     }
  5443.  
  5444.     case TIM_CHANNEL_4:
  5445.     {
  5446.       /* Check the parameters */
  5447.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  5448.  
  5449.       /* Return the capture 4 value */
  5450.       tmpreg =   htim->Instance->CCR4;
  5451.  
  5452.       break;
  5453.     }
  5454.  
  5455.     default:
  5456.       break;
  5457.   }
  5458.  
  5459.   return tmpreg;
  5460. }
  5461.  
  5462. /**
  5463.   * @}
  5464.   */
  5465.  
  5466. /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
  5467.   *  @brief    TIM Callbacks functions
  5468.   *
  5469. @verbatim
  5470.   ==============================================================================
  5471.                         ##### TIM Callbacks functions #####
  5472.   ==============================================================================
  5473.  [..]
  5474.    This section provides TIM callback functions:
  5475.    (+) TIM Period elapsed callback
  5476.    (+) TIM Output Compare callback
  5477.    (+) TIM Input capture callback
  5478.    (+) TIM Trigger callback
  5479.    (+) TIM Error callback
  5480.  
  5481. @endverbatim
  5482.   * @{
  5483.   */
  5484.  
  5485. /**
  5486.   * @brief  Period elapsed callback in non-blocking mode
  5487.   * @param  htim TIM handle
  5488.   * @retval None
  5489.   */
  5490. __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
  5491. {
  5492.   /* Prevent unused argument(s) compilation warning */
  5493.   UNUSED(htim);
  5494.  
  5495.   /* NOTE : This function should not be modified, when the callback is needed,
  5496.             the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
  5497.    */
  5498. }
  5499.  
  5500. /**
  5501.   * @brief  Period elapsed half complete callback in non-blocking mode
  5502.   * @param  htim TIM handle
  5503.   * @retval None
  5504.   */
  5505. __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
  5506. {
  5507.   /* Prevent unused argument(s) compilation warning */
  5508.   UNUSED(htim);
  5509.  
  5510.   /* NOTE : This function should not be modified, when the callback is needed,
  5511.             the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
  5512.    */
  5513. }
  5514.  
  5515. /**
  5516.   * @brief  Output Compare callback in non-blocking mode
  5517.   * @param  htim TIM OC handle
  5518.   * @retval None
  5519.   */
  5520. __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
  5521. {
  5522.   /* Prevent unused argument(s) compilation warning */
  5523.   UNUSED(htim);
  5524.  
  5525.   /* NOTE : This function should not be modified, when the callback is needed,
  5526.             the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
  5527.    */
  5528. }
  5529.  
  5530. /**
  5531.   * @brief  Input Capture callback in non-blocking mode
  5532.   * @param  htim TIM IC handle
  5533.   * @retval None
  5534.   */
  5535. __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
  5536. {
  5537.   /* Prevent unused argument(s) compilation warning */
  5538.   UNUSED(htim);
  5539.  
  5540.   /* NOTE : This function should not be modified, when the callback is needed,
  5541.             the HAL_TIM_IC_CaptureCallback could be implemented in the user file
  5542.    */
  5543. }
  5544.  
  5545. /**
  5546.   * @brief  Input Capture half complete callback in non-blocking mode
  5547.   * @param  htim TIM IC handle
  5548.   * @retval None
  5549.   */
  5550. __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
  5551. {
  5552.   /* Prevent unused argument(s) compilation warning */
  5553.   UNUSED(htim);
  5554.  
  5555.   /* NOTE : This function should not be modified, when the callback is needed,
  5556.             the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
  5557.    */
  5558. }
  5559.  
  5560. /**
  5561.   * @brief  PWM Pulse finished callback in non-blocking mode
  5562.   * @param  htim TIM handle
  5563.   * @retval None
  5564.   */
  5565. __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
  5566. {
  5567.   /* Prevent unused argument(s) compilation warning */
  5568.   UNUSED(htim);
  5569.  
  5570.   /* NOTE : This function should not be modified, when the callback is needed,
  5571.             the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
  5572.    */
  5573. }
  5574.  
  5575. /**
  5576.   * @brief  PWM Pulse finished half complete callback in non-blocking mode
  5577.   * @param  htim TIM handle
  5578.   * @retval None
  5579.   */
  5580. __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
  5581. {
  5582.   /* Prevent unused argument(s) compilation warning */
  5583.   UNUSED(htim);
  5584.  
  5585.   /* NOTE : This function should not be modified, when the callback is needed,
  5586.             the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
  5587.    */
  5588. }
  5589.  
  5590. /**
  5591.   * @brief  Hall Trigger detection callback in non-blocking mode
  5592.   * @param  htim TIM handle
  5593.   * @retval None
  5594.   */
  5595. __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
  5596. {
  5597.   /* Prevent unused argument(s) compilation warning */
  5598.   UNUSED(htim);
  5599.  
  5600.   /* NOTE : This function should not be modified, when the callback is needed,
  5601.             the HAL_TIM_TriggerCallback could be implemented in the user file
  5602.    */
  5603. }
  5604.  
  5605. /**
  5606.   * @brief  Hall Trigger detection half complete callback in non-blocking mode
  5607.   * @param  htim TIM handle
  5608.   * @retval None
  5609.   */
  5610. __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
  5611. {
  5612.   /* Prevent unused argument(s) compilation warning */
  5613.   UNUSED(htim);
  5614.  
  5615.   /* NOTE : This function should not be modified, when the callback is needed,
  5616.             the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
  5617.    */
  5618. }
  5619.  
  5620. /**
  5621.   * @brief  Timer error callback in non-blocking mode
  5622.   * @param  htim TIM handle
  5623.   * @retval None
  5624.   */
  5625. __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
  5626. {
  5627.   /* Prevent unused argument(s) compilation warning */
  5628.   UNUSED(htim);
  5629.  
  5630.   /* NOTE : This function should not be modified, when the callback is needed,
  5631.             the HAL_TIM_ErrorCallback could be implemented in the user file
  5632.    */
  5633. }
  5634.  
  5635. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  5636. /**
  5637.   * @brief  Register a User TIM callback to be used instead of the weak predefined callback
  5638.   * @param htim tim handle
  5639.   * @param CallbackID ID of the callback to be registered
  5640.   *        This parameter can be one of the following values:
  5641.   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  5642.   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  5643.   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  5644.   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  5645.   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  5646.   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  5647.   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  5648.   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  5649.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  5650.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  5651.   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  5652.   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  5653.   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
  5654.   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
  5655.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  5656.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  5657.   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  5658.   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  5659.   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  5660.   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  5661.   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  5662.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  5663.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  5664.   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
  5665.   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
  5666.   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
  5667.   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
  5668.   *          @param pCallback pointer to the callback function
  5669.   *          @retval status
  5670.   */
  5671. HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
  5672.                                            pTIM_CallbackTypeDef pCallback)
  5673. {
  5674.   HAL_StatusTypeDef status = HAL_OK;
  5675.  
  5676.   if (pCallback == NULL)
  5677.   {
  5678.     return HAL_ERROR;
  5679.   }
  5680.   /* Process locked */
  5681.   __HAL_LOCK(htim);
  5682.  
  5683.   if (htim->State == HAL_TIM_STATE_READY)
  5684.   {
  5685.     switch (CallbackID)
  5686.     {
  5687.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5688.         htim->Base_MspInitCallback                 = pCallback;
  5689.         break;
  5690.  
  5691.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5692.         htim->Base_MspDeInitCallback               = pCallback;
  5693.         break;
  5694.  
  5695.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5696.         htim->IC_MspInitCallback                   = pCallback;
  5697.         break;
  5698.  
  5699.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5700.         htim->IC_MspDeInitCallback                 = pCallback;
  5701.         break;
  5702.  
  5703.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5704.         htim->OC_MspInitCallback                   = pCallback;
  5705.         break;
  5706.  
  5707.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5708.         htim->OC_MspDeInitCallback                 = pCallback;
  5709.         break;
  5710.  
  5711.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5712.         htim->PWM_MspInitCallback                  = pCallback;
  5713.         break;
  5714.  
  5715.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  5716.         htim->PWM_MspDeInitCallback                = pCallback;
  5717.         break;
  5718.  
  5719.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  5720.         htim->OnePulse_MspInitCallback             = pCallback;
  5721.         break;
  5722.  
  5723.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  5724.         htim->OnePulse_MspDeInitCallback           = pCallback;
  5725.         break;
  5726.  
  5727.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  5728.         htim->Encoder_MspInitCallback              = pCallback;
  5729.         break;
  5730.  
  5731.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  5732.         htim->Encoder_MspDeInitCallback            = pCallback;
  5733.         break;
  5734.  
  5735.       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
  5736.         htim->HallSensor_MspInitCallback           = pCallback;
  5737.         break;
  5738.  
  5739.       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
  5740.         htim->HallSensor_MspDeInitCallback         = pCallback;
  5741.         break;
  5742.  
  5743.       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
  5744.         htim->PeriodElapsedCallback                = pCallback;
  5745.         break;
  5746.  
  5747.       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
  5748.         htim->PeriodElapsedHalfCpltCallback        = pCallback;
  5749.         break;
  5750.  
  5751.       case HAL_TIM_TRIGGER_CB_ID :
  5752.         htim->TriggerCallback                      = pCallback;
  5753.         break;
  5754.  
  5755.       case HAL_TIM_TRIGGER_HALF_CB_ID :
  5756.         htim->TriggerHalfCpltCallback              = pCallback;
  5757.         break;
  5758.  
  5759.       case HAL_TIM_IC_CAPTURE_CB_ID :
  5760.         htim->IC_CaptureCallback                   = pCallback;
  5761.         break;
  5762.  
  5763.       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
  5764.         htim->IC_CaptureHalfCpltCallback           = pCallback;
  5765.         break;
  5766.  
  5767.       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
  5768.         htim->OC_DelayElapsedCallback              = pCallback;
  5769.         break;
  5770.  
  5771.       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
  5772.         htim->PWM_PulseFinishedCallback            = pCallback;
  5773.         break;
  5774.  
  5775.       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
  5776.         htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
  5777.         break;
  5778.  
  5779.       case HAL_TIM_ERROR_CB_ID :
  5780.         htim->ErrorCallback                        = pCallback;
  5781.         break;
  5782.  
  5783.       case HAL_TIM_COMMUTATION_CB_ID :
  5784.         htim->CommutationCallback                  = pCallback;
  5785.         break;
  5786.  
  5787.       case HAL_TIM_COMMUTATION_HALF_CB_ID :
  5788.         htim->CommutationHalfCpltCallback          = pCallback;
  5789.         break;
  5790.  
  5791.       case HAL_TIM_BREAK_CB_ID :
  5792.         htim->BreakCallback                        = pCallback;
  5793.         break;
  5794.  
  5795.       default :
  5796.         /* Return error status */
  5797.         status =  HAL_ERROR;
  5798.         break;
  5799.     }
  5800.   }
  5801.   else if (htim->State == HAL_TIM_STATE_RESET)
  5802.   {
  5803.     switch (CallbackID)
  5804.     {
  5805.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5806.         htim->Base_MspInitCallback         = pCallback;
  5807.         break;
  5808.  
  5809.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5810.         htim->Base_MspDeInitCallback       = pCallback;
  5811.         break;
  5812.  
  5813.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5814.         htim->IC_MspInitCallback           = pCallback;
  5815.         break;
  5816.  
  5817.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5818.         htim->IC_MspDeInitCallback         = pCallback;
  5819.         break;
  5820.  
  5821.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5822.         htim->OC_MspInitCallback           = pCallback;
  5823.         break;
  5824.  
  5825.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5826.         htim->OC_MspDeInitCallback         = pCallback;
  5827.         break;
  5828.  
  5829.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5830.         htim->PWM_MspInitCallback          = pCallback;
  5831.         break;
  5832.  
  5833.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  5834.         htim->PWM_MspDeInitCallback        = pCallback;
  5835.         break;
  5836.  
  5837.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  5838.         htim->OnePulse_MspInitCallback     = pCallback;
  5839.         break;
  5840.  
  5841.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  5842.         htim->OnePulse_MspDeInitCallback   = pCallback;
  5843.         break;
  5844.  
  5845.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  5846.         htim->Encoder_MspInitCallback      = pCallback;
  5847.         break;
  5848.  
  5849.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  5850.         htim->Encoder_MspDeInitCallback    = pCallback;
  5851.         break;
  5852.  
  5853.       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
  5854.         htim->HallSensor_MspInitCallback   = pCallback;
  5855.         break;
  5856.  
  5857.       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
  5858.         htim->HallSensor_MspDeInitCallback = pCallback;
  5859.         break;
  5860.  
  5861.       default :
  5862.         /* Return error status */
  5863.         status =  HAL_ERROR;
  5864.         break;
  5865.     }
  5866.   }
  5867.   else
  5868.   {
  5869.     /* Return error status */
  5870.     status =  HAL_ERROR;
  5871.   }
  5872.  
  5873.   /* Release Lock */
  5874.   __HAL_UNLOCK(htim);
  5875.  
  5876.   return status;
  5877. }
  5878.  
  5879. /**
  5880.   * @brief  Unregister a TIM callback
  5881.   *         TIM callback is redirected to the weak predefined callback
  5882.   * @param htim tim handle
  5883.   * @param CallbackID ID of the callback to be unregistered
  5884.   *        This parameter can be one of the following values:
  5885.   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  5886.   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  5887.   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  5888.   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  5889.   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  5890.   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  5891.   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  5892.   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  5893.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  5894.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  5895.   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  5896.   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  5897.   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
  5898.   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
  5899.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  5900.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  5901.   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  5902.   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  5903.   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  5904.   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  5905.   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  5906.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  5907.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  5908.   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
  5909.   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
  5910.   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
  5911.   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
  5912.   *          @retval status
  5913.   */
  5914. HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
  5915. {
  5916.   HAL_StatusTypeDef status = HAL_OK;
  5917.  
  5918.   /* Process locked */
  5919.   __HAL_LOCK(htim);
  5920.  
  5921.   if (htim->State == HAL_TIM_STATE_READY)
  5922.   {
  5923.     switch (CallbackID)
  5924.     {
  5925.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5926.         htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;                      /* Legacy weak Base MspInit Callback */
  5927.         break;
  5928.  
  5929.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5930.         htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;                    /* Legacy weak Base Msp DeInit Callback */
  5931.         break;
  5932.  
  5933.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5934.         htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;                        /* Legacy weak IC Msp Init Callback */
  5935.         break;
  5936.  
  5937.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5938.         htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;                      /* Legacy weak IC Msp DeInit Callback */
  5939.         break;
  5940.  
  5941.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5942.         htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;                        /* Legacy weak OC Msp Init Callback */
  5943.         break;
  5944.  
  5945.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5946.         htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;                      /* Legacy weak OC Msp DeInit Callback */
  5947.         break;
  5948.  
  5949.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5950.         htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;                       /* Legacy weak PWM Msp Init Callback */
  5951.         break;
  5952.  
  5953.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  5954.         htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;                     /* Legacy weak PWM Msp DeInit Callback */
  5955.         break;
  5956.  
  5957.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  5958.         htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;                  /* Legacy weak One Pulse Msp Init Callback */
  5959.         break;
  5960.  
  5961.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  5962.         htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;                /* Legacy weak One Pulse Msp DeInit Callback */
  5963.         break;
  5964.  
  5965.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  5966.         htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;                   /* Legacy weak Encoder Msp Init Callback */
  5967.         break;
  5968.  
  5969.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  5970.         htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;                 /* Legacy weak Encoder Msp DeInit Callback */
  5971.         break;
  5972.  
  5973.       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
  5974.         htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;              /* Legacy weak Hall Sensor Msp Init Callback */
  5975.         break;
  5976.  
  5977.       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
  5978.         htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;            /* Legacy weak Hall Sensor Msp DeInit Callback */
  5979.         break;
  5980.  
  5981.       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
  5982.         htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak Period Elapsed Callback */
  5983.         break;
  5984.  
  5985.       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
  5986.         htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak Period Elapsed half complete Callback */
  5987.         break;
  5988.  
  5989.       case HAL_TIM_TRIGGER_CB_ID :
  5990.         htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak Trigger Callback */
  5991.         break;
  5992.  
  5993.       case HAL_TIM_TRIGGER_HALF_CB_ID :
  5994.         htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak Trigger half complete Callback */
  5995.         break;
  5996.  
  5997.       case HAL_TIM_IC_CAPTURE_CB_ID :
  5998.         htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC Capture Callback */
  5999.         break;
  6000.  
  6001.       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
  6002.         htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC Capture half complete Callback */
  6003.         break;
  6004.  
  6005.       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
  6006.         htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC Delay Elapsed Callback */
  6007.         break;
  6008.  
  6009.       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
  6010.         htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM Pulse Finished Callback */
  6011.         break;
  6012.  
  6013.       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
  6014.         htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
  6015.         break;
  6016.  
  6017.       case HAL_TIM_ERROR_CB_ID :
  6018.         htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak Error Callback */
  6019.         break;
  6020.  
  6021.       case HAL_TIM_COMMUTATION_CB_ID :
  6022.         htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak Commutation Callback */
  6023.         break;
  6024.  
  6025.       case HAL_TIM_COMMUTATION_HALF_CB_ID :
  6026.         htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak Commutation half complete Callback */
  6027.         break;
  6028.  
  6029.       case HAL_TIM_BREAK_CB_ID :
  6030.         htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak Break Callback */
  6031.         break;
  6032.  
  6033.       default :
  6034.         /* Return error status */
  6035.         status =  HAL_ERROR;
  6036.         break;
  6037.     }
  6038.   }
  6039.   else if (htim->State == HAL_TIM_STATE_RESET)
  6040.   {
  6041.     switch (CallbackID)
  6042.     {
  6043.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  6044.         htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */
  6045.         break;
  6046.  
  6047.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  6048.         htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */
  6049.         break;
  6050.  
  6051.       case HAL_TIM_IC_MSPINIT_CB_ID :
  6052.         htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */
  6053.         break;
  6054.  
  6055.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  6056.         htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */
  6057.         break;
  6058.  
  6059.       case HAL_TIM_OC_MSPINIT_CB_ID :
  6060.         htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */
  6061.         break;
  6062.  
  6063.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  6064.         htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */
  6065.         break;
  6066.  
  6067.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  6068.         htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */
  6069.         break;
  6070.  
  6071.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  6072.         htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */
  6073.         break;
  6074.  
  6075.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  6076.         htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */
  6077.         break;
  6078.  
  6079.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  6080.         htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */
  6081.         break;
  6082.  
  6083.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  6084.         htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */
  6085.         break;
  6086.  
  6087.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  6088.         htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */
  6089.         break;
  6090.  
  6091.       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
  6092.         htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;      /* Legacy weak Hall Sensor Msp Init Callback */
  6093.         break;
  6094.  
  6095.       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
  6096.         htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;    /* Legacy weak Hall Sensor Msp DeInit Callback */
  6097.         break;
  6098.  
  6099.       default :
  6100.         /* Return error status */
  6101.         status =  HAL_ERROR;
  6102.         break;
  6103.     }
  6104.   }
  6105.   else
  6106.   {
  6107.     /* Return error status */
  6108.     status =  HAL_ERROR;
  6109.   }
  6110.  
  6111.   /* Release Lock */
  6112.   __HAL_UNLOCK(htim);
  6113.  
  6114.   return status;
  6115. }
  6116. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6117.  
  6118. /**
  6119.   * @}
  6120.   */
  6121.  
  6122. /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
  6123.   *  @brief   TIM Peripheral State functions
  6124.   *
  6125. @verbatim
  6126.   ==============================================================================
  6127.                         ##### Peripheral State functions #####
  6128.   ==============================================================================
  6129.     [..]
  6130.     This subsection permits to get in run-time the status of the peripheral
  6131.     and the data flow.
  6132.  
  6133. @endverbatim
  6134.   * @{
  6135.   */
  6136.  
  6137. /**
  6138.   * @brief  Return the TIM Base handle state.
  6139.   * @param  htim TIM Base handle
  6140.   * @retval HAL state
  6141.   */
  6142. HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
  6143. {
  6144.   return htim->State;
  6145. }
  6146.  
  6147. /**
  6148.   * @brief  Return the TIM OC handle state.
  6149.   * @param  htim TIM Output Compare handle
  6150.   * @retval HAL state
  6151.   */
  6152. HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
  6153. {
  6154.   return htim->State;
  6155. }
  6156.  
  6157. /**
  6158.   * @brief  Return the TIM PWM handle state.
  6159.   * @param  htim TIM handle
  6160.   * @retval HAL state
  6161.   */
  6162. HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
  6163. {
  6164.   return htim->State;
  6165. }
  6166.  
  6167. /**
  6168.   * @brief  Return the TIM Input Capture handle state.
  6169.   * @param  htim TIM IC handle
  6170.   * @retval HAL state
  6171.   */
  6172. HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
  6173. {
  6174.   return htim->State;
  6175. }
  6176.  
  6177. /**
  6178.   * @brief  Return the TIM One Pulse Mode handle state.
  6179.   * @param  htim TIM OPM handle
  6180.   * @retval HAL state
  6181.   */
  6182. HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
  6183. {
  6184.   return htim->State;
  6185. }
  6186.  
  6187. /**
  6188.   * @brief  Return the TIM Encoder Mode handle state.
  6189.   * @param  htim TIM Encoder Interface handle
  6190.   * @retval HAL state
  6191.   */
  6192. HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
  6193. {
  6194.   return htim->State;
  6195. }
  6196.  
  6197. /**
  6198.   * @brief  Return the TIM Encoder Mode handle state.
  6199.   * @param  htim TIM handle
  6200.   * @retval Active channel
  6201.   */
  6202. HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
  6203. {
  6204.   return htim->Channel;
  6205. }
  6206.  
  6207. /**
  6208.   * @brief  Return actual state of the TIM channel.
  6209.   * @param  htim TIM handle
  6210.   * @param  Channel TIM Channel
  6211.   *          This parameter can be one of the following values:
  6212.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  6213.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  6214.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  6215.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  6216.   *            @arg TIM_CHANNEL_5: TIM Channel 5
  6217.   *            @arg TIM_CHANNEL_6: TIM Channel 6
  6218.   * @retval TIM Channel state
  6219.   */
  6220. HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel)
  6221. {
  6222.   HAL_TIM_ChannelStateTypeDef channel_state;
  6223.  
  6224.   /* Check the parameters */
  6225.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  6226.  
  6227.   channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  6228.  
  6229.   return channel_state;
  6230. }
  6231.  
  6232. /**
  6233.   * @brief  Return actual state of a DMA burst operation.
  6234.   * @param  htim TIM handle
  6235.   * @retval DMA burst state
  6236.   */
  6237. HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
  6238. {
  6239.   /* Check the parameters */
  6240.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  6241.  
  6242.   return htim->DMABurstState;
  6243. }
  6244.  
  6245. /**
  6246.   * @}
  6247.   */
  6248.  
  6249. /**
  6250.   * @}
  6251.   */
  6252.  
  6253. /** @defgroup TIM_Private_Functions TIM Private Functions
  6254.   * @{
  6255.   */
  6256.  
  6257. /**
  6258.   * @brief  TIM DMA error callback
  6259.   * @param  hdma pointer to DMA handle.
  6260.   * @retval None
  6261.   */
  6262. void TIM_DMAError(DMA_HandleTypeDef *hdma)
  6263. {
  6264.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6265.  
  6266.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6267.   {
  6268.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6269.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6270.   }
  6271.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6272.   {
  6273.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6274.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6275.   }
  6276.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6277.   {
  6278.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6279.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6280.   }
  6281.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6282.   {
  6283.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6284.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6285.   }
  6286.   else
  6287.   {
  6288.     htim->State = HAL_TIM_STATE_READY;
  6289.   }
  6290.  
  6291. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6292.   htim->ErrorCallback(htim);
  6293. #else
  6294.   HAL_TIM_ErrorCallback(htim);
  6295. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6296.  
  6297.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6298. }
  6299.  
  6300. /**
  6301.   * @brief  TIM DMA Delay Pulse complete callback.
  6302.   * @param  hdma pointer to DMA handle.
  6303.   * @retval None
  6304.   */
  6305. static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
  6306. {
  6307.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6308.  
  6309.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6310.   {
  6311.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6312.  
  6313.     if (hdma->Init.Mode == DMA_NORMAL)
  6314.     {
  6315.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6316.     }
  6317.   }
  6318.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6319.   {
  6320.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6321.  
  6322.     if (hdma->Init.Mode == DMA_NORMAL)
  6323.     {
  6324.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6325.     }
  6326.   }
  6327.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6328.   {
  6329.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6330.  
  6331.     if (hdma->Init.Mode == DMA_NORMAL)
  6332.     {
  6333.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6334.     }
  6335.   }
  6336.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6337.   {
  6338.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6339.  
  6340.     if (hdma->Init.Mode == DMA_NORMAL)
  6341.     {
  6342.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6343.     }
  6344.   }
  6345.   else
  6346.   {
  6347.     /* nothing to do */
  6348.   }
  6349.  
  6350. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6351.   htim->PWM_PulseFinishedCallback(htim);
  6352. #else
  6353.   HAL_TIM_PWM_PulseFinishedCallback(htim);
  6354. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6355.  
  6356.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6357. }
  6358.  
  6359. /**
  6360.   * @brief  TIM DMA Delay Pulse half complete callback.
  6361.   * @param  hdma pointer to DMA handle.
  6362.   * @retval None
  6363.   */
  6364. void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
  6365. {
  6366.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6367.  
  6368.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6369.   {
  6370.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6371.   }
  6372.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6373.   {
  6374.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6375.   }
  6376.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6377.   {
  6378.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6379.   }
  6380.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6381.   {
  6382.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6383.   }
  6384.   else
  6385.   {
  6386.     /* nothing to do */
  6387.   }
  6388.  
  6389. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6390.   htim->PWM_PulseFinishedHalfCpltCallback(htim);
  6391. #else
  6392.   HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
  6393. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6394.  
  6395.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6396. }
  6397.  
  6398. /**
  6399.   * @brief  TIM DMA Capture complete callback.
  6400.   * @param  hdma pointer to DMA handle.
  6401.   * @retval None
  6402.   */
  6403. void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
  6404. {
  6405.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6406.  
  6407.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6408.   {
  6409.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6410.  
  6411.     if (hdma->Init.Mode == DMA_NORMAL)
  6412.     {
  6413.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6414.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6415.     }
  6416.   }
  6417.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6418.   {
  6419.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6420.  
  6421.     if (hdma->Init.Mode == DMA_NORMAL)
  6422.     {
  6423.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6424.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6425.     }
  6426.   }
  6427.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6428.   {
  6429.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6430.  
  6431.     if (hdma->Init.Mode == DMA_NORMAL)
  6432.     {
  6433.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6434.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6435.     }
  6436.   }
  6437.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6438.   {
  6439.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6440.  
  6441.     if (hdma->Init.Mode == DMA_NORMAL)
  6442.     {
  6443.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6444.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6445.     }
  6446.   }
  6447.   else
  6448.   {
  6449.     /* nothing to do */
  6450.   }
  6451.  
  6452. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6453.   htim->IC_CaptureCallback(htim);
  6454. #else
  6455.   HAL_TIM_IC_CaptureCallback(htim);
  6456. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6457.  
  6458.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6459. }
  6460.  
  6461. /**
  6462.   * @brief  TIM DMA Capture half complete callback.
  6463.   * @param  hdma pointer to DMA handle.
  6464.   * @retval None
  6465.   */
  6466. void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
  6467. {
  6468.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6469.  
  6470.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6471.   {
  6472.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6473.   }
  6474.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6475.   {
  6476.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6477.   }
  6478.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6479.   {
  6480.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6481.   }
  6482.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6483.   {
  6484.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6485.   }
  6486.   else
  6487.   {
  6488.     /* nothing to do */
  6489.   }
  6490.  
  6491. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6492.   htim->IC_CaptureHalfCpltCallback(htim);
  6493. #else
  6494.   HAL_TIM_IC_CaptureHalfCpltCallback(htim);
  6495. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6496.  
  6497.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6498. }
  6499.  
  6500. /**
  6501.   * @brief  TIM DMA Period Elapse complete callback.
  6502.   * @param  hdma pointer to DMA handle.
  6503.   * @retval None
  6504.   */
  6505. static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
  6506. {
  6507.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6508.  
  6509.   if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
  6510.   {
  6511.     htim->State = HAL_TIM_STATE_READY;
  6512.   }
  6513.  
  6514. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6515.   htim->PeriodElapsedCallback(htim);
  6516. #else
  6517.   HAL_TIM_PeriodElapsedCallback(htim);
  6518. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6519. }
  6520.  
  6521. /**
  6522.   * @brief  TIM DMA Period Elapse half complete callback.
  6523.   * @param  hdma pointer to DMA handle.
  6524.   * @retval None
  6525.   */
  6526. static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
  6527. {
  6528.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6529.  
  6530. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6531.   htim->PeriodElapsedHalfCpltCallback(htim);
  6532. #else
  6533.   HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
  6534. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6535. }
  6536.  
  6537. /**
  6538.   * @brief  TIM DMA Trigger callback.
  6539.   * @param  hdma pointer to DMA handle.
  6540.   * @retval None
  6541.   */
  6542. static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
  6543. {
  6544.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6545.  
  6546.   if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
  6547.   {
  6548.     htim->State = HAL_TIM_STATE_READY;
  6549.   }
  6550.  
  6551. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6552.   htim->TriggerCallback(htim);
  6553. #else
  6554.   HAL_TIM_TriggerCallback(htim);
  6555. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6556. }
  6557.  
  6558. /**
  6559.   * @brief  TIM DMA Trigger half complete callback.
  6560.   * @param  hdma pointer to DMA handle.
  6561.   * @retval None
  6562.   */
  6563. static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
  6564. {
  6565.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6566.  
  6567. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6568.   htim->TriggerHalfCpltCallback(htim);
  6569. #else
  6570.   HAL_TIM_TriggerHalfCpltCallback(htim);
  6571. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6572. }
  6573.  
  6574. /**
  6575.   * @brief  Time Base configuration
  6576.   * @param  TIMx TIM peripheral
  6577.   * @param  Structure TIM Base configuration structure
  6578.   * @retval None
  6579.   */
  6580. void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
  6581. {
  6582.   uint32_t tmpcr1;
  6583.   tmpcr1 = TIMx->CR1;
  6584.  
  6585.   /* Set TIM Time Base Unit parameters ---------------------------------------*/
  6586.   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  6587.   {
  6588.     /* Select the Counter Mode */
  6589.     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
  6590.     tmpcr1 |= Structure->CounterMode;
  6591.   }
  6592.  
  6593.   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  6594.   {
  6595.     /* Set the clock division */
  6596.     tmpcr1 &= ~TIM_CR1_CKD;
  6597.     tmpcr1 |= (uint32_t)Structure->ClockDivision;
  6598.   }
  6599.  
  6600.   /* Set the auto-reload preload */
  6601.   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
  6602.  
  6603.   TIMx->CR1 = tmpcr1;
  6604.  
  6605.   /* Set the Autoreload value */
  6606.   TIMx->ARR = (uint32_t)Structure->Period ;
  6607.  
  6608.   /* Set the Prescaler value */
  6609.   TIMx->PSC = Structure->Prescaler;
  6610.  
  6611.   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  6612.   {
  6613.     /* Set the Repetition Counter value */
  6614.     TIMx->RCR = Structure->RepetitionCounter;
  6615.   }
  6616.  
  6617.   /* Generate an update event to reload the Prescaler
  6618.      and the repetition counter (only for advanced timer) value immediately */
  6619.   TIMx->EGR = TIM_EGR_UG;
  6620. }
  6621.  
  6622. /**
  6623.   * @brief  Timer Output Compare 1 configuration
  6624.   * @param  TIMx to select the TIM peripheral
  6625.   * @param  OC_Config The output configuration structure
  6626.   * @retval None
  6627.   */
  6628. static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6629. {
  6630.   uint32_t tmpccmrx;
  6631.   uint32_t tmpccer;
  6632.   uint32_t tmpcr2;
  6633.  
  6634.   /* Disable the Channel 1: Reset the CC1E Bit */
  6635.   TIMx->CCER &= ~TIM_CCER_CC1E;
  6636.  
  6637.   /* Get the TIMx CCER register value */
  6638.   tmpccer = TIMx->CCER;
  6639.   /* Get the TIMx CR2 register value */
  6640.   tmpcr2 =  TIMx->CR2;
  6641.  
  6642.   /* Get the TIMx CCMR1 register value */
  6643.   tmpccmrx = TIMx->CCMR1;
  6644.  
  6645.   /* Reset the Output Compare Mode Bits */
  6646.   tmpccmrx &= ~TIM_CCMR1_OC1M;
  6647.   tmpccmrx &= ~TIM_CCMR1_CC1S;
  6648.   /* Select the Output Compare Mode */
  6649.   tmpccmrx |= OC_Config->OCMode;
  6650.  
  6651.   /* Reset the Output Polarity level */
  6652.   tmpccer &= ~TIM_CCER_CC1P;
  6653.   /* Set the Output Compare Polarity */
  6654.   tmpccer |= OC_Config->OCPolarity;
  6655.  
  6656.   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
  6657.   {
  6658.     /* Check parameters */
  6659.     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
  6660.  
  6661.     /* Reset the Output N Polarity level */
  6662.     tmpccer &= ~TIM_CCER_CC1NP;
  6663.     /* Set the Output N Polarity */
  6664.     tmpccer |= OC_Config->OCNPolarity;
  6665.     /* Reset the Output N State */
  6666.     tmpccer &= ~TIM_CCER_CC1NE;
  6667.   }
  6668.  
  6669.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  6670.   {
  6671.     /* Check parameters */
  6672.     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
  6673.     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
  6674.  
  6675.     /* Reset the Output Compare and Output Compare N IDLE State */
  6676.     tmpcr2 &= ~TIM_CR2_OIS1;
  6677.     tmpcr2 &= ~TIM_CR2_OIS1N;
  6678.     /* Set the Output Idle state */
  6679.     tmpcr2 |= OC_Config->OCIdleState;
  6680.     /* Set the Output N Idle state */
  6681.     tmpcr2 |= OC_Config->OCNIdleState;
  6682.   }
  6683.  
  6684.   /* Write to TIMx CR2 */
  6685.   TIMx->CR2 = tmpcr2;
  6686.  
  6687.   /* Write to TIMx CCMR1 */
  6688.   TIMx->CCMR1 = tmpccmrx;
  6689.  
  6690.   /* Set the Capture Compare Register value */
  6691.   TIMx->CCR1 = OC_Config->Pulse;
  6692.  
  6693.   /* Write to TIMx CCER */
  6694.   TIMx->CCER = tmpccer;
  6695. }
  6696.  
  6697. /**
  6698.   * @brief  Timer Output Compare 2 configuration
  6699.   * @param  TIMx to select the TIM peripheral
  6700.   * @param  OC_Config The output configuration structure
  6701.   * @retval None
  6702.   */
  6703. void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6704. {
  6705.   uint32_t tmpccmrx;
  6706.   uint32_t tmpccer;
  6707.   uint32_t tmpcr2;
  6708.  
  6709.   /* Disable the Channel 2: Reset the CC2E Bit */
  6710.   TIMx->CCER &= ~TIM_CCER_CC2E;
  6711.  
  6712.   /* Get the TIMx CCER register value */
  6713.   tmpccer = TIMx->CCER;
  6714.   /* Get the TIMx CR2 register value */
  6715.   tmpcr2 =  TIMx->CR2;
  6716.  
  6717.   /* Get the TIMx CCMR1 register value */
  6718.   tmpccmrx = TIMx->CCMR1;
  6719.  
  6720.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  6721.   tmpccmrx &= ~TIM_CCMR1_OC2M;
  6722.   tmpccmrx &= ~TIM_CCMR1_CC2S;
  6723.  
  6724.   /* Select the Output Compare Mode */
  6725.   tmpccmrx |= (OC_Config->OCMode << 8U);
  6726.  
  6727.   /* Reset the Output Polarity level */
  6728.   tmpccer &= ~TIM_CCER_CC2P;
  6729.   /* Set the Output Compare Polarity */
  6730.   tmpccer |= (OC_Config->OCPolarity << 4U);
  6731.  
  6732.   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
  6733.   {
  6734.     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
  6735.  
  6736.     /* Reset the Output N Polarity level */
  6737.     tmpccer &= ~TIM_CCER_CC2NP;
  6738.     /* Set the Output N Polarity */
  6739.     tmpccer |= (OC_Config->OCNPolarity << 4U);
  6740.     /* Reset the Output N State */
  6741.     tmpccer &= ~TIM_CCER_CC2NE;
  6742.  
  6743.   }
  6744.  
  6745.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  6746.   {
  6747.     /* Check parameters */
  6748.     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
  6749.     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
  6750.  
  6751.     /* Reset the Output Compare and Output Compare N IDLE State */
  6752.     tmpcr2 &= ~TIM_CR2_OIS2;
  6753.     tmpcr2 &= ~TIM_CR2_OIS2N;
  6754.     /* Set the Output Idle state */
  6755.     tmpcr2 |= (OC_Config->OCIdleState << 2U);
  6756.     /* Set the Output N Idle state */
  6757.     tmpcr2 |= (OC_Config->OCNIdleState << 2U);
  6758.   }
  6759.  
  6760.   /* Write to TIMx CR2 */
  6761.   TIMx->CR2 = tmpcr2;
  6762.  
  6763.   /* Write to TIMx CCMR1 */
  6764.   TIMx->CCMR1 = tmpccmrx;
  6765.  
  6766.   /* Set the Capture Compare Register value */
  6767.   TIMx->CCR2 = OC_Config->Pulse;
  6768.  
  6769.   /* Write to TIMx CCER */
  6770.   TIMx->CCER = tmpccer;
  6771. }
  6772.  
  6773. /**
  6774.   * @brief  Timer Output Compare 3 configuration
  6775.   * @param  TIMx to select the TIM peripheral
  6776.   * @param  OC_Config The output configuration structure
  6777.   * @retval None
  6778.   */
  6779. static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6780. {
  6781.   uint32_t tmpccmrx;
  6782.   uint32_t tmpccer;
  6783.   uint32_t tmpcr2;
  6784.  
  6785.   /* Disable the Channel 3: Reset the CC2E Bit */
  6786.   TIMx->CCER &= ~TIM_CCER_CC3E;
  6787.  
  6788.   /* Get the TIMx CCER register value */
  6789.   tmpccer = TIMx->CCER;
  6790.   /* Get the TIMx CR2 register value */
  6791.   tmpcr2 =  TIMx->CR2;
  6792.  
  6793.   /* Get the TIMx CCMR2 register value */
  6794.   tmpccmrx = TIMx->CCMR2;
  6795.  
  6796.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  6797.   tmpccmrx &= ~TIM_CCMR2_OC3M;
  6798.   tmpccmrx &= ~TIM_CCMR2_CC3S;
  6799.   /* Select the Output Compare Mode */
  6800.   tmpccmrx |= OC_Config->OCMode;
  6801.  
  6802.   /* Reset the Output Polarity level */
  6803.   tmpccer &= ~TIM_CCER_CC3P;
  6804.   /* Set the Output Compare Polarity */
  6805.   tmpccer |= (OC_Config->OCPolarity << 8U);
  6806.  
  6807.   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
  6808.   {
  6809.     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
  6810.  
  6811.     /* Reset the Output N Polarity level */
  6812.     tmpccer &= ~TIM_CCER_CC3NP;
  6813.     /* Set the Output N Polarity */
  6814.     tmpccer |= (OC_Config->OCNPolarity << 8U);
  6815.     /* Reset the Output N State */
  6816.     tmpccer &= ~TIM_CCER_CC3NE;
  6817.   }
  6818.  
  6819.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  6820.   {
  6821.     /* Check parameters */
  6822.     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
  6823.     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
  6824.  
  6825.     /* Reset the Output Compare and Output Compare N IDLE State */
  6826.     tmpcr2 &= ~TIM_CR2_OIS3;
  6827.     tmpcr2 &= ~TIM_CR2_OIS3N;
  6828.     /* Set the Output Idle state */
  6829.     tmpcr2 |= (OC_Config->OCIdleState << 4U);
  6830.     /* Set the Output N Idle state */
  6831.     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
  6832.   }
  6833.  
  6834.   /* Write to TIMx CR2 */
  6835.   TIMx->CR2 = tmpcr2;
  6836.  
  6837.   /* Write to TIMx CCMR2 */
  6838.   TIMx->CCMR2 = tmpccmrx;
  6839.  
  6840.   /* Set the Capture Compare Register value */
  6841.   TIMx->CCR3 = OC_Config->Pulse;
  6842.  
  6843.   /* Write to TIMx CCER */
  6844.   TIMx->CCER = tmpccer;
  6845. }
  6846.  
  6847. /**
  6848.   * @brief  Timer Output Compare 4 configuration
  6849.   * @param  TIMx to select the TIM peripheral
  6850.   * @param  OC_Config The output configuration structure
  6851.   * @retval None
  6852.   */
  6853. static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6854. {
  6855.   uint32_t tmpccmrx;
  6856.   uint32_t tmpccer;
  6857.   uint32_t tmpcr2;
  6858.  
  6859.   /* Disable the Channel 4: Reset the CC4E Bit */
  6860.   TIMx->CCER &= ~TIM_CCER_CC4E;
  6861.  
  6862.   /* Get the TIMx CCER register value */
  6863.   tmpccer = TIMx->CCER;
  6864.   /* Get the TIMx CR2 register value */
  6865.   tmpcr2 =  TIMx->CR2;
  6866.  
  6867.   /* Get the TIMx CCMR2 register value */
  6868.   tmpccmrx = TIMx->CCMR2;
  6869.  
  6870.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  6871.   tmpccmrx &= ~TIM_CCMR2_OC4M;
  6872.   tmpccmrx &= ~TIM_CCMR2_CC4S;
  6873.  
  6874.   /* Select the Output Compare Mode */
  6875.   tmpccmrx |= (OC_Config->OCMode << 8U);
  6876.  
  6877.   /* Reset the Output Polarity level */
  6878.   tmpccer &= ~TIM_CCER_CC4P;
  6879.   /* Set the Output Compare Polarity */
  6880.   tmpccer |= (OC_Config->OCPolarity << 12U);
  6881.  
  6882.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  6883.   {
  6884.     /* Check parameters */
  6885.     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
  6886.  
  6887.     /* Reset the Output Compare IDLE State */
  6888.     tmpcr2 &= ~TIM_CR2_OIS4;
  6889.  
  6890.     /* Set the Output Idle state */
  6891.     tmpcr2 |= (OC_Config->OCIdleState << 6U);
  6892.   }
  6893.  
  6894.   /* Write to TIMx CR2 */
  6895.   TIMx->CR2 = tmpcr2;
  6896.  
  6897.   /* Write to TIMx CCMR2 */
  6898.   TIMx->CCMR2 = tmpccmrx;
  6899.  
  6900.   /* Set the Capture Compare Register value */
  6901.   TIMx->CCR4 = OC_Config->Pulse;
  6902.  
  6903.   /* Write to TIMx CCER */
  6904.   TIMx->CCER = tmpccer;
  6905. }
  6906.  
  6907. /**
  6908.   * @brief  Slave Timer configuration function
  6909.   * @param  htim TIM handle
  6910.   * @param  sSlaveConfig Slave timer configuration
  6911.   * @retval None
  6912.   */
  6913. static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
  6914.                                                   TIM_SlaveConfigTypeDef *sSlaveConfig)
  6915. {
  6916.   uint32_t tmpsmcr;
  6917.   uint32_t tmpccmr1;
  6918.   uint32_t tmpccer;
  6919.  
  6920.   /* Get the TIMx SMCR register value */
  6921.   tmpsmcr = htim->Instance->SMCR;
  6922.  
  6923.   /* Reset the Trigger Selection Bits */
  6924.   tmpsmcr &= ~TIM_SMCR_TS;
  6925.   /* Set the Input Trigger source */
  6926.   tmpsmcr |= sSlaveConfig->InputTrigger;
  6927.  
  6928.   /* Reset the slave mode Bits */
  6929.   tmpsmcr &= ~TIM_SMCR_SMS;
  6930.   /* Set the slave mode */
  6931.   tmpsmcr |= sSlaveConfig->SlaveMode;
  6932.  
  6933.   /* Write to TIMx SMCR */
  6934.   htim->Instance->SMCR = tmpsmcr;
  6935.  
  6936.   /* Configure the trigger prescaler, filter, and polarity */
  6937.   switch (sSlaveConfig->InputTrigger)
  6938.   {
  6939.     case TIM_TS_ETRF:
  6940.     {
  6941.       /* Check the parameters */
  6942.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
  6943.       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
  6944.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  6945.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  6946.       /* Configure the ETR Trigger source */
  6947.       TIM_ETR_SetConfig(htim->Instance,
  6948.                         sSlaveConfig->TriggerPrescaler,
  6949.                         sSlaveConfig->TriggerPolarity,
  6950.                         sSlaveConfig->TriggerFilter);
  6951.       break;
  6952.     }
  6953.  
  6954.     case TIM_TS_TI1F_ED:
  6955.     {
  6956.       /* Check the parameters */
  6957.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  6958.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  6959.  
  6960.       if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
  6961.       {
  6962.         return HAL_ERROR;
  6963.       }
  6964.  
  6965.       /* Disable the Channel 1: Reset the CC1E Bit */
  6966.       tmpccer = htim->Instance->CCER;
  6967.       htim->Instance->CCER &= ~TIM_CCER_CC1E;
  6968.       tmpccmr1 = htim->Instance->CCMR1;
  6969.  
  6970.       /* Set the filter */
  6971.       tmpccmr1 &= ~TIM_CCMR1_IC1F;
  6972.       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
  6973.  
  6974.       /* Write to TIMx CCMR1 and CCER registers */
  6975.       htim->Instance->CCMR1 = tmpccmr1;
  6976.       htim->Instance->CCER = tmpccer;
  6977.       break;
  6978.     }
  6979.  
  6980.     case TIM_TS_TI1FP1:
  6981.     {
  6982.       /* Check the parameters */
  6983.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  6984.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  6985.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  6986.  
  6987.       /* Configure TI1 Filter and Polarity */
  6988.       TIM_TI1_ConfigInputStage(htim->Instance,
  6989.                                sSlaveConfig->TriggerPolarity,
  6990.                                sSlaveConfig->TriggerFilter);
  6991.       break;
  6992.     }
  6993.  
  6994.     case TIM_TS_TI2FP2:
  6995.     {
  6996.       /* Check the parameters */
  6997.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  6998.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  6999.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  7000.  
  7001.       /* Configure TI2 Filter and Polarity */
  7002.       TIM_TI2_ConfigInputStage(htim->Instance,
  7003.                                sSlaveConfig->TriggerPolarity,
  7004.                                sSlaveConfig->TriggerFilter);
  7005.       break;
  7006.     }
  7007.  
  7008.     case TIM_TS_ITR0:
  7009.     case TIM_TS_ITR1:
  7010.     case TIM_TS_ITR2:
  7011.     case TIM_TS_ITR3:
  7012.       {
  7013.         /* Check the parameter */
  7014.         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  7015.         break;
  7016.       }
  7017.  
  7018.     default:
  7019.       break;
  7020.   }
  7021.   return HAL_OK;
  7022. }
  7023.  
  7024. /**
  7025.   * @brief  Configure the TI1 as Input.
  7026.   * @param  TIMx to select the TIM peripheral.
  7027.   * @param  TIM_ICPolarity The Input Polarity.
  7028.   *          This parameter can be one of the following values:
  7029.   *            @arg TIM_ICPOLARITY_RISING
  7030.   *            @arg TIM_ICPOLARITY_FALLING
  7031.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  7032.   * @param  TIM_ICSelection specifies the input to be used.
  7033.   *          This parameter can be one of the following values:
  7034.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
  7035.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
  7036.   *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
  7037.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7038.   *          This parameter must be a value between 0x00 and 0x0F.
  7039.   * @retval None
  7040.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
  7041.   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
  7042.   *        protected against un-initialized filter and polarity values.
  7043.   */
  7044. void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  7045.                        uint32_t TIM_ICFilter)
  7046. {
  7047.   uint32_t tmpccmr1;
  7048.   uint32_t tmpccer;
  7049.  
  7050.   /* Disable the Channel 1: Reset the CC1E Bit */
  7051.   TIMx->CCER &= ~TIM_CCER_CC1E;
  7052.   tmpccmr1 = TIMx->CCMR1;
  7053.   tmpccer = TIMx->CCER;
  7054.  
  7055.   /* Select the Input */
  7056.   if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
  7057.   {
  7058.     tmpccmr1 &= ~TIM_CCMR1_CC1S;
  7059.     tmpccmr1 |= TIM_ICSelection;
  7060.   }
  7061.   else
  7062.   {
  7063.     tmpccmr1 |= TIM_CCMR1_CC1S_0;
  7064.   }
  7065.  
  7066.   /* Set the filter */
  7067.   tmpccmr1 &= ~TIM_CCMR1_IC1F;
  7068.   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
  7069.  
  7070.   /* Select the Polarity and set the CC1E Bit */
  7071.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  7072.   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
  7073.  
  7074.   /* Write to TIMx CCMR1 and CCER registers */
  7075.   TIMx->CCMR1 = tmpccmr1;
  7076.   TIMx->CCER = tmpccer;
  7077. }
  7078.  
  7079. /**
  7080.   * @brief  Configure the Polarity and Filter for TI1.
  7081.   * @param  TIMx to select the TIM peripheral.
  7082.   * @param  TIM_ICPolarity The Input Polarity.
  7083.   *          This parameter can be one of the following values:
  7084.   *            @arg TIM_ICPOLARITY_RISING
  7085.   *            @arg TIM_ICPOLARITY_FALLING
  7086.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  7087.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7088.   *          This parameter must be a value between 0x00 and 0x0F.
  7089.   * @retval None
  7090.   */
  7091. static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
  7092. {
  7093.   uint32_t tmpccmr1;
  7094.   uint32_t tmpccer;
  7095.  
  7096.   /* Disable the Channel 1: Reset the CC1E Bit */
  7097.   tmpccer = TIMx->CCER;
  7098.   TIMx->CCER &= ~TIM_CCER_CC1E;
  7099.   tmpccmr1 = TIMx->CCMR1;
  7100.  
  7101.   /* Set the filter */
  7102.   tmpccmr1 &= ~TIM_CCMR1_IC1F;
  7103.   tmpccmr1 |= (TIM_ICFilter << 4U);
  7104.  
  7105.   /* Select the Polarity and set the CC1E Bit */
  7106.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  7107.   tmpccer |= TIM_ICPolarity;
  7108.  
  7109.   /* Write to TIMx CCMR1 and CCER registers */
  7110.   TIMx->CCMR1 = tmpccmr1;
  7111.   TIMx->CCER = tmpccer;
  7112. }
  7113.  
  7114. /**
  7115.   * @brief  Configure the TI2 as Input.
  7116.   * @param  TIMx to select the TIM peripheral
  7117.   * @param  TIM_ICPolarity The Input Polarity.
  7118.   *          This parameter can be one of the following values:
  7119.   *            @arg TIM_ICPOLARITY_RISING
  7120.   *            @arg TIM_ICPOLARITY_FALLING
  7121.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  7122.   * @param  TIM_ICSelection specifies the input to be used.
  7123.   *          This parameter can be one of the following values:
  7124.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
  7125.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
  7126.   *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
  7127.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7128.   *          This parameter must be a value between 0x00 and 0x0F.
  7129.   * @retval None
  7130.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
  7131.   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
  7132.   *        protected against un-initialized filter and polarity values.
  7133.   */
  7134. static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  7135.                               uint32_t TIM_ICFilter)
  7136. {
  7137.   uint32_t tmpccmr1;
  7138.   uint32_t tmpccer;
  7139.  
  7140.   /* Disable the Channel 2: Reset the CC2E Bit */
  7141.   TIMx->CCER &= ~TIM_CCER_CC2E;
  7142.   tmpccmr1 = TIMx->CCMR1;
  7143.   tmpccer = TIMx->CCER;
  7144.  
  7145.   /* Select the Input */
  7146.   tmpccmr1 &= ~TIM_CCMR1_CC2S;
  7147.   tmpccmr1 |= (TIM_ICSelection << 8U);
  7148.  
  7149.   /* Set the filter */
  7150.   tmpccmr1 &= ~TIM_CCMR1_IC2F;
  7151.   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
  7152.  
  7153.   /* Select the Polarity and set the CC2E Bit */
  7154.   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  7155.   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
  7156.  
  7157.   /* Write to TIMx CCMR1 and CCER registers */
  7158.   TIMx->CCMR1 = tmpccmr1 ;
  7159.   TIMx->CCER = tmpccer;
  7160. }
  7161.  
  7162. /**
  7163.   * @brief  Configure the Polarity and Filter for TI2.
  7164.   * @param  TIMx to select the TIM peripheral.
  7165.   * @param  TIM_ICPolarity The Input Polarity.
  7166.   *          This parameter can be one of the following values:
  7167.   *            @arg TIM_ICPOLARITY_RISING
  7168.   *            @arg TIM_ICPOLARITY_FALLING
  7169.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  7170.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7171.   *          This parameter must be a value between 0x00 and 0x0F.
  7172.   * @retval None
  7173.   */
  7174. static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
  7175. {
  7176.   uint32_t tmpccmr1;
  7177.   uint32_t tmpccer;
  7178.  
  7179.   /* Disable the Channel 2: Reset the CC2E Bit */
  7180.   TIMx->CCER &= ~TIM_CCER_CC2E;
  7181.   tmpccmr1 = TIMx->CCMR1;
  7182.   tmpccer = TIMx->CCER;
  7183.  
  7184.   /* Set the filter */
  7185.   tmpccmr1 &= ~TIM_CCMR1_IC2F;
  7186.   tmpccmr1 |= (TIM_ICFilter << 12U);
  7187.  
  7188.   /* Select the Polarity and set the CC2E Bit */
  7189.   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  7190.   tmpccer |= (TIM_ICPolarity << 4U);
  7191.  
  7192.   /* Write to TIMx CCMR1 and CCER registers */
  7193.   TIMx->CCMR1 = tmpccmr1 ;
  7194.   TIMx->CCER = tmpccer;
  7195. }
  7196.  
  7197. /**
  7198.   * @brief  Configure the TI3 as Input.
  7199.   * @param  TIMx to select the TIM peripheral
  7200.   * @param  TIM_ICPolarity The Input Polarity.
  7201.   *          This parameter can be one of the following values:
  7202.   *            @arg TIM_ICPOLARITY_RISING
  7203.   *            @arg TIM_ICPOLARITY_FALLING
  7204.   * @param  TIM_ICSelection specifies the input to be used.
  7205.   *          This parameter can be one of the following values:
  7206.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
  7207.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
  7208.   *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
  7209.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7210.   *          This parameter must be a value between 0x00 and 0x0F.
  7211.   * @retval None
  7212.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
  7213.   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
  7214.   *        protected against un-initialized filter and polarity values.
  7215.   */
  7216. static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  7217.                               uint32_t TIM_ICFilter)
  7218. {
  7219.   uint32_t tmpccmr2;
  7220.   uint32_t tmpccer;
  7221.  
  7222.   /* Disable the Channel 3: Reset the CC3E Bit */
  7223.   TIMx->CCER &= ~TIM_CCER_CC3E;
  7224.   tmpccmr2 = TIMx->CCMR2;
  7225.   tmpccer = TIMx->CCER;
  7226.  
  7227.   /* Select the Input */
  7228.   tmpccmr2 &= ~TIM_CCMR2_CC3S;
  7229.   tmpccmr2 |= TIM_ICSelection;
  7230.  
  7231.   /* Set the filter */
  7232.   tmpccmr2 &= ~TIM_CCMR2_IC3F;
  7233.   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
  7234.  
  7235.   /* Select the Polarity and set the CC3E Bit */
  7236.   tmpccer &= ~(TIM_CCER_CC3P);
  7237.   tmpccer |= ((TIM_ICPolarity << 8U) & TIM_CCER_CC3P);
  7238.  
  7239.   /* Write to TIMx CCMR2 and CCER registers */
  7240.   TIMx->CCMR2 = tmpccmr2;
  7241.   TIMx->CCER = tmpccer;
  7242. }
  7243.  
  7244. /**
  7245.   * @brief  Configure the TI4 as Input.
  7246.   * @param  TIMx to select the TIM peripheral
  7247.   * @param  TIM_ICPolarity The Input Polarity.
  7248.   *          This parameter can be one of the following values:
  7249.   *            @arg TIM_ICPOLARITY_RISING
  7250.   *            @arg TIM_ICPOLARITY_FALLING
  7251.   * @param  TIM_ICSelection specifies the input to be used.
  7252.   *          This parameter can be one of the following values:
  7253.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
  7254.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
  7255.   *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
  7256.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7257.   *          This parameter must be a value between 0x00 and 0x0F.
  7258.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
  7259.   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
  7260.   *        protected against un-initialized filter and polarity values.
  7261.   * @retval None
  7262.   */
  7263. static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  7264.                               uint32_t TIM_ICFilter)
  7265. {
  7266.   uint32_t tmpccmr2;
  7267.   uint32_t tmpccer;
  7268.  
  7269.   /* Disable the Channel 4: Reset the CC4E Bit */
  7270.   TIMx->CCER &= ~TIM_CCER_CC4E;
  7271.   tmpccmr2 = TIMx->CCMR2;
  7272.   tmpccer = TIMx->CCER;
  7273.  
  7274.   /* Select the Input */
  7275.   tmpccmr2 &= ~TIM_CCMR2_CC4S;
  7276.   tmpccmr2 |= (TIM_ICSelection << 8U);
  7277.  
  7278.   /* Set the filter */
  7279.   tmpccmr2 &= ~TIM_CCMR2_IC4F;
  7280.   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
  7281.  
  7282.   /* Select the Polarity and set the CC4E Bit */
  7283.   tmpccer &= ~(TIM_CCER_CC4P);
  7284.   tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P);
  7285.  
  7286.   /* Write to TIMx CCMR2 and CCER registers */
  7287.   TIMx->CCMR2 = tmpccmr2;
  7288.   TIMx->CCER = tmpccer ;
  7289. }
  7290.  
  7291. /**
  7292.   * @brief  Selects the Input Trigger source
  7293.   * @param  TIMx to select the TIM peripheral
  7294.   * @param  InputTriggerSource The Input Trigger source.
  7295.   *          This parameter can be one of the following values:
  7296.   *            @arg TIM_TS_ITR0: Internal Trigger 0
  7297.   *            @arg TIM_TS_ITR1: Internal Trigger 1
  7298.   *            @arg TIM_TS_ITR2: Internal Trigger 2
  7299.   *            @arg TIM_TS_ITR3: Internal Trigger 3
  7300.   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
  7301.   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
  7302.   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
  7303.   *            @arg TIM_TS_ETRF: External Trigger input
  7304.   * @retval None
  7305.   */
  7306. static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
  7307. {
  7308.   uint32_t tmpsmcr;
  7309.  
  7310.   /* Get the TIMx SMCR register value */
  7311.   tmpsmcr = TIMx->SMCR;
  7312.   /* Reset the TS Bits */
  7313.   tmpsmcr &= ~TIM_SMCR_TS;
  7314.   /* Set the Input Trigger source and the slave mode*/
  7315.   tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
  7316.   /* Write to TIMx SMCR */
  7317.   TIMx->SMCR = tmpsmcr;
  7318. }
  7319. /**
  7320.   * @brief  Configures the TIMx External Trigger (ETR).
  7321.   * @param  TIMx to select the TIM peripheral
  7322.   * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
  7323.   *          This parameter can be one of the following values:
  7324.   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
  7325.   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
  7326.   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
  7327.   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
  7328.   * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
  7329.   *          This parameter can be one of the following values:
  7330.   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
  7331.   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
  7332.   * @param  ExtTRGFilter External Trigger Filter.
  7333.   *          This parameter must be a value between 0x00 and 0x0F
  7334.   * @retval None
  7335.   */
  7336. void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
  7337.                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
  7338. {
  7339.   uint32_t tmpsmcr;
  7340.  
  7341.   tmpsmcr = TIMx->SMCR;
  7342.  
  7343.   /* Reset the ETR Bits */
  7344.   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  7345.  
  7346.   /* Set the Prescaler, the Filter value and the Polarity */
  7347.   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
  7348.  
  7349.   /* Write to TIMx SMCR */
  7350.   TIMx->SMCR = tmpsmcr;
  7351. }
  7352.  
  7353. /**
  7354.   * @brief  Enables or disables the TIM Capture Compare Channel x.
  7355.   * @param  TIMx to select the TIM peripheral
  7356.   * @param  Channel specifies the TIM Channel
  7357.   *          This parameter can be one of the following values:
  7358.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  7359.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  7360.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  7361.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  7362.   * @param  ChannelState specifies the TIM Channel CCxE bit new state.
  7363.   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
  7364.   * @retval None
  7365.   */
  7366. void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
  7367. {
  7368.   uint32_t tmp;
  7369.  
  7370.   /* Check the parameters */
  7371.   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  7372.   assert_param(IS_TIM_CHANNELS(Channel));
  7373.  
  7374.   tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
  7375.  
  7376.   /* Reset the CCxE Bit */
  7377.   TIMx->CCER &= ~tmp;
  7378.  
  7379.   /* Set or reset the CCxE Bit */
  7380.   TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
  7381. }
  7382.  
  7383. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  7384. /**
  7385.   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
  7386.   * @param  htim pointer to a TIM_HandleTypeDef structure that contains
  7387.   *                the configuration information for TIM module.
  7388.   * @retval None
  7389.   */
  7390. void TIM_ResetCallback(TIM_HandleTypeDef *htim)
  7391. {
  7392.   /* Reset the TIM callback to the legacy weak callbacks */
  7393.   htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */
  7394.   htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */
  7395.   htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */
  7396.   htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */
  7397.   htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */
  7398.   htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */
  7399.   htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */
  7400.   htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */
  7401.   htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
  7402.   htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */
  7403.   htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak CommutationCallback               */
  7404.   htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak CommutationHalfCpltCallback       */
  7405.   htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak BreakCallback                     */
  7406. }
  7407. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  7408.  
  7409. /**
  7410.   * @}
  7411.   */
  7412.  
  7413. #endif /* HAL_TIM_MODULE_ENABLED */
  7414. /**
  7415.   * @}
  7416.   */
  7417.  
  7418. /**
  7419.   * @}
  7420.   */
  7421. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  7422.