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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_tim.c
  4.   * @author  MCD Application Team
  5.   * @brief   TIM HAL module driver.
  6.   *          This file provides firmware functions to manage the following
  7.   *          functionalities of the Timer (TIM) peripheral:
  8.   *           + TIM Time Base Initialization
  9.   *           + TIM Time Base Start
  10.   *           + TIM Time Base Start Interruption
  11.   *           + TIM Time Base Start DMA
  12.   *           + TIM Output Compare/PWM Initialization
  13.   *           + TIM Output Compare/PWM Channel Configuration
  14.   *           + TIM Output Compare/PWM  Start
  15.   *           + TIM Output Compare/PWM  Start Interruption
  16.   *           + TIM Output Compare/PWM Start DMA
  17.   *           + TIM Input Capture Initialization
  18.   *           + TIM Input Capture Channel Configuration
  19.   *           + TIM Input Capture Start
  20.   *           + TIM Input Capture Start Interruption
  21.   *           + TIM Input Capture Start DMA
  22.   *           + TIM One Pulse Initialization
  23.   *           + TIM One Pulse Channel Configuration
  24.   *           + TIM One Pulse Start
  25.   *           + TIM Encoder Interface Initialization
  26.   *           + TIM Encoder Interface Start
  27.   *           + TIM Encoder Interface Start Interruption
  28.   *           + TIM Encoder Interface Start DMA
  29.   *           + Commutation Event configuration with Interruption and DMA
  30.   *           + TIM OCRef clear configuration
  31.   *           + TIM External Clock configuration
  32.   ******************************************************************************
  33.   * @attention
  34.   *
  35.   * Copyright (c) 2016 STMicroelectronics.
  36.   * All rights reserved.
  37.   *
  38.   * This software is licensed under terms that can be found in the LICENSE file
  39.   * in the root directory of this software component.
  40.   * If no LICENSE file comes with this software, it is provided AS-IS.
  41.   *
  42.   ******************************************************************************
  43.   @verbatim
  44.   ==============================================================================
  45.                       ##### TIMER Generic features #####
  46.   ==============================================================================
  47.   [..] The Timer features include:
  48.        (#) 16-bit up, down, up/down auto-reload counter.
  49.        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
  50.            counter clock frequency either by any factor between 1 and 65536.
  51.        (#) Up to 4 independent channels for:
  52.            (++) Input Capture
  53.            (++) Output Compare
  54.            (++) PWM generation (Edge and Center-aligned Mode)
  55.            (++) One-pulse mode output
  56.        (#) Synchronization circuit to control the timer with external signals and to interconnect
  57.             several timers together.
  58.        (#) Supports incremental encoder for positioning purposes
  59.  
  60.             ##### How to use this driver #####
  61.   ==============================================================================
  62.     [..]
  63.      (#) Initialize the TIM low level resources by implementing the following functions
  64.          depending on the selected feature:
  65.            (++) Time Base : HAL_TIM_Base_MspInit()
  66.            (++) Input Capture : HAL_TIM_IC_MspInit()
  67.            (++) Output Compare : HAL_TIM_OC_MspInit()
  68.            (++) PWM generation : HAL_TIM_PWM_MspInit()
  69.            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
  70.            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
  71.  
  72.      (#) Initialize the TIM low level resources :
  73.         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
  74.         (##) TIM pins configuration
  75.             (+++) Enable the clock for the TIM GPIOs using the following function:
  76.              __HAL_RCC_GPIOx_CLK_ENABLE();
  77.             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
  78.  
  79.      (#) The external Clock can be configured, if needed (the default clock is the
  80.          internal clock from the APBx), using the following function:
  81.          HAL_TIM_ConfigClockSource, the clock configuration should be done before
  82.          any start function.
  83.  
  84.      (#) Configure the TIM in the desired functioning mode using one of the
  85.        Initialization function of this driver:
  86.        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
  87.        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
  88.             Output Compare signal.
  89.        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
  90.             PWM signal.
  91.        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
  92.             external signal.
  93.        (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
  94.             in One Pulse Mode.
  95.        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
  96.  
  97.      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
  98.            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
  99.            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
  100.            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
  101.            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
  102.            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
  103.            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
  104.  
  105.      (#) The DMA Burst is managed with the two following functions:
  106.          HAL_TIM_DMABurst_WriteStart()
  107.          HAL_TIM_DMABurst_ReadStart()
  108.  
  109.     *** Callback registration ***
  110.   =============================================
  111.  
  112.   [..]
  113.   The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
  114.   allows the user to configure dynamically the driver callbacks.
  115.  
  116.   [..]
  117.   Use Function HAL_TIM_RegisterCallback() to register a callback.
  118.   HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
  119.   the Callback ID and a pointer to the user callback function.
  120.  
  121.   [..]
  122.   Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
  123.   weak function.
  124.   HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
  125.   and the Callback ID.
  126.  
  127.   [..]
  128.   These functions allow to register/unregister following callbacks:
  129.     (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
  130.     (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
  131.     (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
  132.     (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
  133.     (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
  134.     (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
  135.     (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
  136.     (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
  137.     (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
  138.     (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
  139.     (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
  140.     (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
  141.     (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
  142.     (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
  143.     (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
  144.     (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
  145.     (+) TriggerCallback                   : TIM Trigger Callback.
  146.     (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
  147.     (+) IC_CaptureCallback                : TIM Input Capture Callback.
  148.     (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
  149.     (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
  150.     (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
  151.     (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
  152.     (+) ErrorCallback                     : TIM Error Callback.
  153.     (+) CommutationCallback               : TIM Commutation Callback.
  154.     (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
  155.     (+) BreakCallback                     : TIM Break Callback.
  156.  
  157.   [..]
  158. By default, after the Init and when the state is HAL_TIM_STATE_RESET
  159. all interrupt callbacks are set to the corresponding weak functions:
  160.   examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
  161.  
  162.   [..]
  163.   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
  164.   functionalities in the Init / DeInit only when these callbacks are null
  165.   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
  166.     keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
  167.  
  168.   [..]
  169.     Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
  170.     Exception done MspInit / MspDeInit that can be registered / unregistered
  171.     in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
  172.     thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
  173.   In that case first register the MspInit/MspDeInit user callbacks
  174.       using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
  175.  
  176.   [..]
  177.       When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
  178.       not defined, the callback registration feature is not available and all callbacks
  179.       are set to the corresponding weak functions.
  180.  
  181.   @endverbatim
  182.   ******************************************************************************
  183.   */
  184.  
  185. /* Includes ------------------------------------------------------------------*/
  186. #include "stm32f1xx_hal.h"
  187.  
  188. /** @addtogroup STM32F1xx_HAL_Driver
  189.   * @{
  190.   */
  191.  
  192. /** @defgroup TIM TIM
  193.   * @brief TIM HAL module driver
  194.   * @{
  195.   */
  196.  
  197. #ifdef HAL_TIM_MODULE_ENABLED
  198.  
  199. /* Private typedef -----------------------------------------------------------*/
  200. /* Private define ------------------------------------------------------------*/
  201. /* Private macros ------------------------------------------------------------*/
  202. /* Private variables ---------------------------------------------------------*/
  203. /* Private function prototypes -----------------------------------------------*/
  204. /** @addtogroup TIM_Private_Functions
  205.   * @{
  206.   */
  207. static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
  208. static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
  209. static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
  210. static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
  211. static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  212.                               uint32_t TIM_ICFilter);
  213. static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
  214. static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  215.                               uint32_t TIM_ICFilter);
  216. static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  217.                               uint32_t TIM_ICFilter);
  218. static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
  219. static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
  220. static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
  221. static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
  222. static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
  223. static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
  224. static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
  225.                                                   const TIM_SlaveConfigTypeDef *sSlaveConfig);
  226. /**
  227.   * @}
  228.   */
  229. /* Exported functions --------------------------------------------------------*/
  230.  
  231. /** @defgroup TIM_Exported_Functions TIM Exported Functions
  232.   * @{
  233.   */
  234.  
  235. /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
  236.   *  @brief    Time Base functions
  237.   *
  238. @verbatim
  239.   ==============================================================================
  240.               ##### Time Base functions #####
  241.   ==============================================================================
  242.   [..]
  243.     This section provides functions allowing to:
  244.     (+) Initialize and configure the TIM base.
  245.     (+) De-initialize the TIM base.
  246.     (+) Start the Time Base.
  247.     (+) Stop the Time Base.
  248.     (+) Start the Time Base and enable interrupt.
  249.     (+) Stop the Time Base and disable interrupt.
  250.     (+) Start the Time Base and enable DMA transfer.
  251.     (+) Stop the Time Base and disable DMA transfer.
  252.  
  253. @endverbatim
  254.   * @{
  255.   */
  256. /**
  257.   * @brief  Initializes the TIM Time base Unit according to the specified
  258.   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
  259.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  260.   *         requires a timer reset to avoid unexpected direction
  261.   *         due to DIR bit readonly in center aligned mode.
  262.   *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  263.   * @param  htim TIM Base handle
  264.   * @retval HAL status
  265.   */
  266. HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
  267. {
  268.   /* Check the TIM handle allocation */
  269.   if (htim == NULL)
  270.   {
  271.     return HAL_ERROR;
  272.   }
  273.  
  274.   /* Check the parameters */
  275.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  276.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  277.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  278.   assert_param(IS_TIM_PERIOD(htim->Init.Period));
  279.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  280.  
  281.   if (htim->State == HAL_TIM_STATE_RESET)
  282.   {
  283.     /* Allocate lock resource and initialize it */
  284.     htim->Lock = HAL_UNLOCKED;
  285.  
  286. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  287.     /* Reset interrupt callbacks to legacy weak callbacks */
  288.     TIM_ResetCallback(htim);
  289.  
  290.     if (htim->Base_MspInitCallback == NULL)
  291.     {
  292.       htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
  293.     }
  294.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  295.     htim->Base_MspInitCallback(htim);
  296. #else
  297.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  298.     HAL_TIM_Base_MspInit(htim);
  299. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  300.   }
  301.  
  302.   /* Set the TIM state */
  303.   htim->State = HAL_TIM_STATE_BUSY;
  304.  
  305.   /* Set the Time Base configuration */
  306.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  307.  
  308.   /* Initialize the DMA burst operation state */
  309.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  310.  
  311.   /* Initialize the TIM channels state */
  312.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  313.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  314.  
  315.   /* Initialize the TIM state*/
  316.   htim->State = HAL_TIM_STATE_READY;
  317.  
  318.   return HAL_OK;
  319. }
  320.  
  321. /**
  322.   * @brief  DeInitializes the TIM Base peripheral
  323.   * @param  htim TIM Base handle
  324.   * @retval HAL status
  325.   */
  326. HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
  327. {
  328.   /* Check the parameters */
  329.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  330.  
  331.   htim->State = HAL_TIM_STATE_BUSY;
  332.  
  333.   /* Disable the TIM Peripheral Clock */
  334.   __HAL_TIM_DISABLE(htim);
  335.  
  336. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  337.   if (htim->Base_MspDeInitCallback == NULL)
  338.   {
  339.     htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
  340.   }
  341.   /* DeInit the low level hardware */
  342.   htim->Base_MspDeInitCallback(htim);
  343. #else
  344.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  345.   HAL_TIM_Base_MspDeInit(htim);
  346. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  347.  
  348.   /* Change the DMA burst operation state */
  349.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  350.  
  351.   /* Change the TIM channels state */
  352.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  353.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  354.  
  355.   /* Change TIM state */
  356.   htim->State = HAL_TIM_STATE_RESET;
  357.  
  358.   /* Release Lock */
  359.   __HAL_UNLOCK(htim);
  360.  
  361.   return HAL_OK;
  362. }
  363.  
  364. /**
  365.   * @brief  Initializes the TIM Base MSP.
  366.   * @param  htim TIM Base handle
  367.   * @retval None
  368.   */
  369. __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
  370. {
  371.   /* Prevent unused argument(s) compilation warning */
  372.   UNUSED(htim);
  373.  
  374.   /* NOTE : This function should not be modified, when the callback is needed,
  375.             the HAL_TIM_Base_MspInit could be implemented in the user file
  376.    */
  377. }
  378.  
  379. /**
  380.   * @brief  DeInitializes TIM Base MSP.
  381.   * @param  htim TIM Base handle
  382.   * @retval None
  383.   */
  384. __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
  385. {
  386.   /* Prevent unused argument(s) compilation warning */
  387.   UNUSED(htim);
  388.  
  389.   /* NOTE : This function should not be modified, when the callback is needed,
  390.             the HAL_TIM_Base_MspDeInit could be implemented in the user file
  391.    */
  392. }
  393.  
  394.  
  395. /**
  396.   * @brief  Starts the TIM Base generation.
  397.   * @param  htim TIM Base handle
  398.   * @retval HAL status
  399.   */
  400. HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
  401. {
  402.   uint32_t tmpsmcr;
  403.  
  404.   /* Check the parameters */
  405.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  406.  
  407.   /* Check the TIM state */
  408.   if (htim->State != HAL_TIM_STATE_READY)
  409.   {
  410.     return HAL_ERROR;
  411.   }
  412.  
  413.   /* Set the TIM state */
  414.   htim->State = HAL_TIM_STATE_BUSY;
  415.  
  416.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  417.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  418.   {
  419.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  420.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  421.     {
  422.       __HAL_TIM_ENABLE(htim);
  423.     }
  424.   }
  425.   else
  426.   {
  427.     __HAL_TIM_ENABLE(htim);
  428.   }
  429.  
  430.   /* Return function status */
  431.   return HAL_OK;
  432. }
  433.  
  434. /**
  435.   * @brief  Stops the TIM Base generation.
  436.   * @param  htim TIM Base handle
  437.   * @retval HAL status
  438.   */
  439. HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
  440. {
  441.   /* Check the parameters */
  442.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  443.  
  444.   /* Disable the Peripheral */
  445.   __HAL_TIM_DISABLE(htim);
  446.  
  447.   /* Set the TIM state */
  448.   htim->State = HAL_TIM_STATE_READY;
  449.  
  450.   /* Return function status */
  451.   return HAL_OK;
  452. }
  453.  
  454. /**
  455.   * @brief  Starts the TIM Base generation in interrupt mode.
  456.   * @param  htim TIM Base handle
  457.   * @retval HAL status
  458.   */
  459. HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
  460. {
  461.   uint32_t tmpsmcr;
  462.  
  463.   /* Check the parameters */
  464.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  465.  
  466.   /* Check the TIM state */
  467.   if (htim->State != HAL_TIM_STATE_READY)
  468.   {
  469.     return HAL_ERROR;
  470.   }
  471.  
  472.   /* Set the TIM state */
  473.   htim->State = HAL_TIM_STATE_BUSY;
  474.  
  475.   /* Enable the TIM Update interrupt */
  476.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
  477.  
  478.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  479.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  480.   {
  481.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  482.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  483.     {
  484.       __HAL_TIM_ENABLE(htim);
  485.     }
  486.   }
  487.   else
  488.   {
  489.     __HAL_TIM_ENABLE(htim);
  490.   }
  491.  
  492.   /* Return function status */
  493.   return HAL_OK;
  494. }
  495.  
  496. /**
  497.   * @brief  Stops the TIM Base generation in interrupt mode.
  498.   * @param  htim TIM Base handle
  499.   * @retval HAL status
  500.   */
  501. HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
  502. {
  503.   /* Check the parameters */
  504.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  505.  
  506.   /* Disable the TIM Update interrupt */
  507.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
  508.  
  509.   /* Disable the Peripheral */
  510.   __HAL_TIM_DISABLE(htim);
  511.  
  512.   /* Set the TIM state */
  513.   htim->State = HAL_TIM_STATE_READY;
  514.  
  515.   /* Return function status */
  516.   return HAL_OK;
  517. }
  518.  
  519. /**
  520.   * @brief  Starts the TIM Base generation in DMA mode.
  521.   * @param  htim TIM Base handle
  522.   * @param  pData The source Buffer address.
  523.   * @param  Length The length of data to be transferred from memory to peripheral.
  524.   * @retval HAL status
  525.   */
  526. HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
  527. {
  528.   uint32_t tmpsmcr;
  529.  
  530.   /* Check the parameters */
  531.   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
  532.  
  533.   /* Set the TIM state */
  534.   if (htim->State == HAL_TIM_STATE_BUSY)
  535.   {
  536.     return HAL_BUSY;
  537.   }
  538.   else if (htim->State == HAL_TIM_STATE_READY)
  539.   {
  540.     if ((pData == NULL) || (Length == 0U))
  541.     {
  542.       return HAL_ERROR;
  543.     }
  544.     else
  545.     {
  546.       htim->State = HAL_TIM_STATE_BUSY;
  547.     }
  548.   }
  549.   else
  550.   {
  551.     return HAL_ERROR;
  552.   }
  553.  
  554.   /* Set the DMA Period elapsed callbacks */
  555.   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  556.   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  557.  
  558.   /* Set the DMA error callback */
  559.   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  560.  
  561.   /* Enable the DMA channel */
  562.   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
  563.                        Length) != HAL_OK)
  564.   {
  565.     /* Return error status */
  566.     return HAL_ERROR;
  567.   }
  568.  
  569.   /* Enable the TIM Update DMA request */
  570.   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
  571.  
  572.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  573.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  574.   {
  575.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  576.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  577.     {
  578.       __HAL_TIM_ENABLE(htim);
  579.     }
  580.   }
  581.   else
  582.   {
  583.     __HAL_TIM_ENABLE(htim);
  584.   }
  585.  
  586.   /* Return function status */
  587.   return HAL_OK;
  588. }
  589.  
  590. /**
  591.   * @brief  Stops the TIM Base generation in DMA mode.
  592.   * @param  htim TIM Base handle
  593.   * @retval HAL status
  594.   */
  595. HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
  596. {
  597.   /* Check the parameters */
  598.   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
  599.  
  600.   /* Disable the TIM Update DMA request */
  601.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
  602.  
  603.   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  604.  
  605.   /* Disable the Peripheral */
  606.   __HAL_TIM_DISABLE(htim);
  607.  
  608.   /* Set the TIM state */
  609.   htim->State = HAL_TIM_STATE_READY;
  610.  
  611.   /* Return function status */
  612.   return HAL_OK;
  613. }
  614.  
  615. /**
  616.   * @}
  617.   */
  618.  
  619. /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
  620.   *  @brief    TIM Output Compare functions
  621.   *
  622. @verbatim
  623.   ==============================================================================
  624.                   ##### TIM Output Compare functions #####
  625.   ==============================================================================
  626.   [..]
  627.     This section provides functions allowing to:
  628.     (+) Initialize and configure the TIM Output Compare.
  629.     (+) De-initialize the TIM Output Compare.
  630.     (+) Start the TIM Output Compare.
  631.     (+) Stop the TIM Output Compare.
  632.     (+) Start the TIM Output Compare and enable interrupt.
  633.     (+) Stop the TIM Output Compare and disable interrupt.
  634.     (+) Start the TIM Output Compare and enable DMA transfer.
  635.     (+) Stop the TIM Output Compare and disable DMA transfer.
  636.  
  637. @endverbatim
  638.   * @{
  639.   */
  640. /**
  641.   * @brief  Initializes the TIM Output Compare according to the specified
  642.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  643.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  644.   *         requires a timer reset to avoid unexpected direction
  645.   *         due to DIR bit readonly in center aligned mode.
  646.   *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
  647.   * @param  htim TIM Output Compare handle
  648.   * @retval HAL status
  649.   */
  650. HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
  651. {
  652.   /* Check the TIM handle allocation */
  653.   if (htim == NULL)
  654.   {
  655.     return HAL_ERROR;
  656.   }
  657.  
  658.   /* Check the parameters */
  659.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  660.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  661.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  662.   assert_param(IS_TIM_PERIOD(htim->Init.Period));
  663.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  664.  
  665.   if (htim->State == HAL_TIM_STATE_RESET)
  666.   {
  667.     /* Allocate lock resource and initialize it */
  668.     htim->Lock = HAL_UNLOCKED;
  669.  
  670. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  671.     /* Reset interrupt callbacks to legacy weak callbacks */
  672.     TIM_ResetCallback(htim);
  673.  
  674.     if (htim->OC_MspInitCallback == NULL)
  675.     {
  676.       htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
  677.     }
  678.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  679.     htim->OC_MspInitCallback(htim);
  680. #else
  681.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  682.     HAL_TIM_OC_MspInit(htim);
  683. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  684.   }
  685.  
  686.   /* Set the TIM state */
  687.   htim->State = HAL_TIM_STATE_BUSY;
  688.  
  689.   /* Init the base time for the Output Compare */
  690.   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
  691.  
  692.   /* Initialize the DMA burst operation state */
  693.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  694.  
  695.   /* Initialize the TIM channels state */
  696.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  697.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  698.  
  699.   /* Initialize the TIM state*/
  700.   htim->State = HAL_TIM_STATE_READY;
  701.  
  702.   return HAL_OK;
  703. }
  704.  
  705. /**
  706.   * @brief  DeInitializes the TIM peripheral
  707.   * @param  htim TIM Output Compare handle
  708.   * @retval HAL status
  709.   */
  710. HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
  711. {
  712.   /* Check the parameters */
  713.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  714.  
  715.   htim->State = HAL_TIM_STATE_BUSY;
  716.  
  717.   /* Disable the TIM Peripheral Clock */
  718.   __HAL_TIM_DISABLE(htim);
  719.  
  720. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  721.   if (htim->OC_MspDeInitCallback == NULL)
  722.   {
  723.     htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
  724.   }
  725.   /* DeInit the low level hardware */
  726.   htim->OC_MspDeInitCallback(htim);
  727. #else
  728.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  729.   HAL_TIM_OC_MspDeInit(htim);
  730. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  731.  
  732.   /* Change the DMA burst operation state */
  733.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  734.  
  735.   /* Change the TIM channels state */
  736.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  737.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  738.  
  739.   /* Change TIM state */
  740.   htim->State = HAL_TIM_STATE_RESET;
  741.  
  742.   /* Release Lock */
  743.   __HAL_UNLOCK(htim);
  744.  
  745.   return HAL_OK;
  746. }
  747.  
  748. /**
  749.   * @brief  Initializes the TIM Output Compare MSP.
  750.   * @param  htim TIM Output Compare handle
  751.   * @retval None
  752.   */
  753. __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
  754. {
  755.   /* Prevent unused argument(s) compilation warning */
  756.   UNUSED(htim);
  757.  
  758.   /* NOTE : This function should not be modified, when the callback is needed,
  759.             the HAL_TIM_OC_MspInit could be implemented in the user file
  760.    */
  761. }
  762.  
  763. /**
  764.   * @brief  DeInitializes TIM Output Compare MSP.
  765.   * @param  htim TIM Output Compare handle
  766.   * @retval None
  767.   */
  768. __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
  769. {
  770.   /* Prevent unused argument(s) compilation warning */
  771.   UNUSED(htim);
  772.  
  773.   /* NOTE : This function should not be modified, when the callback is needed,
  774.             the HAL_TIM_OC_MspDeInit could be implemented in the user file
  775.    */
  776. }
  777.  
  778. /**
  779.   * @brief  Starts the TIM Output Compare signal generation.
  780.   * @param  htim TIM Output Compare handle
  781.   * @param  Channel TIM Channel to be enabled
  782.   *          This parameter can be one of the following values:
  783.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  784.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  785.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  786.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  787.   * @retval HAL status
  788.   */
  789. HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  790. {
  791.   uint32_t tmpsmcr;
  792.  
  793.   /* Check the parameters */
  794.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  795.  
  796.   /* Check the TIM channel state */
  797.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  798.   {
  799.     return HAL_ERROR;
  800.   }
  801.  
  802.   /* Set the TIM channel state */
  803.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  804.  
  805.   /* Enable the Output compare channel */
  806.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  807.  
  808.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  809.   {
  810.     /* Enable the main output */
  811.     __HAL_TIM_MOE_ENABLE(htim);
  812.   }
  813.  
  814.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  815.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  816.   {
  817.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  818.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  819.     {
  820.       __HAL_TIM_ENABLE(htim);
  821.     }
  822.   }
  823.   else
  824.   {
  825.     __HAL_TIM_ENABLE(htim);
  826.   }
  827.  
  828.   /* Return function status */
  829.   return HAL_OK;
  830. }
  831.  
  832. /**
  833.   * @brief  Stops the TIM Output Compare signal generation.
  834.   * @param  htim TIM Output Compare handle
  835.   * @param  Channel TIM Channel to be disabled
  836.   *          This parameter can be one of the following values:
  837.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  838.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  839.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  840.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  841.   * @retval HAL status
  842.   */
  843. HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  844. {
  845.   /* Check the parameters */
  846.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  847.  
  848.   /* Disable the Output compare channel */
  849.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  850.  
  851.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  852.   {
  853.     /* Disable the Main Output */
  854.     __HAL_TIM_MOE_DISABLE(htim);
  855.   }
  856.  
  857.   /* Disable the Peripheral */
  858.   __HAL_TIM_DISABLE(htim);
  859.  
  860.   /* Set the TIM channel state */
  861.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  862.  
  863.   /* Return function status */
  864.   return HAL_OK;
  865. }
  866.  
  867. /**
  868.   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
  869.   * @param  htim TIM Output Compare handle
  870.   * @param  Channel TIM Channel to be enabled
  871.   *          This parameter can be one of the following values:
  872.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  873.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  874.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  875.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  876.   * @retval HAL status
  877.   */
  878. HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  879. {
  880.   HAL_StatusTypeDef status = HAL_OK;
  881.   uint32_t tmpsmcr;
  882.  
  883.   /* Check the parameters */
  884.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  885.  
  886.   /* Check the TIM channel state */
  887.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  888.   {
  889.     return HAL_ERROR;
  890.   }
  891.  
  892.   /* Set the TIM channel state */
  893.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  894.  
  895.   switch (Channel)
  896.   {
  897.     case TIM_CHANNEL_1:
  898.     {
  899.       /* Enable the TIM Capture/Compare 1 interrupt */
  900.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  901.       break;
  902.     }
  903.  
  904.     case TIM_CHANNEL_2:
  905.     {
  906.       /* Enable the TIM Capture/Compare 2 interrupt */
  907.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  908.       break;
  909.     }
  910.  
  911.     case TIM_CHANNEL_3:
  912.     {
  913.       /* Enable the TIM Capture/Compare 3 interrupt */
  914.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  915.       break;
  916.     }
  917.  
  918.     case TIM_CHANNEL_4:
  919.     {
  920.       /* Enable the TIM Capture/Compare 4 interrupt */
  921.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  922.       break;
  923.     }
  924.  
  925.     default:
  926.       status = HAL_ERROR;
  927.       break;
  928.   }
  929.  
  930.   if (status == HAL_OK)
  931.   {
  932.     /* Enable the Output compare channel */
  933.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  934.  
  935.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  936.     {
  937.       /* Enable the main output */
  938.       __HAL_TIM_MOE_ENABLE(htim);
  939.     }
  940.  
  941.     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  942.     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  943.     {
  944.       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  945.       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  946.       {
  947.         __HAL_TIM_ENABLE(htim);
  948.       }
  949.     }
  950.     else
  951.     {
  952.       __HAL_TIM_ENABLE(htim);
  953.     }
  954.   }
  955.  
  956.   /* Return function status */
  957.   return status;
  958. }
  959.  
  960. /**
  961.   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
  962.   * @param  htim TIM Output Compare handle
  963.   * @param  Channel TIM Channel to be disabled
  964.   *          This parameter can be one of the following values:
  965.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  966.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  967.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  968.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  969.   * @retval HAL status
  970.   */
  971. HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  972. {
  973.   HAL_StatusTypeDef status = HAL_OK;
  974.  
  975.   /* Check the parameters */
  976.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  977.  
  978.   switch (Channel)
  979.   {
  980.     case TIM_CHANNEL_1:
  981.     {
  982.       /* Disable the TIM Capture/Compare 1 interrupt */
  983.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  984.       break;
  985.     }
  986.  
  987.     case TIM_CHANNEL_2:
  988.     {
  989.       /* Disable the TIM Capture/Compare 2 interrupt */
  990.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  991.       break;
  992.     }
  993.  
  994.     case TIM_CHANNEL_3:
  995.     {
  996.       /* Disable the TIM Capture/Compare 3 interrupt */
  997.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  998.       break;
  999.     }
  1000.  
  1001.     case TIM_CHANNEL_4:
  1002.     {
  1003.       /* Disable the TIM Capture/Compare 4 interrupt */
  1004.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  1005.       break;
  1006.     }
  1007.  
  1008.     default:
  1009.       status = HAL_ERROR;
  1010.       break;
  1011.   }
  1012.  
  1013.   if (status == HAL_OK)
  1014.   {
  1015.     /* Disable the Output compare channel */
  1016.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1017.  
  1018.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1019.     {
  1020.       /* Disable the Main Output */
  1021.       __HAL_TIM_MOE_DISABLE(htim);
  1022.     }
  1023.  
  1024.     /* Disable the Peripheral */
  1025.     __HAL_TIM_DISABLE(htim);
  1026.  
  1027.     /* Set the TIM channel state */
  1028.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1029.   }
  1030.  
  1031.   /* Return function status */
  1032.   return status;
  1033. }
  1034.  
  1035. /**
  1036.   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
  1037.   * @param  htim TIM Output Compare handle
  1038.   * @param  Channel TIM Channel to be enabled
  1039.   *          This parameter can be one of the following values:
  1040.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1041.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1042.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1043.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1044.   * @param  pData The source Buffer address.
  1045.   * @param  Length The length of data to be transferred from memory to TIM peripheral
  1046.   * @retval HAL status
  1047.   */
  1048. HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
  1049.                                        uint16_t Length)
  1050. {
  1051.   HAL_StatusTypeDef status = HAL_OK;
  1052.   uint32_t tmpsmcr;
  1053.  
  1054.   /* Check the parameters */
  1055.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1056.  
  1057.   /* Set the TIM channel state */
  1058.   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
  1059.   {
  1060.     return HAL_BUSY;
  1061.   }
  1062.   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
  1063.   {
  1064.     if ((pData == NULL) || (Length == 0U))
  1065.     {
  1066.       return HAL_ERROR;
  1067.     }
  1068.     else
  1069.     {
  1070.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1071.     }
  1072.   }
  1073.   else
  1074.   {
  1075.     return HAL_ERROR;
  1076.   }
  1077.  
  1078.   switch (Channel)
  1079.   {
  1080.     case TIM_CHANNEL_1:
  1081.     {
  1082.       /* Set the DMA compare callbacks */
  1083.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1084.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1085.  
  1086.       /* Set the DMA error callback */
  1087.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  1088.  
  1089.       /* Enable the DMA channel */
  1090.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
  1091.                            Length) != HAL_OK)
  1092.       {
  1093.         /* Return error status */
  1094.         return HAL_ERROR;
  1095.       }
  1096.  
  1097.       /* Enable the TIM Capture/Compare 1 DMA request */
  1098.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  1099.       break;
  1100.     }
  1101.  
  1102.     case TIM_CHANNEL_2:
  1103.     {
  1104.       /* Set the DMA compare callbacks */
  1105.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1106.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1107.  
  1108.       /* Set the DMA error callback */
  1109.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  1110.  
  1111.       /* Enable the DMA channel */
  1112.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
  1113.                            Length) != HAL_OK)
  1114.       {
  1115.         /* Return error status */
  1116.         return HAL_ERROR;
  1117.       }
  1118.  
  1119.       /* Enable the TIM Capture/Compare 2 DMA request */
  1120.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  1121.       break;
  1122.     }
  1123.  
  1124.     case TIM_CHANNEL_3:
  1125.     {
  1126.       /* Set the DMA compare callbacks */
  1127.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1128.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1129.  
  1130.       /* Set the DMA error callback */
  1131.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  1132.  
  1133.       /* Enable the DMA channel */
  1134.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
  1135.                            Length) != HAL_OK)
  1136.       {
  1137.         /* Return error status */
  1138.         return HAL_ERROR;
  1139.       }
  1140.       /* Enable the TIM Capture/Compare 3 DMA request */
  1141.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  1142.       break;
  1143.     }
  1144.  
  1145.     case TIM_CHANNEL_4:
  1146.     {
  1147.       /* Set the DMA compare callbacks */
  1148.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1149.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1150.  
  1151.       /* Set the DMA error callback */
  1152.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  1153.  
  1154.       /* Enable the DMA channel */
  1155.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
  1156.                            Length) != HAL_OK)
  1157.       {
  1158.         /* Return error status */
  1159.         return HAL_ERROR;
  1160.       }
  1161.       /* Enable the TIM Capture/Compare 4 DMA request */
  1162.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  1163.       break;
  1164.     }
  1165.  
  1166.     default:
  1167.       status = HAL_ERROR;
  1168.       break;
  1169.   }
  1170.  
  1171.   if (status == HAL_OK)
  1172.   {
  1173.     /* Enable the Output compare channel */
  1174.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1175.  
  1176.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1177.     {
  1178.       /* Enable the main output */
  1179.       __HAL_TIM_MOE_ENABLE(htim);
  1180.     }
  1181.  
  1182.     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1183.     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1184.     {
  1185.       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1186.       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1187.       {
  1188.         __HAL_TIM_ENABLE(htim);
  1189.       }
  1190.     }
  1191.     else
  1192.     {
  1193.       __HAL_TIM_ENABLE(htim);
  1194.     }
  1195.   }
  1196.  
  1197.   /* Return function status */
  1198.   return status;
  1199. }
  1200.  
  1201. /**
  1202.   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
  1203.   * @param  htim TIM Output Compare handle
  1204.   * @param  Channel TIM Channel to be disabled
  1205.   *          This parameter can be one of the following values:
  1206.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1207.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1208.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1209.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1210.   * @retval HAL status
  1211.   */
  1212. HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  1213. {
  1214.   HAL_StatusTypeDef status = HAL_OK;
  1215.  
  1216.   /* Check the parameters */
  1217.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1218.  
  1219.   switch (Channel)
  1220.   {
  1221.     case TIM_CHANNEL_1:
  1222.     {
  1223.       /* Disable the TIM Capture/Compare 1 DMA request */
  1224.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  1225.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  1226.       break;
  1227.     }
  1228.  
  1229.     case TIM_CHANNEL_2:
  1230.     {
  1231.       /* Disable the TIM Capture/Compare 2 DMA request */
  1232.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  1233.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  1234.       break;
  1235.     }
  1236.  
  1237.     case TIM_CHANNEL_3:
  1238.     {
  1239.       /* Disable the TIM Capture/Compare 3 DMA request */
  1240.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  1241.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  1242.       break;
  1243.     }
  1244.  
  1245.     case TIM_CHANNEL_4:
  1246.     {
  1247.       /* Disable the TIM Capture/Compare 4 interrupt */
  1248.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  1249.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  1250.       break;
  1251.     }
  1252.  
  1253.     default:
  1254.       status = HAL_ERROR;
  1255.       break;
  1256.   }
  1257.  
  1258.   if (status == HAL_OK)
  1259.   {
  1260.     /* Disable the Output compare channel */
  1261.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1262.  
  1263.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1264.     {
  1265.       /* Disable the Main Output */
  1266.       __HAL_TIM_MOE_DISABLE(htim);
  1267.     }
  1268.  
  1269.     /* Disable the Peripheral */
  1270.     __HAL_TIM_DISABLE(htim);
  1271.  
  1272.     /* Set the TIM channel state */
  1273.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1274.   }
  1275.  
  1276.   /* Return function status */
  1277.   return status;
  1278. }
  1279.  
  1280. /**
  1281.   * @}
  1282.   */
  1283.  
  1284. /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
  1285.   *  @brief    TIM PWM functions
  1286.   *
  1287. @verbatim
  1288.   ==============================================================================
  1289.                           ##### TIM PWM functions #####
  1290.   ==============================================================================
  1291.   [..]
  1292.     This section provides functions allowing to:
  1293.     (+) Initialize and configure the TIM PWM.
  1294.     (+) De-initialize the TIM PWM.
  1295.     (+) Start the TIM PWM.
  1296.     (+) Stop the TIM PWM.
  1297.     (+) Start the TIM PWM and enable interrupt.
  1298.     (+) Stop the TIM PWM and disable interrupt.
  1299.     (+) Start the TIM PWM and enable DMA transfer.
  1300.     (+) Stop the TIM PWM and disable DMA transfer.
  1301.  
  1302. @endverbatim
  1303.   * @{
  1304.   */
  1305. /**
  1306.   * @brief  Initializes the TIM PWM Time Base according to the specified
  1307.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  1308.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  1309.   *         requires a timer reset to avoid unexpected direction
  1310.   *         due to DIR bit readonly in center aligned mode.
  1311.   *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
  1312.   * @param  htim TIM PWM handle
  1313.   * @retval HAL status
  1314.   */
  1315. HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
  1316. {
  1317.   /* Check the TIM handle allocation */
  1318.   if (htim == NULL)
  1319.   {
  1320.     return HAL_ERROR;
  1321.   }
  1322.  
  1323.   /* Check the parameters */
  1324.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1325.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  1326.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  1327.   assert_param(IS_TIM_PERIOD(htim->Init.Period));
  1328.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  1329.  
  1330.   if (htim->State == HAL_TIM_STATE_RESET)
  1331.   {
  1332.     /* Allocate lock resource and initialize it */
  1333.     htim->Lock = HAL_UNLOCKED;
  1334.  
  1335. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1336.     /* Reset interrupt callbacks to legacy weak callbacks */
  1337.     TIM_ResetCallback(htim);
  1338.  
  1339.     if (htim->PWM_MspInitCallback == NULL)
  1340.     {
  1341.       htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
  1342.     }
  1343.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  1344.     htim->PWM_MspInitCallback(htim);
  1345. #else
  1346.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  1347.     HAL_TIM_PWM_MspInit(htim);
  1348. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1349.   }
  1350.  
  1351.   /* Set the TIM state */
  1352.   htim->State = HAL_TIM_STATE_BUSY;
  1353.  
  1354.   /* Init the base time for the PWM */
  1355.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  1356.  
  1357.   /* Initialize the DMA burst operation state */
  1358.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  1359.  
  1360.   /* Initialize the TIM channels state */
  1361.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  1362.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  1363.  
  1364.   /* Initialize the TIM state*/
  1365.   htim->State = HAL_TIM_STATE_READY;
  1366.  
  1367.   return HAL_OK;
  1368. }
  1369.  
  1370. /**
  1371.   * @brief  DeInitializes the TIM peripheral
  1372.   * @param  htim TIM PWM handle
  1373.   * @retval HAL status
  1374.   */
  1375. HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
  1376. {
  1377.   /* Check the parameters */
  1378.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1379.  
  1380.   htim->State = HAL_TIM_STATE_BUSY;
  1381.  
  1382.   /* Disable the TIM Peripheral Clock */
  1383.   __HAL_TIM_DISABLE(htim);
  1384.  
  1385. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1386.   if (htim->PWM_MspDeInitCallback == NULL)
  1387.   {
  1388.     htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
  1389.   }
  1390.   /* DeInit the low level hardware */
  1391.   htim->PWM_MspDeInitCallback(htim);
  1392. #else
  1393.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  1394.   HAL_TIM_PWM_MspDeInit(htim);
  1395. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1396.  
  1397.   /* Change the DMA burst operation state */
  1398.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  1399.  
  1400.   /* Change the TIM channels state */
  1401.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  1402.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  1403.  
  1404.   /* Change TIM state */
  1405.   htim->State = HAL_TIM_STATE_RESET;
  1406.  
  1407.   /* Release Lock */
  1408.   __HAL_UNLOCK(htim);
  1409.  
  1410.   return HAL_OK;
  1411. }
  1412.  
  1413. /**
  1414.   * @brief  Initializes the TIM PWM MSP.
  1415.   * @param  htim TIM PWM handle
  1416.   * @retval None
  1417.   */
  1418. __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
  1419. {
  1420.   /* Prevent unused argument(s) compilation warning */
  1421.   UNUSED(htim);
  1422.  
  1423.   /* NOTE : This function should not be modified, when the callback is needed,
  1424.             the HAL_TIM_PWM_MspInit could be implemented in the user file
  1425.    */
  1426. }
  1427.  
  1428. /**
  1429.   * @brief  DeInitializes TIM PWM MSP.
  1430.   * @param  htim TIM PWM handle
  1431.   * @retval None
  1432.   */
  1433. __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
  1434. {
  1435.   /* Prevent unused argument(s) compilation warning */
  1436.   UNUSED(htim);
  1437.  
  1438.   /* NOTE : This function should not be modified, when the callback is needed,
  1439.             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
  1440.    */
  1441. }
  1442.  
  1443. /**
  1444.   * @brief  Starts the PWM signal generation.
  1445.   * @param  htim TIM handle
  1446.   * @param  Channel TIM Channels to be enabled
  1447.   *          This parameter can be one of the following values:
  1448.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1449.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1450.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1451.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1452.   * @retval HAL status
  1453.   */
  1454. HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  1455. {
  1456.   uint32_t tmpsmcr;
  1457.  
  1458.   /* Check the parameters */
  1459.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1460.  
  1461.   /* Check the TIM channel state */
  1462.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  1463.   {
  1464.     return HAL_ERROR;
  1465.   }
  1466.  
  1467.   /* Set the TIM channel state */
  1468.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1469.  
  1470.   /* Enable the Capture compare channel */
  1471.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1472.  
  1473.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1474.   {
  1475.     /* Enable the main output */
  1476.     __HAL_TIM_MOE_ENABLE(htim);
  1477.   }
  1478.  
  1479.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1480.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1481.   {
  1482.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1483.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1484.     {
  1485.       __HAL_TIM_ENABLE(htim);
  1486.     }
  1487.   }
  1488.   else
  1489.   {
  1490.     __HAL_TIM_ENABLE(htim);
  1491.   }
  1492.  
  1493.   /* Return function status */
  1494.   return HAL_OK;
  1495. }
  1496.  
  1497. /**
  1498.   * @brief  Stops the PWM signal generation.
  1499.   * @param  htim TIM PWM handle
  1500.   * @param  Channel TIM Channels to be disabled
  1501.   *          This parameter can be one of the following values:
  1502.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1503.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1504.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1505.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1506.   * @retval HAL status
  1507.   */
  1508. HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  1509. {
  1510.   /* Check the parameters */
  1511.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1512.  
  1513.   /* Disable the Capture compare channel */
  1514.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1515.  
  1516.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1517.   {
  1518.     /* Disable the Main Output */
  1519.     __HAL_TIM_MOE_DISABLE(htim);
  1520.   }
  1521.  
  1522.   /* Disable the Peripheral */
  1523.   __HAL_TIM_DISABLE(htim);
  1524.  
  1525.   /* Set the TIM channel state */
  1526.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1527.  
  1528.   /* Return function status */
  1529.   return HAL_OK;
  1530. }
  1531.  
  1532. /**
  1533.   * @brief  Starts the PWM signal generation in interrupt mode.
  1534.   * @param  htim TIM PWM handle
  1535.   * @param  Channel TIM Channel to be enabled
  1536.   *          This parameter can be one of the following values:
  1537.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1538.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1539.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1540.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1541.   * @retval HAL status
  1542.   */
  1543. HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  1544. {
  1545.   HAL_StatusTypeDef status = HAL_OK;
  1546.   uint32_t tmpsmcr;
  1547.  
  1548.   /* Check the parameters */
  1549.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1550.  
  1551.   /* Check the TIM channel state */
  1552.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  1553.   {
  1554.     return HAL_ERROR;
  1555.   }
  1556.  
  1557.   /* Set the TIM channel state */
  1558.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1559.  
  1560.   switch (Channel)
  1561.   {
  1562.     case TIM_CHANNEL_1:
  1563.     {
  1564.       /* Enable the TIM Capture/Compare 1 interrupt */
  1565.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  1566.       break;
  1567.     }
  1568.  
  1569.     case TIM_CHANNEL_2:
  1570.     {
  1571.       /* Enable the TIM Capture/Compare 2 interrupt */
  1572.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  1573.       break;
  1574.     }
  1575.  
  1576.     case TIM_CHANNEL_3:
  1577.     {
  1578.       /* Enable the TIM Capture/Compare 3 interrupt */
  1579.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  1580.       break;
  1581.     }
  1582.  
  1583.     case TIM_CHANNEL_4:
  1584.     {
  1585.       /* Enable the TIM Capture/Compare 4 interrupt */
  1586.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  1587.       break;
  1588.     }
  1589.  
  1590.     default:
  1591.       status = HAL_ERROR;
  1592.       break;
  1593.   }
  1594.  
  1595.   if (status == HAL_OK)
  1596.   {
  1597.     /* Enable the Capture compare channel */
  1598.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1599.  
  1600.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1601.     {
  1602.       /* Enable the main output */
  1603.       __HAL_TIM_MOE_ENABLE(htim);
  1604.     }
  1605.  
  1606.     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1607.     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1608.     {
  1609.       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1610.       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1611.       {
  1612.         __HAL_TIM_ENABLE(htim);
  1613.       }
  1614.     }
  1615.     else
  1616.     {
  1617.       __HAL_TIM_ENABLE(htim);
  1618.     }
  1619.   }
  1620.  
  1621.   /* Return function status */
  1622.   return status;
  1623. }
  1624.  
  1625. /**
  1626.   * @brief  Stops the PWM signal generation in interrupt mode.
  1627.   * @param  htim TIM PWM handle
  1628.   * @param  Channel TIM Channels to be disabled
  1629.   *          This parameter can be one of the following values:
  1630.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1631.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1632.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1633.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1634.   * @retval HAL status
  1635.   */
  1636. HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  1637. {
  1638.   HAL_StatusTypeDef status = HAL_OK;
  1639.  
  1640.   /* Check the parameters */
  1641.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1642.  
  1643.   switch (Channel)
  1644.   {
  1645.     case TIM_CHANNEL_1:
  1646.     {
  1647.       /* Disable the TIM Capture/Compare 1 interrupt */
  1648.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  1649.       break;
  1650.     }
  1651.  
  1652.     case TIM_CHANNEL_2:
  1653.     {
  1654.       /* Disable the TIM Capture/Compare 2 interrupt */
  1655.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  1656.       break;
  1657.     }
  1658.  
  1659.     case TIM_CHANNEL_3:
  1660.     {
  1661.       /* Disable the TIM Capture/Compare 3 interrupt */
  1662.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  1663.       break;
  1664.     }
  1665.  
  1666.     case TIM_CHANNEL_4:
  1667.     {
  1668.       /* Disable the TIM Capture/Compare 4 interrupt */
  1669.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  1670.       break;
  1671.     }
  1672.  
  1673.     default:
  1674.       status = HAL_ERROR;
  1675.       break;
  1676.   }
  1677.  
  1678.   if (status == HAL_OK)
  1679.   {
  1680.     /* Disable the Capture compare channel */
  1681.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1682.  
  1683.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1684.     {
  1685.       /* Disable the Main Output */
  1686.       __HAL_TIM_MOE_DISABLE(htim);
  1687.     }
  1688.  
  1689.     /* Disable the Peripheral */
  1690.     __HAL_TIM_DISABLE(htim);
  1691.  
  1692.     /* Set the TIM channel state */
  1693.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1694.   }
  1695.  
  1696.   /* Return function status */
  1697.   return status;
  1698. }
  1699.  
  1700. /**
  1701.   * @brief  Starts the TIM PWM signal generation in DMA mode.
  1702.   * @param  htim TIM PWM handle
  1703.   * @param  Channel TIM Channels to be enabled
  1704.   *          This parameter can be one of the following values:
  1705.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1706.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1707.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1708.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1709.   * @param  pData The source Buffer address.
  1710.   * @param  Length The length of data to be transferred from memory to TIM peripheral
  1711.   * @retval HAL status
  1712.   */
  1713. HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
  1714.                                         uint16_t Length)
  1715. {
  1716.   HAL_StatusTypeDef status = HAL_OK;
  1717.   uint32_t tmpsmcr;
  1718.  
  1719.   /* Check the parameters */
  1720.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1721.  
  1722.   /* Set the TIM channel state */
  1723.   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
  1724.   {
  1725.     return HAL_BUSY;
  1726.   }
  1727.   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
  1728.   {
  1729.     if ((pData == NULL) || (Length == 0U))
  1730.     {
  1731.       return HAL_ERROR;
  1732.     }
  1733.     else
  1734.     {
  1735.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1736.     }
  1737.   }
  1738.   else
  1739.   {
  1740.     return HAL_ERROR;
  1741.   }
  1742.  
  1743.   switch (Channel)
  1744.   {
  1745.     case TIM_CHANNEL_1:
  1746.     {
  1747.       /* Set the DMA compare callbacks */
  1748.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1749.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1750.  
  1751.       /* Set the DMA error callback */
  1752.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  1753.  
  1754.       /* Enable the DMA channel */
  1755.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
  1756.                            Length) != HAL_OK)
  1757.       {
  1758.         /* Return error status */
  1759.         return HAL_ERROR;
  1760.       }
  1761.  
  1762.       /* Enable the TIM Capture/Compare 1 DMA request */
  1763.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  1764.       break;
  1765.     }
  1766.  
  1767.     case TIM_CHANNEL_2:
  1768.     {
  1769.       /* Set the DMA compare callbacks */
  1770.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1771.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1772.  
  1773.       /* Set the DMA error callback */
  1774.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  1775.  
  1776.       /* Enable the DMA channel */
  1777.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
  1778.                            Length) != HAL_OK)
  1779.       {
  1780.         /* Return error status */
  1781.         return HAL_ERROR;
  1782.       }
  1783.       /* Enable the TIM Capture/Compare 2 DMA request */
  1784.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  1785.       break;
  1786.     }
  1787.  
  1788.     case TIM_CHANNEL_3:
  1789.     {
  1790.       /* Set the DMA compare callbacks */
  1791.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1792.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1793.  
  1794.       /* Set the DMA error callback */
  1795.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  1796.  
  1797.       /* Enable the DMA channel */
  1798.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
  1799.                            Length) != HAL_OK)
  1800.       {
  1801.         /* Return error status */
  1802.         return HAL_ERROR;
  1803.       }
  1804.       /* Enable the TIM Output Capture/Compare 3 request */
  1805.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  1806.       break;
  1807.     }
  1808.  
  1809.     case TIM_CHANNEL_4:
  1810.     {
  1811.       /* Set the DMA compare callbacks */
  1812.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1813.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1814.  
  1815.       /* Set the DMA error callback */
  1816.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  1817.  
  1818.       /* Enable the DMA channel */
  1819.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
  1820.                            Length) != HAL_OK)
  1821.       {
  1822.         /* Return error status */
  1823.         return HAL_ERROR;
  1824.       }
  1825.       /* Enable the TIM Capture/Compare 4 DMA request */
  1826.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  1827.       break;
  1828.     }
  1829.  
  1830.     default:
  1831.       status = HAL_ERROR;
  1832.       break;
  1833.   }
  1834.  
  1835.   if (status == HAL_OK)
  1836.   {
  1837.     /* Enable the Capture compare channel */
  1838.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1839.  
  1840.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1841.     {
  1842.       /* Enable the main output */
  1843.       __HAL_TIM_MOE_ENABLE(htim);
  1844.     }
  1845.  
  1846.     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1847.     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1848.     {
  1849.       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1850.       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1851.       {
  1852.         __HAL_TIM_ENABLE(htim);
  1853.       }
  1854.     }
  1855.     else
  1856.     {
  1857.       __HAL_TIM_ENABLE(htim);
  1858.     }
  1859.   }
  1860.  
  1861.   /* Return function status */
  1862.   return status;
  1863. }
  1864.  
  1865. /**
  1866.   * @brief  Stops the TIM PWM signal generation in DMA mode.
  1867.   * @param  htim TIM PWM handle
  1868.   * @param  Channel TIM Channels to be disabled
  1869.   *          This parameter can be one of the following values:
  1870.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1871.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1872.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1873.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1874.   * @retval HAL status
  1875.   */
  1876. HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  1877. {
  1878.   HAL_StatusTypeDef status = HAL_OK;
  1879.  
  1880.   /* Check the parameters */
  1881.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1882.  
  1883.   switch (Channel)
  1884.   {
  1885.     case TIM_CHANNEL_1:
  1886.     {
  1887.       /* Disable the TIM Capture/Compare 1 DMA request */
  1888.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  1889.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  1890.       break;
  1891.     }
  1892.  
  1893.     case TIM_CHANNEL_2:
  1894.     {
  1895.       /* Disable the TIM Capture/Compare 2 DMA request */
  1896.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  1897.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  1898.       break;
  1899.     }
  1900.  
  1901.     case TIM_CHANNEL_3:
  1902.     {
  1903.       /* Disable the TIM Capture/Compare 3 DMA request */
  1904.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  1905.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  1906.       break;
  1907.     }
  1908.  
  1909.     case TIM_CHANNEL_4:
  1910.     {
  1911.       /* Disable the TIM Capture/Compare 4 interrupt */
  1912.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  1913.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  1914.       break;
  1915.     }
  1916.  
  1917.     default:
  1918.       status = HAL_ERROR;
  1919.       break;
  1920.   }
  1921.  
  1922.   if (status == HAL_OK)
  1923.   {
  1924.     /* Disable the Capture compare channel */
  1925.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1926.  
  1927.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1928.     {
  1929.       /* Disable the Main Output */
  1930.       __HAL_TIM_MOE_DISABLE(htim);
  1931.     }
  1932.  
  1933.     /* Disable the Peripheral */
  1934.     __HAL_TIM_DISABLE(htim);
  1935.  
  1936.     /* Set the TIM channel state */
  1937.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1938.   }
  1939.  
  1940.   /* Return function status */
  1941.   return status;
  1942. }
  1943.  
  1944. /**
  1945.   * @}
  1946.   */
  1947.  
  1948. /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
  1949.   *  @brief    TIM Input Capture functions
  1950.   *
  1951. @verbatim
  1952.   ==============================================================================
  1953.               ##### TIM Input Capture functions #####
  1954.   ==============================================================================
  1955.  [..]
  1956.    This section provides functions allowing to:
  1957.    (+) Initialize and configure the TIM Input Capture.
  1958.    (+) De-initialize the TIM Input Capture.
  1959.    (+) Start the TIM Input Capture.
  1960.    (+) Stop the TIM Input Capture.
  1961.    (+) Start the TIM Input Capture and enable interrupt.
  1962.    (+) Stop the TIM Input Capture and disable interrupt.
  1963.    (+) Start the TIM Input Capture and enable DMA transfer.
  1964.    (+) Stop the TIM Input Capture and disable DMA transfer.
  1965.  
  1966. @endverbatim
  1967.   * @{
  1968.   */
  1969. /**
  1970.   * @brief  Initializes the TIM Input Capture Time base according to the specified
  1971.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  1972.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  1973.   *         requires a timer reset to avoid unexpected direction
  1974.   *         due to DIR bit readonly in center aligned mode.
  1975.   *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
  1976.   * @param  htim TIM Input Capture handle
  1977.   * @retval HAL status
  1978.   */
  1979. HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
  1980. {
  1981.   /* Check the TIM handle allocation */
  1982.   if (htim == NULL)
  1983.   {
  1984.     return HAL_ERROR;
  1985.   }
  1986.  
  1987.   /* Check the parameters */
  1988.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1989.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  1990.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  1991.   assert_param(IS_TIM_PERIOD(htim->Init.Period));
  1992.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  1993.  
  1994.   if (htim->State == HAL_TIM_STATE_RESET)
  1995.   {
  1996.     /* Allocate lock resource and initialize it */
  1997.     htim->Lock = HAL_UNLOCKED;
  1998.  
  1999. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2000.     /* Reset interrupt callbacks to legacy weak callbacks */
  2001.     TIM_ResetCallback(htim);
  2002.  
  2003.     if (htim->IC_MspInitCallback == NULL)
  2004.     {
  2005.       htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
  2006.     }
  2007.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  2008.     htim->IC_MspInitCallback(htim);
  2009. #else
  2010.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  2011.     HAL_TIM_IC_MspInit(htim);
  2012. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2013.   }
  2014.  
  2015.   /* Set the TIM state */
  2016.   htim->State = HAL_TIM_STATE_BUSY;
  2017.  
  2018.   /* Init the base time for the input capture */
  2019.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  2020.  
  2021.   /* Initialize the DMA burst operation state */
  2022.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  2023.  
  2024.   /* Initialize the TIM channels state */
  2025.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  2026.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  2027.  
  2028.   /* Initialize the TIM state*/
  2029.   htim->State = HAL_TIM_STATE_READY;
  2030.  
  2031.   return HAL_OK;
  2032. }
  2033.  
  2034. /**
  2035.   * @brief  DeInitializes the TIM peripheral
  2036.   * @param  htim TIM Input Capture handle
  2037.   * @retval HAL status
  2038.   */
  2039. HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
  2040. {
  2041.   /* Check the parameters */
  2042.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  2043.  
  2044.   htim->State = HAL_TIM_STATE_BUSY;
  2045.  
  2046.   /* Disable the TIM Peripheral Clock */
  2047.   __HAL_TIM_DISABLE(htim);
  2048.  
  2049. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2050.   if (htim->IC_MspDeInitCallback == NULL)
  2051.   {
  2052.     htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
  2053.   }
  2054.   /* DeInit the low level hardware */
  2055.   htim->IC_MspDeInitCallback(htim);
  2056. #else
  2057.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  2058.   HAL_TIM_IC_MspDeInit(htim);
  2059. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2060.  
  2061.   /* Change the DMA burst operation state */
  2062.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  2063.  
  2064.   /* Change the TIM channels state */
  2065.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  2066.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  2067.  
  2068.   /* Change TIM state */
  2069.   htim->State = HAL_TIM_STATE_RESET;
  2070.  
  2071.   /* Release Lock */
  2072.   __HAL_UNLOCK(htim);
  2073.  
  2074.   return HAL_OK;
  2075. }
  2076.  
  2077. /**
  2078.   * @brief  Initializes the TIM Input Capture MSP.
  2079.   * @param  htim TIM Input Capture handle
  2080.   * @retval None
  2081.   */
  2082. __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
  2083. {
  2084.   /* Prevent unused argument(s) compilation warning */
  2085.   UNUSED(htim);
  2086.  
  2087.   /* NOTE : This function should not be modified, when the callback is needed,
  2088.             the HAL_TIM_IC_MspInit could be implemented in the user file
  2089.    */
  2090. }
  2091.  
  2092. /**
  2093.   * @brief  DeInitializes TIM Input Capture MSP.
  2094.   * @param  htim TIM handle
  2095.   * @retval None
  2096.   */
  2097. __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
  2098. {
  2099.   /* Prevent unused argument(s) compilation warning */
  2100.   UNUSED(htim);
  2101.  
  2102.   /* NOTE : This function should not be modified, when the callback is needed,
  2103.             the HAL_TIM_IC_MspDeInit could be implemented in the user file
  2104.    */
  2105. }
  2106.  
  2107. /**
  2108.   * @brief  Starts the TIM Input Capture measurement.
  2109.   * @param  htim TIM Input Capture handle
  2110.   * @param  Channel TIM Channels to be enabled
  2111.   *          This parameter can be one of the following values:
  2112.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2113.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2114.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2115.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2116.   * @retval HAL status
  2117.   */
  2118. HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  2119. {
  2120.   uint32_t tmpsmcr;
  2121.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  2122.   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
  2123.  
  2124.   /* Check the parameters */
  2125.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2126.  
  2127.   /* Check the TIM channel state */
  2128.   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
  2129.       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
  2130.   {
  2131.     return HAL_ERROR;
  2132.   }
  2133.  
  2134.   /* Set the TIM channel state */
  2135.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2136.   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2137.  
  2138.   /* Enable the Input Capture channel */
  2139.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  2140.  
  2141.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  2142.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  2143.   {
  2144.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  2145.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  2146.     {
  2147.       __HAL_TIM_ENABLE(htim);
  2148.     }
  2149.   }
  2150.   else
  2151.   {
  2152.     __HAL_TIM_ENABLE(htim);
  2153.   }
  2154.  
  2155.   /* Return function status */
  2156.   return HAL_OK;
  2157. }
  2158.  
  2159. /**
  2160.   * @brief  Stops the TIM Input Capture measurement.
  2161.   * @param  htim TIM Input Capture handle
  2162.   * @param  Channel TIM Channels to be disabled
  2163.   *          This parameter can be one of the following values:
  2164.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2165.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2166.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2167.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2168.   * @retval HAL status
  2169.   */
  2170. HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  2171. {
  2172.   /* Check the parameters */
  2173.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2174.  
  2175.   /* Disable the Input Capture channel */
  2176.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2177.  
  2178.   /* Disable the Peripheral */
  2179.   __HAL_TIM_DISABLE(htim);
  2180.  
  2181.   /* Set the TIM channel state */
  2182.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2183.   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2184.  
  2185.   /* Return function status */
  2186.   return HAL_OK;
  2187. }
  2188.  
  2189. /**
  2190.   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
  2191.   * @param  htim TIM Input Capture handle
  2192.   * @param  Channel TIM Channels to be enabled
  2193.   *          This parameter can be one of the following values:
  2194.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2195.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2196.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2197.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2198.   * @retval HAL status
  2199.   */
  2200. HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  2201. {
  2202.   HAL_StatusTypeDef status = HAL_OK;
  2203.   uint32_t tmpsmcr;
  2204.  
  2205.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  2206.   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
  2207.  
  2208.   /* Check the parameters */
  2209.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2210.  
  2211.   /* Check the TIM channel state */
  2212.   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
  2213.       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
  2214.   {
  2215.     return HAL_ERROR;
  2216.   }
  2217.  
  2218.   /* Set the TIM channel state */
  2219.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2220.   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2221.  
  2222.   switch (Channel)
  2223.   {
  2224.     case TIM_CHANNEL_1:
  2225.     {
  2226.       /* Enable the TIM Capture/Compare 1 interrupt */
  2227.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  2228.       break;
  2229.     }
  2230.  
  2231.     case TIM_CHANNEL_2:
  2232.     {
  2233.       /* Enable the TIM Capture/Compare 2 interrupt */
  2234.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  2235.       break;
  2236.     }
  2237.  
  2238.     case TIM_CHANNEL_3:
  2239.     {
  2240.       /* Enable the TIM Capture/Compare 3 interrupt */
  2241.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  2242.       break;
  2243.     }
  2244.  
  2245.     case TIM_CHANNEL_4:
  2246.     {
  2247.       /* Enable the TIM Capture/Compare 4 interrupt */
  2248.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  2249.       break;
  2250.     }
  2251.  
  2252.     default:
  2253.       status = HAL_ERROR;
  2254.       break;
  2255.   }
  2256.  
  2257.   if (status == HAL_OK)
  2258.   {
  2259.     /* Enable the Input Capture channel */
  2260.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  2261.  
  2262.     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  2263.     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  2264.     {
  2265.       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  2266.       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  2267.       {
  2268.         __HAL_TIM_ENABLE(htim);
  2269.       }
  2270.     }
  2271.     else
  2272.     {
  2273.       __HAL_TIM_ENABLE(htim);
  2274.     }
  2275.   }
  2276.  
  2277.   /* Return function status */
  2278.   return status;
  2279. }
  2280.  
  2281. /**
  2282.   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
  2283.   * @param  htim TIM Input Capture handle
  2284.   * @param  Channel TIM Channels to be disabled
  2285.   *          This parameter can be one of the following values:
  2286.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2287.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2288.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2289.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2290.   * @retval HAL status
  2291.   */
  2292. HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  2293. {
  2294.   HAL_StatusTypeDef status = HAL_OK;
  2295.  
  2296.   /* Check the parameters */
  2297.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2298.  
  2299.   switch (Channel)
  2300.   {
  2301.     case TIM_CHANNEL_1:
  2302.     {
  2303.       /* Disable the TIM Capture/Compare 1 interrupt */
  2304.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  2305.       break;
  2306.     }
  2307.  
  2308.     case TIM_CHANNEL_2:
  2309.     {
  2310.       /* Disable the TIM Capture/Compare 2 interrupt */
  2311.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  2312.       break;
  2313.     }
  2314.  
  2315.     case TIM_CHANNEL_3:
  2316.     {
  2317.       /* Disable the TIM Capture/Compare 3 interrupt */
  2318.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  2319.       break;
  2320.     }
  2321.  
  2322.     case TIM_CHANNEL_4:
  2323.     {
  2324.       /* Disable the TIM Capture/Compare 4 interrupt */
  2325.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  2326.       break;
  2327.     }
  2328.  
  2329.     default:
  2330.       status = HAL_ERROR;
  2331.       break;
  2332.   }
  2333.  
  2334.   if (status == HAL_OK)
  2335.   {
  2336.     /* Disable the Input Capture channel */
  2337.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2338.  
  2339.     /* Disable the Peripheral */
  2340.     __HAL_TIM_DISABLE(htim);
  2341.  
  2342.     /* Set the TIM channel state */
  2343.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2344.     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2345.   }
  2346.  
  2347.   /* Return function status */
  2348.   return status;
  2349. }
  2350.  
  2351. /**
  2352.   * @brief  Starts the TIM Input Capture measurement in DMA mode.
  2353.   * @param  htim TIM Input Capture handle
  2354.   * @param  Channel TIM Channels to be enabled
  2355.   *          This parameter can be one of the following values:
  2356.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2357.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2358.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2359.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2360.   * @param  pData The destination Buffer address.
  2361.   * @param  Length The length of data to be transferred from TIM peripheral to memory.
  2362.   * @retval HAL status
  2363.   */
  2364. HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
  2365. {
  2366.   HAL_StatusTypeDef status = HAL_OK;
  2367.   uint32_t tmpsmcr;
  2368.  
  2369.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  2370.   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
  2371.  
  2372.   /* Check the parameters */
  2373.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2374.   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
  2375.  
  2376.   /* Set the TIM channel state */
  2377.   if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
  2378.       || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
  2379.   {
  2380.     return HAL_BUSY;
  2381.   }
  2382.   else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
  2383.            && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
  2384.   {
  2385.     if ((pData == NULL) || (Length == 0U))
  2386.     {
  2387.       return HAL_ERROR;
  2388.     }
  2389.     else
  2390.     {
  2391.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2392.       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2393.     }
  2394.   }
  2395.   else
  2396.   {
  2397.     return HAL_ERROR;
  2398.   }
  2399.  
  2400.   /* Enable the Input Capture channel */
  2401.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  2402.  
  2403.   switch (Channel)
  2404.   {
  2405.     case TIM_CHANNEL_1:
  2406.     {
  2407.       /* Set the DMA capture callbacks */
  2408.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  2409.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2410.  
  2411.       /* Set the DMA error callback */
  2412.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  2413.  
  2414.       /* Enable the DMA channel */
  2415.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
  2416.                            Length) != HAL_OK)
  2417.       {
  2418.         /* Return error status */
  2419.         return HAL_ERROR;
  2420.       }
  2421.       /* Enable the TIM Capture/Compare 1 DMA request */
  2422.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  2423.       break;
  2424.     }
  2425.  
  2426.     case TIM_CHANNEL_2:
  2427.     {
  2428.       /* Set the DMA capture callbacks */
  2429.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  2430.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2431.  
  2432.       /* Set the DMA error callback */
  2433.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  2434.  
  2435.       /* Enable the DMA channel */
  2436.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
  2437.                            Length) != HAL_OK)
  2438.       {
  2439.         /* Return error status */
  2440.         return HAL_ERROR;
  2441.       }
  2442.       /* Enable the TIM Capture/Compare 2  DMA request */
  2443.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  2444.       break;
  2445.     }
  2446.  
  2447.     case TIM_CHANNEL_3:
  2448.     {
  2449.       /* Set the DMA capture callbacks */
  2450.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
  2451.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2452.  
  2453.       /* Set the DMA error callback */
  2454.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  2455.  
  2456.       /* Enable the DMA channel */
  2457.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
  2458.                            Length) != HAL_OK)
  2459.       {
  2460.         /* Return error status */
  2461.         return HAL_ERROR;
  2462.       }
  2463.       /* Enable the TIM Capture/Compare 3  DMA request */
  2464.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  2465.       break;
  2466.     }
  2467.  
  2468.     case TIM_CHANNEL_4:
  2469.     {
  2470.       /* Set the DMA capture callbacks */
  2471.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
  2472.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2473.  
  2474.       /* Set the DMA error callback */
  2475.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  2476.  
  2477.       /* Enable the DMA channel */
  2478.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
  2479.                            Length) != HAL_OK)
  2480.       {
  2481.         /* Return error status */
  2482.         return HAL_ERROR;
  2483.       }
  2484.       /* Enable the TIM Capture/Compare 4  DMA request */
  2485.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  2486.       break;
  2487.     }
  2488.  
  2489.     default:
  2490.       status = HAL_ERROR;
  2491.       break;
  2492.   }
  2493.  
  2494.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  2495.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  2496.   {
  2497.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  2498.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  2499.     {
  2500.       __HAL_TIM_ENABLE(htim);
  2501.     }
  2502.   }
  2503.   else
  2504.   {
  2505.     __HAL_TIM_ENABLE(htim);
  2506.   }
  2507.  
  2508.   /* Return function status */
  2509.   return status;
  2510. }
  2511.  
  2512. /**
  2513.   * @brief  Stops the TIM Input Capture measurement in DMA mode.
  2514.   * @param  htim TIM Input Capture handle
  2515.   * @param  Channel TIM Channels to be disabled
  2516.   *          This parameter can be one of the following values:
  2517.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2518.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2519.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2520.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2521.   * @retval HAL status
  2522.   */
  2523. HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  2524. {
  2525.   HAL_StatusTypeDef status = HAL_OK;
  2526.  
  2527.   /* Check the parameters */
  2528.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2529.   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
  2530.  
  2531.   /* Disable the Input Capture channel */
  2532.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2533.  
  2534.   switch (Channel)
  2535.   {
  2536.     case TIM_CHANNEL_1:
  2537.     {
  2538.       /* Disable the TIM Capture/Compare 1 DMA request */
  2539.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  2540.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  2541.       break;
  2542.     }
  2543.  
  2544.     case TIM_CHANNEL_2:
  2545.     {
  2546.       /* Disable the TIM Capture/Compare 2 DMA request */
  2547.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  2548.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  2549.       break;
  2550.     }
  2551.  
  2552.     case TIM_CHANNEL_3:
  2553.     {
  2554.       /* Disable the TIM Capture/Compare 3  DMA request */
  2555.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  2556.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  2557.       break;
  2558.     }
  2559.  
  2560.     case TIM_CHANNEL_4:
  2561.     {
  2562.       /* Disable the TIM Capture/Compare 4  DMA request */
  2563.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  2564.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  2565.       break;
  2566.     }
  2567.  
  2568.     default:
  2569.       status = HAL_ERROR;
  2570.       break;
  2571.   }
  2572.  
  2573.   if (status == HAL_OK)
  2574.   {
  2575.     /* Disable the Peripheral */
  2576.     __HAL_TIM_DISABLE(htim);
  2577.  
  2578.     /* Set the TIM channel state */
  2579.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2580.     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2581.   }
  2582.  
  2583.   /* Return function status */
  2584.   return status;
  2585. }
  2586. /**
  2587.   * @}
  2588.   */
  2589.  
  2590. /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
  2591.   *  @brief    TIM One Pulse functions
  2592.   *
  2593. @verbatim
  2594.   ==============================================================================
  2595.                         ##### TIM One Pulse functions #####
  2596.   ==============================================================================
  2597.   [..]
  2598.     This section provides functions allowing to:
  2599.     (+) Initialize and configure the TIM One Pulse.
  2600.     (+) De-initialize the TIM One Pulse.
  2601.     (+) Start the TIM One Pulse.
  2602.     (+) Stop the TIM One Pulse.
  2603.     (+) Start the TIM One Pulse and enable interrupt.
  2604.     (+) Stop the TIM One Pulse and disable interrupt.
  2605.     (+) Start the TIM One Pulse and enable DMA transfer.
  2606.     (+) Stop the TIM One Pulse and disable DMA transfer.
  2607.  
  2608. @endverbatim
  2609.   * @{
  2610.   */
  2611. /**
  2612.   * @brief  Initializes the TIM One Pulse Time Base according to the specified
  2613.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  2614.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  2615.   *         requires a timer reset to avoid unexpected direction
  2616.   *         due to DIR bit readonly in center aligned mode.
  2617.   *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
  2618.   * @note   When the timer instance is initialized in One Pulse mode, timer
  2619.   *         channels 1 and channel 2 are reserved and cannot be used for other
  2620.   *         purpose.
  2621.   * @param  htim TIM One Pulse handle
  2622.   * @param  OnePulseMode Select the One pulse mode.
  2623.   *         This parameter can be one of the following values:
  2624.   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
  2625.   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
  2626.   * @retval HAL status
  2627.   */
  2628. HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
  2629. {
  2630.   /* Check the TIM handle allocation */
  2631.   if (htim == NULL)
  2632.   {
  2633.     return HAL_ERROR;
  2634.   }
  2635.  
  2636.   /* Check the parameters */
  2637.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  2638.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  2639.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  2640.   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
  2641.   assert_param(IS_TIM_PERIOD(htim->Init.Period));
  2642.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  2643.  
  2644.   if (htim->State == HAL_TIM_STATE_RESET)
  2645.   {
  2646.     /* Allocate lock resource and initialize it */
  2647.     htim->Lock = HAL_UNLOCKED;
  2648.  
  2649. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2650.     /* Reset interrupt callbacks to legacy weak callbacks */
  2651.     TIM_ResetCallback(htim);
  2652.  
  2653.     if (htim->OnePulse_MspInitCallback == NULL)
  2654.     {
  2655.       htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
  2656.     }
  2657.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  2658.     htim->OnePulse_MspInitCallback(htim);
  2659. #else
  2660.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  2661.     HAL_TIM_OnePulse_MspInit(htim);
  2662. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2663.   }
  2664.  
  2665.   /* Set the TIM state */
  2666.   htim->State = HAL_TIM_STATE_BUSY;
  2667.  
  2668.   /* Configure the Time base in the One Pulse Mode */
  2669.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  2670.  
  2671.   /* Reset the OPM Bit */
  2672.   htim->Instance->CR1 &= ~TIM_CR1_OPM;
  2673.  
  2674.   /* Configure the OPM Mode */
  2675.   htim->Instance->CR1 |= OnePulseMode;
  2676.  
  2677.   /* Initialize the DMA burst operation state */
  2678.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  2679.  
  2680.   /* Initialize the TIM channels state */
  2681.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2682.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2683.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2684.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2685.  
  2686.   /* Initialize the TIM state*/
  2687.   htim->State = HAL_TIM_STATE_READY;
  2688.  
  2689.   return HAL_OK;
  2690. }
  2691.  
  2692. /**
  2693.   * @brief  DeInitializes the TIM One Pulse
  2694.   * @param  htim TIM One Pulse handle
  2695.   * @retval HAL status
  2696.   */
  2697. HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
  2698. {
  2699.   /* Check the parameters */
  2700.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  2701.  
  2702.   htim->State = HAL_TIM_STATE_BUSY;
  2703.  
  2704.   /* Disable the TIM Peripheral Clock */
  2705.   __HAL_TIM_DISABLE(htim);
  2706.  
  2707. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2708.   if (htim->OnePulse_MspDeInitCallback == NULL)
  2709.   {
  2710.     htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
  2711.   }
  2712.   /* DeInit the low level hardware */
  2713.   htim->OnePulse_MspDeInitCallback(htim);
  2714. #else
  2715.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  2716.   HAL_TIM_OnePulse_MspDeInit(htim);
  2717. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2718.  
  2719.   /* Change the DMA burst operation state */
  2720.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  2721.  
  2722.   /* Set the TIM channel state */
  2723.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  2724.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  2725.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  2726.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  2727.  
  2728.   /* Change TIM state */
  2729.   htim->State = HAL_TIM_STATE_RESET;
  2730.  
  2731.   /* Release Lock */
  2732.   __HAL_UNLOCK(htim);
  2733.  
  2734.   return HAL_OK;
  2735. }
  2736.  
  2737. /**
  2738.   * @brief  Initializes the TIM One Pulse MSP.
  2739.   * @param  htim TIM One Pulse handle
  2740.   * @retval None
  2741.   */
  2742. __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
  2743. {
  2744.   /* Prevent unused argument(s) compilation warning */
  2745.   UNUSED(htim);
  2746.  
  2747.   /* NOTE : This function should not be modified, when the callback is needed,
  2748.             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
  2749.    */
  2750. }
  2751.  
  2752. /**
  2753.   * @brief  DeInitializes TIM One Pulse MSP.
  2754.   * @param  htim TIM One Pulse handle
  2755.   * @retval None
  2756.   */
  2757. __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
  2758. {
  2759.   /* Prevent unused argument(s) compilation warning */
  2760.   UNUSED(htim);
  2761.  
  2762.   /* NOTE : This function should not be modified, when the callback is needed,
  2763.             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
  2764.    */
  2765. }
  2766.  
  2767. /**
  2768.   * @brief  Starts the TIM One Pulse signal generation.
  2769.   * @note Though OutputChannel parameter is deprecated and ignored by the function
  2770.   *        it has been kept to avoid HAL_TIM API compatibility break.
  2771.   * @note The pulse output channel is determined when calling
  2772.   *       @ref HAL_TIM_OnePulse_ConfigChannel().
  2773.   * @param  htim TIM One Pulse handle
  2774.   * @param  OutputChannel See note above
  2775.   * @retval HAL status
  2776.   */
  2777. HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2778. {
  2779.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  2780.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  2781.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  2782.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  2783.  
  2784.   /* Prevent unused argument(s) compilation warning */
  2785.   UNUSED(OutputChannel);
  2786.  
  2787.   /* Check the TIM channels state */
  2788.   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2789.       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  2790.       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2791.       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  2792.   {
  2793.     return HAL_ERROR;
  2794.   }
  2795.  
  2796.   /* Set the TIM channels state */
  2797.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2798.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2799.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2800.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2801.  
  2802.   /* Enable the Capture compare and the Input Capture channels
  2803.     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2804.     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2805.     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2806.     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
  2807.  
  2808.     No need to enable the counter, it's enabled automatically by hardware
  2809.     (the counter starts in response to a stimulus and generate a pulse */
  2810.  
  2811.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  2812.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  2813.  
  2814.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  2815.   {
  2816.     /* Enable the main output */
  2817.     __HAL_TIM_MOE_ENABLE(htim);
  2818.   }
  2819.  
  2820.   /* Return function status */
  2821.   return HAL_OK;
  2822. }
  2823.  
  2824. /**
  2825.   * @brief  Stops the TIM One Pulse signal generation.
  2826.   * @note Though OutputChannel parameter is deprecated and ignored by the function
  2827.   *        it has been kept to avoid HAL_TIM API compatibility break.
  2828.   * @note The pulse output channel is determined when calling
  2829.   *       @ref HAL_TIM_OnePulse_ConfigChannel().
  2830.   * @param  htim TIM One Pulse handle
  2831.   * @param  OutputChannel See note above
  2832.   * @retval HAL status
  2833.   */
  2834. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2835. {
  2836.   /* Prevent unused argument(s) compilation warning */
  2837.   UNUSED(OutputChannel);
  2838.  
  2839.   /* Disable the Capture compare and the Input Capture channels
  2840.   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2841.   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2842.   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2843.   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
  2844.  
  2845.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  2846.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  2847.  
  2848.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  2849.   {
  2850.     /* Disable the Main Output */
  2851.     __HAL_TIM_MOE_DISABLE(htim);
  2852.   }
  2853.  
  2854.   /* Disable the Peripheral */
  2855.   __HAL_TIM_DISABLE(htim);
  2856.  
  2857.   /* Set the TIM channels state */
  2858.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2859.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2860.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2861.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2862.  
  2863.   /* Return function status */
  2864.   return HAL_OK;
  2865. }
  2866.  
  2867. /**
  2868.   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
  2869.   * @note Though OutputChannel parameter is deprecated and ignored by the function
  2870.   *        it has been kept to avoid HAL_TIM API compatibility break.
  2871.   * @note The pulse output channel is determined when calling
  2872.   *       @ref HAL_TIM_OnePulse_ConfigChannel().
  2873.   * @param  htim TIM One Pulse handle
  2874.   * @param  OutputChannel See note above
  2875.   * @retval HAL status
  2876.   */
  2877. HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2878. {
  2879.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  2880.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  2881.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  2882.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  2883.  
  2884.   /* Prevent unused argument(s) compilation warning */
  2885.   UNUSED(OutputChannel);
  2886.  
  2887.   /* Check the TIM channels state */
  2888.   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2889.       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  2890.       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2891.       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  2892.   {
  2893.     return HAL_ERROR;
  2894.   }
  2895.  
  2896.   /* Set the TIM channels state */
  2897.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2898.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2899.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2900.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2901.  
  2902.   /* Enable the Capture compare and the Input Capture channels
  2903.     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2904.     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2905.     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2906.     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
  2907.  
  2908.     No need to enable the counter, it's enabled automatically by hardware
  2909.     (the counter starts in response to a stimulus and generate a pulse */
  2910.  
  2911.   /* Enable the TIM Capture/Compare 1 interrupt */
  2912.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  2913.  
  2914.   /* Enable the TIM Capture/Compare 2 interrupt */
  2915.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  2916.  
  2917.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  2918.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  2919.  
  2920.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  2921.   {
  2922.     /* Enable the main output */
  2923.     __HAL_TIM_MOE_ENABLE(htim);
  2924.   }
  2925.  
  2926.   /* Return function status */
  2927.   return HAL_OK;
  2928. }
  2929.  
  2930. /**
  2931.   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
  2932.   * @note Though OutputChannel parameter is deprecated and ignored by the function
  2933.   *        it has been kept to avoid HAL_TIM API compatibility break.
  2934.   * @note The pulse output channel is determined when calling
  2935.   *       @ref HAL_TIM_OnePulse_ConfigChannel().
  2936.   * @param  htim TIM One Pulse handle
  2937.   * @param  OutputChannel See note above
  2938.   * @retval HAL status
  2939.   */
  2940. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2941. {
  2942.   /* Prevent unused argument(s) compilation warning */
  2943.   UNUSED(OutputChannel);
  2944.  
  2945.   /* Disable the TIM Capture/Compare 1 interrupt */
  2946.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  2947.  
  2948.   /* Disable the TIM Capture/Compare 2 interrupt */
  2949.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  2950.  
  2951.   /* Disable the Capture compare and the Input Capture channels
  2952.   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2953.   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2954.   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2955.   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
  2956.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  2957.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  2958.  
  2959.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  2960.   {
  2961.     /* Disable the Main Output */
  2962.     __HAL_TIM_MOE_DISABLE(htim);
  2963.   }
  2964.  
  2965.   /* Disable the Peripheral */
  2966.   __HAL_TIM_DISABLE(htim);
  2967.  
  2968.   /* Set the TIM channels state */
  2969.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2970.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2971.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2972.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2973.  
  2974.   /* Return function status */
  2975.   return HAL_OK;
  2976. }
  2977.  
  2978. /**
  2979.   * @}
  2980.   */
  2981.  
  2982. /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
  2983.   *  @brief    TIM Encoder functions
  2984.   *
  2985. @verbatim
  2986.   ==============================================================================
  2987.                           ##### TIM Encoder functions #####
  2988.   ==============================================================================
  2989.   [..]
  2990.     This section provides functions allowing to:
  2991.     (+) Initialize and configure the TIM Encoder.
  2992.     (+) De-initialize the TIM Encoder.
  2993.     (+) Start the TIM Encoder.
  2994.     (+) Stop the TIM Encoder.
  2995.     (+) Start the TIM Encoder and enable interrupt.
  2996.     (+) Stop the TIM Encoder and disable interrupt.
  2997.     (+) Start the TIM Encoder and enable DMA transfer.
  2998.     (+) Stop the TIM Encoder and disable DMA transfer.
  2999.  
  3000. @endverbatim
  3001.   * @{
  3002.   */
  3003. /**
  3004.   * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
  3005.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  3006.   *         requires a timer reset to avoid unexpected direction
  3007.   *         due to DIR bit readonly in center aligned mode.
  3008.   *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
  3009.   * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
  3010.   *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
  3011.   *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
  3012.   * @note   When the timer instance is initialized in Encoder mode, timer
  3013.   *         channels 1 and channel 2 are reserved and cannot be used for other
  3014.   *         purpose.
  3015.   * @param  htim TIM Encoder Interface handle
  3016.   * @param  sConfig TIM Encoder Interface configuration structure
  3017.   * @retval HAL status
  3018.   */
  3019. HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
  3020. {
  3021.   uint32_t tmpsmcr;
  3022.   uint32_t tmpccmr1;
  3023.   uint32_t tmpccer;
  3024.  
  3025.   /* Check the TIM handle allocation */
  3026.   if (htim == NULL)
  3027.   {
  3028.     return HAL_ERROR;
  3029.   }
  3030.  
  3031.   /* Check the parameters */
  3032.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3033.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  3034.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  3035.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  3036.   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
  3037.   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
  3038.   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
  3039.   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
  3040.   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
  3041.   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
  3042.   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
  3043.   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
  3044.   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
  3045.   assert_param(IS_TIM_PERIOD(htim->Init.Period));
  3046.  
  3047.   if (htim->State == HAL_TIM_STATE_RESET)
  3048.   {
  3049.     /* Allocate lock resource and initialize it */
  3050.     htim->Lock = HAL_UNLOCKED;
  3051.  
  3052. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3053.     /* Reset interrupt callbacks to legacy weak callbacks */
  3054.     TIM_ResetCallback(htim);
  3055.  
  3056.     if (htim->Encoder_MspInitCallback == NULL)
  3057.     {
  3058.       htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
  3059.     }
  3060.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  3061.     htim->Encoder_MspInitCallback(htim);
  3062. #else
  3063.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  3064.     HAL_TIM_Encoder_MspInit(htim);
  3065. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3066.   }
  3067.  
  3068.   /* Set the TIM state */
  3069.   htim->State = HAL_TIM_STATE_BUSY;
  3070.  
  3071.   /* Reset the SMS and ECE bits */
  3072.   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
  3073.  
  3074.   /* Configure the Time base in the Encoder Mode */
  3075.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  3076.  
  3077.   /* Get the TIMx SMCR register value */
  3078.   tmpsmcr = htim->Instance->SMCR;
  3079.  
  3080.   /* Get the TIMx CCMR1 register value */
  3081.   tmpccmr1 = htim->Instance->CCMR1;
  3082.  
  3083.   /* Get the TIMx CCER register value */
  3084.   tmpccer = htim->Instance->CCER;
  3085.  
  3086.   /* Set the encoder Mode */
  3087.   tmpsmcr |= sConfig->EncoderMode;
  3088.  
  3089.   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
  3090.   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
  3091.   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
  3092.  
  3093.   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
  3094.   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
  3095.   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
  3096.   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
  3097.   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
  3098.  
  3099.   /* Set the TI1 and the TI2 Polarities */
  3100.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
  3101.   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
  3102.  
  3103.   /* Write to TIMx SMCR */
  3104.   htim->Instance->SMCR = tmpsmcr;
  3105.  
  3106.   /* Write to TIMx CCMR1 */
  3107.   htim->Instance->CCMR1 = tmpccmr1;
  3108.  
  3109.   /* Write to TIMx CCER */
  3110.   htim->Instance->CCER = tmpccer;
  3111.  
  3112.   /* Initialize the DMA burst operation state */
  3113.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  3114.  
  3115.   /* Set the TIM channels state */
  3116.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3117.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3118.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3119.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3120.  
  3121.   /* Initialize the TIM state*/
  3122.   htim->State = HAL_TIM_STATE_READY;
  3123.  
  3124.   return HAL_OK;
  3125. }
  3126.  
  3127.  
  3128. /**
  3129.   * @brief  DeInitializes the TIM Encoder interface
  3130.   * @param  htim TIM Encoder Interface handle
  3131.   * @retval HAL status
  3132.   */
  3133. HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
  3134. {
  3135.   /* Check the parameters */
  3136.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  3137.  
  3138.   htim->State = HAL_TIM_STATE_BUSY;
  3139.  
  3140.   /* Disable the TIM Peripheral Clock */
  3141.   __HAL_TIM_DISABLE(htim);
  3142.  
  3143. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3144.   if (htim->Encoder_MspDeInitCallback == NULL)
  3145.   {
  3146.     htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
  3147.   }
  3148.   /* DeInit the low level hardware */
  3149.   htim->Encoder_MspDeInitCallback(htim);
  3150. #else
  3151.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  3152.   HAL_TIM_Encoder_MspDeInit(htim);
  3153. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3154.  
  3155.   /* Change the DMA burst operation state */
  3156.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  3157.  
  3158.   /* Set the TIM channels state */
  3159.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  3160.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  3161.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  3162.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  3163.  
  3164.   /* Change TIM state */
  3165.   htim->State = HAL_TIM_STATE_RESET;
  3166.  
  3167.   /* Release Lock */
  3168.   __HAL_UNLOCK(htim);
  3169.  
  3170.   return HAL_OK;
  3171. }
  3172.  
  3173. /**
  3174.   * @brief  Initializes the TIM Encoder Interface MSP.
  3175.   * @param  htim TIM Encoder Interface handle
  3176.   * @retval None
  3177.   */
  3178. __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
  3179. {
  3180.   /* Prevent unused argument(s) compilation warning */
  3181.   UNUSED(htim);
  3182.  
  3183.   /* NOTE : This function should not be modified, when the callback is needed,
  3184.             the HAL_TIM_Encoder_MspInit could be implemented in the user file
  3185.    */
  3186. }
  3187.  
  3188. /**
  3189.   * @brief  DeInitializes TIM Encoder Interface MSP.
  3190.   * @param  htim TIM Encoder Interface handle
  3191.   * @retval None
  3192.   */
  3193. __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
  3194. {
  3195.   /* Prevent unused argument(s) compilation warning */
  3196.   UNUSED(htim);
  3197.  
  3198.   /* NOTE : This function should not be modified, when the callback is needed,
  3199.             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
  3200.    */
  3201. }
  3202.  
  3203. /**
  3204.   * @brief  Starts the TIM Encoder Interface.
  3205.   * @param  htim TIM Encoder Interface handle
  3206.   * @param  Channel TIM Channels to be enabled
  3207.   *          This parameter can be one of the following values:
  3208.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3209.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3210.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3211.   * @retval HAL status
  3212.   */
  3213. HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  3214. {
  3215.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  3216.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  3217.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  3218.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  3219.  
  3220.   /* Check the parameters */
  3221.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3222.  
  3223.   /* Set the TIM channel(s) state */
  3224.   if (Channel == TIM_CHANNEL_1)
  3225.   {
  3226.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3227.         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
  3228.     {
  3229.       return HAL_ERROR;
  3230.     }
  3231.     else
  3232.     {
  3233.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3234.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3235.     }
  3236.   }
  3237.   else if (Channel == TIM_CHANNEL_2)
  3238.   {
  3239.     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3240.         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3241.     {
  3242.       return HAL_ERROR;
  3243.     }
  3244.     else
  3245.     {
  3246.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3247.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3248.     }
  3249.   }
  3250.   else
  3251.   {
  3252.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3253.         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3254.         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3255.         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3256.     {
  3257.       return HAL_ERROR;
  3258.     }
  3259.     else
  3260.     {
  3261.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3262.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3263.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3264.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3265.     }
  3266.   }
  3267.  
  3268.   /* Enable the encoder interface channels */
  3269.   switch (Channel)
  3270.   {
  3271.     case TIM_CHANNEL_1:
  3272.     {
  3273.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3274.       break;
  3275.     }
  3276.  
  3277.     case TIM_CHANNEL_2:
  3278.     {
  3279.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3280.       break;
  3281.     }
  3282.  
  3283.     default :
  3284.     {
  3285.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3286.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3287.       break;
  3288.     }
  3289.   }
  3290.   /* Enable the Peripheral */
  3291.   __HAL_TIM_ENABLE(htim);
  3292.  
  3293.   /* Return function status */
  3294.   return HAL_OK;
  3295. }
  3296.  
  3297. /**
  3298.   * @brief  Stops the TIM Encoder Interface.
  3299.   * @param  htim TIM Encoder Interface handle
  3300.   * @param  Channel TIM Channels to be disabled
  3301.   *          This parameter can be one of the following values:
  3302.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3303.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3304.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3305.   * @retval HAL status
  3306.   */
  3307. HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  3308. {
  3309.   /* Check the parameters */
  3310.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3311.  
  3312.   /* Disable the Input Capture channels 1 and 2
  3313.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3314.   switch (Channel)
  3315.   {
  3316.     case TIM_CHANNEL_1:
  3317.     {
  3318.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3319.       break;
  3320.     }
  3321.  
  3322.     case TIM_CHANNEL_2:
  3323.     {
  3324.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3325.       break;
  3326.     }
  3327.  
  3328.     default :
  3329.     {
  3330.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3331.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3332.       break;
  3333.     }
  3334.   }
  3335.  
  3336.   /* Disable the Peripheral */
  3337.   __HAL_TIM_DISABLE(htim);
  3338.  
  3339.   /* Set the TIM channel(s) state */
  3340.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3341.   {
  3342.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3343.     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3344.   }
  3345.   else
  3346.   {
  3347.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3348.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3349.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3350.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3351.   }
  3352.  
  3353.   /* Return function status */
  3354.   return HAL_OK;
  3355. }
  3356.  
  3357. /**
  3358.   * @brief  Starts the TIM Encoder Interface in interrupt mode.
  3359.   * @param  htim TIM Encoder Interface handle
  3360.   * @param  Channel TIM Channels to be enabled
  3361.   *          This parameter can be one of the following values:
  3362.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3363.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3364.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3365.   * @retval HAL status
  3366.   */
  3367. HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  3368. {
  3369.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  3370.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  3371.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  3372.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  3373.  
  3374.   /* Check the parameters */
  3375.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3376.  
  3377.   /* Set the TIM channel(s) state */
  3378.   if (Channel == TIM_CHANNEL_1)
  3379.   {
  3380.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3381.         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
  3382.     {
  3383.       return HAL_ERROR;
  3384.     }
  3385.     else
  3386.     {
  3387.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3388.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3389.     }
  3390.   }
  3391.   else if (Channel == TIM_CHANNEL_2)
  3392.   {
  3393.     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3394.         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3395.     {
  3396.       return HAL_ERROR;
  3397.     }
  3398.     else
  3399.     {
  3400.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3401.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3402.     }
  3403.   }
  3404.   else
  3405.   {
  3406.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3407.         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3408.         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3409.         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3410.     {
  3411.       return HAL_ERROR;
  3412.     }
  3413.     else
  3414.     {
  3415.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3416.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3417.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3418.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3419.     }
  3420.   }
  3421.  
  3422.   /* Enable the encoder interface channels */
  3423.   /* Enable the capture compare Interrupts 1 and/or 2 */
  3424.   switch (Channel)
  3425.   {
  3426.     case TIM_CHANNEL_1:
  3427.     {
  3428.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3429.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  3430.       break;
  3431.     }
  3432.  
  3433.     case TIM_CHANNEL_2:
  3434.     {
  3435.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3436.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  3437.       break;
  3438.     }
  3439.  
  3440.     default :
  3441.     {
  3442.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3443.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3444.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  3445.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  3446.       break;
  3447.     }
  3448.   }
  3449.  
  3450.   /* Enable the Peripheral */
  3451.   __HAL_TIM_ENABLE(htim);
  3452.  
  3453.   /* Return function status */
  3454.   return HAL_OK;
  3455. }
  3456.  
  3457. /**
  3458.   * @brief  Stops the TIM Encoder Interface in interrupt mode.
  3459.   * @param  htim TIM Encoder Interface handle
  3460.   * @param  Channel TIM Channels to be disabled
  3461.   *          This parameter can be one of the following values:
  3462.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3463.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3464.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3465.   * @retval HAL status
  3466.   */
  3467. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  3468. {
  3469.   /* Check the parameters */
  3470.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3471.  
  3472.   /* Disable the Input Capture channels 1 and 2
  3473.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3474.   if (Channel == TIM_CHANNEL_1)
  3475.   {
  3476.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3477.  
  3478.     /* Disable the capture compare Interrupts 1 */
  3479.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  3480.   }
  3481.   else if (Channel == TIM_CHANNEL_2)
  3482.   {
  3483.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3484.  
  3485.     /* Disable the capture compare Interrupts 2 */
  3486.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  3487.   }
  3488.   else
  3489.   {
  3490.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3491.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3492.  
  3493.     /* Disable the capture compare Interrupts 1 and 2 */
  3494.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  3495.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  3496.   }
  3497.  
  3498.   /* Disable the Peripheral */
  3499.   __HAL_TIM_DISABLE(htim);
  3500.  
  3501.   /* Set the TIM channel(s) state */
  3502.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3503.   {
  3504.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3505.     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3506.   }
  3507.   else
  3508.   {
  3509.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3510.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3511.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3512.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3513.   }
  3514.  
  3515.   /* Return function status */
  3516.   return HAL_OK;
  3517. }
  3518.  
  3519. /**
  3520.   * @brief  Starts the TIM Encoder Interface in DMA mode.
  3521.   * @param  htim TIM Encoder Interface handle
  3522.   * @param  Channel TIM Channels to be enabled
  3523.   *          This parameter can be one of the following values:
  3524.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3525.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3526.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3527.   * @param  pData1 The destination Buffer address for IC1.
  3528.   * @param  pData2 The destination Buffer address for IC2.
  3529.   * @param  Length The length of data to be transferred from TIM peripheral to memory.
  3530.   * @retval HAL status
  3531.   */
  3532. HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
  3533.                                             uint32_t *pData2, uint16_t Length)
  3534. {
  3535.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  3536.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  3537.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  3538.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  3539.  
  3540.   /* Check the parameters */
  3541.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3542.  
  3543.   /* Set the TIM channel(s) state */
  3544.   if (Channel == TIM_CHANNEL_1)
  3545.   {
  3546.     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3547.         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
  3548.     {
  3549.       return HAL_BUSY;
  3550.     }
  3551.     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
  3552.              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
  3553.     {
  3554.       if ((pData1 == NULL) || (Length == 0U))
  3555.       {
  3556.         return HAL_ERROR;
  3557.       }
  3558.       else
  3559.       {
  3560.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3561.         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3562.       }
  3563.     }
  3564.     else
  3565.     {
  3566.       return HAL_ERROR;
  3567.     }
  3568.   }
  3569.   else if (Channel == TIM_CHANNEL_2)
  3570.   {
  3571.     if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3572.         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
  3573.     {
  3574.       return HAL_BUSY;
  3575.     }
  3576.     else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
  3577.              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
  3578.     {
  3579.       if ((pData2 == NULL) || (Length == 0U))
  3580.       {
  3581.         return HAL_ERROR;
  3582.       }
  3583.       else
  3584.       {
  3585.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3586.         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3587.       }
  3588.     }
  3589.     else
  3590.     {
  3591.       return HAL_ERROR;
  3592.     }
  3593.   }
  3594.   else
  3595.   {
  3596.     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3597.         || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3598.         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3599.         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
  3600.     {
  3601.       return HAL_BUSY;
  3602.     }
  3603.     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
  3604.              && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
  3605.              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
  3606.              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
  3607.     {
  3608.       if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
  3609.       {
  3610.         return HAL_ERROR;
  3611.       }
  3612.       else
  3613.       {
  3614.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3615.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3616.         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3617.         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3618.       }
  3619.     }
  3620.     else
  3621.     {
  3622.       return HAL_ERROR;
  3623.     }
  3624.   }
  3625.  
  3626.   switch (Channel)
  3627.   {
  3628.     case TIM_CHANNEL_1:
  3629.     {
  3630.       /* Set the DMA capture callbacks */
  3631.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  3632.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3633.  
  3634.       /* Set the DMA error callback */
  3635.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  3636.  
  3637.       /* Enable the DMA channel */
  3638.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
  3639.                            Length) != HAL_OK)
  3640.       {
  3641.         /* Return error status */
  3642.         return HAL_ERROR;
  3643.       }
  3644.       /* Enable the TIM Input Capture DMA request */
  3645.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  3646.  
  3647.       /* Enable the Capture compare channel */
  3648.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3649.  
  3650.       /* Enable the Peripheral */
  3651.       __HAL_TIM_ENABLE(htim);
  3652.  
  3653.       break;
  3654.     }
  3655.  
  3656.     case TIM_CHANNEL_2:
  3657.     {
  3658.       /* Set the DMA capture callbacks */
  3659.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  3660.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3661.  
  3662.       /* Set the DMA error callback */
  3663.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
  3664.       /* Enable the DMA channel */
  3665.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
  3666.                            Length) != HAL_OK)
  3667.       {
  3668.         /* Return error status */
  3669.         return HAL_ERROR;
  3670.       }
  3671.       /* Enable the TIM Input Capture  DMA request */
  3672.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  3673.  
  3674.       /* Enable the Capture compare channel */
  3675.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3676.  
  3677.       /* Enable the Peripheral */
  3678.       __HAL_TIM_ENABLE(htim);
  3679.  
  3680.       break;
  3681.     }
  3682.  
  3683.     default:
  3684.     {
  3685.       /* Set the DMA capture callbacks */
  3686.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  3687.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3688.  
  3689.       /* Set the DMA error callback */
  3690.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  3691.  
  3692.       /* Enable the DMA channel */
  3693.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
  3694.                            Length) != HAL_OK)
  3695.       {
  3696.         /* Return error status */
  3697.         return HAL_ERROR;
  3698.       }
  3699.  
  3700.       /* Set the DMA capture callbacks */
  3701.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  3702.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3703.  
  3704.       /* Set the DMA error callback */
  3705.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  3706.  
  3707.       /* Enable the DMA channel */
  3708.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
  3709.                            Length) != HAL_OK)
  3710.       {
  3711.         /* Return error status */
  3712.         return HAL_ERROR;
  3713.       }
  3714.  
  3715.       /* Enable the TIM Input Capture  DMA request */
  3716.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  3717.       /* Enable the TIM Input Capture  DMA request */
  3718.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  3719.  
  3720.       /* Enable the Capture compare channel */
  3721.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3722.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3723.  
  3724.       /* Enable the Peripheral */
  3725.       __HAL_TIM_ENABLE(htim);
  3726.  
  3727.       break;
  3728.     }
  3729.   }
  3730.  
  3731.   /* Return function status */
  3732.   return HAL_OK;
  3733. }
  3734.  
  3735. /**
  3736.   * @brief  Stops the TIM Encoder Interface in DMA mode.
  3737.   * @param  htim TIM Encoder Interface handle
  3738.   * @param  Channel TIM Channels to be enabled
  3739.   *          This parameter can be one of the following values:
  3740.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3741.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3742.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3743.   * @retval HAL status
  3744.   */
  3745. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  3746. {
  3747.   /* Check the parameters */
  3748.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3749.  
  3750.   /* Disable the Input Capture channels 1 and 2
  3751.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3752.   if (Channel == TIM_CHANNEL_1)
  3753.   {
  3754.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3755.  
  3756.     /* Disable the capture compare DMA Request 1 */
  3757.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  3758.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  3759.   }
  3760.   else if (Channel == TIM_CHANNEL_2)
  3761.   {
  3762.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3763.  
  3764.     /* Disable the capture compare DMA Request 2 */
  3765.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  3766.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  3767.   }
  3768.   else
  3769.   {
  3770.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3771.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3772.  
  3773.     /* Disable the capture compare DMA Request 1 and 2 */
  3774.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  3775.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  3776.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  3777.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  3778.   }
  3779.  
  3780.   /* Disable the Peripheral */
  3781.   __HAL_TIM_DISABLE(htim);
  3782.  
  3783.   /* Set the TIM channel(s) state */
  3784.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3785.   {
  3786.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3787.     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3788.   }
  3789.   else
  3790.   {
  3791.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3792.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3793.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3794.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3795.   }
  3796.  
  3797.   /* Return function status */
  3798.   return HAL_OK;
  3799. }
  3800.  
  3801. /**
  3802.   * @}
  3803.   */
  3804. /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
  3805.   *  @brief    TIM IRQ handler management
  3806.   *
  3807. @verbatim
  3808.   ==============================================================================
  3809.                         ##### IRQ handler management #####
  3810.   ==============================================================================
  3811.   [..]
  3812.     This section provides Timer IRQ handler function.
  3813.  
  3814. @endverbatim
  3815.   * @{
  3816.   */
  3817. /**
  3818.   * @brief  This function handles TIM interrupts requests.
  3819.   * @param  htim TIM  handle
  3820.   * @retval None
  3821.   */
  3822. void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
  3823. {
  3824.   /* Capture compare 1 event */
  3825.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
  3826.   {
  3827.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
  3828.     {
  3829.       {
  3830.         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
  3831.         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  3832.  
  3833.         /* Input capture event */
  3834.         if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
  3835.         {
  3836. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3837.           htim->IC_CaptureCallback(htim);
  3838. #else
  3839.           HAL_TIM_IC_CaptureCallback(htim);
  3840. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3841.         }
  3842.         /* Output compare event */
  3843.         else
  3844.         {
  3845. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3846.           htim->OC_DelayElapsedCallback(htim);
  3847.           htim->PWM_PulseFinishedCallback(htim);
  3848. #else
  3849.           HAL_TIM_OC_DelayElapsedCallback(htim);
  3850.           HAL_TIM_PWM_PulseFinishedCallback(htim);
  3851. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3852.         }
  3853.         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3854.       }
  3855.     }
  3856.   }
  3857.   /* Capture compare 2 event */
  3858.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
  3859.   {
  3860.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
  3861.     {
  3862.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
  3863.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  3864.       /* Input capture event */
  3865.       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
  3866.       {
  3867. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3868.         htim->IC_CaptureCallback(htim);
  3869. #else
  3870.         HAL_TIM_IC_CaptureCallback(htim);
  3871. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3872.       }
  3873.       /* Output compare event */
  3874.       else
  3875.       {
  3876. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3877.         htim->OC_DelayElapsedCallback(htim);
  3878.         htim->PWM_PulseFinishedCallback(htim);
  3879. #else
  3880.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3881.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3882. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3883.       }
  3884.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3885.     }
  3886.   }
  3887.   /* Capture compare 3 event */
  3888.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
  3889.   {
  3890.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
  3891.     {
  3892.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
  3893.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  3894.       /* Input capture event */
  3895.       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
  3896.       {
  3897. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3898.         htim->IC_CaptureCallback(htim);
  3899. #else
  3900.         HAL_TIM_IC_CaptureCallback(htim);
  3901. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3902.       }
  3903.       /* Output compare event */
  3904.       else
  3905.       {
  3906. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3907.         htim->OC_DelayElapsedCallback(htim);
  3908.         htim->PWM_PulseFinishedCallback(htim);
  3909. #else
  3910.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3911.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3912. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3913.       }
  3914.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3915.     }
  3916.   }
  3917.   /* Capture compare 4 event */
  3918.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
  3919.   {
  3920.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
  3921.     {
  3922.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
  3923.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  3924.       /* Input capture event */
  3925.       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
  3926.       {
  3927. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3928.         htim->IC_CaptureCallback(htim);
  3929. #else
  3930.         HAL_TIM_IC_CaptureCallback(htim);
  3931. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3932.       }
  3933.       /* Output compare event */
  3934.       else
  3935.       {
  3936. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3937.         htim->OC_DelayElapsedCallback(htim);
  3938.         htim->PWM_PulseFinishedCallback(htim);
  3939. #else
  3940.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3941.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3942. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3943.       }
  3944.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3945.     }
  3946.   }
  3947.   /* TIM Update event */
  3948.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
  3949.   {
  3950.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
  3951.     {
  3952.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
  3953. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3954.       htim->PeriodElapsedCallback(htim);
  3955. #else
  3956.       HAL_TIM_PeriodElapsedCallback(htim);
  3957. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3958.     }
  3959.   }
  3960.   /* TIM Break input event */
  3961.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
  3962.   {
  3963.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
  3964.     {
  3965.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
  3966. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3967.       htim->BreakCallback(htim);
  3968. #else
  3969.       HAL_TIMEx_BreakCallback(htim);
  3970. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3971.     }
  3972.   }
  3973.   /* TIM Trigger detection event */
  3974.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
  3975.   {
  3976.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
  3977.     {
  3978.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
  3979. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3980.       htim->TriggerCallback(htim);
  3981. #else
  3982.       HAL_TIM_TriggerCallback(htim);
  3983. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3984.     }
  3985.   }
  3986.   /* TIM commutation event */
  3987.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
  3988.   {
  3989.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
  3990.     {
  3991.       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
  3992. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3993.       htim->CommutationCallback(htim);
  3994. #else
  3995.       HAL_TIMEx_CommutCallback(htim);
  3996. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3997.     }
  3998.   }
  3999. }
  4000.  
  4001. /**
  4002.   * @}
  4003.   */
  4004.  
  4005. /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
  4006.   *  @brief    TIM Peripheral Control functions
  4007.   *
  4008. @verbatim
  4009.   ==============================================================================
  4010.                    ##### Peripheral Control functions #####
  4011.   ==============================================================================
  4012.  [..]
  4013.    This section provides functions allowing to:
  4014.       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
  4015.       (+) Configure External Clock source.
  4016.       (+) Configure Complementary channels, break features and dead time.
  4017.       (+) Configure Master and the Slave synchronization.
  4018.       (+) Configure the DMA Burst Mode.
  4019.  
  4020. @endverbatim
  4021.   * @{
  4022.   */
  4023.  
  4024. /**
  4025.   * @brief  Initializes the TIM Output Compare Channels according to the specified
  4026.   *         parameters in the TIM_OC_InitTypeDef.
  4027.   * @param  htim TIM Output Compare handle
  4028.   * @param  sConfig TIM Output Compare configuration structure
  4029.   * @param  Channel TIM Channels to configure
  4030.   *          This parameter can be one of the following values:
  4031.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4032.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4033.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  4034.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  4035.   * @retval HAL status
  4036.   */
  4037. HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
  4038.                                            const TIM_OC_InitTypeDef *sConfig,
  4039.                                            uint32_t Channel)
  4040. {
  4041.   HAL_StatusTypeDef status = HAL_OK;
  4042.  
  4043.   /* Check the parameters */
  4044.   assert_param(IS_TIM_CHANNELS(Channel));
  4045.   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
  4046.   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
  4047.  
  4048.   /* Process Locked */
  4049.   __HAL_LOCK(htim);
  4050.  
  4051.   switch (Channel)
  4052.   {
  4053.     case TIM_CHANNEL_1:
  4054.     {
  4055.       /* Check the parameters */
  4056.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4057.  
  4058.       /* Configure the TIM Channel 1 in Output Compare */
  4059.       TIM_OC1_SetConfig(htim->Instance, sConfig);
  4060.       break;
  4061.     }
  4062.  
  4063.     case TIM_CHANNEL_2:
  4064.     {
  4065.       /* Check the parameters */
  4066.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4067.  
  4068.       /* Configure the TIM Channel 2 in Output Compare */
  4069.       TIM_OC2_SetConfig(htim->Instance, sConfig);
  4070.       break;
  4071.     }
  4072.  
  4073.     case TIM_CHANNEL_3:
  4074.     {
  4075.       /* Check the parameters */
  4076.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  4077.  
  4078.       /* Configure the TIM Channel 3 in Output Compare */
  4079.       TIM_OC3_SetConfig(htim->Instance, sConfig);
  4080.       break;
  4081.     }
  4082.  
  4083.     case TIM_CHANNEL_4:
  4084.     {
  4085.       /* Check the parameters */
  4086.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  4087.  
  4088.       /* Configure the TIM Channel 4 in Output Compare */
  4089.       TIM_OC4_SetConfig(htim->Instance, sConfig);
  4090.       break;
  4091.     }
  4092.  
  4093.     default:
  4094.       status = HAL_ERROR;
  4095.       break;
  4096.   }
  4097.  
  4098.   __HAL_UNLOCK(htim);
  4099.  
  4100.   return status;
  4101. }
  4102.  
  4103. /**
  4104.   * @brief  Initializes the TIM Input Capture Channels according to the specified
  4105.   *         parameters in the TIM_IC_InitTypeDef.
  4106.   * @param  htim TIM IC handle
  4107.   * @param  sConfig TIM Input Capture configuration structure
  4108.   * @param  Channel TIM Channel to configure
  4109.   *          This parameter can be one of the following values:
  4110.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4111.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4112.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  4113.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  4114.   * @retval HAL status
  4115.   */
  4116. HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
  4117. {
  4118.   HAL_StatusTypeDef status = HAL_OK;
  4119.  
  4120.   /* Check the parameters */
  4121.   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4122.   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
  4123.   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
  4124.   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
  4125.   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
  4126.  
  4127.   /* Process Locked */
  4128.   __HAL_LOCK(htim);
  4129.  
  4130.   if (Channel == TIM_CHANNEL_1)
  4131.   {
  4132.     /* TI1 Configuration */
  4133.     TIM_TI1_SetConfig(htim->Instance,
  4134.                       sConfig->ICPolarity,
  4135.                       sConfig->ICSelection,
  4136.                       sConfig->ICFilter);
  4137.  
  4138.     /* Reset the IC1PSC Bits */
  4139.     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
  4140.  
  4141.     /* Set the IC1PSC value */
  4142.     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
  4143.   }
  4144.   else if (Channel == TIM_CHANNEL_2)
  4145.   {
  4146.     /* TI2 Configuration */
  4147.     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4148.  
  4149.     TIM_TI2_SetConfig(htim->Instance,
  4150.                       sConfig->ICPolarity,
  4151.                       sConfig->ICSelection,
  4152.                       sConfig->ICFilter);
  4153.  
  4154.     /* Reset the IC2PSC Bits */
  4155.     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
  4156.  
  4157.     /* Set the IC2PSC value */
  4158.     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
  4159.   }
  4160.   else if (Channel == TIM_CHANNEL_3)
  4161.   {
  4162.     /* TI3 Configuration */
  4163.     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  4164.  
  4165.     TIM_TI3_SetConfig(htim->Instance,
  4166.                       sConfig->ICPolarity,
  4167.                       sConfig->ICSelection,
  4168.                       sConfig->ICFilter);
  4169.  
  4170.     /* Reset the IC3PSC Bits */
  4171.     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
  4172.  
  4173.     /* Set the IC3PSC value */
  4174.     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
  4175.   }
  4176.   else if (Channel == TIM_CHANNEL_4)
  4177.   {
  4178.     /* TI4 Configuration */
  4179.     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  4180.  
  4181.     TIM_TI4_SetConfig(htim->Instance,
  4182.                       sConfig->ICPolarity,
  4183.                       sConfig->ICSelection,
  4184.                       sConfig->ICFilter);
  4185.  
  4186.     /* Reset the IC4PSC Bits */
  4187.     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
  4188.  
  4189.     /* Set the IC4PSC value */
  4190.     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
  4191.   }
  4192.   else
  4193.   {
  4194.     status = HAL_ERROR;
  4195.   }
  4196.  
  4197.   __HAL_UNLOCK(htim);
  4198.  
  4199.   return status;
  4200. }
  4201.  
  4202. /**
  4203.   * @brief  Initializes the TIM PWM  channels according to the specified
  4204.   *         parameters in the TIM_OC_InitTypeDef.
  4205.   * @param  htim TIM PWM handle
  4206.   * @param  sConfig TIM PWM configuration structure
  4207.   * @param  Channel TIM Channels to be configured
  4208.   *          This parameter can be one of the following values:
  4209.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4210.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4211.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  4212.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  4213.   * @retval HAL status
  4214.   */
  4215. HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
  4216.                                             const TIM_OC_InitTypeDef *sConfig,
  4217.                                             uint32_t Channel)
  4218. {
  4219.   HAL_StatusTypeDef status = HAL_OK;
  4220.  
  4221.   /* Check the parameters */
  4222.   assert_param(IS_TIM_CHANNELS(Channel));
  4223.   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
  4224.   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
  4225.   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
  4226.  
  4227.   /* Process Locked */
  4228.   __HAL_LOCK(htim);
  4229.  
  4230.   switch (Channel)
  4231.   {
  4232.     case TIM_CHANNEL_1:
  4233.     {
  4234.       /* Check the parameters */
  4235.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4236.  
  4237.       /* Configure the Channel 1 in PWM mode */
  4238.       TIM_OC1_SetConfig(htim->Instance, sConfig);
  4239.  
  4240.       /* Set the Preload enable bit for channel1 */
  4241.       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
  4242.  
  4243.       /* Configure the Output Fast mode */
  4244.       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
  4245.       htim->Instance->CCMR1 |= sConfig->OCFastMode;
  4246.       break;
  4247.     }
  4248.  
  4249.     case TIM_CHANNEL_2:
  4250.     {
  4251.       /* Check the parameters */
  4252.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4253.  
  4254.       /* Configure the Channel 2 in PWM mode */
  4255.       TIM_OC2_SetConfig(htim->Instance, sConfig);
  4256.  
  4257.       /* Set the Preload enable bit for channel2 */
  4258.       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
  4259.  
  4260.       /* Configure the Output Fast mode */
  4261.       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
  4262.       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
  4263.       break;
  4264.     }
  4265.  
  4266.     case TIM_CHANNEL_3:
  4267.     {
  4268.       /* Check the parameters */
  4269.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  4270.  
  4271.       /* Configure the Channel 3 in PWM mode */
  4272.       TIM_OC3_SetConfig(htim->Instance, sConfig);
  4273.  
  4274.       /* Set the Preload enable bit for channel3 */
  4275.       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
  4276.  
  4277.       /* Configure the Output Fast mode */
  4278.       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
  4279.       htim->Instance->CCMR2 |= sConfig->OCFastMode;
  4280.       break;
  4281.     }
  4282.  
  4283.     case TIM_CHANNEL_4:
  4284.     {
  4285.       /* Check the parameters */
  4286.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  4287.  
  4288.       /* Configure the Channel 4 in PWM mode */
  4289.       TIM_OC4_SetConfig(htim->Instance, sConfig);
  4290.  
  4291.       /* Set the Preload enable bit for channel4 */
  4292.       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
  4293.  
  4294.       /* Configure the Output Fast mode */
  4295.       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
  4296.       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
  4297.       break;
  4298.     }
  4299.  
  4300.     default:
  4301.       status = HAL_ERROR;
  4302.       break;
  4303.   }
  4304.  
  4305.   __HAL_UNLOCK(htim);
  4306.  
  4307.   return status;
  4308. }
  4309.  
  4310. /**
  4311.   * @brief  Initializes the TIM One Pulse Channels according to the specified
  4312.   *         parameters in the TIM_OnePulse_InitTypeDef.
  4313.   * @param  htim TIM One Pulse handle
  4314.   * @param  sConfig TIM One Pulse configuration structure
  4315.   * @param  OutputChannel TIM output channel to configure
  4316.   *          This parameter can be one of the following values:
  4317.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4318.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4319.   * @param  InputChannel TIM input Channel to configure
  4320.   *          This parameter can be one of the following values:
  4321.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4322.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4323.   * @note  To output a waveform with a minimum delay user can enable the fast
  4324.   *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
  4325.   *        output is forced in response to the edge detection on TIx input,
  4326.   *        without taking in account the comparison.
  4327.   * @retval HAL status
  4328.   */
  4329. HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
  4330.                                                  uint32_t OutputChannel,  uint32_t InputChannel)
  4331. {
  4332.   HAL_StatusTypeDef status = HAL_OK;
  4333.   TIM_OC_InitTypeDef temp1;
  4334.  
  4335.   /* Check the parameters */
  4336.   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
  4337.   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
  4338.  
  4339.   if (OutputChannel != InputChannel)
  4340.   {
  4341.     /* Process Locked */
  4342.     __HAL_LOCK(htim);
  4343.  
  4344.     htim->State = HAL_TIM_STATE_BUSY;
  4345.  
  4346.     /* Extract the Output compare configuration from sConfig structure */
  4347.     temp1.OCMode = sConfig->OCMode;
  4348.     temp1.Pulse = sConfig->Pulse;
  4349.     temp1.OCPolarity = sConfig->OCPolarity;
  4350.     temp1.OCNPolarity = sConfig->OCNPolarity;
  4351.     temp1.OCIdleState = sConfig->OCIdleState;
  4352.     temp1.OCNIdleState = sConfig->OCNIdleState;
  4353.  
  4354.     switch (OutputChannel)
  4355.     {
  4356.       case TIM_CHANNEL_1:
  4357.       {
  4358.         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4359.  
  4360.         TIM_OC1_SetConfig(htim->Instance, &temp1);
  4361.         break;
  4362.       }
  4363.  
  4364.       case TIM_CHANNEL_2:
  4365.       {
  4366.         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4367.  
  4368.         TIM_OC2_SetConfig(htim->Instance, &temp1);
  4369.         break;
  4370.       }
  4371.  
  4372.       default:
  4373.         status = HAL_ERROR;
  4374.         break;
  4375.     }
  4376.  
  4377.     if (status == HAL_OK)
  4378.     {
  4379.       switch (InputChannel)
  4380.       {
  4381.         case TIM_CHANNEL_1:
  4382.         {
  4383.           assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4384.  
  4385.           TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
  4386.                             sConfig->ICSelection, sConfig->ICFilter);
  4387.  
  4388.           /* Reset the IC1PSC Bits */
  4389.           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
  4390.  
  4391.           /* Select the Trigger source */
  4392.           htim->Instance->SMCR &= ~TIM_SMCR_TS;
  4393.           htim->Instance->SMCR |= TIM_TS_TI1FP1;
  4394.  
  4395.           /* Select the Slave Mode */
  4396.           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
  4397.           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
  4398.           break;
  4399.         }
  4400.  
  4401.         case TIM_CHANNEL_2:
  4402.         {
  4403.           assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4404.  
  4405.           TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
  4406.                             sConfig->ICSelection, sConfig->ICFilter);
  4407.  
  4408.           /* Reset the IC2PSC Bits */
  4409.           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
  4410.  
  4411.           /* Select the Trigger source */
  4412.           htim->Instance->SMCR &= ~TIM_SMCR_TS;
  4413.           htim->Instance->SMCR |= TIM_TS_TI2FP2;
  4414.  
  4415.           /* Select the Slave Mode */
  4416.           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
  4417.           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
  4418.           break;
  4419.         }
  4420.  
  4421.         default:
  4422.           status = HAL_ERROR;
  4423.           break;
  4424.       }
  4425.     }
  4426.  
  4427.     htim->State = HAL_TIM_STATE_READY;
  4428.  
  4429.     __HAL_UNLOCK(htim);
  4430.  
  4431.     return status;
  4432.   }
  4433.   else
  4434.   {
  4435.     return HAL_ERROR;
  4436.   }
  4437. }
  4438.  
  4439. /**
  4440.   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
  4441.   * @param  htim TIM handle
  4442.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
  4443.   *         This parameter can be one of the following values:
  4444.   *            @arg TIM_DMABASE_CR1
  4445.   *            @arg TIM_DMABASE_CR2
  4446.   *            @arg TIM_DMABASE_SMCR
  4447.   *            @arg TIM_DMABASE_DIER
  4448.   *            @arg TIM_DMABASE_SR
  4449.   *            @arg TIM_DMABASE_EGR
  4450.   *            @arg TIM_DMABASE_CCMR1
  4451.   *            @arg TIM_DMABASE_CCMR2
  4452.   *            @arg TIM_DMABASE_CCER
  4453.   *            @arg TIM_DMABASE_CNT
  4454.   *            @arg TIM_DMABASE_PSC
  4455.   *            @arg TIM_DMABASE_ARR
  4456.   *            @arg TIM_DMABASE_RCR
  4457.   *            @arg TIM_DMABASE_CCR1
  4458.   *            @arg TIM_DMABASE_CCR2
  4459.   *            @arg TIM_DMABASE_CCR3
  4460.   *            @arg TIM_DMABASE_CCR4
  4461.   *            @arg TIM_DMABASE_BDTR
  4462.   * @param  BurstRequestSrc TIM DMA Request sources
  4463.   *         This parameter can be one of the following values:
  4464.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4465.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4466.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4467.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4468.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4469.   *            @arg TIM_DMA_COM: TIM Commutation DMA source
  4470.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4471.   * @param  BurstBuffer The Buffer address.
  4472.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4473.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4474.   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
  4475.   * @retval HAL status
  4476.   */
  4477. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4478.                                               uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t  BurstLength)
  4479. {
  4480.   HAL_StatusTypeDef status;
  4481.  
  4482.   status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
  4483.                                             ((BurstLength) >> 8U) + 1U);
  4484.  
  4485.  
  4486.  
  4487.   return status;
  4488. }
  4489.  
  4490. /**
  4491.   * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
  4492.   * @param  htim TIM handle
  4493.   * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
  4494.   *         This parameter can be one of the following values:
  4495.   *            @arg TIM_DMABASE_CR1
  4496.   *            @arg TIM_DMABASE_CR2
  4497.   *            @arg TIM_DMABASE_SMCR
  4498.   *            @arg TIM_DMABASE_DIER
  4499.   *            @arg TIM_DMABASE_SR
  4500.   *            @arg TIM_DMABASE_EGR
  4501.   *            @arg TIM_DMABASE_CCMR1
  4502.   *            @arg TIM_DMABASE_CCMR2
  4503.   *            @arg TIM_DMABASE_CCER
  4504.   *            @arg TIM_DMABASE_CNT
  4505.   *            @arg TIM_DMABASE_PSC
  4506.   *            @arg TIM_DMABASE_ARR
  4507.   *            @arg TIM_DMABASE_RCR
  4508.   *            @arg TIM_DMABASE_CCR1
  4509.   *            @arg TIM_DMABASE_CCR2
  4510.   *            @arg TIM_DMABASE_CCR3
  4511.   *            @arg TIM_DMABASE_CCR4
  4512.   *            @arg TIM_DMABASE_BDTR
  4513.   * @param  BurstRequestSrc TIM DMA Request sources
  4514.   *         This parameter can be one of the following values:
  4515.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4516.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4517.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4518.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4519.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4520.   *            @arg TIM_DMA_COM: TIM Commutation DMA source
  4521.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4522.   * @param  BurstBuffer The Buffer address.
  4523.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4524.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4525.   * @param  DataLength Data length. This parameter can be one value
  4526.   *         between 1 and 0xFFFF.
  4527.   * @retval HAL status
  4528.   */
  4529. HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4530.                                                    uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
  4531.                                                    uint32_t  BurstLength,  uint32_t  DataLength)
  4532. {
  4533.   HAL_StatusTypeDef status = HAL_OK;
  4534.  
  4535.   /* Check the parameters */
  4536.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  4537.   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
  4538.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4539.   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
  4540.   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
  4541.  
  4542.   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
  4543.   {
  4544.     return HAL_BUSY;
  4545.   }
  4546.   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
  4547.   {
  4548.     if ((BurstBuffer == NULL) && (BurstLength > 0U))
  4549.     {
  4550.       return HAL_ERROR;
  4551.     }
  4552.     else
  4553.     {
  4554.       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
  4555.     }
  4556.   }
  4557.   else
  4558.   {
  4559.     /* nothing to do */
  4560.   }
  4561.  
  4562.   switch (BurstRequestSrc)
  4563.   {
  4564.     case TIM_DMA_UPDATE:
  4565.     {
  4566.       /* Set the DMA Period elapsed callbacks */
  4567.       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  4568.       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  4569.  
  4570.       /* Set the DMA error callback */
  4571.       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  4572.  
  4573.       /* Enable the DMA channel */
  4574.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
  4575.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4576.       {
  4577.         /* Return error status */
  4578.         return HAL_ERROR;
  4579.       }
  4580.       break;
  4581.     }
  4582.     case TIM_DMA_CC1:
  4583.     {
  4584.       /* Set the DMA compare callbacks */
  4585.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4586.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4587.  
  4588.       /* Set the DMA error callback */
  4589.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  4590.  
  4591.       /* Enable the DMA channel */
  4592.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
  4593.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4594.       {
  4595.         /* Return error status */
  4596.         return HAL_ERROR;
  4597.       }
  4598.       break;
  4599.     }
  4600.     case TIM_DMA_CC2:
  4601.     {
  4602.       /* Set the DMA compare callbacks */
  4603.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4604.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4605.  
  4606.       /* Set the DMA error callback */
  4607.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  4608.  
  4609.       /* Enable the DMA channel */
  4610.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
  4611.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4612.       {
  4613.         /* Return error status */
  4614.         return HAL_ERROR;
  4615.       }
  4616.       break;
  4617.     }
  4618.     case TIM_DMA_CC3:
  4619.     {
  4620.       /* Set the DMA compare callbacks */
  4621.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4622.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4623.  
  4624.       /* Set the DMA error callback */
  4625.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  4626.  
  4627.       /* Enable the DMA channel */
  4628.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
  4629.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4630.       {
  4631.         /* Return error status */
  4632.         return HAL_ERROR;
  4633.       }
  4634.       break;
  4635.     }
  4636.     case TIM_DMA_CC4:
  4637.     {
  4638.       /* Set the DMA compare callbacks */
  4639.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4640.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4641.  
  4642.       /* Set the DMA error callback */
  4643.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  4644.  
  4645.       /* Enable the DMA channel */
  4646.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
  4647.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4648.       {
  4649.         /* Return error status */
  4650.         return HAL_ERROR;
  4651.       }
  4652.       break;
  4653.     }
  4654.     case TIM_DMA_COM:
  4655.     {
  4656.       /* Set the DMA commutation callbacks */
  4657.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
  4658.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
  4659.  
  4660.       /* Set the DMA error callback */
  4661.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
  4662.  
  4663.       /* Enable the DMA channel */
  4664.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
  4665.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4666.       {
  4667.         /* Return error status */
  4668.         return HAL_ERROR;
  4669.       }
  4670.       break;
  4671.     }
  4672.     case TIM_DMA_TRIGGER:
  4673.     {
  4674.       /* Set the DMA trigger callbacks */
  4675.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
  4676.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
  4677.  
  4678.       /* Set the DMA error callback */
  4679.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
  4680.  
  4681.       /* Enable the DMA channel */
  4682.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
  4683.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4684.       {
  4685.         /* Return error status */
  4686.         return HAL_ERROR;
  4687.       }
  4688.       break;
  4689.     }
  4690.     default:
  4691.       status = HAL_ERROR;
  4692.       break;
  4693.   }
  4694.  
  4695.   if (status == HAL_OK)
  4696.   {
  4697.     /* Configure the DMA Burst Mode */
  4698.     htim->Instance->DCR = (BurstBaseAddress | BurstLength);
  4699.     /* Enable the TIM DMA Request */
  4700.     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
  4701.   }
  4702.  
  4703.   /* Return function status */
  4704.   return status;
  4705. }
  4706.  
  4707. /**
  4708.   * @brief  Stops the TIM DMA Burst mode
  4709.   * @param  htim TIM handle
  4710.   * @param  BurstRequestSrc TIM DMA Request sources to disable
  4711.   * @retval HAL status
  4712.   */
  4713. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
  4714. {
  4715.   HAL_StatusTypeDef status = HAL_OK;
  4716.  
  4717.   /* Check the parameters */
  4718.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4719.  
  4720.   /* Abort the DMA transfer (at least disable the DMA channel) */
  4721.   switch (BurstRequestSrc)
  4722.   {
  4723.     case TIM_DMA_UPDATE:
  4724.     {
  4725.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  4726.       break;
  4727.     }
  4728.     case TIM_DMA_CC1:
  4729.     {
  4730.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  4731.       break;
  4732.     }
  4733.     case TIM_DMA_CC2:
  4734.     {
  4735.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  4736.       break;
  4737.     }
  4738.     case TIM_DMA_CC3:
  4739.     {
  4740.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  4741.       break;
  4742.     }
  4743.     case TIM_DMA_CC4:
  4744.     {
  4745.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  4746.       break;
  4747.     }
  4748.     case TIM_DMA_COM:
  4749.     {
  4750.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
  4751.       break;
  4752.     }
  4753.     case TIM_DMA_TRIGGER:
  4754.     {
  4755.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
  4756.       break;
  4757.     }
  4758.     default:
  4759.       status = HAL_ERROR;
  4760.       break;
  4761.   }
  4762.  
  4763.   if (status == HAL_OK)
  4764.   {
  4765.     /* Disable the TIM Update DMA request */
  4766.     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
  4767.  
  4768.     /* Change the DMA burst operation state */
  4769.     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  4770.   }
  4771.  
  4772.   /* Return function status */
  4773.   return status;
  4774. }
  4775.  
  4776. /**
  4777.   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
  4778.   * @param  htim TIM handle
  4779.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
  4780.   *         This parameter can be one of the following values:
  4781.   *            @arg TIM_DMABASE_CR1
  4782.   *            @arg TIM_DMABASE_CR2
  4783.   *            @arg TIM_DMABASE_SMCR
  4784.   *            @arg TIM_DMABASE_DIER
  4785.   *            @arg TIM_DMABASE_SR
  4786.   *            @arg TIM_DMABASE_EGR
  4787.   *            @arg TIM_DMABASE_CCMR1
  4788.   *            @arg TIM_DMABASE_CCMR2
  4789.   *            @arg TIM_DMABASE_CCER
  4790.   *            @arg TIM_DMABASE_CNT
  4791.   *            @arg TIM_DMABASE_PSC
  4792.   *            @arg TIM_DMABASE_ARR
  4793.   *            @arg TIM_DMABASE_RCR
  4794.   *            @arg TIM_DMABASE_CCR1
  4795.   *            @arg TIM_DMABASE_CCR2
  4796.   *            @arg TIM_DMABASE_CCR3
  4797.   *            @arg TIM_DMABASE_CCR4
  4798.   *            @arg TIM_DMABASE_BDTR
  4799.   * @param  BurstRequestSrc TIM DMA Request sources
  4800.   *         This parameter can be one of the following values:
  4801.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4802.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4803.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4804.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4805.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4806.   *            @arg TIM_DMA_COM: TIM Commutation DMA source
  4807.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4808.   * @param  BurstBuffer The Buffer address.
  4809.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4810.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4811.   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
  4812.   * @retval HAL status
  4813.   */
  4814. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4815.                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
  4816. {
  4817.   HAL_StatusTypeDef status;
  4818.  
  4819.   status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
  4820.                                            ((BurstLength) >> 8U) + 1U);
  4821.  
  4822.  
  4823.   return status;
  4824. }
  4825.  
  4826. /**
  4827.   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
  4828.   * @param  htim TIM handle
  4829.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
  4830.   *         This parameter can be one of the following values:
  4831.   *            @arg TIM_DMABASE_CR1
  4832.   *            @arg TIM_DMABASE_CR2
  4833.   *            @arg TIM_DMABASE_SMCR
  4834.   *            @arg TIM_DMABASE_DIER
  4835.   *            @arg TIM_DMABASE_SR
  4836.   *            @arg TIM_DMABASE_EGR
  4837.   *            @arg TIM_DMABASE_CCMR1
  4838.   *            @arg TIM_DMABASE_CCMR2
  4839.   *            @arg TIM_DMABASE_CCER
  4840.   *            @arg TIM_DMABASE_CNT
  4841.   *            @arg TIM_DMABASE_PSC
  4842.   *            @arg TIM_DMABASE_ARR
  4843.   *            @arg TIM_DMABASE_RCR
  4844.   *            @arg TIM_DMABASE_CCR1
  4845.   *            @arg TIM_DMABASE_CCR2
  4846.   *            @arg TIM_DMABASE_CCR3
  4847.   *            @arg TIM_DMABASE_CCR4
  4848.   *            @arg TIM_DMABASE_BDTR
  4849.   * @param  BurstRequestSrc TIM DMA Request sources
  4850.   *         This parameter can be one of the following values:
  4851.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4852.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4853.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4854.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4855.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4856.   *            @arg TIM_DMA_COM: TIM Commutation DMA source
  4857.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4858.   * @param  BurstBuffer The Buffer address.
  4859.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4860.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4861.   * @param  DataLength Data length. This parameter can be one value
  4862.   *         between 1 and 0xFFFF.
  4863.   * @retval HAL status
  4864.   */
  4865. HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4866.                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
  4867.                                                   uint32_t  BurstLength, uint32_t  DataLength)
  4868. {
  4869.   HAL_StatusTypeDef status = HAL_OK;
  4870.  
  4871.   /* Check the parameters */
  4872.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  4873.   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
  4874.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4875.   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
  4876.   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
  4877.  
  4878.   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
  4879.   {
  4880.     return HAL_BUSY;
  4881.   }
  4882.   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
  4883.   {
  4884.     if ((BurstBuffer == NULL) && (BurstLength > 0U))
  4885.     {
  4886.       return HAL_ERROR;
  4887.     }
  4888.     else
  4889.     {
  4890.       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
  4891.     }
  4892.   }
  4893.   else
  4894.   {
  4895.     /* nothing to do */
  4896.   }
  4897.   switch (BurstRequestSrc)
  4898.   {
  4899.     case TIM_DMA_UPDATE:
  4900.     {
  4901.       /* Set the DMA Period elapsed callbacks */
  4902.       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  4903.       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  4904.  
  4905.       /* Set the DMA error callback */
  4906.       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  4907.  
  4908.       /* Enable the DMA channel */
  4909.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4910.                            DataLength) != HAL_OK)
  4911.       {
  4912.         /* Return error status */
  4913.         return HAL_ERROR;
  4914.       }
  4915.       break;
  4916.     }
  4917.     case TIM_DMA_CC1:
  4918.     {
  4919.       /* Set the DMA capture callbacks */
  4920.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  4921.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4922.  
  4923.       /* Set the DMA error callback */
  4924.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  4925.  
  4926.       /* Enable the DMA channel */
  4927.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4928.                            DataLength) != HAL_OK)
  4929.       {
  4930.         /* Return error status */
  4931.         return HAL_ERROR;
  4932.       }
  4933.       break;
  4934.     }
  4935.     case TIM_DMA_CC2:
  4936.     {
  4937.       /* Set the DMA capture callbacks */
  4938.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  4939.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4940.  
  4941.       /* Set the DMA error callback */
  4942.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  4943.  
  4944.       /* Enable the DMA channel */
  4945.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4946.                            DataLength) != HAL_OK)
  4947.       {
  4948.         /* Return error status */
  4949.         return HAL_ERROR;
  4950.       }
  4951.       break;
  4952.     }
  4953.     case TIM_DMA_CC3:
  4954.     {
  4955.       /* Set the DMA capture callbacks */
  4956.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
  4957.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4958.  
  4959.       /* Set the DMA error callback */
  4960.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  4961.  
  4962.       /* Enable the DMA channel */
  4963.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4964.                            DataLength) != HAL_OK)
  4965.       {
  4966.         /* Return error status */
  4967.         return HAL_ERROR;
  4968.       }
  4969.       break;
  4970.     }
  4971.     case TIM_DMA_CC4:
  4972.     {
  4973.       /* Set the DMA capture callbacks */
  4974.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
  4975.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4976.  
  4977.       /* Set the DMA error callback */
  4978.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  4979.  
  4980.       /* Enable the DMA channel */
  4981.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4982.                            DataLength) != HAL_OK)
  4983.       {
  4984.         /* Return error status */
  4985.         return HAL_ERROR;
  4986.       }
  4987.       break;
  4988.     }
  4989.     case TIM_DMA_COM:
  4990.     {
  4991.       /* Set the DMA commutation callbacks */
  4992.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
  4993.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
  4994.  
  4995.       /* Set the DMA error callback */
  4996.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
  4997.  
  4998.       /* Enable the DMA channel */
  4999.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  5000.                            DataLength) != HAL_OK)
  5001.       {
  5002.         /* Return error status */
  5003.         return HAL_ERROR;
  5004.       }
  5005.       break;
  5006.     }
  5007.     case TIM_DMA_TRIGGER:
  5008.     {
  5009.       /* Set the DMA trigger callbacks */
  5010.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
  5011.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
  5012.  
  5013.       /* Set the DMA error callback */
  5014.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
  5015.  
  5016.       /* Enable the DMA channel */
  5017.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  5018.                            DataLength) != HAL_OK)
  5019.       {
  5020.         /* Return error status */
  5021.         return HAL_ERROR;
  5022.       }
  5023.       break;
  5024.     }
  5025.     default:
  5026.       status = HAL_ERROR;
  5027.       break;
  5028.   }
  5029.  
  5030.   if (status == HAL_OK)
  5031.   {
  5032.     /* Configure the DMA Burst Mode */
  5033.     htim->Instance->DCR = (BurstBaseAddress | BurstLength);
  5034.  
  5035.     /* Enable the TIM DMA Request */
  5036.     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
  5037.   }
  5038.  
  5039.   /* Return function status */
  5040.   return status;
  5041. }
  5042.  
  5043. /**
  5044.   * @brief  Stop the DMA burst reading
  5045.   * @param  htim TIM handle
  5046.   * @param  BurstRequestSrc TIM DMA Request sources to disable.
  5047.   * @retval HAL status
  5048.   */
  5049. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
  5050. {
  5051.   HAL_StatusTypeDef status = HAL_OK;
  5052.  
  5053.   /* Check the parameters */
  5054.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  5055.  
  5056.   /* Abort the DMA transfer (at least disable the DMA channel) */
  5057.   switch (BurstRequestSrc)
  5058.   {
  5059.     case TIM_DMA_UPDATE:
  5060.     {
  5061.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  5062.       break;
  5063.     }
  5064.     case TIM_DMA_CC1:
  5065.     {
  5066.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  5067.       break;
  5068.     }
  5069.     case TIM_DMA_CC2:
  5070.     {
  5071.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  5072.       break;
  5073.     }
  5074.     case TIM_DMA_CC3:
  5075.     {
  5076.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  5077.       break;
  5078.     }
  5079.     case TIM_DMA_CC4:
  5080.     {
  5081.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  5082.       break;
  5083.     }
  5084.     case TIM_DMA_COM:
  5085.     {
  5086.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
  5087.       break;
  5088.     }
  5089.     case TIM_DMA_TRIGGER:
  5090.     {
  5091.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
  5092.       break;
  5093.     }
  5094.     default:
  5095.       status = HAL_ERROR;
  5096.       break;
  5097.   }
  5098.  
  5099.   if (status == HAL_OK)
  5100.   {
  5101.     /* Disable the TIM Update DMA request */
  5102.     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
  5103.  
  5104.     /* Change the DMA burst operation state */
  5105.     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  5106.   }
  5107.  
  5108.   /* Return function status */
  5109.   return status;
  5110. }
  5111.  
  5112. /**
  5113.   * @brief  Generate a software event
  5114.   * @param  htim TIM handle
  5115.   * @param  EventSource specifies the event source.
  5116.   *          This parameter can be one of the following values:
  5117.   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
  5118.   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
  5119.   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
  5120.   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
  5121.   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
  5122.   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
  5123.   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
  5124.   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
  5125.   * @note   Basic timers can only generate an update event.
  5126.   * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
  5127.   * @note   TIM_EVENTSOURCE_BREAK are relevant only for timer instances
  5128.   *         supporting a break input.
  5129.   * @retval HAL status
  5130.   */
  5131.  
  5132. HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
  5133. {
  5134.   /* Check the parameters */
  5135.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  5136.   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
  5137.  
  5138.   /* Process Locked */
  5139.   __HAL_LOCK(htim);
  5140.  
  5141.   /* Change the TIM state */
  5142.   htim->State = HAL_TIM_STATE_BUSY;
  5143.  
  5144.   /* Set the event sources */
  5145.   htim->Instance->EGR = EventSource;
  5146.  
  5147.   /* Change the TIM state */
  5148.   htim->State = HAL_TIM_STATE_READY;
  5149.  
  5150.   __HAL_UNLOCK(htim);
  5151.  
  5152.   /* Return function status */
  5153.   return HAL_OK;
  5154. }
  5155.  
  5156. /**
  5157.   * @brief  Configures the OCRef clear feature
  5158.   * @param  htim TIM handle
  5159.   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
  5160.   *         contains the OCREF clear feature and parameters for the TIM peripheral.
  5161.   * @param  Channel specifies the TIM Channel
  5162.   *          This parameter can be one of the following values:
  5163.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  5164.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  5165.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  5166.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  5167.   * @retval HAL status
  5168.   */
  5169. HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
  5170.                                            const TIM_ClearInputConfigTypeDef *sClearInputConfig,
  5171.                                            uint32_t Channel)
  5172. {
  5173.   HAL_StatusTypeDef status = HAL_OK;
  5174.  
  5175.   /* Check the parameters */
  5176.   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
  5177.   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
  5178.  
  5179.   /* Process Locked */
  5180.   __HAL_LOCK(htim);
  5181.  
  5182.   htim->State = HAL_TIM_STATE_BUSY;
  5183.  
  5184.   switch (sClearInputConfig->ClearInputSource)
  5185.   {
  5186.     case TIM_CLEARINPUTSOURCE_NONE:
  5187.     {
  5188.       /* Clear the OCREF clear selection bit and the the ETR Bits */
  5189.       CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
  5190.       break;
  5191.     }
  5192.  
  5193.     case TIM_CLEARINPUTSOURCE_ETR:
  5194.     {
  5195.       /* Check the parameters */
  5196.       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
  5197.       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
  5198.       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
  5199.  
  5200.       /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
  5201.       if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
  5202.       {
  5203.         htim->State = HAL_TIM_STATE_READY;
  5204.         __HAL_UNLOCK(htim);
  5205.         return HAL_ERROR;
  5206.       }
  5207.  
  5208.       TIM_ETR_SetConfig(htim->Instance,
  5209.                         sClearInputConfig->ClearInputPrescaler,
  5210.                         sClearInputConfig->ClearInputPolarity,
  5211.                         sClearInputConfig->ClearInputFilter);
  5212.       break;
  5213.     }
  5214.  
  5215.     default:
  5216.       status = HAL_ERROR;
  5217.       break;
  5218.   }
  5219.  
  5220.   if (status == HAL_OK)
  5221.   {
  5222.     switch (Channel)
  5223.     {
  5224.       case TIM_CHANNEL_1:
  5225.       {
  5226.         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  5227.         {
  5228.           /* Enable the OCREF clear feature for Channel 1 */
  5229.           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
  5230.         }
  5231.         else
  5232.         {
  5233.           /* Disable the OCREF clear feature for Channel 1 */
  5234.           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
  5235.         }
  5236.         break;
  5237.       }
  5238.       case TIM_CHANNEL_2:
  5239.       {
  5240.         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  5241.         {
  5242.           /* Enable the OCREF clear feature for Channel 2 */
  5243.           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
  5244.         }
  5245.         else
  5246.         {
  5247.           /* Disable the OCREF clear feature for Channel 2 */
  5248.           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
  5249.         }
  5250.         break;
  5251.       }
  5252.       case TIM_CHANNEL_3:
  5253.       {
  5254.         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  5255.         {
  5256.           /* Enable the OCREF clear feature for Channel 3 */
  5257.           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
  5258.         }
  5259.         else
  5260.         {
  5261.           /* Disable the OCREF clear feature for Channel 3 */
  5262.           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
  5263.         }
  5264.         break;
  5265.       }
  5266.       case TIM_CHANNEL_4:
  5267.       {
  5268.         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  5269.         {
  5270.           /* Enable the OCREF clear feature for Channel 4 */
  5271.           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
  5272.         }
  5273.         else
  5274.         {
  5275.           /* Disable the OCREF clear feature for Channel 4 */
  5276.           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
  5277.         }
  5278.         break;
  5279.       }
  5280.       default:
  5281.         break;
  5282.     }
  5283.   }
  5284.  
  5285.   htim->State = HAL_TIM_STATE_READY;
  5286.  
  5287.   __HAL_UNLOCK(htim);
  5288.  
  5289.   return status;
  5290. }
  5291.  
  5292. /**
  5293.   * @brief   Configures the clock source to be used
  5294.   * @param  htim TIM handle
  5295.   * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
  5296.   *         contains the clock source information for the TIM peripheral.
  5297.   * @retval HAL status
  5298.   */
  5299. HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
  5300. {
  5301.   HAL_StatusTypeDef status = HAL_OK;
  5302.   uint32_t tmpsmcr;
  5303.  
  5304.   /* Process Locked */
  5305.   __HAL_LOCK(htim);
  5306.  
  5307.   htim->State = HAL_TIM_STATE_BUSY;
  5308.  
  5309.   /* Check the parameters */
  5310.   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
  5311.  
  5312.   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
  5313.   tmpsmcr = htim->Instance->SMCR;
  5314.   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
  5315.   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  5316.   htim->Instance->SMCR = tmpsmcr;
  5317.  
  5318.   switch (sClockSourceConfig->ClockSource)
  5319.   {
  5320.     case TIM_CLOCKSOURCE_INTERNAL:
  5321.     {
  5322.       assert_param(IS_TIM_INSTANCE(htim->Instance));
  5323.       break;
  5324.     }
  5325.  
  5326.     case TIM_CLOCKSOURCE_ETRMODE1:
  5327.     {
  5328.       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
  5329.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
  5330.  
  5331.       /* Check ETR input conditioning related parameters */
  5332.       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
  5333.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5334.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5335.  
  5336.       /* Configure the ETR Clock source */
  5337.       TIM_ETR_SetConfig(htim->Instance,
  5338.                         sClockSourceConfig->ClockPrescaler,
  5339.                         sClockSourceConfig->ClockPolarity,
  5340.                         sClockSourceConfig->ClockFilter);
  5341.  
  5342.       /* Select the External clock mode1 and the ETRF trigger */
  5343.       tmpsmcr = htim->Instance->SMCR;
  5344.       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
  5345.       /* Write to TIMx SMCR */
  5346.       htim->Instance->SMCR = tmpsmcr;
  5347.       break;
  5348.     }
  5349.  
  5350.     case TIM_CLOCKSOURCE_ETRMODE2:
  5351.     {
  5352.       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
  5353.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
  5354.  
  5355.       /* Check ETR input conditioning related parameters */
  5356.       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
  5357.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5358.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5359.  
  5360.       /* Configure the ETR Clock source */
  5361.       TIM_ETR_SetConfig(htim->Instance,
  5362.                         sClockSourceConfig->ClockPrescaler,
  5363.                         sClockSourceConfig->ClockPolarity,
  5364.                         sClockSourceConfig->ClockFilter);
  5365.       /* Enable the External clock mode2 */
  5366.       htim->Instance->SMCR |= TIM_SMCR_ECE;
  5367.       break;
  5368.     }
  5369.  
  5370.     case TIM_CLOCKSOURCE_TI1:
  5371.     {
  5372.       /* Check whether or not the timer instance supports external clock mode 1 */
  5373.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  5374.  
  5375.       /* Check TI1 input conditioning related parameters */
  5376.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5377.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5378.  
  5379.       TIM_TI1_ConfigInputStage(htim->Instance,
  5380.                                sClockSourceConfig->ClockPolarity,
  5381.                                sClockSourceConfig->ClockFilter);
  5382.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
  5383.       break;
  5384.     }
  5385.  
  5386.     case TIM_CLOCKSOURCE_TI2:
  5387.     {
  5388.       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
  5389.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  5390.  
  5391.       /* Check TI2 input conditioning related parameters */
  5392.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5393.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5394.  
  5395.       TIM_TI2_ConfigInputStage(htim->Instance,
  5396.                                sClockSourceConfig->ClockPolarity,
  5397.                                sClockSourceConfig->ClockFilter);
  5398.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
  5399.       break;
  5400.     }
  5401.  
  5402.     case TIM_CLOCKSOURCE_TI1ED:
  5403.     {
  5404.       /* Check whether or not the timer instance supports external clock mode 1 */
  5405.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  5406.  
  5407.       /* Check TI1 input conditioning related parameters */
  5408.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5409.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5410.  
  5411.       TIM_TI1_ConfigInputStage(htim->Instance,
  5412.                                sClockSourceConfig->ClockPolarity,
  5413.                                sClockSourceConfig->ClockFilter);
  5414.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
  5415.       break;
  5416.     }
  5417.  
  5418.     case TIM_CLOCKSOURCE_ITR0:
  5419.     case TIM_CLOCKSOURCE_ITR1:
  5420.     case TIM_CLOCKSOURCE_ITR2:
  5421.     case TIM_CLOCKSOURCE_ITR3:
  5422.     {
  5423.       /* Check whether or not the timer instance supports internal trigger input */
  5424.       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
  5425.  
  5426.       TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
  5427.       break;
  5428.     }
  5429.  
  5430.     default:
  5431.       status = HAL_ERROR;
  5432.       break;
  5433.   }
  5434.   htim->State = HAL_TIM_STATE_READY;
  5435.  
  5436.   __HAL_UNLOCK(htim);
  5437.  
  5438.   return status;
  5439. }
  5440.  
  5441. /**
  5442.   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
  5443.   *         or a XOR combination between CH1_input, CH2_input & CH3_input
  5444.   * @param  htim TIM handle.
  5445.   * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
  5446.   *         output of a XOR gate.
  5447.   *          This parameter can be one of the following values:
  5448.   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  5449.   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
  5450.   *            pins are connected to the TI1 input (XOR combination)
  5451.   * @retval HAL status
  5452.   */
  5453. HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
  5454. {
  5455.   uint32_t tmpcr2;
  5456.  
  5457.   /* Check the parameters */
  5458.   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
  5459.   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
  5460.  
  5461.   /* Get the TIMx CR2 register value */
  5462.   tmpcr2 = htim->Instance->CR2;
  5463.  
  5464.   /* Reset the TI1 selection */
  5465.   tmpcr2 &= ~TIM_CR2_TI1S;
  5466.  
  5467.   /* Set the TI1 selection */
  5468.   tmpcr2 |= TI1_Selection;
  5469.  
  5470.   /* Write to TIMxCR2 */
  5471.   htim->Instance->CR2 = tmpcr2;
  5472.  
  5473.   return HAL_OK;
  5474. }
  5475.  
  5476. /**
  5477.   * @brief  Configures the TIM in Slave mode
  5478.   * @param  htim TIM handle.
  5479.   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
  5480.   *         contains the selected trigger (internal trigger input, filtered
  5481.   *         timer input or external trigger input) and the Slave mode
  5482.   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
  5483.   * @retval HAL status
  5484.   */
  5485. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
  5486. {
  5487.   /* Check the parameters */
  5488.   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
  5489.   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
  5490.   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
  5491.  
  5492.   __HAL_LOCK(htim);
  5493.  
  5494.   htim->State = HAL_TIM_STATE_BUSY;
  5495.  
  5496.   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
  5497.   {
  5498.     htim->State = HAL_TIM_STATE_READY;
  5499.     __HAL_UNLOCK(htim);
  5500.     return HAL_ERROR;
  5501.   }
  5502.  
  5503.   /* Disable Trigger Interrupt */
  5504.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
  5505.  
  5506.   /* Disable Trigger DMA request */
  5507.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
  5508.  
  5509.   htim->State = HAL_TIM_STATE_READY;
  5510.  
  5511.   __HAL_UNLOCK(htim);
  5512.  
  5513.   return HAL_OK;
  5514. }
  5515.  
  5516. /**
  5517.   * @brief  Configures the TIM in Slave mode in interrupt mode
  5518.   * @param  htim TIM handle.
  5519.   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
  5520.   *         contains the selected trigger (internal trigger input, filtered
  5521.   *         timer input or external trigger input) and the Slave mode
  5522.   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
  5523.   * @retval HAL status
  5524.   */
  5525. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
  5526.                                                 const TIM_SlaveConfigTypeDef *sSlaveConfig)
  5527. {
  5528.   /* Check the parameters */
  5529.   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
  5530.   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
  5531.   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
  5532.  
  5533.   __HAL_LOCK(htim);
  5534.  
  5535.   htim->State = HAL_TIM_STATE_BUSY;
  5536.  
  5537.   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
  5538.   {
  5539.     htim->State = HAL_TIM_STATE_READY;
  5540.     __HAL_UNLOCK(htim);
  5541.     return HAL_ERROR;
  5542.   }
  5543.  
  5544.   /* Enable Trigger Interrupt */
  5545.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
  5546.  
  5547.   /* Disable Trigger DMA request */
  5548.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
  5549.  
  5550.   htim->State = HAL_TIM_STATE_READY;
  5551.  
  5552.   __HAL_UNLOCK(htim);
  5553.  
  5554.   return HAL_OK;
  5555. }
  5556.  
  5557. /**
  5558.   * @brief  Read the captured value from Capture Compare unit
  5559.   * @param  htim TIM handle.
  5560.   * @param  Channel TIM Channels to be enabled
  5561.   *          This parameter can be one of the following values:
  5562.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  5563.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  5564.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  5565.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  5566.   * @retval Captured value
  5567.   */
  5568. uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
  5569. {
  5570.   uint32_t tmpreg = 0U;
  5571.  
  5572.   switch (Channel)
  5573.   {
  5574.     case TIM_CHANNEL_1:
  5575.     {
  5576.       /* Check the parameters */
  5577.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  5578.  
  5579.       /* Return the capture 1 value */
  5580.       tmpreg =  htim->Instance->CCR1;
  5581.  
  5582.       break;
  5583.     }
  5584.     case TIM_CHANNEL_2:
  5585.     {
  5586.       /* Check the parameters */
  5587.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  5588.  
  5589.       /* Return the capture 2 value */
  5590.       tmpreg =   htim->Instance->CCR2;
  5591.  
  5592.       break;
  5593.     }
  5594.  
  5595.     case TIM_CHANNEL_3:
  5596.     {
  5597.       /* Check the parameters */
  5598.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  5599.  
  5600.       /* Return the capture 3 value */
  5601.       tmpreg =   htim->Instance->CCR3;
  5602.  
  5603.       break;
  5604.     }
  5605.  
  5606.     case TIM_CHANNEL_4:
  5607.     {
  5608.       /* Check the parameters */
  5609.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  5610.  
  5611.       /* Return the capture 4 value */
  5612.       tmpreg =   htim->Instance->CCR4;
  5613.  
  5614.       break;
  5615.     }
  5616.  
  5617.     default:
  5618.       break;
  5619.   }
  5620.  
  5621.   return tmpreg;
  5622. }
  5623.  
  5624. /**
  5625.   * @}
  5626.   */
  5627.  
  5628. /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
  5629.   *  @brief    TIM Callbacks functions
  5630.   *
  5631. @verbatim
  5632.   ==============================================================================
  5633.                         ##### TIM Callbacks functions #####
  5634.   ==============================================================================
  5635.  [..]
  5636.    This section provides TIM callback functions:
  5637.    (+) TIM Period elapsed callback
  5638.    (+) TIM Output Compare callback
  5639.    (+) TIM Input capture callback
  5640.    (+) TIM Trigger callback
  5641.    (+) TIM Error callback
  5642.  
  5643. @endverbatim
  5644.   * @{
  5645.   */
  5646.  
  5647. /**
  5648.   * @brief  Period elapsed callback in non-blocking mode
  5649.   * @param  htim TIM handle
  5650.   * @retval None
  5651.   */
  5652. __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
  5653. {
  5654.   /* Prevent unused argument(s) compilation warning */
  5655.   UNUSED(htim);
  5656.  
  5657.   /* NOTE : This function should not be modified, when the callback is needed,
  5658.             the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
  5659.    */
  5660. }
  5661.  
  5662. /**
  5663.   * @brief  Period elapsed half complete callback in non-blocking mode
  5664.   * @param  htim TIM handle
  5665.   * @retval None
  5666.   */
  5667. __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
  5668. {
  5669.   /* Prevent unused argument(s) compilation warning */
  5670.   UNUSED(htim);
  5671.  
  5672.   /* NOTE : This function should not be modified, when the callback is needed,
  5673.             the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
  5674.    */
  5675. }
  5676.  
  5677. /**
  5678.   * @brief  Output Compare callback in non-blocking mode
  5679.   * @param  htim TIM OC handle
  5680.   * @retval None
  5681.   */
  5682. __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
  5683. {
  5684.   /* Prevent unused argument(s) compilation warning */
  5685.   UNUSED(htim);
  5686.  
  5687.   /* NOTE : This function should not be modified, when the callback is needed,
  5688.             the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
  5689.    */
  5690. }
  5691.  
  5692. /**
  5693.   * @brief  Input Capture callback in non-blocking mode
  5694.   * @param  htim TIM IC handle
  5695.   * @retval None
  5696.   */
  5697. __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
  5698. {
  5699.   /* Prevent unused argument(s) compilation warning */
  5700.   UNUSED(htim);
  5701.  
  5702.   /* NOTE : This function should not be modified, when the callback is needed,
  5703.             the HAL_TIM_IC_CaptureCallback could be implemented in the user file
  5704.    */
  5705. }
  5706.  
  5707. /**
  5708.   * @brief  Input Capture half complete callback in non-blocking mode
  5709.   * @param  htim TIM IC handle
  5710.   * @retval None
  5711.   */
  5712. __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
  5713. {
  5714.   /* Prevent unused argument(s) compilation warning */
  5715.   UNUSED(htim);
  5716.  
  5717.   /* NOTE : This function should not be modified, when the callback is needed,
  5718.             the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
  5719.    */
  5720. }
  5721.  
  5722. /**
  5723.   * @brief  PWM Pulse finished callback in non-blocking mode
  5724.   * @param  htim TIM handle
  5725.   * @retval None
  5726.   */
  5727. __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
  5728. {
  5729.   /* Prevent unused argument(s) compilation warning */
  5730.   UNUSED(htim);
  5731.  
  5732.   /* NOTE : This function should not be modified, when the callback is needed,
  5733.             the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
  5734.    */
  5735. }
  5736.  
  5737. /**
  5738.   * @brief  PWM Pulse finished half complete callback in non-blocking mode
  5739.   * @param  htim TIM handle
  5740.   * @retval None
  5741.   */
  5742. __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
  5743. {
  5744.   /* Prevent unused argument(s) compilation warning */
  5745.   UNUSED(htim);
  5746.  
  5747.   /* NOTE : This function should not be modified, when the callback is needed,
  5748.             the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
  5749.    */
  5750. }
  5751.  
  5752. /**
  5753.   * @brief  Hall Trigger detection callback in non-blocking mode
  5754.   * @param  htim TIM handle
  5755.   * @retval None
  5756.   */
  5757. __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
  5758. {
  5759.   /* Prevent unused argument(s) compilation warning */
  5760.   UNUSED(htim);
  5761.  
  5762.   /* NOTE : This function should not be modified, when the callback is needed,
  5763.             the HAL_TIM_TriggerCallback could be implemented in the user file
  5764.    */
  5765. }
  5766.  
  5767. /**
  5768.   * @brief  Hall Trigger detection half complete callback in non-blocking mode
  5769.   * @param  htim TIM handle
  5770.   * @retval None
  5771.   */
  5772. __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
  5773. {
  5774.   /* Prevent unused argument(s) compilation warning */
  5775.   UNUSED(htim);
  5776.  
  5777.   /* NOTE : This function should not be modified, when the callback is needed,
  5778.             the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
  5779.    */
  5780. }
  5781.  
  5782. /**
  5783.   * @brief  Timer error callback in non-blocking mode
  5784.   * @param  htim TIM handle
  5785.   * @retval None
  5786.   */
  5787. __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
  5788. {
  5789.   /* Prevent unused argument(s) compilation warning */
  5790.   UNUSED(htim);
  5791.  
  5792.   /* NOTE : This function should not be modified, when the callback is needed,
  5793.             the HAL_TIM_ErrorCallback could be implemented in the user file
  5794.    */
  5795. }
  5796.  
  5797. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  5798. /**
  5799.   * @brief  Register a User TIM callback to be used instead of the weak predefined callback
  5800.   * @param htim tim handle
  5801.   * @param CallbackID ID of the callback to be registered
  5802.   *        This parameter can be one of the following values:
  5803.   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  5804.   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  5805.   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  5806.   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  5807.   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  5808.   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  5809.   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  5810.   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  5811.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  5812.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  5813.   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  5814.   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  5815.   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
  5816.   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
  5817.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  5818.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  5819.   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  5820.   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  5821.   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  5822.   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  5823.   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  5824.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  5825.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  5826.   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
  5827.   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
  5828.   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
  5829.   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
  5830.   *          @param pCallback pointer to the callback function
  5831.   *          @retval status
  5832.   */
  5833. HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
  5834.                                            pTIM_CallbackTypeDef pCallback)
  5835. {
  5836.   HAL_StatusTypeDef status = HAL_OK;
  5837.  
  5838.   if (pCallback == NULL)
  5839.   {
  5840.     return HAL_ERROR;
  5841.   }
  5842.  
  5843.   if (htim->State == HAL_TIM_STATE_READY)
  5844.   {
  5845.     switch (CallbackID)
  5846.     {
  5847.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5848.         htim->Base_MspInitCallback                 = pCallback;
  5849.         break;
  5850.  
  5851.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5852.         htim->Base_MspDeInitCallback               = pCallback;
  5853.         break;
  5854.  
  5855.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5856.         htim->IC_MspInitCallback                   = pCallback;
  5857.         break;
  5858.  
  5859.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5860.         htim->IC_MspDeInitCallback                 = pCallback;
  5861.         break;
  5862.  
  5863.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5864.         htim->OC_MspInitCallback                   = pCallback;
  5865.         break;
  5866.  
  5867.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5868.         htim->OC_MspDeInitCallback                 = pCallback;
  5869.         break;
  5870.  
  5871.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5872.         htim->PWM_MspInitCallback                  = pCallback;
  5873.         break;
  5874.  
  5875.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  5876.         htim->PWM_MspDeInitCallback                = pCallback;
  5877.         break;
  5878.  
  5879.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  5880.         htim->OnePulse_MspInitCallback             = pCallback;
  5881.         break;
  5882.  
  5883.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  5884.         htim->OnePulse_MspDeInitCallback           = pCallback;
  5885.         break;
  5886.  
  5887.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  5888.         htim->Encoder_MspInitCallback              = pCallback;
  5889.         break;
  5890.  
  5891.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  5892.         htim->Encoder_MspDeInitCallback            = pCallback;
  5893.         break;
  5894.  
  5895.       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
  5896.         htim->HallSensor_MspInitCallback           = pCallback;
  5897.         break;
  5898.  
  5899.       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
  5900.         htim->HallSensor_MspDeInitCallback         = pCallback;
  5901.         break;
  5902.  
  5903.       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
  5904.         htim->PeriodElapsedCallback                = pCallback;
  5905.         break;
  5906.  
  5907.       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
  5908.         htim->PeriodElapsedHalfCpltCallback        = pCallback;
  5909.         break;
  5910.  
  5911.       case HAL_TIM_TRIGGER_CB_ID :
  5912.         htim->TriggerCallback                      = pCallback;
  5913.         break;
  5914.  
  5915.       case HAL_TIM_TRIGGER_HALF_CB_ID :
  5916.         htim->TriggerHalfCpltCallback              = pCallback;
  5917.         break;
  5918.  
  5919.       case HAL_TIM_IC_CAPTURE_CB_ID :
  5920.         htim->IC_CaptureCallback                   = pCallback;
  5921.         break;
  5922.  
  5923.       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
  5924.         htim->IC_CaptureHalfCpltCallback           = pCallback;
  5925.         break;
  5926.  
  5927.       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
  5928.         htim->OC_DelayElapsedCallback              = pCallback;
  5929.         break;
  5930.  
  5931.       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
  5932.         htim->PWM_PulseFinishedCallback            = pCallback;
  5933.         break;
  5934.  
  5935.       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
  5936.         htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
  5937.         break;
  5938.  
  5939.       case HAL_TIM_ERROR_CB_ID :
  5940.         htim->ErrorCallback                        = pCallback;
  5941.         break;
  5942.  
  5943.       case HAL_TIM_COMMUTATION_CB_ID :
  5944.         htim->CommutationCallback                  = pCallback;
  5945.         break;
  5946.  
  5947.       case HAL_TIM_COMMUTATION_HALF_CB_ID :
  5948.         htim->CommutationHalfCpltCallback          = pCallback;
  5949.         break;
  5950.  
  5951.       case HAL_TIM_BREAK_CB_ID :
  5952.         htim->BreakCallback                        = pCallback;
  5953.         break;
  5954.  
  5955.       default :
  5956.         /* Return error status */
  5957.         status = HAL_ERROR;
  5958.         break;
  5959.     }
  5960.   }
  5961.   else if (htim->State == HAL_TIM_STATE_RESET)
  5962.   {
  5963.     switch (CallbackID)
  5964.     {
  5965.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5966.         htim->Base_MspInitCallback         = pCallback;
  5967.         break;
  5968.  
  5969.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5970.         htim->Base_MspDeInitCallback       = pCallback;
  5971.         break;
  5972.  
  5973.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5974.         htim->IC_MspInitCallback           = pCallback;
  5975.         break;
  5976.  
  5977.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5978.         htim->IC_MspDeInitCallback         = pCallback;
  5979.         break;
  5980.  
  5981.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5982.         htim->OC_MspInitCallback           = pCallback;
  5983.         break;
  5984.  
  5985.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5986.         htim->OC_MspDeInitCallback         = pCallback;
  5987.         break;
  5988.  
  5989.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5990.         htim->PWM_MspInitCallback          = pCallback;
  5991.         break;
  5992.  
  5993.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  5994.         htim->PWM_MspDeInitCallback        = pCallback;
  5995.         break;
  5996.  
  5997.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  5998.         htim->OnePulse_MspInitCallback     = pCallback;
  5999.         break;
  6000.  
  6001.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  6002.         htim->OnePulse_MspDeInitCallback   = pCallback;
  6003.         break;
  6004.  
  6005.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  6006.         htim->Encoder_MspInitCallback      = pCallback;
  6007.         break;
  6008.  
  6009.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  6010.         htim->Encoder_MspDeInitCallback    = pCallback;
  6011.         break;
  6012.  
  6013.       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
  6014.         htim->HallSensor_MspInitCallback   = pCallback;
  6015.         break;
  6016.  
  6017.       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
  6018.         htim->HallSensor_MspDeInitCallback = pCallback;
  6019.         break;
  6020.  
  6021.       default :
  6022.         /* Return error status */
  6023.         status = HAL_ERROR;
  6024.         break;
  6025.     }
  6026.   }
  6027.   else
  6028.   {
  6029.     /* Return error status */
  6030.     status = HAL_ERROR;
  6031.   }
  6032.  
  6033.   return status;
  6034. }
  6035.  
  6036. /**
  6037.   * @brief  Unregister a TIM callback
  6038.   *         TIM callback is redirected to the weak predefined callback
  6039.   * @param htim tim handle
  6040.   * @param CallbackID ID of the callback to be unregistered
  6041.   *        This parameter can be one of the following values:
  6042.   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  6043.   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  6044.   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  6045.   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  6046.   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  6047.   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  6048.   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  6049.   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  6050.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  6051.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  6052.   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  6053.   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  6054.   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
  6055.   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
  6056.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  6057.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  6058.   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  6059.   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  6060.   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  6061.   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  6062.   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  6063.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  6064.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  6065.   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
  6066.   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
  6067.   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
  6068.   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
  6069.   *          @retval status
  6070.   */
  6071. HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
  6072. {
  6073.   HAL_StatusTypeDef status = HAL_OK;
  6074.  
  6075.   if (htim->State == HAL_TIM_STATE_READY)
  6076.   {
  6077.     switch (CallbackID)
  6078.     {
  6079.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  6080.         /* Legacy weak Base MspInit Callback */
  6081.         htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
  6082.         break;
  6083.  
  6084.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  6085.         /* Legacy weak Base Msp DeInit Callback */
  6086.         htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
  6087.         break;
  6088.  
  6089.       case HAL_TIM_IC_MSPINIT_CB_ID :
  6090.         /* Legacy weak IC Msp Init Callback */
  6091.         htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
  6092.         break;
  6093.  
  6094.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  6095.         /* Legacy weak IC Msp DeInit Callback */
  6096.         htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
  6097.         break;
  6098.  
  6099.       case HAL_TIM_OC_MSPINIT_CB_ID :
  6100.         /* Legacy weak OC Msp Init Callback */
  6101.         htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
  6102.         break;
  6103.  
  6104.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  6105.         /* Legacy weak OC Msp DeInit Callback */
  6106.         htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
  6107.         break;
  6108.  
  6109.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  6110.         /* Legacy weak PWM Msp Init Callback */
  6111.         htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
  6112.         break;
  6113.  
  6114.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  6115.         /* Legacy weak PWM Msp DeInit Callback */
  6116.         htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
  6117.         break;
  6118.  
  6119.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  6120.         /* Legacy weak One Pulse Msp Init Callback */
  6121.         htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
  6122.         break;
  6123.  
  6124.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  6125.         /* Legacy weak One Pulse Msp DeInit Callback */
  6126.         htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
  6127.         break;
  6128.  
  6129.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  6130.         /* Legacy weak Encoder Msp Init Callback */
  6131.         htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
  6132.         break;
  6133.  
  6134.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  6135.         /* Legacy weak Encoder Msp DeInit Callback */
  6136.         htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
  6137.         break;
  6138.  
  6139.       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
  6140.         /* Legacy weak Hall Sensor Msp Init Callback */
  6141.         htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;
  6142.         break;
  6143.  
  6144.       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
  6145.         /* Legacy weak Hall Sensor Msp DeInit Callback */
  6146.         htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;
  6147.         break;
  6148.  
  6149.       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
  6150.         /* Legacy weak Period Elapsed Callback */
  6151.         htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
  6152.         break;
  6153.  
  6154.       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
  6155.         /* Legacy weak Period Elapsed half complete Callback */
  6156.         htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
  6157.         break;
  6158.  
  6159.       case HAL_TIM_TRIGGER_CB_ID :
  6160.         /* Legacy weak Trigger Callback */
  6161.         htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
  6162.         break;
  6163.  
  6164.       case HAL_TIM_TRIGGER_HALF_CB_ID :
  6165.         /* Legacy weak Trigger half complete Callback */
  6166.         htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
  6167.         break;
  6168.  
  6169.       case HAL_TIM_IC_CAPTURE_CB_ID :
  6170.         /* Legacy weak IC Capture Callback */
  6171.         htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
  6172.         break;
  6173.  
  6174.       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
  6175.         /* Legacy weak IC Capture half complete Callback */
  6176.         htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
  6177.         break;
  6178.  
  6179.       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
  6180.         /* Legacy weak OC Delay Elapsed Callback */
  6181.         htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
  6182.         break;
  6183.  
  6184.       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
  6185.         /* Legacy weak PWM Pulse Finished Callback */
  6186.         htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
  6187.         break;
  6188.  
  6189.       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
  6190.         /* Legacy weak PWM Pulse Finished half complete Callback */
  6191.         htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
  6192.         break;
  6193.  
  6194.       case HAL_TIM_ERROR_CB_ID :
  6195.         /* Legacy weak Error Callback */
  6196.         htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
  6197.         break;
  6198.  
  6199.       case HAL_TIM_COMMUTATION_CB_ID :
  6200.         /* Legacy weak Commutation Callback */
  6201.         htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
  6202.         break;
  6203.  
  6204.       case HAL_TIM_COMMUTATION_HALF_CB_ID :
  6205.         /* Legacy weak Commutation half complete Callback */
  6206.         htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
  6207.         break;
  6208.  
  6209.       case HAL_TIM_BREAK_CB_ID :
  6210.         /* Legacy weak Break Callback */
  6211.         htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
  6212.         break;
  6213.  
  6214.       default :
  6215.         /* Return error status */
  6216.         status = HAL_ERROR;
  6217.         break;
  6218.     }
  6219.   }
  6220.   else if (htim->State == HAL_TIM_STATE_RESET)
  6221.   {
  6222.     switch (CallbackID)
  6223.     {
  6224.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  6225.         /* Legacy weak Base MspInit Callback */
  6226.         htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
  6227.         break;
  6228.  
  6229.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  6230.         /* Legacy weak Base Msp DeInit Callback */
  6231.         htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
  6232.         break;
  6233.  
  6234.       case HAL_TIM_IC_MSPINIT_CB_ID :
  6235.         /* Legacy weak IC Msp Init Callback */
  6236.         htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
  6237.         break;
  6238.  
  6239.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  6240.         /* Legacy weak IC Msp DeInit Callback */
  6241.         htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
  6242.         break;
  6243.  
  6244.       case HAL_TIM_OC_MSPINIT_CB_ID :
  6245.         /* Legacy weak OC Msp Init Callback */
  6246.         htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
  6247.         break;
  6248.  
  6249.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  6250.         /* Legacy weak OC Msp DeInit Callback */
  6251.         htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
  6252.         break;
  6253.  
  6254.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  6255.         /* Legacy weak PWM Msp Init Callback */
  6256.         htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
  6257.         break;
  6258.  
  6259.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  6260.         /* Legacy weak PWM Msp DeInit Callback */
  6261.         htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
  6262.         break;
  6263.  
  6264.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  6265.         /* Legacy weak One Pulse Msp Init Callback */
  6266.         htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
  6267.         break;
  6268.  
  6269.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  6270.         /* Legacy weak One Pulse Msp DeInit Callback */
  6271.         htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
  6272.         break;
  6273.  
  6274.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  6275.         /* Legacy weak Encoder Msp Init Callback */
  6276.         htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
  6277.         break;
  6278.  
  6279.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  6280.         /* Legacy weak Encoder Msp DeInit Callback */
  6281.         htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
  6282.         break;
  6283.  
  6284.       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
  6285.         /* Legacy weak Hall Sensor Msp Init Callback */
  6286.         htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;
  6287.         break;
  6288.  
  6289.       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
  6290.         /* Legacy weak Hall Sensor Msp DeInit Callback */
  6291.         htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
  6292.         break;
  6293.  
  6294.       default :
  6295.         /* Return error status */
  6296.         status = HAL_ERROR;
  6297.         break;
  6298.     }
  6299.   }
  6300.   else
  6301.   {
  6302.     /* Return error status */
  6303.     status = HAL_ERROR;
  6304.   }
  6305.  
  6306.   return status;
  6307. }
  6308. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6309.  
  6310. /**
  6311.   * @}
  6312.   */
  6313.  
  6314. /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
  6315.   *  @brief   TIM Peripheral State functions
  6316.   *
  6317. @verbatim
  6318.   ==============================================================================
  6319.                         ##### Peripheral State functions #####
  6320.   ==============================================================================
  6321.     [..]
  6322.     This subsection permits to get in run-time the status of the peripheral
  6323.     and the data flow.
  6324.  
  6325. @endverbatim
  6326.   * @{
  6327.   */
  6328.  
  6329. /**
  6330.   * @brief  Return the TIM Base handle state.
  6331.   * @param  htim TIM Base handle
  6332.   * @retval HAL state
  6333.   */
  6334. HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
  6335. {
  6336.   return htim->State;
  6337. }
  6338.  
  6339. /**
  6340.   * @brief  Return the TIM OC handle state.
  6341.   * @param  htim TIM Output Compare handle
  6342.   * @retval HAL state
  6343.   */
  6344. HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
  6345. {
  6346.   return htim->State;
  6347. }
  6348.  
  6349. /**
  6350.   * @brief  Return the TIM PWM handle state.
  6351.   * @param  htim TIM handle
  6352.   * @retval HAL state
  6353.   */
  6354. HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
  6355. {
  6356.   return htim->State;
  6357. }
  6358.  
  6359. /**
  6360.   * @brief  Return the TIM Input Capture handle state.
  6361.   * @param  htim TIM IC handle
  6362.   * @retval HAL state
  6363.   */
  6364. HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
  6365. {
  6366.   return htim->State;
  6367. }
  6368.  
  6369. /**
  6370.   * @brief  Return the TIM One Pulse Mode handle state.
  6371.   * @param  htim TIM OPM handle
  6372.   * @retval HAL state
  6373.   */
  6374. HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
  6375. {
  6376.   return htim->State;
  6377. }
  6378.  
  6379. /**
  6380.   * @brief  Return the TIM Encoder Mode handle state.
  6381.   * @param  htim TIM Encoder Interface handle
  6382.   * @retval HAL state
  6383.   */
  6384. HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
  6385. {
  6386.   return htim->State;
  6387. }
  6388.  
  6389. /**
  6390.   * @brief  Return the TIM Encoder Mode handle state.
  6391.   * @param  htim TIM handle
  6392.   * @retval Active channel
  6393.   */
  6394. HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
  6395. {
  6396.   return htim->Channel;
  6397. }
  6398.  
  6399. /**
  6400.   * @brief  Return actual state of the TIM channel.
  6401.   * @param  htim TIM handle
  6402.   * @param  Channel TIM Channel
  6403.   *          This parameter can be one of the following values:
  6404.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  6405.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  6406.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  6407.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  6408.   *            @arg TIM_CHANNEL_5: TIM Channel 5
  6409.   *            @arg TIM_CHANNEL_6: TIM Channel 6
  6410.   * @retval TIM Channel state
  6411.   */
  6412. HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel)
  6413. {
  6414.   HAL_TIM_ChannelStateTypeDef channel_state;
  6415.  
  6416.   /* Check the parameters */
  6417.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  6418.  
  6419.   channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  6420.  
  6421.   return channel_state;
  6422. }
  6423.  
  6424. /**
  6425.   * @brief  Return actual state of a DMA burst operation.
  6426.   * @param  htim TIM handle
  6427.   * @retval DMA burst state
  6428.   */
  6429. HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
  6430. {
  6431.   /* Check the parameters */
  6432.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  6433.  
  6434.   return htim->DMABurstState;
  6435. }
  6436.  
  6437. /**
  6438.   * @}
  6439.   */
  6440.  
  6441. /**
  6442.   * @}
  6443.   */
  6444.  
  6445. /** @defgroup TIM_Private_Functions TIM Private Functions
  6446.   * @{
  6447.   */
  6448.  
  6449. /**
  6450.   * @brief  TIM DMA error callback
  6451.   * @param  hdma pointer to DMA handle.
  6452.   * @retval None
  6453.   */
  6454. void TIM_DMAError(DMA_HandleTypeDef *hdma)
  6455. {
  6456.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6457.  
  6458.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6459.   {
  6460.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6461.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6462.   }
  6463.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6464.   {
  6465.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6466.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6467.   }
  6468.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6469.   {
  6470.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6471.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6472.   }
  6473.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6474.   {
  6475.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6476.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6477.   }
  6478.   else
  6479.   {
  6480.     htim->State = HAL_TIM_STATE_READY;
  6481.   }
  6482.  
  6483. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6484.   htim->ErrorCallback(htim);
  6485. #else
  6486.   HAL_TIM_ErrorCallback(htim);
  6487. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6488.  
  6489.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6490. }
  6491.  
  6492. /**
  6493.   * @brief  TIM DMA Delay Pulse complete callback.
  6494.   * @param  hdma pointer to DMA handle.
  6495.   * @retval None
  6496.   */
  6497. static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
  6498. {
  6499.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6500.  
  6501.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6502.   {
  6503.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6504.  
  6505.     if (hdma->Init.Mode == DMA_NORMAL)
  6506.     {
  6507.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6508.     }
  6509.   }
  6510.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6511.   {
  6512.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6513.  
  6514.     if (hdma->Init.Mode == DMA_NORMAL)
  6515.     {
  6516.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6517.     }
  6518.   }
  6519.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6520.   {
  6521.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6522.  
  6523.     if (hdma->Init.Mode == DMA_NORMAL)
  6524.     {
  6525.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6526.     }
  6527.   }
  6528.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6529.   {
  6530.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6531.  
  6532.     if (hdma->Init.Mode == DMA_NORMAL)
  6533.     {
  6534.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6535.     }
  6536.   }
  6537.   else
  6538.   {
  6539.     /* nothing to do */
  6540.   }
  6541.  
  6542. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6543.   htim->PWM_PulseFinishedCallback(htim);
  6544. #else
  6545.   HAL_TIM_PWM_PulseFinishedCallback(htim);
  6546. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6547.  
  6548.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6549. }
  6550.  
  6551. /**
  6552.   * @brief  TIM DMA Delay Pulse half complete callback.
  6553.   * @param  hdma pointer to DMA handle.
  6554.   * @retval None
  6555.   */
  6556. void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
  6557. {
  6558.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6559.  
  6560.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6561.   {
  6562.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6563.   }
  6564.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6565.   {
  6566.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6567.   }
  6568.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6569.   {
  6570.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6571.   }
  6572.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6573.   {
  6574.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6575.   }
  6576.   else
  6577.   {
  6578.     /* nothing to do */
  6579.   }
  6580.  
  6581. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6582.   htim->PWM_PulseFinishedHalfCpltCallback(htim);
  6583. #else
  6584.   HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
  6585. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6586.  
  6587.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6588. }
  6589.  
  6590. /**
  6591.   * @brief  TIM DMA Capture complete callback.
  6592.   * @param  hdma pointer to DMA handle.
  6593.   * @retval None
  6594.   */
  6595. void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
  6596. {
  6597.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6598.  
  6599.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6600.   {
  6601.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6602.  
  6603.     if (hdma->Init.Mode == DMA_NORMAL)
  6604.     {
  6605.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6606.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6607.     }
  6608.   }
  6609.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6610.   {
  6611.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6612.  
  6613.     if (hdma->Init.Mode == DMA_NORMAL)
  6614.     {
  6615.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6616.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6617.     }
  6618.   }
  6619.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6620.   {
  6621.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6622.  
  6623.     if (hdma->Init.Mode == DMA_NORMAL)
  6624.     {
  6625.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6626.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6627.     }
  6628.   }
  6629.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6630.   {
  6631.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6632.  
  6633.     if (hdma->Init.Mode == DMA_NORMAL)
  6634.     {
  6635.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6636.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6637.     }
  6638.   }
  6639.   else
  6640.   {
  6641.     /* nothing to do */
  6642.   }
  6643.  
  6644. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6645.   htim->IC_CaptureCallback(htim);
  6646. #else
  6647.   HAL_TIM_IC_CaptureCallback(htim);
  6648. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6649.  
  6650.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6651. }
  6652.  
  6653. /**
  6654.   * @brief  TIM DMA Capture half complete callback.
  6655.   * @param  hdma pointer to DMA handle.
  6656.   * @retval None
  6657.   */
  6658. void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
  6659. {
  6660.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6661.  
  6662.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6663.   {
  6664.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6665.   }
  6666.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6667.   {
  6668.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6669.   }
  6670.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6671.   {
  6672.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6673.   }
  6674.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6675.   {
  6676.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6677.   }
  6678.   else
  6679.   {
  6680.     /* nothing to do */
  6681.   }
  6682.  
  6683. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6684.   htim->IC_CaptureHalfCpltCallback(htim);
  6685. #else
  6686.   HAL_TIM_IC_CaptureHalfCpltCallback(htim);
  6687. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6688.  
  6689.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6690. }
  6691.  
  6692. /**
  6693.   * @brief  TIM DMA Period Elapse complete callback.
  6694.   * @param  hdma pointer to DMA handle.
  6695.   * @retval None
  6696.   */
  6697. static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
  6698. {
  6699.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6700.  
  6701.   if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
  6702.   {
  6703.     htim->State = HAL_TIM_STATE_READY;
  6704.   }
  6705.  
  6706. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6707.   htim->PeriodElapsedCallback(htim);
  6708. #else
  6709.   HAL_TIM_PeriodElapsedCallback(htim);
  6710. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6711. }
  6712.  
  6713. /**
  6714.   * @brief  TIM DMA Period Elapse half complete callback.
  6715.   * @param  hdma pointer to DMA handle.
  6716.   * @retval None
  6717.   */
  6718. static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
  6719. {
  6720.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6721.  
  6722. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6723.   htim->PeriodElapsedHalfCpltCallback(htim);
  6724. #else
  6725.   HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
  6726. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6727. }
  6728.  
  6729. /**
  6730.   * @brief  TIM DMA Trigger callback.
  6731.   * @param  hdma pointer to DMA handle.
  6732.   * @retval None
  6733.   */
  6734. static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
  6735. {
  6736.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6737.  
  6738.   if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
  6739.   {
  6740.     htim->State = HAL_TIM_STATE_READY;
  6741.   }
  6742.  
  6743. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6744.   htim->TriggerCallback(htim);
  6745. #else
  6746.   HAL_TIM_TriggerCallback(htim);
  6747. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6748. }
  6749.  
  6750. /**
  6751.   * @brief  TIM DMA Trigger half complete callback.
  6752.   * @param  hdma pointer to DMA handle.
  6753.   * @retval None
  6754.   */
  6755. static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
  6756. {
  6757.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6758.  
  6759. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6760.   htim->TriggerHalfCpltCallback(htim);
  6761. #else
  6762.   HAL_TIM_TriggerHalfCpltCallback(htim);
  6763. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6764. }
  6765.  
  6766. /**
  6767.   * @brief  Time Base configuration
  6768.   * @param  TIMx TIM peripheral
  6769.   * @param  Structure TIM Base configuration structure
  6770.   * @retval None
  6771.   */
  6772. void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
  6773. {
  6774.   uint32_t tmpcr1;
  6775.   tmpcr1 = TIMx->CR1;
  6776.  
  6777.   /* Set TIM Time Base Unit parameters ---------------------------------------*/
  6778.   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  6779.   {
  6780.     /* Select the Counter Mode */
  6781.     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
  6782.     tmpcr1 |= Structure->CounterMode;
  6783.   }
  6784.  
  6785.   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  6786.   {
  6787.     /* Set the clock division */
  6788.     tmpcr1 &= ~TIM_CR1_CKD;
  6789.     tmpcr1 |= (uint32_t)Structure->ClockDivision;
  6790.   }
  6791.  
  6792.   /* Set the auto-reload preload */
  6793.   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
  6794.  
  6795.   TIMx->CR1 = tmpcr1;
  6796.  
  6797.   /* Set the Autoreload value */
  6798.   TIMx->ARR = (uint32_t)Structure->Period ;
  6799.  
  6800.   /* Set the Prescaler value */
  6801.   TIMx->PSC = Structure->Prescaler;
  6802.  
  6803.   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  6804.   {
  6805.     /* Set the Repetition Counter value */
  6806.     TIMx->RCR = Structure->RepetitionCounter;
  6807.   }
  6808.  
  6809.   /* Generate an update event to reload the Prescaler
  6810.      and the repetition counter (only for advanced timer) value immediately */
  6811.   TIMx->EGR = TIM_EGR_UG;
  6812. }
  6813.  
  6814. /**
  6815.   * @brief  Timer Output Compare 1 configuration
  6816.   * @param  TIMx to select the TIM peripheral
  6817.   * @param  OC_Config The output configuration structure
  6818.   * @retval None
  6819.   */
  6820. static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
  6821. {
  6822.   uint32_t tmpccmrx;
  6823.   uint32_t tmpccer;
  6824.   uint32_t tmpcr2;
  6825.  
  6826.   /* Get the TIMx CCER register value */
  6827.   tmpccer = TIMx->CCER;
  6828.  
  6829.   /* Disable the Channel 1: Reset the CC1E Bit */
  6830.   TIMx->CCER &= ~TIM_CCER_CC1E;
  6831.  
  6832.   /* Get the TIMx CR2 register value */
  6833.   tmpcr2 =  TIMx->CR2;
  6834.  
  6835.   /* Get the TIMx CCMR1 register value */
  6836.   tmpccmrx = TIMx->CCMR1;
  6837.  
  6838.   /* Reset the Output Compare Mode Bits */
  6839.   tmpccmrx &= ~TIM_CCMR1_OC1M;
  6840.   tmpccmrx &= ~TIM_CCMR1_CC1S;
  6841.   /* Select the Output Compare Mode */
  6842.   tmpccmrx |= OC_Config->OCMode;
  6843.  
  6844.   /* Reset the Output Polarity level */
  6845.   tmpccer &= ~TIM_CCER_CC1P;
  6846.   /* Set the Output Compare Polarity */
  6847.   tmpccer |= OC_Config->OCPolarity;
  6848.  
  6849.   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
  6850.   {
  6851.     /* Check parameters */
  6852.     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
  6853.  
  6854.     /* Reset the Output N Polarity level */
  6855.     tmpccer &= ~TIM_CCER_CC1NP;
  6856.     /* Set the Output N Polarity */
  6857.     tmpccer |= OC_Config->OCNPolarity;
  6858.     /* Reset the Output N State */
  6859.     tmpccer &= ~TIM_CCER_CC1NE;
  6860.   }
  6861.  
  6862.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  6863.   {
  6864.     /* Check parameters */
  6865.     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
  6866.     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
  6867.  
  6868.     /* Reset the Output Compare and Output Compare N IDLE State */
  6869.     tmpcr2 &= ~TIM_CR2_OIS1;
  6870.     tmpcr2 &= ~TIM_CR2_OIS1N;
  6871.     /* Set the Output Idle state */
  6872.     tmpcr2 |= OC_Config->OCIdleState;
  6873.     /* Set the Output N Idle state */
  6874.     tmpcr2 |= OC_Config->OCNIdleState;
  6875.   }
  6876.  
  6877.   /* Write to TIMx CR2 */
  6878.   TIMx->CR2 = tmpcr2;
  6879.  
  6880.   /* Write to TIMx CCMR1 */
  6881.   TIMx->CCMR1 = tmpccmrx;
  6882.  
  6883.   /* Set the Capture Compare Register value */
  6884.   TIMx->CCR1 = OC_Config->Pulse;
  6885.  
  6886.   /* Write to TIMx CCER */
  6887.   TIMx->CCER = tmpccer;
  6888. }
  6889.  
  6890. /**
  6891.   * @brief  Timer Output Compare 2 configuration
  6892.   * @param  TIMx to select the TIM peripheral
  6893.   * @param  OC_Config The output configuration structure
  6894.   * @retval None
  6895.   */
  6896. void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
  6897. {
  6898.   uint32_t tmpccmrx;
  6899.   uint32_t tmpccer;
  6900.   uint32_t tmpcr2;
  6901.  
  6902.   /* Get the TIMx CCER register value */
  6903.   tmpccer = TIMx->CCER;
  6904.  
  6905.   /* Disable the Channel 2: Reset the CC2E Bit */
  6906.   TIMx->CCER &= ~TIM_CCER_CC2E;
  6907.  
  6908.   /* Get the TIMx CR2 register value */
  6909.   tmpcr2 =  TIMx->CR2;
  6910.  
  6911.   /* Get the TIMx CCMR1 register value */
  6912.   tmpccmrx = TIMx->CCMR1;
  6913.  
  6914.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  6915.   tmpccmrx &= ~TIM_CCMR1_OC2M;
  6916.   tmpccmrx &= ~TIM_CCMR1_CC2S;
  6917.  
  6918.   /* Select the Output Compare Mode */
  6919.   tmpccmrx |= (OC_Config->OCMode << 8U);
  6920.  
  6921.   /* Reset the Output Polarity level */
  6922.   tmpccer &= ~TIM_CCER_CC2P;
  6923.   /* Set the Output Compare Polarity */
  6924.   tmpccer |= (OC_Config->OCPolarity << 4U);
  6925.  
  6926.   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
  6927.   {
  6928.     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
  6929.  
  6930.     /* Reset the Output N Polarity level */
  6931.     tmpccer &= ~TIM_CCER_CC2NP;
  6932.     /* Set the Output N Polarity */
  6933.     tmpccer |= (OC_Config->OCNPolarity << 4U);
  6934.     /* Reset the Output N State */
  6935.     tmpccer &= ~TIM_CCER_CC2NE;
  6936.  
  6937.   }
  6938.  
  6939.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  6940.   {
  6941.     /* Check parameters */
  6942.     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
  6943.     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
  6944.  
  6945.     /* Reset the Output Compare and Output Compare N IDLE State */
  6946.     tmpcr2 &= ~TIM_CR2_OIS2;
  6947.     tmpcr2 &= ~TIM_CR2_OIS2N;
  6948.     /* Set the Output Idle state */
  6949.     tmpcr2 |= (OC_Config->OCIdleState << 2U);
  6950.     /* Set the Output N Idle state */
  6951.     tmpcr2 |= (OC_Config->OCNIdleState << 2U);
  6952.   }
  6953.  
  6954.   /* Write to TIMx CR2 */
  6955.   TIMx->CR2 = tmpcr2;
  6956.  
  6957.   /* Write to TIMx CCMR1 */
  6958.   TIMx->CCMR1 = tmpccmrx;
  6959.  
  6960.   /* Set the Capture Compare Register value */
  6961.   TIMx->CCR2 = OC_Config->Pulse;
  6962.  
  6963.   /* Write to TIMx CCER */
  6964.   TIMx->CCER = tmpccer;
  6965. }
  6966.  
  6967. /**
  6968.   * @brief  Timer Output Compare 3 configuration
  6969.   * @param  TIMx to select the TIM peripheral
  6970.   * @param  OC_Config The output configuration structure
  6971.   * @retval None
  6972.   */
  6973. static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
  6974. {
  6975.   uint32_t tmpccmrx;
  6976.   uint32_t tmpccer;
  6977.   uint32_t tmpcr2;
  6978.  
  6979.   /* Get the TIMx CCER register value */
  6980.   tmpccer = TIMx->CCER;
  6981.  
  6982.   /* Disable the Channel 3: Reset the CC2E Bit */
  6983.   TIMx->CCER &= ~TIM_CCER_CC3E;
  6984.  
  6985.   /* Get the TIMx CR2 register value */
  6986.   tmpcr2 =  TIMx->CR2;
  6987.  
  6988.   /* Get the TIMx CCMR2 register value */
  6989.   tmpccmrx = TIMx->CCMR2;
  6990.  
  6991.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  6992.   tmpccmrx &= ~TIM_CCMR2_OC3M;
  6993.   tmpccmrx &= ~TIM_CCMR2_CC3S;
  6994.   /* Select the Output Compare Mode */
  6995.   tmpccmrx |= OC_Config->OCMode;
  6996.  
  6997.   /* Reset the Output Polarity level */
  6998.   tmpccer &= ~TIM_CCER_CC3P;
  6999.   /* Set the Output Compare Polarity */
  7000.   tmpccer |= (OC_Config->OCPolarity << 8U);
  7001.  
  7002.   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
  7003.   {
  7004.     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
  7005.  
  7006.     /* Reset the Output N Polarity level */
  7007.     tmpccer &= ~TIM_CCER_CC3NP;
  7008.     /* Set the Output N Polarity */
  7009.     tmpccer |= (OC_Config->OCNPolarity << 8U);
  7010.     /* Reset the Output N State */
  7011.     tmpccer &= ~TIM_CCER_CC3NE;
  7012.   }
  7013.  
  7014.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  7015.   {
  7016.     /* Check parameters */
  7017.     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
  7018.     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
  7019.  
  7020.     /* Reset the Output Compare and Output Compare N IDLE State */
  7021.     tmpcr2 &= ~TIM_CR2_OIS3;
  7022.     tmpcr2 &= ~TIM_CR2_OIS3N;
  7023.     /* Set the Output Idle state */
  7024.     tmpcr2 |= (OC_Config->OCIdleState << 4U);
  7025.     /* Set the Output N Idle state */
  7026.     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
  7027.   }
  7028.  
  7029.   /* Write to TIMx CR2 */
  7030.   TIMx->CR2 = tmpcr2;
  7031.  
  7032.   /* Write to TIMx CCMR2 */
  7033.   TIMx->CCMR2 = tmpccmrx;
  7034.  
  7035.   /* Set the Capture Compare Register value */
  7036.   TIMx->CCR3 = OC_Config->Pulse;
  7037.  
  7038.   /* Write to TIMx CCER */
  7039.   TIMx->CCER = tmpccer;
  7040. }
  7041.  
  7042. /**
  7043.   * @brief  Timer Output Compare 4 configuration
  7044.   * @param  TIMx to select the TIM peripheral
  7045.   * @param  OC_Config The output configuration structure
  7046.   * @retval None
  7047.   */
  7048. static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
  7049. {
  7050.   uint32_t tmpccmrx;
  7051.   uint32_t tmpccer;
  7052.   uint32_t tmpcr2;
  7053.  
  7054.   /* Get the TIMx CCER register value */
  7055.   tmpccer = TIMx->CCER;
  7056.  
  7057.   /* Disable the Channel 4: Reset the CC4E Bit */
  7058.   TIMx->CCER &= ~TIM_CCER_CC4E;
  7059.  
  7060.   /* Get the TIMx CR2 register value */
  7061.   tmpcr2 =  TIMx->CR2;
  7062.  
  7063.   /* Get the TIMx CCMR2 register value */
  7064.   tmpccmrx = TIMx->CCMR2;
  7065.  
  7066.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  7067.   tmpccmrx &= ~TIM_CCMR2_OC4M;
  7068.   tmpccmrx &= ~TIM_CCMR2_CC4S;
  7069.  
  7070.   /* Select the Output Compare Mode */
  7071.   tmpccmrx |= (OC_Config->OCMode << 8U);
  7072.  
  7073.   /* Reset the Output Polarity level */
  7074.   tmpccer &= ~TIM_CCER_CC4P;
  7075.   /* Set the Output Compare Polarity */
  7076.   tmpccer |= (OC_Config->OCPolarity << 12U);
  7077.  
  7078.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  7079.   {
  7080.     /* Check parameters */
  7081.     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
  7082.  
  7083.     /* Reset the Output Compare IDLE State */
  7084.     tmpcr2 &= ~TIM_CR2_OIS4;
  7085.  
  7086.     /* Set the Output Idle state */
  7087.     tmpcr2 |= (OC_Config->OCIdleState << 6U);
  7088.   }
  7089.  
  7090.   /* Write to TIMx CR2 */
  7091.   TIMx->CR2 = tmpcr2;
  7092.  
  7093.   /* Write to TIMx CCMR2 */
  7094.   TIMx->CCMR2 = tmpccmrx;
  7095.  
  7096.   /* Set the Capture Compare Register value */
  7097.   TIMx->CCR4 = OC_Config->Pulse;
  7098.  
  7099.   /* Write to TIMx CCER */
  7100.   TIMx->CCER = tmpccer;
  7101. }
  7102.  
  7103. /**
  7104.   * @brief  Slave Timer configuration function
  7105.   * @param  htim TIM handle
  7106.   * @param  sSlaveConfig Slave timer configuration
  7107.   * @retval None
  7108.   */
  7109. static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
  7110.                                                   const TIM_SlaveConfigTypeDef *sSlaveConfig)
  7111. {
  7112.   HAL_StatusTypeDef status = HAL_OK;
  7113.   uint32_t tmpsmcr;
  7114.   uint32_t tmpccmr1;
  7115.   uint32_t tmpccer;
  7116.  
  7117.   /* Get the TIMx SMCR register value */
  7118.   tmpsmcr = htim->Instance->SMCR;
  7119.  
  7120.   /* Reset the Trigger Selection Bits */
  7121.   tmpsmcr &= ~TIM_SMCR_TS;
  7122.   /* Set the Input Trigger source */
  7123.   tmpsmcr |= sSlaveConfig->InputTrigger;
  7124.  
  7125.   /* Reset the slave mode Bits */
  7126.   tmpsmcr &= ~TIM_SMCR_SMS;
  7127.   /* Set the slave mode */
  7128.   tmpsmcr |= sSlaveConfig->SlaveMode;
  7129.  
  7130.   /* Write to TIMx SMCR */
  7131.   htim->Instance->SMCR = tmpsmcr;
  7132.  
  7133.   /* Configure the trigger prescaler, filter, and polarity */
  7134.   switch (sSlaveConfig->InputTrigger)
  7135.   {
  7136.     case TIM_TS_ETRF:
  7137.     {
  7138.       /* Check the parameters */
  7139.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
  7140.       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
  7141.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  7142.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  7143.       /* Configure the ETR Trigger source */
  7144.       TIM_ETR_SetConfig(htim->Instance,
  7145.                         sSlaveConfig->TriggerPrescaler,
  7146.                         sSlaveConfig->TriggerPolarity,
  7147.                         sSlaveConfig->TriggerFilter);
  7148.       break;
  7149.     }
  7150.  
  7151.     case TIM_TS_TI1F_ED:
  7152.     {
  7153.       /* Check the parameters */
  7154.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  7155.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  7156.  
  7157.       if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
  7158.       {
  7159.         return HAL_ERROR;
  7160.       }
  7161.  
  7162.       /* Disable the Channel 1: Reset the CC1E Bit */
  7163.       tmpccer = htim->Instance->CCER;
  7164.       htim->Instance->CCER &= ~TIM_CCER_CC1E;
  7165.       tmpccmr1 = htim->Instance->CCMR1;
  7166.  
  7167.       /* Set the filter */
  7168.       tmpccmr1 &= ~TIM_CCMR1_IC1F;
  7169.       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
  7170.  
  7171.       /* Write to TIMx CCMR1 and CCER registers */
  7172.       htim->Instance->CCMR1 = tmpccmr1;
  7173.       htim->Instance->CCER = tmpccer;
  7174.       break;
  7175.     }
  7176.  
  7177.     case TIM_TS_TI1FP1:
  7178.     {
  7179.       /* Check the parameters */
  7180.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  7181.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  7182.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  7183.  
  7184.       /* Configure TI1 Filter and Polarity */
  7185.       TIM_TI1_ConfigInputStage(htim->Instance,
  7186.                                sSlaveConfig->TriggerPolarity,
  7187.                                sSlaveConfig->TriggerFilter);
  7188.       break;
  7189.     }
  7190.  
  7191.     case TIM_TS_TI2FP2:
  7192.     {
  7193.       /* Check the parameters */
  7194.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  7195.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  7196.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  7197.  
  7198.       /* Configure TI2 Filter and Polarity */
  7199.       TIM_TI2_ConfigInputStage(htim->Instance,
  7200.                                sSlaveConfig->TriggerPolarity,
  7201.                                sSlaveConfig->TriggerFilter);
  7202.       break;
  7203.     }
  7204.  
  7205.     case TIM_TS_ITR0:
  7206.     case TIM_TS_ITR1:
  7207.     case TIM_TS_ITR2:
  7208.     case TIM_TS_ITR3:
  7209.     {
  7210.       /* Check the parameter */
  7211.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  7212.       break;
  7213.     }
  7214.  
  7215.     default:
  7216.       status = HAL_ERROR;
  7217.       break;
  7218.   }
  7219.  
  7220.   return status;
  7221. }
  7222.  
  7223. /**
  7224.   * @brief  Configure the TI1 as Input.
  7225.   * @param  TIMx to select the TIM peripheral.
  7226.   * @param  TIM_ICPolarity The Input Polarity.
  7227.   *          This parameter can be one of the following values:
  7228.   *            @arg TIM_ICPOLARITY_RISING
  7229.   *            @arg TIM_ICPOLARITY_FALLING
  7230.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  7231.   * @param  TIM_ICSelection specifies the input to be used.
  7232.   *          This parameter can be one of the following values:
  7233.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
  7234.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
  7235.   *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
  7236.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7237.   *          This parameter must be a value between 0x00 and 0x0F.
  7238.   * @retval None
  7239.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
  7240.   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
  7241.   *        protected against un-initialized filter and polarity values.
  7242.   */
  7243. void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  7244.                        uint32_t TIM_ICFilter)
  7245. {
  7246.   uint32_t tmpccmr1;
  7247.   uint32_t tmpccer;
  7248.  
  7249.   /* Disable the Channel 1: Reset the CC1E Bit */
  7250.   tmpccer = TIMx->CCER;
  7251.   TIMx->CCER &= ~TIM_CCER_CC1E;
  7252.   tmpccmr1 = TIMx->CCMR1;
  7253.  
  7254.   /* Select the Input */
  7255.   if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
  7256.   {
  7257.     tmpccmr1 &= ~TIM_CCMR1_CC1S;
  7258.     tmpccmr1 |= TIM_ICSelection;
  7259.   }
  7260.   else
  7261.   {
  7262.     tmpccmr1 |= TIM_CCMR1_CC1S_0;
  7263.   }
  7264.  
  7265.   /* Set the filter */
  7266.   tmpccmr1 &= ~TIM_CCMR1_IC1F;
  7267.   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
  7268.  
  7269.   /* Select the Polarity and set the CC1E Bit */
  7270.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  7271.   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
  7272.  
  7273.   /* Write to TIMx CCMR1 and CCER registers */
  7274.   TIMx->CCMR1 = tmpccmr1;
  7275.   TIMx->CCER = tmpccer;
  7276. }
  7277.  
  7278. /**
  7279.   * @brief  Configure the Polarity and Filter for TI1.
  7280.   * @param  TIMx to select the TIM peripheral.
  7281.   * @param  TIM_ICPolarity The Input Polarity.
  7282.   *          This parameter can be one of the following values:
  7283.   *            @arg TIM_ICPOLARITY_RISING
  7284.   *            @arg TIM_ICPOLARITY_FALLING
  7285.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  7286.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7287.   *          This parameter must be a value between 0x00 and 0x0F.
  7288.   * @retval None
  7289.   */
  7290. static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
  7291. {
  7292.   uint32_t tmpccmr1;
  7293.   uint32_t tmpccer;
  7294.  
  7295.   /* Disable the Channel 1: Reset the CC1E Bit */
  7296.   tmpccer = TIMx->CCER;
  7297.   TIMx->CCER &= ~TIM_CCER_CC1E;
  7298.   tmpccmr1 = TIMx->CCMR1;
  7299.  
  7300.   /* Set the filter */
  7301.   tmpccmr1 &= ~TIM_CCMR1_IC1F;
  7302.   tmpccmr1 |= (TIM_ICFilter << 4U);
  7303.  
  7304.   /* Select the Polarity and set the CC1E Bit */
  7305.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  7306.   tmpccer |= TIM_ICPolarity;
  7307.  
  7308.   /* Write to TIMx CCMR1 and CCER registers */
  7309.   TIMx->CCMR1 = tmpccmr1;
  7310.   TIMx->CCER = tmpccer;
  7311. }
  7312.  
  7313. /**
  7314.   * @brief  Configure the TI2 as Input.
  7315.   * @param  TIMx to select the TIM peripheral
  7316.   * @param  TIM_ICPolarity The Input Polarity.
  7317.   *          This parameter can be one of the following values:
  7318.   *            @arg TIM_ICPOLARITY_RISING
  7319.   *            @arg TIM_ICPOLARITY_FALLING
  7320.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  7321.   * @param  TIM_ICSelection specifies the input to be used.
  7322.   *          This parameter can be one of the following values:
  7323.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
  7324.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
  7325.   *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
  7326.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7327.   *          This parameter must be a value between 0x00 and 0x0F.
  7328.   * @retval None
  7329.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
  7330.   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
  7331.   *        protected against un-initialized filter and polarity values.
  7332.   */
  7333. static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  7334.                               uint32_t TIM_ICFilter)
  7335. {
  7336.   uint32_t tmpccmr1;
  7337.   uint32_t tmpccer;
  7338.  
  7339.   /* Disable the Channel 2: Reset the CC2E Bit */
  7340.   tmpccer = TIMx->CCER;
  7341.   TIMx->CCER &= ~TIM_CCER_CC2E;
  7342.   tmpccmr1 = TIMx->CCMR1;
  7343.  
  7344.   /* Select the Input */
  7345.   tmpccmr1 &= ~TIM_CCMR1_CC2S;
  7346.   tmpccmr1 |= (TIM_ICSelection << 8U);
  7347.  
  7348.   /* Set the filter */
  7349.   tmpccmr1 &= ~TIM_CCMR1_IC2F;
  7350.   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
  7351.  
  7352.   /* Select the Polarity and set the CC2E Bit */
  7353.   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  7354.   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
  7355.  
  7356.   /* Write to TIMx CCMR1 and CCER registers */
  7357.   TIMx->CCMR1 = tmpccmr1 ;
  7358.   TIMx->CCER = tmpccer;
  7359. }
  7360.  
  7361. /**
  7362.   * @brief  Configure the Polarity and Filter for TI2.
  7363.   * @param  TIMx to select the TIM peripheral.
  7364.   * @param  TIM_ICPolarity The Input Polarity.
  7365.   *          This parameter can be one of the following values:
  7366.   *            @arg TIM_ICPOLARITY_RISING
  7367.   *            @arg TIM_ICPOLARITY_FALLING
  7368.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  7369.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7370.   *          This parameter must be a value between 0x00 and 0x0F.
  7371.   * @retval None
  7372.   */
  7373. static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
  7374. {
  7375.   uint32_t tmpccmr1;
  7376.   uint32_t tmpccer;
  7377.  
  7378.   /* Disable the Channel 2: Reset the CC2E Bit */
  7379.   tmpccer = TIMx->CCER;
  7380.   TIMx->CCER &= ~TIM_CCER_CC2E;
  7381.   tmpccmr1 = TIMx->CCMR1;
  7382.  
  7383.   /* Set the filter */
  7384.   tmpccmr1 &= ~TIM_CCMR1_IC2F;
  7385.   tmpccmr1 |= (TIM_ICFilter << 12U);
  7386.  
  7387.   /* Select the Polarity and set the CC2E Bit */
  7388.   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  7389.   tmpccer |= (TIM_ICPolarity << 4U);
  7390.  
  7391.   /* Write to TIMx CCMR1 and CCER registers */
  7392.   TIMx->CCMR1 = tmpccmr1 ;
  7393.   TIMx->CCER = tmpccer;
  7394. }
  7395.  
  7396. /**
  7397.   * @brief  Configure the TI3 as Input.
  7398.   * @param  TIMx to select the TIM peripheral
  7399.   * @param  TIM_ICPolarity The Input Polarity.
  7400.   *          This parameter can be one of the following values:
  7401.   *            @arg TIM_ICPOLARITY_RISING
  7402.   *            @arg TIM_ICPOLARITY_FALLING
  7403.   * @param  TIM_ICSelection specifies the input to be used.
  7404.   *          This parameter can be one of the following values:
  7405.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
  7406.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
  7407.   *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
  7408.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7409.   *          This parameter must be a value between 0x00 and 0x0F.
  7410.   * @retval None
  7411.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
  7412.   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
  7413.   *        protected against un-initialized filter and polarity values.
  7414.   */
  7415. static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  7416.                               uint32_t TIM_ICFilter)
  7417. {
  7418.   uint32_t tmpccmr2;
  7419.   uint32_t tmpccer;
  7420.  
  7421.   /* Disable the Channel 3: Reset the CC3E Bit */
  7422.   tmpccer = TIMx->CCER;
  7423.   TIMx->CCER &= ~TIM_CCER_CC3E;
  7424.   tmpccmr2 = TIMx->CCMR2;
  7425.  
  7426.   /* Select the Input */
  7427.   tmpccmr2 &= ~TIM_CCMR2_CC3S;
  7428.   tmpccmr2 |= TIM_ICSelection;
  7429.  
  7430.   /* Set the filter */
  7431.   tmpccmr2 &= ~TIM_CCMR2_IC3F;
  7432.   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
  7433.  
  7434.   /* Select the Polarity and set the CC3E Bit */
  7435.   tmpccer &= ~(TIM_CCER_CC3P);
  7436.   tmpccer |= ((TIM_ICPolarity << 8U) & TIM_CCER_CC3P);
  7437.  
  7438.   /* Write to TIMx CCMR2 and CCER registers */
  7439.   TIMx->CCMR2 = tmpccmr2;
  7440.   TIMx->CCER = tmpccer;
  7441. }
  7442.  
  7443. /**
  7444.   * @brief  Configure the TI4 as Input.
  7445.   * @param  TIMx to select the TIM peripheral
  7446.   * @param  TIM_ICPolarity The Input Polarity.
  7447.   *          This parameter can be one of the following values:
  7448.   *            @arg TIM_ICPOLARITY_RISING
  7449.   *            @arg TIM_ICPOLARITY_FALLING
  7450.   * @param  TIM_ICSelection specifies the input to be used.
  7451.   *          This parameter can be one of the following values:
  7452.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
  7453.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
  7454.   *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
  7455.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7456.   *          This parameter must be a value between 0x00 and 0x0F.
  7457.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
  7458.   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
  7459.   *        protected against un-initialized filter and polarity values.
  7460.   * @retval None
  7461.   */
  7462. static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  7463.                               uint32_t TIM_ICFilter)
  7464. {
  7465.   uint32_t tmpccmr2;
  7466.   uint32_t tmpccer;
  7467.  
  7468.   /* Disable the Channel 4: Reset the CC4E Bit */
  7469.   tmpccer = TIMx->CCER;
  7470.   TIMx->CCER &= ~TIM_CCER_CC4E;
  7471.   tmpccmr2 = TIMx->CCMR2;
  7472.  
  7473.   /* Select the Input */
  7474.   tmpccmr2 &= ~TIM_CCMR2_CC4S;
  7475.   tmpccmr2 |= (TIM_ICSelection << 8U);
  7476.  
  7477.   /* Set the filter */
  7478.   tmpccmr2 &= ~TIM_CCMR2_IC4F;
  7479.   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
  7480.  
  7481.   /* Select the Polarity and set the CC4E Bit */
  7482.   tmpccer &= ~(TIM_CCER_CC4P);
  7483.   tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P);
  7484.  
  7485.   /* Write to TIMx CCMR2 and CCER registers */
  7486.   TIMx->CCMR2 = tmpccmr2;
  7487.   TIMx->CCER = tmpccer ;
  7488. }
  7489.  
  7490. /**
  7491.   * @brief  Selects the Input Trigger source
  7492.   * @param  TIMx to select the TIM peripheral
  7493.   * @param  InputTriggerSource The Input Trigger source.
  7494.   *          This parameter can be one of the following values:
  7495.   *            @arg TIM_TS_ITR0: Internal Trigger 0
  7496.   *            @arg TIM_TS_ITR1: Internal Trigger 1
  7497.   *            @arg TIM_TS_ITR2: Internal Trigger 2
  7498.   *            @arg TIM_TS_ITR3: Internal Trigger 3
  7499.   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
  7500.   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
  7501.   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
  7502.   *            @arg TIM_TS_ETRF: External Trigger input
  7503.   * @retval None
  7504.   */
  7505. static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
  7506. {
  7507.   uint32_t tmpsmcr;
  7508.  
  7509.   /* Get the TIMx SMCR register value */
  7510.   tmpsmcr = TIMx->SMCR;
  7511.   /* Reset the TS Bits */
  7512.   tmpsmcr &= ~TIM_SMCR_TS;
  7513.   /* Set the Input Trigger source and the slave mode*/
  7514.   tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
  7515.   /* Write to TIMx SMCR */
  7516.   TIMx->SMCR = tmpsmcr;
  7517. }
  7518. /**
  7519.   * @brief  Configures the TIMx External Trigger (ETR).
  7520.   * @param  TIMx to select the TIM peripheral
  7521.   * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
  7522.   *          This parameter can be one of the following values:
  7523.   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
  7524.   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
  7525.   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
  7526.   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
  7527.   * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
  7528.   *          This parameter can be one of the following values:
  7529.   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
  7530.   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
  7531.   * @param  ExtTRGFilter External Trigger Filter.
  7532.   *          This parameter must be a value between 0x00 and 0x0F
  7533.   * @retval None
  7534.   */
  7535. void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
  7536.                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
  7537. {
  7538.   uint32_t tmpsmcr;
  7539.  
  7540.   tmpsmcr = TIMx->SMCR;
  7541.  
  7542.   /* Reset the ETR Bits */
  7543.   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  7544.  
  7545.   /* Set the Prescaler, the Filter value and the Polarity */
  7546.   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
  7547.  
  7548.   /* Write to TIMx SMCR */
  7549.   TIMx->SMCR = tmpsmcr;
  7550. }
  7551.  
  7552. /**
  7553.   * @brief  Enables or disables the TIM Capture Compare Channel x.
  7554.   * @param  TIMx to select the TIM peripheral
  7555.   * @param  Channel specifies the TIM Channel
  7556.   *          This parameter can be one of the following values:
  7557.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  7558.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  7559.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  7560.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  7561.   * @param  ChannelState specifies the TIM Channel CCxE bit new state.
  7562.   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
  7563.   * @retval None
  7564.   */
  7565. void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
  7566. {
  7567.   uint32_t tmp;
  7568.  
  7569.   /* Check the parameters */
  7570.   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  7571.   assert_param(IS_TIM_CHANNELS(Channel));
  7572.  
  7573.   tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
  7574.  
  7575.   /* Reset the CCxE Bit */
  7576.   TIMx->CCER &= ~tmp;
  7577.  
  7578.   /* Set or reset the CCxE Bit */
  7579.   TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
  7580. }
  7581.  
  7582. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  7583. /**
  7584.   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
  7585.   * @param  htim pointer to a TIM_HandleTypeDef structure that contains
  7586.   *                the configuration information for TIM module.
  7587.   * @retval None
  7588.   */
  7589. void TIM_ResetCallback(TIM_HandleTypeDef *htim)
  7590. {
  7591.   /* Reset the TIM callback to the legacy weak callbacks */
  7592.   htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
  7593.   htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
  7594.   htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
  7595.   htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
  7596.   htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
  7597.   htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
  7598.   htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
  7599.   htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
  7600.   htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
  7601.   htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
  7602.   htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
  7603.   htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
  7604.   htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
  7605. }
  7606. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  7607.  
  7608. /**
  7609.   * @}
  7610.   */
  7611.  
  7612. #endif /* HAL_TIM_MODULE_ENABLED */
  7613. /**
  7614.   * @}
  7615.   */
  7616.  
  7617. /**
  7618.   * @}
  7619.   */
  7620.