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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_rcc.c
  4.   * @author  MCD Application Team
  5.   * @version V1.0.1
  6.   * @date    31-July-2015
  7.   * @brief   RCC HAL module driver.
  8.   *          This file provides firmware functions to manage the following
  9.   *          functionalities of the Reset and Clock Control (RCC) peripheral:
  10.   *           + Initialization and de-initialization functions
  11.   *           + Peripheral Control functions
  12.   *      
  13.   @verbatim                
  14.   ==============================================================================
  15.                       ##### RCC specific features #####
  16.   ==============================================================================
  17.     [..]  
  18.       After reset the device is running from Internal High Speed oscillator
  19.       (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
  20.       and all peripherals are off except internal SRAM, Flash and JTAG.
  21.       (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
  22.           all peripherals mapped on these busses are running at HSI speed.
  23.       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
  24.       (+) All GPIOs are in input floating state, except the JTAG pins which
  25.           are assigned to be used for debug purpose.
  26.     [..] Once the device started from reset, the user application has to:
  27.       (+) Configure the clock source to be used to drive the System clock
  28.           (if the application needs higher frequency/performance)
  29.       (+) Configure the System clock frequency and Flash settings  
  30.       (+) Configure the AHB and APB busses prescalers
  31.       (+) Enable the clock for the peripheral(s) to be used
  32.       (+) Configure the clock source(s) for peripherals whose clocks are not
  33.           derived from the System clock (I2S, RTC, ADC, USB OTG FS)
  34.  
  35.                       ##### RCC Limitations #####
  36.   ==============================================================================
  37.     [..]  
  38.       A delay between an RCC peripheral clock enable and the effective peripheral
  39.       enabling should be taken into account in order to manage the peripheral read/write
  40.       from/to registers.
  41.       (+) This delay depends on the peripheral mapping.
  42.         (++) AHB & APB peripherals, 1 dummy read is necessary
  43.  
  44.     [..]  
  45.       Workarounds:
  46.       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
  47.           inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
  48.  
  49.   @endverbatim
  50.   ******************************************************************************
  51.   * @attention
  52.   *
  53.   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  54.   *
  55.   * Redistribution and use in source and binary forms, with or without modification,
  56.   * are permitted provided that the following conditions are met:
  57.   *   1. Redistributions of source code must retain the above copyright notice,
  58.   *      this list of conditions and the following disclaimer.
  59.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  60.   *      this list of conditions and the following disclaimer in the documentation
  61.   *      and/or other materials provided with the distribution.
  62.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  63.   *      may be used to endorse or promote products derived from this software
  64.   *      without specific prior written permission.
  65.   *
  66.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  67.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  68.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  69.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  70.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  71.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  72.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  73.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  74.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  75.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  76.   *
  77.   ******************************************************************************  
  78. */
  79.  
  80. /* Includes ------------------------------------------------------------------*/
  81. #include "stm32f1xx_hal.h"
  82.  
  83. /** @addtogroup STM32F1xx_HAL_Driver
  84.   * @{
  85.   */
  86.  
  87. /** @defgroup RCC RCC
  88. * @brief RCC HAL module driver
  89.   * @{
  90.   */
  91.  
  92. #ifdef HAL_RCC_MODULE_ENABLED
  93.  
  94. /* Private typedef -----------------------------------------------------------*/
  95. /* Private define ------------------------------------------------------------*/
  96. /** @defgroup RCC_Private_Constants RCC Private Constants
  97.  * @{
  98.  */
  99. /**
  100.   * @}
  101.   */
  102. /* Private macro -------------------------------------------------------------*/
  103. /** @defgroup RCC_Private_Macros RCC Private Macros
  104.   * @{
  105.   */
  106.  
  107. #define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
  108. #define MCO1_GPIO_PORT        GPIOA
  109. #define MCO1_PIN              GPIO_PIN_8
  110.  
  111. /**
  112.   * @}
  113.   */
  114.  
  115. /* Private variables ---------------------------------------------------------*/
  116. /** @defgroup RCC_Private_Variables RCC Private Variables
  117.   * @{
  118.   */
  119. const uint8_t aAPBAHBPrescTable[16]       = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
  120. /**
  121.   * @}
  122.   */
  123.  
  124. /* Private function prototypes -----------------------------------------------*/
  125. /* Exported functions ---------------------------------------------------------*/
  126.  
  127. /** @defgroup RCC_Exported_Functions RCC Exported Functions
  128.   * @{
  129.   */
  130.  
  131. /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
  132.   *  @brief    Initialization and Configuration functions
  133.   *
  134.   @verbatim    
  135.   ===============================================================================
  136.            ##### Initialization and de-initialization functions #####
  137.   ===============================================================================
  138.     [..]
  139.       This section provides functions allowing to configure the internal/external oscillators
  140.       (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
  141.       and APB2).
  142.  
  143.     [..] Internal/external clock and PLL configuration
  144.       (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
  145.           the PLL as System clock source.
  146.       (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
  147.           clock source.
  148.  
  149.       (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x)  crystal oscillator used directly or
  150.           through the PLL as System clock source. Can be used also as RTC clock source.
  151.  
  152.       (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.  
  153.  
  154.       (#) PLL (clocked by HSI or HSE), featuring different output clocks:
  155.         (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
  156.         (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
  157.  
  158.       (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
  159.           and if a HSE clock failure occurs(HSE used directly or through PLL as System
  160.           clock source), the System clocks automatically switched to HSI and an interrupt
  161.           is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
  162.           (Non-Maskable Interrupt) exception vector.  
  163.  
  164.       (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,  
  165.           HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
  166.  
  167.     [..] System, AHB and APB buses clocks configuration
  168.       (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
  169.           HSE and PLL.
  170.           The AHB clock (HCLK) is derived from System clock through configurable
  171.           prescaler and used to clock the CPU, memory and peripherals mapped
  172.           on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
  173.           from AHB clock through configurable prescalers and used to clock
  174.           the peripherals mapped on these buses. You can use
  175.           "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
  176.  
  177.       -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
  178.           (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
  179.               divided by 128.
  180.           (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
  181.               to work correctly. This clock is derived of the main PLL through PLL Multiplier.
  182.           (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
  183.           (+@) IWDG clock which is always the LSI clock.
  184.  
  185.       (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
  186.           For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.  
  187.              Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
  188.         +-----------------------------------------------+
  189.         | Latency       | SYSCLK clock frequency (MHz)  |
  190.         |---------------|-------------------------------|
  191.         |0WS(1CPU cycle)|       0 < SYSCLK <= 24        |
  192.         |---------------|-------------------------------|
  193.         |1WS(2CPU cycle)|      24 < SYSCLK <= 48        |
  194.         |---------------|-------------------------------|
  195.         |2WS(3CPU cycle)|      48 < SYSCLK <= 72        |
  196.         +-----------------------------------------------+
  197.   @endverbatim
  198.   * @{
  199.   */
  200.  
  201. /**
  202.   * @brief  Resets the RCC clock configuration to the default reset state.
  203.   * @note   The default reset state of the clock configuration is given below:
  204.   *            - HSI ON and used as system clock source
  205.   *            - HSE and PLL OFF
  206.   *            - AHB, APB1 and APB2 prescaler set to 1.
  207.   *            - CSS and MCO1 OFF
  208.   *            - All interrupts disabled
  209.   * @note   This function doesn't modify the configuration of the
  210.   *            - Peripheral clocks  
  211.   *            - LSI, LSE and RTC clocks
  212.   * @retval None
  213.   */
  214. void HAL_RCC_DeInit(void)
  215. {
  216.   /* Switch SYSCLK to HSI */
  217.   CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
  218.  
  219.   /* Reset HSEON, CSSON, & PLLON bits */
  220.   CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
  221.  
  222.   /* Reset HSEBYP bit */
  223.   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
  224.  
  225.   /* Reset CFGR register */
  226.   CLEAR_REG(RCC->CFGR);
  227.  
  228.   /* Set HSITRIM bits to the reset value */
  229.   MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM)));
  230.  
  231. #if (defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE))
  232.   /* Reset CFGR2 register */
  233.   CLEAR_REG(RCC->CFGR2);
  234.  
  235. #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
  236.   /* Disable all interrupts */
  237.   CLEAR_REG(RCC->CIR);
  238. }
  239.  
  240. /**
  241.   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
  242.   *         RCC_OscInitTypeDef.
  243.   * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
  244.   *         contains the configuration information for the RCC Oscillators.
  245.   * @note   The PLL is not disabled when used as system clock.
  246.   * @note   The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
  247.   * @retval HAL status
  248.   */
  249. HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
  250. {
  251.    uint32_t tickstart = 0;
  252.  
  253.   /* Check the parameters */
  254.   assert_param(RCC_OscInitStruct != NULL);
  255.   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  256.  
  257.   /*------------------------------- HSE Configuration ------------------------*/
  258.   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
  259.   {
  260.     /* Check the parameters */
  261.     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
  262.        
  263.     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
  264.     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
  265.        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
  266.     {
  267.       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
  268.       {
  269.         return HAL_ERROR;
  270.       }
  271.     }
  272.     else
  273.     {
  274.       /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
  275.       __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
  276.      
  277.       /* Get Start Tick */
  278.       tickstart = HAL_GetTick();
  279.      
  280.       /* Wait till HSE is disabled */  
  281.       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
  282.       {
  283.         if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
  284.         {
  285.           return HAL_TIMEOUT;
  286.         }
  287.       }
  288.      
  289.       /* Set the new HSE configuration ---------------------------------------*/
  290.       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
  291.      
  292.  
  293.        /* Check the HSE State */
  294.       if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
  295.       {
  296.         /* Get Start Tick */
  297.         tickstart = HAL_GetTick();
  298.        
  299.         /* Wait till HSE is ready */
  300.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
  301.         {
  302.           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
  303.           {
  304.             return HAL_TIMEOUT;
  305.           }
  306.         }
  307.       }
  308.       else
  309.       {
  310.         /* Get Start Tick */
  311.         tickstart = HAL_GetTick();
  312.        
  313.         /* Wait till HSE is bypassed or disabled */
  314.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
  315.         {
  316.            if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
  317.           {
  318.             return HAL_TIMEOUT;
  319.           }
  320.         }
  321.       }
  322.     }
  323.   }
  324.   /*----------------------------- HSI Configuration --------------------------*/
  325.   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
  326.   {
  327.     /* Check the parameters */
  328.     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
  329.     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
  330.    
  331.     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
  332.     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
  333.        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
  334.     {
  335.       /* When HSI is used as system clock it will not disabled */
  336.       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
  337.       {
  338.         return HAL_ERROR;
  339.       }
  340.       /* Otherwise, just the calibration is allowed */
  341.       else
  342.       {
  343.         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
  344.         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
  345.       }
  346.     }
  347.     else
  348.     {
  349.       /* Check the HSI State */
  350.       if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
  351.       {
  352.        /* Enable the Internal High Speed oscillator (HSI). */
  353.         __HAL_RCC_HSI_ENABLE();
  354.        
  355.         /* Get Start Tick */
  356.         tickstart = HAL_GetTick();
  357.        
  358.         /* Wait till HSI is ready */
  359.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
  360.         {
  361.           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
  362.           {
  363.             return HAL_TIMEOUT;
  364.           }
  365.         }
  366.                
  367.         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
  368.         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
  369.       }
  370.       else
  371.       {
  372.         /* Disable the Internal High Speed oscillator (HSI). */
  373.         __HAL_RCC_HSI_DISABLE();
  374.        
  375.         /* Get Start Tick */
  376.         tickstart = HAL_GetTick();
  377.        
  378.         /* Wait till HSI is disabled */
  379.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
  380.         {
  381.           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
  382.           {
  383.             return HAL_TIMEOUT;
  384.           }
  385.         }
  386.       }
  387.     }
  388.   }
  389.   /*------------------------------ LSI Configuration -------------------------*/
  390.   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
  391.   {
  392.     /* Check the parameters */
  393.     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
  394.    
  395.     /* Check the LSI State */
  396.     if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
  397.     {
  398.       /* Enable the Internal Low Speed oscillator (LSI). */
  399.       __HAL_RCC_LSI_ENABLE();
  400.      
  401.       /* Get Start Tick */
  402.       tickstart = HAL_GetTick();
  403.      
  404.       /* Wait till LSI is ready */  
  405.       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
  406.       {
  407.         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
  408.         {
  409.           return HAL_TIMEOUT;
  410.         }
  411.       }
  412.       /*  To have a fully stabilized clock in the specified range, a software temporization of 1ms
  413.           should be added.*/
  414.       HAL_Delay(1);
  415.     }
  416.     else
  417.     {
  418.       /* Disable the Internal Low Speed oscillator (LSI). */
  419.       __HAL_RCC_LSI_DISABLE();
  420.      
  421.       /* Get Start Tick */
  422.       tickstart = HAL_GetTick();
  423.      
  424.       /* Wait till LSI is disabled */  
  425.       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
  426.       {
  427.         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
  428.         {
  429.           return HAL_TIMEOUT;
  430.         }
  431.       }
  432.     }
  433.   }
  434.   /*------------------------------ LSE Configuration -------------------------*/
  435.   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
  436.   {
  437.     /* Check the parameters */
  438.     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
  439.    
  440.     /* Enable Power Clock*/
  441.     __HAL_RCC_PWR_CLK_ENABLE();
  442.    
  443.     /* Enable write access to Backup domain */
  444.     SET_BIT(PWR->CR, PWR_CR_DBP);
  445.  
  446.     /* Wait for Backup domain Write protection disable */
  447.     tickstart = HAL_GetTick();
  448.    
  449.     while((PWR->CR & PWR_CR_DBP) == RESET)
  450.     {
  451.       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
  452.       {
  453.         return HAL_TIMEOUT;
  454.       }      
  455.     }
  456.    
  457.     /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
  458.     __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
  459.    
  460.     /* Get Start Tick */
  461.     tickstart = HAL_GetTick();
  462.    
  463.     /* Wait till LSE is disabled */  
  464.     while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
  465.     {
  466.       if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  467.       {
  468.         return HAL_TIMEOUT;
  469.       }
  470.     }
  471.    
  472.     /* Set the new LSE configuration -----------------------------------------*/
  473.     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
  474.     /* Check the LSE State */
  475.     if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
  476.     {
  477.       /* Get Start Tick */
  478.       tickstart = HAL_GetTick();
  479.      
  480.       /* Wait till LSE is ready */  
  481.       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
  482.       {
  483.         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  484.         {
  485.           return HAL_TIMEOUT;
  486.         }
  487.       }
  488.     }
  489.     else
  490.     {
  491.       /* Get Start Tick */
  492.       tickstart = HAL_GetTick();
  493.      
  494.       /* Wait till LSE is disabled */  
  495.       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
  496.       {
  497.         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  498.         {
  499.           return HAL_TIMEOUT;
  500.         }
  501.       }
  502.     }
  503.   }
  504.  
  505. #if defined(RCC_CR_PLL2ON)
  506.   /*-------------------------------- PLL2 Configuration -----------------------*/
  507.   /* Check the parameters */
  508.   assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
  509.   if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
  510.   {
  511.     /* This bit can not be cleared if the PLL2 clock is used indirectly as system
  512.       clock (i.e. it is used as PLL clock entry that is used as system clock). */
  513.     if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
  514.         (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
  515.         ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
  516.     {
  517.       return HAL_ERROR;
  518.     }
  519.     else
  520.     {
  521.       if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
  522.       {
  523.         /* Check the parameters */
  524.         assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
  525.         assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
  526.  
  527.         /* Prediv2 can be written only when the PLLI2S is disabled. */
  528.         /* Return an error only if new value is different from the programmed value */
  529.         if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
  530.           (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
  531.         {
  532.           return HAL_ERROR;
  533.         }
  534.        
  535.         /* Disable the main PLL2. */
  536.         __HAL_RCC_PLL2_DISABLE();
  537.        
  538.         /* Get Start Tick */
  539.         tickstart = HAL_GetTick();
  540.        
  541.         /* Wait till PLL2 is disabled */
  542.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
  543.         {
  544.           if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
  545.           {
  546.             return HAL_TIMEOUT;
  547.           }
  548.         }
  549.        
  550.         /* Configure the HSE prediv2 factor --------------------------------*/
  551.         __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
  552.  
  553.         /* Configure the main PLL2 multiplication factors. */
  554.         __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
  555.        
  556.         /* Enable the main PLL2. */
  557.         __HAL_RCC_PLL2_ENABLE();
  558.        
  559.         /* Get Start Tick */
  560.         tickstart = HAL_GetTick();
  561.        
  562.         /* Wait till PLL2 is ready */
  563.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  == RESET)
  564.         {
  565.           if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
  566.           {
  567.             return HAL_TIMEOUT;
  568.           }
  569.         }
  570.       }
  571.       else
  572.       {
  573.        /* Set PREDIV1 source to HSE */
  574.         CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
  575.  
  576.         /* Disable the main PLL2. */
  577.         __HAL_RCC_PLL2_DISABLE();
  578.  
  579.         /* Get Start Tick */
  580.         tickstart = HAL_GetTick();
  581.        
  582.         /* Wait till PLL2 is disabled */  
  583.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  != RESET)
  584.         {
  585.           if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
  586.           {
  587.             return HAL_TIMEOUT;
  588.           }
  589.         }
  590.       }
  591.     }
  592.   }
  593.  
  594. #endif /* RCC_CR_PLL2ON */
  595.   /*-------------------------------- PLL Configuration -----------------------*/
  596.   /* Check the parameters */
  597.   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  598.   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
  599.   {
  600.     /* Check if the PLL is used as system clock or not */
  601.     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
  602.     {
  603.       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
  604.       {
  605.         /* Check the parameters */
  606.         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
  607.         assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
  608.  
  609.         /* Disable the main PLL. */
  610.         __HAL_RCC_PLL_DISABLE();
  611.        
  612.         /* Get Start Tick */
  613.         tickstart = HAL_GetTick();
  614.        
  615.         /* Wait till PLL is disabled */
  616.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
  617.         {
  618.           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  619.           {
  620.             return HAL_TIMEOUT;
  621.           }
  622.         }
  623.  
  624.         /* Configure the HSE prediv factor --------------------------------*/
  625.         /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
  626.         if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
  627.         {
  628.           /* Check the parameter */
  629.           assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
  630. #if defined(RCC_CFGR2_PREDIV1SRC)
  631.           assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
  632.          
  633.           /* Set PREDIV1 source */
  634.           SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
  635. #endif /* RCC_CFGR2_PREDIV1SRC */
  636.  
  637.           /* Set PREDIV1 Value */
  638.           __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
  639.         }
  640.  
  641.         /* Configure the main PLL clock source and multiplication factors. */
  642.         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
  643.                              RCC_OscInitStruct->PLL.PLLMUL);
  644.         /* Enable the main PLL. */
  645.         __HAL_RCC_PLL_ENABLE();
  646.        
  647.         /* Get Start Tick */
  648.         tickstart = HAL_GetTick();
  649.        
  650.         /* Wait till PLL is ready */
  651.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
  652.         {
  653.           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  654.           {
  655.             return HAL_TIMEOUT;
  656.           }
  657.         }
  658.       }
  659.       else
  660.       {
  661.         /* Disable the main PLL. */
  662.         __HAL_RCC_PLL_DISABLE();
  663.  
  664.         /* Get Start Tick */
  665.         tickstart = HAL_GetTick();
  666.        
  667.         /* Wait till PLL is disabled */  
  668.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
  669.         {
  670.           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  671.           {
  672.             return HAL_TIMEOUT;
  673.           }
  674.         }
  675.       }
  676.     }
  677.     else
  678.     {
  679.       return HAL_ERROR;
  680.     }
  681.   }
  682.  
  683.   return HAL_OK;
  684. }
  685.  
  686. /**
  687.   * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
  688.   *         parameters in the RCC_ClkInitStruct.
  689.   * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
  690.   *         contains the configuration information for the RCC peripheral.
  691.   * @param  FLatency FLASH Latency                  
  692.   *          The value of this parameter depend on device used within the same series
  693.   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
  694.   *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
  695.   *
  696.   * @note   The HSI is used (enabled by hardware) as system clock source after
  697.   *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
  698.   *         of failure of the HSE used directly or indirectly as system clock
  699.   *         (if the Clock Security System CSS is enabled).
  700.   *          
  701.   * @note   A switch from one clock source to another occurs only if the target
  702.   *         clock source is ready (clock stable after startup delay or PLL locked).
  703.   *         If a clock source which is not yet ready is selected, the switch will
  704.   *         occur when the clock source will be ready.
  705.   *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
  706.   *         currently used as system clock source.
  707.   * @retval HAL status
  708.   */
  709. HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
  710. {
  711.   uint32_t tickstart = 0;
  712.  
  713.   /* Check the parameters */
  714.   assert_param(RCC_ClkInitStruct != NULL);
  715.   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
  716.   assert_param(IS_FLASH_LATENCY(FLatency));
  717.  
  718.   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
  719.   must be correctly programmed according to the frequency of the CPU clock
  720.     (HCLK) of the device. */
  721.  
  722. #if defined(FLASH_ACR_LATENCY)
  723.   /* Increasing the CPU frequency */
  724.   if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
  725.   {    
  726.     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
  727.     __HAL_FLASH_SET_LATENCY(FLatency);
  728.    
  729.     /* Check that the new number of wait states is taken into account to access the Flash
  730.     memory by reading the FLASH_ACR register */
  731.     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
  732.     {
  733.       return HAL_ERROR;
  734.     }
  735.    
  736. #endif /* FLASH_ACR_LATENCY */
  737.     /*-------------------------- HCLK Configuration --------------------------*/
  738.     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
  739.     {
  740.       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
  741.       MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
  742.     }
  743.  
  744.     /*------------------------- SYSCLK Configuration ---------------------------*/
  745.     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
  746.     {    
  747.       assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
  748.      
  749.       /* HSE is selected as System Clock Source */
  750.       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  751.       {
  752.         /* Check the HSE ready flag */  
  753.         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
  754.         {
  755.           return HAL_ERROR;
  756.         }
  757.       }
  758.       /* PLL is selected as System Clock Source */
  759.       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
  760.       {
  761.         /* Check the PLL ready flag */  
  762.         if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
  763.         {
  764.           return HAL_ERROR;
  765.         }
  766.       }
  767.       /* HSI is selected as System Clock Source */
  768.       else
  769.       {
  770.         /* Check the HSI ready flag */  
  771.         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
  772.         {
  773.           return HAL_ERROR;
  774.         }
  775.       }
  776.       __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
  777.  
  778.       /* Get Start Tick */
  779.       tickstart = HAL_GetTick();
  780.      
  781.       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  782.       {
  783.         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
  784.         {
  785.           if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  786.           {
  787.             return HAL_TIMEOUT;
  788.           }
  789.         }
  790.       }
  791.       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
  792.       {
  793.         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
  794.         {
  795.           if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  796.           {
  797.             return HAL_TIMEOUT;
  798.           }
  799.         }
  800.       }
  801.       else
  802.       {
  803.         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
  804.         {
  805.           if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  806.           {
  807.             return HAL_TIMEOUT;
  808.           }
  809.         }
  810.       }      
  811.     }    
  812. #if defined(FLASH_ACR_LATENCY)
  813.   }
  814.   /* Decreasing the CPU frequency */
  815.   else
  816.   {
  817.     /*-------------------------- HCLK Configuration --------------------------*/
  818.     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
  819.     {
  820.       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
  821.       MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
  822.     }
  823.    
  824.     /*------------------------- SYSCLK Configuration -------------------------*/
  825.     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
  826.     {    
  827.       assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
  828.      
  829.       /* HSE is selected as System Clock Source */
  830.       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  831.       {
  832.         /* Check the HSE ready flag */  
  833.         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
  834.         {
  835.           return HAL_ERROR;
  836.         }
  837.       }
  838.       /* PLL is selected as System Clock Source */
  839.       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
  840.       {
  841.         /* Check the PLL ready flag */  
  842.         if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
  843.         {
  844.           return HAL_ERROR;
  845.         }
  846.       }
  847.       /* HSI is selected as System Clock Source */
  848.       else
  849.       {
  850.         /* Check the HSI ready flag */  
  851.         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
  852.         {
  853.           return HAL_ERROR;
  854.         }
  855.       }
  856.       __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
  857.      
  858.       /* Get Start Tick */
  859.       tickstart = HAL_GetTick();
  860.      
  861.       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  862.       {
  863.         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
  864.         {
  865.           if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  866.           {
  867.             return HAL_TIMEOUT;
  868.           }
  869.         }
  870.       }
  871.       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
  872.       {
  873.         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
  874.         {
  875.           if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  876.           {
  877.             return HAL_TIMEOUT;
  878.           }
  879.         }
  880.       }
  881.       else
  882.       {
  883.         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
  884.         {
  885.           if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  886.           {
  887.             return HAL_TIMEOUT;
  888.           }
  889.         }
  890.       }      
  891.     }
  892.    
  893.     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
  894.     __HAL_FLASH_SET_LATENCY(FLatency);
  895.    
  896.     /* Check that the new number of wait states is taken into account to access the Flash
  897.     memory by reading the FLASH_ACR register */
  898.     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
  899.     {
  900.       return HAL_ERROR;
  901.     }
  902.   }
  903. #endif /* FLASH_ACR_LATENCY */
  904.  
  905.   /*-------------------------- PCLK1 Configuration ---------------------------*/
  906.   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
  907.   {
  908.     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
  909.     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
  910.   }
  911.  
  912.   /*-------------------------- PCLK2 Configuration ---------------------------*/
  913.   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
  914.   {
  915.     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
  916.     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
  917.   }
  918.  
  919.   /* Configure the source of time base considering new system clocks settings*/
  920.   HAL_InitTick (TICK_INT_PRIORITY);
  921.  
  922.   return HAL_OK;
  923. }
  924.  
  925. /**
  926.   * @}
  927.   */
  928.  
  929. /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
  930.   *  @brief   RCC clocks control functions
  931.   *
  932.   @verbatim  
  933.   ===============================================================================
  934.                   ##### Peripheral Control functions #####
  935.   ===============================================================================  
  936.     [..]
  937.     This subsection provides a set of functions allowing to control the RCC Clocks
  938.     frequencies.
  939.  
  940.   @endverbatim
  941.   * @{
  942.   */
  943.  
  944. /**
  945.   * @brief  Selects the clock source to output on MCO pin.
  946.   * @note   MCO pin should be configured in alternate function mode.
  947.   * @param  RCC_MCOx specifies the output direction for the clock source.
  948.   *          This parameter can be one of the following values:
  949.   *            @arg RCC_MCO Clock source to output on MCO1 pin(PA8).
  950.   * @param  RCC_MCOSource specifies the clock source to output.
  951.   *          This parameter can be one of the following values:
  952.   *            @arg RCC_MCO1SOURCE_NOCLOCK No clock selected
  953.   *            @arg RCC_MCO1SOURCE_SYSCLK System clock selected
  954.   *            @arg RCC_MCO1SOURCE_HSI HSI oscillator clock selected
  955.   *            @arg RCC_MCO1SOURCE_HSE HSE oscillator clock selected
  956.   *            @arg RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
  957.   *            @arg RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source (only for connectivity line devices)
  958.   *            @arg RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source (only for connectivity line devices)
  959.   *            @arg RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source (only for connectivity line devices)
  960.   *            @arg RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source (only for connectivity line devices)
  961.   * @param  RCC_MCODiv specifies the MCO DIV.
  962.   *          This parameter can be one of the following values:
  963.   *            @arg RCC_MCODIV_1 no division applied to MCO clock
  964.   * @retval None
  965.   */
  966. void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
  967. {
  968.   GPIO_InitTypeDef gpio = {0};
  969.  
  970.   /* Check the parameters */
  971.   assert_param(IS_RCC_MCO(RCC_MCOx));
  972.   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
  973.   assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
  974.  
  975.   /* MCO Clock Enable */
  976.   MCO1_CLK_ENABLE();
  977.  
  978.   /* Configure the MCO1 pin in alternate function mode */
  979.   gpio.Pin = MCO1_PIN;
  980.   gpio.Mode = GPIO_MODE_AF_PP;
  981.   gpio.Speed = GPIO_SPEED_HIGH;
  982.   gpio.Pull = GPIO_NOPULL;
  983.   HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
  984.  
  985.   /* Configure the MCO clock source */
  986.   __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
  987. }
  988.  
  989. /**
  990.   * @brief  Enables the Clock Security System.
  991.   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
  992.   *         is automatically disabled and an interrupt is generated to inform the
  993.   *         software about the failure (Clock Security System Interrupt, CSSI),
  994.   *         allowing the MCU to perform rescue operations. The CSSI is linked to
  995.   *         the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.  
  996.   * @retval None
  997.   */
  998. void HAL_RCC_EnableCSS(void)
  999. {
  1000.   *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
  1001. }
  1002.  
  1003. /**
  1004.   * @brief  Disables the Clock Security System.
  1005.   * @retval None
  1006.   */
  1007. void HAL_RCC_DisableCSS(void)
  1008. {
  1009.   *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
  1010. }
  1011.  
  1012. /**
  1013.   * @brief  Returns the SYSCLK frequency    
  1014.   * @note   The system frequency computed by this function is not the real
  1015.   *         frequency in the chip. It is calculated based on the predefined
  1016.   *         constant and the selected clock source:
  1017.   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
  1018.   * @note     If SYSCLK source is HSE, function returns a value based on HSE_VALUE
  1019.   *           divided by PREDIV factor(**)
  1020.   * @note     If SYSCLK source is PLL, function returns a value based on HSE_VALUE
  1021.   *           divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
  1022.   * @note     (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
  1023.   *               8 MHz) but the real value may vary depending on the variations
  1024.   *               in voltage and temperature.
  1025.   * @note     (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
  1026.   *                8 MHz), user has to ensure that HSE_VALUE is same as the real
  1027.   *                frequency of the crystal used. Otherwise, this function may
  1028.   *                have wrong result.
  1029.   *                  
  1030.   * @note   The result of this function could be not correct when using fractional
  1031.   *         value for HSE crystal.
  1032.   *          
  1033.   * @note   This function can be used by the user application to compute the
  1034.   *         baudrate for the communication peripherals or configure other parameters.
  1035.   *          
  1036.   * @note   Each time SYSCLK changes, this function must be called to update the
  1037.   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
  1038.   *        
  1039.   * @retval SYSCLK frequency
  1040.   */
  1041. uint32_t HAL_RCC_GetSysClockFreq(void)
  1042. {
  1043. #if   defined(RCC_CFGR2_PREDIV1SRC)
  1044.   const uint8_t aPLLMULFactorTable[12] = {0, 0, 4,  5,  6,  7,  8,  9, 0, 0, 0, 13};
  1045.   const uint8_t aPredivFactorTable[16] = { 1, 2,  3,  4,  5,  6,  7,  8, 9,10, 11, 12, 13, 14, 15, 16};
  1046. #else
  1047.   const uint8_t aPLLMULFactorTable[16] = { 2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 16, 16};
  1048. #if defined(RCC_CFGR2_PREDIV1)
  1049.   const uint8_t aPredivFactorTable[16] = { 1, 2,  3,  4,  5,  6,  7,  8, 9,10, 11, 12, 13, 14, 15, 16};
  1050. #else
  1051.   const uint8_t aPredivFactorTable[2] = { 1, 2};
  1052. #endif /*RCC_CFGR2_PREDIV1*/
  1053.  
  1054. #endif
  1055.   uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0;
  1056.   uint32_t sysclockfreq = 0;
  1057. #if defined(RCC_CFGR2_PREDIV1SRC)
  1058.   uint32_t prediv2 = 0, pll2mul = 0;
  1059. #endif /*RCC_CFGR2_PREDIV1SRC*/
  1060.  
  1061.   tmpreg = RCC->CFGR;
  1062.  
  1063.   /* Get SYSCLK source -------------------------------------------------------*/
  1064.   switch (tmpreg & RCC_CFGR_SWS)
  1065.   {
  1066.     case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
  1067.     {
  1068.       sysclockfreq = HSE_VALUE;
  1069.       break;
  1070.     }
  1071.     case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
  1072.     {
  1073.       pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
  1074.       if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
  1075.       {
  1076. #if defined(RCC_CFGR2_PREDIV1)
  1077.         prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
  1078. #else
  1079.         prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
  1080. #endif /*RCC_CFGR2_PREDIV1*/
  1081. #if defined(RCC_CFGR2_PREDIV1SRC)
  1082.  
  1083.         if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
  1084.         {
  1085.           /* PLL2 selected as Prediv1 source */
  1086.           /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
  1087.           prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
  1088.           pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
  1089.           pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv) * pllmul);
  1090.         }
  1091.         else
  1092.         {
  1093.           /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
  1094.           pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
  1095.         }
  1096.        
  1097.         /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
  1098.         /* In this case need to divide pllclk by 2 */
  1099.         if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
  1100.         {
  1101.             pllclk = pllclk / 2;
  1102.         }
  1103. #else
  1104.         /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
  1105.         pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
  1106. #endif /*RCC_CFGR2_PREDIV1SRC*/
  1107.       }
  1108.       else
  1109.       {
  1110.         /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
  1111.         pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
  1112.       }
  1113.       sysclockfreq = pllclk;
  1114.       break;
  1115.     }
  1116.     case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
  1117.     default: /* HSI used as system clock */
  1118.     {
  1119.       sysclockfreq = HSI_VALUE;
  1120.       break;
  1121.     }
  1122.   }
  1123.   return sysclockfreq;
  1124. }
  1125.  
  1126. /**
  1127.   * @brief  Returns the HCLK frequency    
  1128.   * @note   Each time HCLK changes, this function must be called to update the
  1129.   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
  1130.   *
  1131.   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
  1132.   *         and updated within this function
  1133.   * @retval HCLK frequency
  1134.   */
  1135. uint32_t HAL_RCC_GetHCLKFreq(void)
  1136. {
  1137.   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
  1138.   return SystemCoreClock;
  1139. }
  1140.  
  1141. /**
  1142.   * @brief  Returns the PCLK1 frequency    
  1143.   * @note   Each time PCLK1 changes, this function must be called to update the
  1144.   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  1145.   * @retval PCLK1 frequency
  1146.   */
  1147. uint32_t HAL_RCC_GetPCLK1Freq(void)
  1148. {
  1149.   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  1150.   return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
  1151. }    
  1152.  
  1153. /**
  1154.   * @brief  Returns the PCLK2 frequency    
  1155.   * @note   Each time PCLK2 changes, this function must be called to update the
  1156.   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  1157.   * @retval PCLK2 frequency
  1158.   */
  1159. uint32_t HAL_RCC_GetPCLK2Freq(void)
  1160. {
  1161.   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
  1162.   return (HAL_RCC_GetHCLKFreq()>> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
  1163. }
  1164.  
  1165. /**
  1166.   * @brief  Configures the RCC_OscInitStruct according to the internal
  1167.   * RCC configuration registers.
  1168.   * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
  1169.   * will be configured.
  1170.   * @retval None
  1171.   */
  1172. void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
  1173. {
  1174.   /* Check the parameters */
  1175.   assert_param(RCC_OscInitStruct != NULL);
  1176.  
  1177.   /* Set all possible values for the Oscillator type parameter ---------------*/
  1178.   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI  \
  1179.                   | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
  1180.  
  1181. #if defined(RCC_CFGR2_PREDIV1SRC)
  1182.   /* Get the Prediv1 source --------------------------------------------------*/
  1183.   RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
  1184. #endif /* RCC_CFGR2_PREDIV1SRC */
  1185.  
  1186.   /* Get the HSE configuration -----------------------------------------------*/
  1187.   if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
  1188.   {
  1189.     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
  1190.   }
  1191.   else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
  1192.   {
  1193.     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
  1194.   }
  1195.   else
  1196.   {
  1197.     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
  1198.   }
  1199.   RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
  1200.  
  1201.   /* Get the HSI configuration -----------------------------------------------*/
  1202.   if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
  1203.   {
  1204.     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
  1205.   }
  1206.   else
  1207.   {
  1208.     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
  1209.   }
  1210.  
  1211.   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
  1212.  
  1213.   /* Get the LSE configuration -----------------------------------------------*/
  1214.   if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
  1215.   {
  1216.     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
  1217.   }
  1218.   else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
  1219.   {
  1220.     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
  1221.   }
  1222.   else
  1223.   {
  1224.     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
  1225.   }
  1226.  
  1227.   /* Get the LSI configuration -----------------------------------------------*/
  1228.   if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
  1229.   {
  1230.     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
  1231.   }
  1232.   else
  1233.   {
  1234.     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
  1235.   }
  1236.  
  1237.   /* Get the PLL configuration -----------------------------------------------*/
  1238.   if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
  1239.   {
  1240.     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
  1241.   }
  1242.   else
  1243.   {
  1244.     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
  1245.   }
  1246.   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
  1247.   RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
  1248. #if defined(RCC_CR_PLL2ON)
  1249.   /* Get the PLL2 configuration -----------------------------------------------*/
  1250.   if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
  1251.   {
  1252.     RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
  1253.   }
  1254.   else
  1255.   {
  1256.     RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
  1257.   }
  1258.   RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
  1259.   RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
  1260. #endif /* RCC_CR_PLL2ON */
  1261. }
  1262.  
  1263. /**
  1264.   * @brief  Get the RCC_ClkInitStruct according to the internal
  1265.   * RCC configuration registers.
  1266.   * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
  1267.   * contains the current clock configuration.
  1268.   * @param  pFLatency Pointer on the Flash Latency.
  1269.   * @retval None
  1270.   */
  1271. void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
  1272. {
  1273.   /* Check the parameters */
  1274.   assert_param(RCC_ClkInitStruct != NULL);
  1275.   assert_param(pFLatency != NULL);
  1276.  
  1277.   /* Set all possible values for the Clock type parameter --------------------*/
  1278.   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
  1279.  
  1280.   /* Get the SYSCLK configuration --------------------------------------------*/
  1281.   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
  1282.  
  1283.   /* Get the HCLK configuration ----------------------------------------------*/
  1284.   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
  1285.  
  1286.   /* Get the APB1 configuration ----------------------------------------------*/
  1287.   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);  
  1288.  
  1289.   /* Get the APB2 configuration ----------------------------------------------*/
  1290.   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
  1291.  
  1292. #if   defined(FLASH_ACR_LATENCY)
  1293.   /* Get the Flash Wait State (Latency) configuration ------------------------*/  
  1294.   *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
  1295. #else
  1296.   /* For VALUE lines devices, only LATENCY_0 can be set*/
  1297.   *pFLatency = (uint32_t)FLASH_LATENCY_0;
  1298. #endif
  1299. }
  1300.  
  1301. /**
  1302.   * @brief This function handles the RCC CSS interrupt request.
  1303.   * @note This API should be called under the NMI_Handler().
  1304.   * @retval None
  1305.   */
  1306. void HAL_RCC_NMI_IRQHandler(void)
  1307. {
  1308.   /* Check RCC CSSF flag  */
  1309.   if(__HAL_RCC_GET_IT(RCC_IT_CSS))
  1310.   {
  1311.     /* RCC Clock Security System interrupt user callback */
  1312.     HAL_RCC_CSSCallback();
  1313.    
  1314.     /* Clear RCC CSS pending bit */
  1315.     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
  1316.   }
  1317. }
  1318.  
  1319. /**
  1320.   * @brief  RCC Clock Security System interrupt callback
  1321.   * @retval none
  1322.   */
  1323. __weak void HAL_RCC_CSSCallback(void)
  1324. {
  1325.   /* NOTE : This function Should not be modified, when the callback is needed,
  1326.     the HAL_RCC_CSSCallback could be implemented in the user file
  1327.     */
  1328. }
  1329.  
  1330. /**
  1331.   * @}
  1332.   */
  1333.  
  1334. /**
  1335.   * @}
  1336.   */
  1337.  
  1338. #endif /* HAL_RCC_MODULE_ENABLED */
  1339. /**
  1340.   * @}
  1341.   */
  1342.  
  1343. /**
  1344.   * @}
  1345.   */
  1346.  
  1347. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1348.