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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_pwr.c
  4.   * @author  MCD Application Team
  5.   * @brief   PWR HAL module driver.
  6.   *
  7.   *          This file provides firmware functions to manage the following
  8.   *          functionalities of the Power Controller (PWR) peripheral:
  9.   *           + Initialization/de-initialization functions
  10.   *           + Peripheral Control functions
  11.   *
  12.   ******************************************************************************
  13.   * @attention
  14.   *
  15.   * Copyright (c) 2016 STMicroelectronics.
  16.   * All rights reserved.
  17.   *
  18.   * This software is licensed under terms that can be found in the LICENSE file
  19.   * in the root directory of this software component.
  20.   * If no LICENSE file comes with this software, it is provided AS-IS.
  21.   *
  22.   ******************************************************************************
  23.   */
  24.  
  25. /* Includes ------------------------------------------------------------------*/
  26. #include "stm32f1xx_hal.h"
  27.  
  28. /** @addtogroup STM32F1xx_HAL_Driver
  29.   * @{
  30.   */
  31.  
  32. /** @defgroup PWR PWR
  33.   * @brief    PWR HAL module driver
  34.   * @{
  35.   */
  36.  
  37. #ifdef HAL_PWR_MODULE_ENABLED
  38.  
  39. /* Private typedef -----------------------------------------------------------*/
  40. /* Private define ------------------------------------------------------------*/
  41.  
  42. /** @defgroup PWR_Private_Constants PWR Private Constants
  43.   * @{
  44.   */
  45.  
  46. /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
  47.   * @{
  48.   */
  49. #define PVD_MODE_IT               0x00010000U
  50. #define PVD_MODE_EVT              0x00020000U
  51. #define PVD_RISING_EDGE           0x00000001U
  52. #define PVD_FALLING_EDGE          0x00000002U
  53. /**
  54.   * @}
  55.   */
  56.  
  57.  
  58. /** @defgroup PWR_register_alias_address PWR Register alias address
  59.   * @{
  60.   */
  61. /* ------------- PWR registers bit address in the alias region ---------------*/
  62. #define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
  63. #define PWR_CR_OFFSET            0x00U
  64. #define PWR_CSR_OFFSET           0x04U
  65. #define PWR_CR_OFFSET_BB         (PWR_OFFSET + PWR_CR_OFFSET)
  66. #define PWR_CSR_OFFSET_BB        (PWR_OFFSET + PWR_CSR_OFFSET)
  67. /**
  68.   * @}
  69.   */
  70.    
  71. /** @defgroup PWR_CR_register_alias PWR CR Register alias address
  72.   * @{
  73.   */  
  74. /* --- CR Register ---*/
  75. /* Alias word address of LPSDSR bit */
  76. #define LPSDSR_BIT_NUMBER        PWR_CR_LPDS_Pos
  77. #define CR_LPSDSR_BB             ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))
  78.  
  79. /* Alias word address of DBP bit */
  80. #define DBP_BIT_NUMBER            PWR_CR_DBP_Pos
  81. #define CR_DBP_BB                ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))
  82.  
  83. /* Alias word address of PVDE bit */
  84. #define PVDE_BIT_NUMBER           PWR_CR_PVDE_Pos
  85. #define CR_PVDE_BB               ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))
  86.  
  87. /**
  88.   * @}
  89.   */
  90.  
  91. /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
  92.   * @{
  93.   */
  94.  
  95. /* --- CSR Register ---*/
  96. /* Alias word address of EWUP1 bit */
  97. #define CSR_EWUP_BB(VAL)         ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U)))
  98. /**
  99.   * @}
  100.   */
  101.  
  102. /**
  103.   * @}
  104.   */
  105.  
  106. /* Private variables ---------------------------------------------------------*/
  107. /* Private function prototypes -----------------------------------------------*/
  108. /** @defgroup PWR_Private_Functions PWR Private Functions
  109.  * brief   WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section)
  110.  * @{
  111.  */
  112. static void PWR_OverloadWfe(void);
  113.  
  114. /* Private functions ---------------------------------------------------------*/
  115. __NOINLINE
  116. static void PWR_OverloadWfe(void)
  117. {
  118.   __asm volatile( "wfe" );
  119.   __asm volatile( "nop" );
  120. }
  121.  
  122. /**
  123.   * @}
  124.   */
  125.  
  126.  
  127. /** @defgroup PWR_Exported_Functions PWR Exported Functions
  128.   * @{
  129.   */
  130.  
  131. /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
  132.   *  @brief   Initialization and de-initialization functions
  133.   *
  134. @verbatim
  135.  ===============================================================================
  136.               ##### Initialization and de-initialization functions #####
  137.  ===============================================================================
  138.     [..]
  139.       After reset, the backup domain (RTC registers, RTC backup data
  140.       registers) is protected against possible unwanted
  141.       write accesses.
  142.       To enable access to the RTC Domain and RTC registers, proceed as follows:
  143.         (+) Enable the Power Controller (PWR) APB1 interface clock using the
  144.             __HAL_RCC_PWR_CLK_ENABLE() macro.
  145.         (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
  146.  
  147. @endverbatim
  148.   * @{
  149.   */
  150.  
  151. /**
  152.   * @brief  Deinitializes the PWR peripheral registers to their default reset values.  
  153.   * @retval None
  154.   */
  155. void HAL_PWR_DeInit(void)
  156. {
  157.   __HAL_RCC_PWR_FORCE_RESET();
  158.   __HAL_RCC_PWR_RELEASE_RESET();
  159. }
  160.  
  161. /**
  162.   * @brief  Enables access to the backup domain (RTC registers, RTC
  163.   *         backup data registers ).
  164.   * @note   If the HSE divided by 128 is used as the RTC clock, the
  165.   *         Backup Domain Access should be kept enabled.
  166.   * @retval None
  167.   */
  168. void HAL_PWR_EnableBkUpAccess(void)
  169. {
  170.   /* Enable access to RTC and backup registers */
  171.   *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
  172. }
  173.  
  174. /**
  175.   * @brief  Disables access to the backup domain (RTC registers, RTC
  176.   *         backup data registers).
  177.   * @note   If the HSE divided by 128 is used as the RTC clock, the
  178.   *         Backup Domain Access should be kept enabled.
  179.   * @retval None
  180.   */
  181. void HAL_PWR_DisableBkUpAccess(void)
  182. {
  183.   /* Disable access to RTC and backup registers */
  184.   *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
  185. }
  186.  
  187. /**
  188.   * @}
  189.   */
  190.  
  191. /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
  192.   * @brief    Low Power modes configuration functions
  193.   *
  194. @verbatim
  195.  ===============================================================================
  196.                  ##### Peripheral Control functions #####
  197.  ===============================================================================
  198.      
  199.     *** PVD configuration ***
  200.     =========================
  201.     [..]
  202.       (+) The PVD is used to monitor the VDD power supply by comparing it to a
  203.           threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
  204.  
  205.       (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
  206.           than the PVD threshold. This event is internally connected to the EXTI
  207.           line16 and can generate an interrupt if enabled. This is done through
  208.           __HAL_PVD_EXTI_ENABLE_IT() macro.
  209.       (+) The PVD is stopped in Standby mode.
  210.  
  211.     *** WakeUp pin configuration ***
  212.     ================================
  213.     [..]
  214.       (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
  215.           forced in input pull-down configuration and is active on rising edges.
  216.       (+) There is one WakeUp pin:
  217.           WakeUp Pin 1 on PA.00.
  218.  
  219.     [..]
  220.  
  221.     *** Low Power modes configuration ***
  222.     =====================================
  223.      [..]
  224.       The device features 3 low-power modes:
  225.       (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
  226.                       NVIC, SysTick, etc. are kept running
  227.       (+) Stop mode: All clocks are stopped
  228.       (+) Standby mode: 1.8V domain powered off
  229.  
  230.  
  231.    *** Sleep mode ***
  232.    ==================
  233.     [..]
  234.       (+) Entry:
  235.           The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
  236.               functions with
  237.           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  238.           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
  239.      
  240.       (+) Exit:
  241.         (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
  242.              controller (NVIC) can wake up the device from Sleep mode.
  243.         (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.
  244.            (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend)
  245.            (+++) Any EXTI Line (Internal or External) configured in Event mode
  246.  
  247.    *** Stop mode ***
  248.    =================
  249.     [..]
  250.       The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
  251.       clock gating. The voltage regulator can be configured either in normal or low-power mode.
  252.       In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
  253.       oscillators are disabled. SRAM and register contents are preserved.
  254.       In Stop mode, all I/O pins keep the same state as in Run mode.
  255.  
  256.       (+) Entry:
  257.            The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx )
  258.              function with:
  259.           (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.
  260.           (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
  261.           (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
  262.           (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
  263.       (+) Exit:
  264.           (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured
  265.           (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode.
  266.  
  267.    *** Standby mode ***
  268.    ====================
  269.      [..]
  270.       The Standby mode allows to achieve the lowest power consumption. It is based on the
  271.       Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
  272.       consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
  273.       switched off. SRAM and register contents are lost except for registers in the Backup domain
  274.       and Standby circuitry
  275.      
  276.       (+) Entry:
  277.         (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
  278.       (+) Exit:
  279.         (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
  280.              NRSTpin, IWDG Reset
  281.  
  282.    *** Auto-wakeup (AWU) from low-power mode ***
  283.        =============================================
  284.        [..]
  285.        
  286.        (+) The MCU can be woken up from low-power mode by an RTC Alarm event,
  287.            without depending on an external interrupt (Auto-wakeup mode).
  288.    
  289.        (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
  290.  
  291.            (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
  292.                 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
  293.  
  294.    *** PWR Workarounds linked to Silicon Limitation ***
  295.        ====================================================
  296.        [..]
  297.        Below the list of all silicon limitations known on STM32F1xx prouct.
  298.  
  299.        (#)Workarounds Implemented inside PWR HAL Driver
  300.           (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function    
  301.        
  302. @endverbatim
  303.   * @{
  304.   */
  305.  
  306. /**
  307.   * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
  308.   * @param  sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
  309.   *         information for the PVD.
  310.   * @note   Refer to the electrical characteristics of your device datasheet for
  311.   *         more details about the voltage threshold corresponding to each
  312.   *         detection level.
  313.   * @retval None
  314.   */
  315. void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
  316. {
  317.   /* Check the parameters */
  318.   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
  319.   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
  320.  
  321.   /* Set PLS[7:5] bits according to PVDLevel value */
  322.   MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
  323.  
  324.   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
  325.   __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
  326.   __HAL_PWR_PVD_EXTI_DISABLE_IT();
  327.   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
  328.   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
  329.  
  330.   /* Configure interrupt mode */
  331.   if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
  332.   {
  333.     __HAL_PWR_PVD_EXTI_ENABLE_IT();
  334.   }
  335.  
  336.   /* Configure event mode */
  337.   if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
  338.   {
  339.     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
  340.   }
  341.  
  342.   /* Configure the edge */
  343.   if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
  344.   {
  345.     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
  346.   }
  347.  
  348.   if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
  349.   {
  350.     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
  351.   }
  352. }
  353.  
  354. /**
  355.   * @brief  Enables the Power Voltage Detector(PVD).
  356.   * @retval None
  357.   */
  358. void HAL_PWR_EnablePVD(void)
  359. {
  360.   /* Enable the power voltage detector */
  361.   *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
  362. }
  363.  
  364. /**
  365.   * @brief  Disables the Power Voltage Detector(PVD).
  366.   * @retval None
  367.   */
  368. void HAL_PWR_DisablePVD(void)
  369. {
  370.   /* Disable the power voltage detector */
  371.   *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
  372. }
  373.  
  374. /**
  375.   * @brief Enables the WakeUp PINx functionality.
  376.   * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
  377.   *        This parameter can be one of the following values:
  378.   *           @arg PWR_WAKEUP_PIN1
  379.   * @retval None
  380.   */
  381. void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
  382. {
  383.   /* Check the parameter */
  384.   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
  385.   /* Enable the EWUPx pin */
  386.   *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
  387. }
  388.  
  389. /**
  390.   * @brief Disables the WakeUp PINx functionality.
  391.   * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
  392.   *        This parameter can be one of the following values:
  393.   *           @arg PWR_WAKEUP_PIN1
  394.   * @retval None
  395.   */
  396. void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
  397. {
  398.   /* Check the parameter */
  399.   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
  400.   /* Disable the EWUPx pin */
  401.   *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
  402. }
  403.  
  404. /**
  405.   * @brief Enters Sleep mode.
  406.   * @note  In Sleep mode, all I/O pins keep the same state as in Run mode.
  407.   * @param Regulator: Regulator state as no effect in SLEEP mode -  allows to support portability from legacy software
  408.   * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
  409.   *           When WFI entry is used, tick interrupt have to be disabled if not desired as
  410.   *           the interrupt wake up source.
  411.   *           This parameter can be one of the following values:
  412.   *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  413.   *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
  414.   * @retval None
  415.   */
  416. void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
  417. {
  418.   /* Check the parameters */
  419.   /* No check on Regulator because parameter not used in SLEEP mode */
  420.   /* Prevent unused argument(s) compilation warning */
  421.   UNUSED(Regulator);
  422.  
  423.   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
  424.  
  425.   /* Clear SLEEPDEEP bit of Cortex System Control Register */
  426.   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
  427.  
  428.   /* Select SLEEP mode entry -------------------------------------------------*/
  429.   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
  430.   {
  431.     /* Request Wait For Interrupt */
  432.     __WFI();
  433.   }
  434.   else
  435.   {
  436.     /* Request Wait For Event */
  437.     __SEV();
  438.     __WFE();
  439.     __WFE();
  440.   }
  441. }
  442.  
  443. /**
  444.   * @brief Enters Stop mode.
  445.   * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
  446.   * @note  When exiting Stop mode by using an interrupt or a wakeup event,
  447.   *        HSI RC oscillator is selected as system clock.
  448.   * @note  When the voltage regulator operates in low power mode, an additional
  449.   *         startup delay is incurred when waking up from Stop mode.
  450.   *         By keeping the internal regulator ON during Stop mode, the consumption
  451.   *         is higher although the startup time is reduced.    
  452.   * @param Regulator: Specifies the regulator state in Stop mode.
  453.   *          This parameter can be one of the following values:
  454.   *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
  455.   *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
  456.   * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
  457.   *          This parameter can be one of the following values:
  458.   *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
  459.   *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction  
  460.   * @retval None
  461.   */
  462. void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
  463. {
  464.   /* Check the parameters */
  465.   assert_param(IS_PWR_REGULATOR(Regulator));
  466.   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
  467.  
  468.   /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
  469.   CLEAR_BIT(PWR->CR,  PWR_CR_PDDS);
  470.  
  471.   /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */
  472.   MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);
  473.  
  474.   /* Set SLEEPDEEP bit of Cortex System Control Register */
  475.   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
  476.  
  477.   /* Select Stop mode entry --------------------------------------------------*/
  478.   if(STOPEntry == PWR_STOPENTRY_WFI)
  479.   {
  480.     /* Request Wait For Interrupt */
  481.     __WFI();
  482.   }
  483.   else
  484.   {
  485.     /* Request Wait For Event */
  486.     __SEV();
  487.     PWR_OverloadWfe(); /* WFE redefine locally */
  488.     PWR_OverloadWfe(); /* WFE redefine locally */
  489.   }
  490.   /* Reset SLEEPDEEP bit of Cortex System Control Register */
  491.   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
  492. }
  493.  
  494. /**
  495.   * @brief Enters Standby mode.
  496.   * @note  In Standby mode, all I/O pins are high impedance except for:
  497.   *          - Reset pad (still available)
  498.   *          - TAMPER pin if configured for tamper or calibration out.
  499.   *          - WKUP pin (PA0) if enabled.
  500.   * @retval None
  501.   */
  502. void HAL_PWR_EnterSTANDBYMode(void)
  503. {
  504.   /* Select Standby mode */
  505.   SET_BIT(PWR->CR, PWR_CR_PDDS);
  506.  
  507.   /* Set SLEEPDEEP bit of Cortex System Control Register */
  508.   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
  509.  
  510.   /* This option is used to ensure that store operations are completed */
  511. #if defined ( __CC_ARM)
  512.   __force_stores();
  513. #endif
  514.   /* Request Wait For Interrupt */
  515.   __WFI();
  516. }
  517.  
  518.  
  519. /**
  520.   * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
  521.   * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
  522.   *       re-enters SLEEP mode when an interruption handling is over.
  523.   *       Setting this bit is useful when the processor is expected to run only on
  524.   *       interruptions handling.        
  525.   * @retval None
  526.   */
  527. void HAL_PWR_EnableSleepOnExit(void)
  528. {
  529.   /* Set SLEEPONEXIT bit of Cortex System Control Register */
  530.   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
  531. }
  532.  
  533.  
  534. /**
  535.   * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
  536.   * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
  537.   *       re-enters SLEEP mode when an interruption handling is over.          
  538.   * @retval None
  539.   */
  540. void HAL_PWR_DisableSleepOnExit(void)
  541. {
  542.   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
  543.   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
  544. }
  545.  
  546.  
  547. /**
  548.   * @brief Enables CORTEX M3 SEVONPEND bit.
  549.   * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
  550.   *       WFE to wake up when an interrupt moves from inactive to pended.
  551.   * @retval None
  552.   */
  553. void HAL_PWR_EnableSEVOnPend(void)
  554. {
  555.   /* Set SEVONPEND bit of Cortex System Control Register */
  556.   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
  557. }
  558.  
  559.  
  560. /**
  561.   * @brief Disables CORTEX M3 SEVONPEND bit.
  562.   * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
  563.   *       WFE to wake up when an interrupt moves from inactive to pended.        
  564.   * @retval None
  565.   */
  566. void HAL_PWR_DisableSEVOnPend(void)
  567. {
  568.   /* Clear SEVONPEND bit of Cortex System Control Register */
  569.   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
  570. }
  571.  
  572.  
  573.  
  574. /**
  575.   * @brief  This function handles the PWR PVD interrupt request.
  576.   * @note   This API should be called under the PVD_IRQHandler().
  577.   * @retval None
  578.   */
  579. void HAL_PWR_PVD_IRQHandler(void)
  580. {
  581.   /* Check PWR exti flag */
  582.   if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
  583.   {
  584.     /* PWR PVD interrupt user callback */
  585.     HAL_PWR_PVDCallback();
  586.  
  587.     /* Clear PWR Exti pending bit */
  588.     __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
  589.   }
  590. }
  591.  
  592. /**
  593.   * @brief  PWR PVD interrupt callback
  594.   * @retval None
  595.   */
  596. __weak void HAL_PWR_PVDCallback(void)
  597. {
  598.   /* NOTE : This function Should not be modified, when the callback is needed,
  599.             the HAL_PWR_PVDCallback could be implemented in the user file
  600.    */
  601. }
  602.  
  603. /**
  604.   * @}
  605.   */
  606.  
  607. /**
  608.   * @}
  609.   */
  610.  
  611. #endif /* HAL_PWR_MODULE_ENABLED */
  612. /**
  613.   * @}
  614.   */
  615.  
  616. /**
  617.   * @}
  618.   */
  619.