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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_nor.c
  4.   * @author  MCD Application Team
  5.   * @version V1.0.4
  6.   * @date    29-April-2016
  7.   * @brief   NOR HAL module driver.
  8.   *          This file provides a generic firmware to drive NOR memories mounted
  9.   *          as external device.
  10.   *        
  11.   @verbatim
  12.   ==============================================================================
  13.                      ##### How to use this driver #####
  14.   ==============================================================================      
  15.     [..]
  16.       This driver is a generic layered driver which contains a set of APIs used to
  17.       control NOR flash memories. It uses the FSMC layer functions to interface
  18.       with NOR devices. This driver is used as follows:
  19.    
  20.       (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
  21.           with control and timing parameters for both normal and extended mode.
  22.            
  23.       (+) Read NOR flash memory manufacturer code and device IDs using the function
  24.           HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
  25.           structure declared by the function caller.
  26.        
  27.       (+) Access NOR flash memory by read/write data unit operations using the functions
  28.           HAL_NOR_Read(), HAL_NOR_Program().
  29.        
  30.       (+) Perform NOR flash erase block/chip operations using the functions
  31.           HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
  32.        
  33.       (+) Read the NOR flash CFI (common flash interface) IDs using the function
  34.           HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
  35.           structure declared by the function caller.
  36.        
  37.       (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
  38.           HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation  
  39.        
  40.       (+) You can monitor the NOR device HAL state by calling the function
  41.           HAL_NOR_GetState()
  42.     [..]
  43.      (@) This driver is a set of generic APIs which handle standard NOR flash operations.
  44.          If a NOR flash device contains different operations and/or implementations,
  45.          it should be implemented separately.
  46.  
  47.      *** NOR HAL driver macros list ***
  48.      =============================================
  49.      [..]
  50.        Below the list of most used macros in NOR HAL driver.
  51.        
  52.       (+) NOR_WRITE : NOR memory write data to specified address
  53.  
  54.   @endverbatim
  55.   ******************************************************************************
  56.   * @attention
  57.   *
  58.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  59.   *
  60.   * Redistribution and use in source and binary forms, with or without modification,
  61.   * are permitted provided that the following conditions are met:
  62.   *   1. Redistributions of source code must retain the above copyright notice,
  63.   *      this list of conditions and the following disclaimer.
  64.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  65.   *      this list of conditions and the following disclaimer in the documentation
  66.   *      and/or other materials provided with the distribution.
  67.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  68.   *      may be used to endorse or promote products derived from this software
  69.   *      without specific prior written permission.
  70.   *
  71.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  72.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  73.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  74.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  75.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  76.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  77.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  78.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  79.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  80.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  81.   *
  82.   ******************************************************************************
  83.   */
  84.  
  85. /* Includes ------------------------------------------------------------------*/
  86. #include "stm32f1xx_hal.h"
  87.  
  88. /** @addtogroup STM32F1xx_HAL_Driver
  89.   * @{
  90.   */
  91.  
  92. #ifdef HAL_NOR_MODULE_ENABLED
  93. #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
  94.  
  95. /** @defgroup NOR NOR
  96.   * @brief NOR driver modules
  97.   * @{
  98.   */
  99. /* Private typedef -----------------------------------------------------------*/
  100. /* Private define ------------------------------------------------------------*/
  101. /** @defgroup NOR_Private_Constants NOR Private Constants
  102.   * @{
  103.   */
  104.  
  105. /* Constants to define address to set to write a command */
  106. #define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555
  107. #define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055
  108. #define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AA
  109. #define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555
  110. #define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555
  111. #define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AA
  112. #define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555
  113.  
  114. /* Constants to define data to program a command */
  115. #define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0
  116. #define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AA
  117. #define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055
  118. #define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090
  119. #define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0
  120. #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080
  121. #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AA
  122. #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055
  123. #define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010
  124. #define NOR_CMD_DATA_CFI                      (uint16_t)0x0098
  125.  
  126. #define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25
  127. #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29
  128. #define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30
  129.  
  130. /* Mask on NOR STATUS REGISTER */
  131. #define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020
  132. #define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040
  133.  
  134. /**
  135.   * @}
  136.   */
  137.  
  138. /* Private macro -------------------------------------------------------------*/
  139. /** @defgroup NOR_Private_Macros NOR Private Macros
  140.   * @{
  141.   */
  142.  
  143. /**
  144.   * @}
  145.   */
  146.  
  147. /* Private variables ---------------------------------------------------------*/
  148.  
  149. /** @defgroup NOR_Private_Variables NOR Private Variables
  150.   * @{
  151.   */
  152.  
  153. static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
  154.  
  155. /**
  156.   * @}
  157.   */
  158.  
  159. /* Private function prototypes -----------------------------------------------*/
  160. /* Private functions ---------------------------------------------------------*/
  161.  
  162. /** @defgroup NOR_Exported_Functions NOR Exported Functions
  163.   * @{
  164.   */
  165.  
  166. /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
  167.   * @brief    Initialization and Configuration functions
  168.   *
  169.   @verbatim    
  170.   ==============================================================================
  171.            ##### NOR Initialization and de_initialization functions #####
  172.   ==============================================================================
  173.   [..]  
  174.     This section provides functions allowing to initialize/de-initialize
  175.     the NOR memory
  176.  
  177. @endverbatim
  178.   * @{
  179.   */
  180.    
  181. /**
  182.   * @brief  Perform the NOR memory Initialization sequence
  183.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  184.   *                the configuration information for NOR module.
  185.   * @param  Timing: pointer to NOR control timing structure
  186.   * @param  ExtTiming: pointer to NOR extended mode timing structure    
  187.   * @retval HAL status
  188.   */
  189. HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
  190. {
  191.   /* Check the NOR handle parameter */
  192.   if(hnor == NULL)
  193.   {
  194.      return HAL_ERROR;
  195.   }
  196.  
  197.   if(hnor->State == HAL_NOR_STATE_RESET)
  198.   {
  199.     /* Allocate lock resource and initialize it */
  200.     hnor->Lock = HAL_UNLOCKED;
  201.    
  202.     /* Initialize the low level hardware (MSP) */
  203.     HAL_NOR_MspInit(hnor);
  204.   }
  205.  
  206.   /* Initialize NOR control Interface */
  207.   FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
  208.  
  209.   /* Initialize NOR timing Interface */
  210.   FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
  211.  
  212.   /* Initialize NOR extended mode timing Interface */
  213.   FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
  214.  
  215.   /* Enable the NORSRAM device */
  216.   __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);  
  217.  
  218.   /* Initialize NOR Memory Data Width*/
  219.   if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
  220.   {
  221.     uwNORMemoryDataWidth = NOR_MEMORY_8B;
  222.   }
  223.   else
  224.   {
  225.     uwNORMemoryDataWidth = NOR_MEMORY_16B;
  226.   }
  227.  
  228.   /* Check the NOR controller state */
  229.   hnor->State = HAL_NOR_STATE_READY;
  230.  
  231.   return HAL_OK;
  232. }
  233.  
  234. /**
  235.   * @brief  Perform NOR memory De-Initialization sequence
  236.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  237.   *                the configuration information for NOR module.
  238.   * @retval HAL status
  239.   */
  240. HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)  
  241. {
  242.   /* De-Initialize the low level hardware (MSP) */
  243.   HAL_NOR_MspDeInit(hnor);
  244.  
  245.   /* Configure the NOR registers with their reset values */
  246.   FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
  247.  
  248.   /* Update the NOR controller state */
  249.   hnor->State = HAL_NOR_STATE_RESET;
  250.  
  251.   /* Release Lock */
  252.   __HAL_UNLOCK(hnor);
  253.  
  254.   return HAL_OK;
  255. }
  256.  
  257. /**
  258.   * @brief  NOR MSP Init
  259.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  260.   *                the configuration information for NOR module.
  261.   * @retval None
  262.   */
  263. __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
  264. {
  265.   /* Prevent unused argument(s) compilation warning */
  266.   UNUSED(hnor);
  267.   /* NOTE : This function Should not be modified, when the callback is needed,
  268.             the HAL_NOR_MspInit could be implemented in the user file
  269.    */
  270. }
  271.  
  272. /**
  273.   * @brief  NOR MSP DeInit
  274.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  275.   *                the configuration information for NOR module.
  276.   * @retval None
  277.   */
  278. __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
  279. {
  280.   /* Prevent unused argument(s) compilation warning */
  281.   UNUSED(hnor);
  282.   /* NOTE : This function Should not be modified, when the callback is needed,
  283.             the HAL_NOR_MspDeInit could be implemented in the user file
  284.    */
  285. }
  286.  
  287. /**
  288.   * @brief  NOR MSP Wait fro Ready/Busy signal
  289.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  290.   *                the configuration information for NOR module.
  291.   * @param  Timeout: Maximum timeout value
  292.   * @retval None
  293.   */
  294. __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
  295. {
  296.   /* Prevent unused argument(s) compilation warning */
  297.   UNUSED(hnor);
  298.   /* NOTE : This function Should not be modified, when the callback is needed,
  299.             the HAL_NOR_MspWait could be implemented in the user file
  300.    */
  301. }
  302.  
  303. /**
  304.   * @}
  305.   */
  306.  
  307. /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
  308.   * @brief    Input Output and memory control functions
  309.   *
  310.   @verbatim    
  311.   ==============================================================================
  312.                 ##### NOR Input and Output functions #####
  313.   ==============================================================================
  314.   [..]  
  315.     This section provides functions allowing to use and control the NOR memory
  316.  
  317. @endverbatim
  318.   * @{
  319.   */
  320.  
  321. /**
  322.   * @brief  Read NOR flash IDs
  323.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  324.   *                the configuration information for NOR module.
  325.   * @param  pNOR_ID : pointer to NOR ID structure
  326.   * @retval HAL status
  327.   */
  328. HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
  329. {
  330.   uint32_t deviceaddress = 0;
  331.  
  332.   /* Process Locked */
  333.   __HAL_LOCK(hnor);
  334.  
  335.   /* Check the NOR controller state */
  336.   if(hnor->State == HAL_NOR_STATE_BUSY)
  337.   {
  338.      return HAL_BUSY;
  339.   }
  340.  
  341.   /* Select the NOR device address */
  342.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  343.   {
  344.     deviceaddress = NOR_MEMORY_ADRESS1;
  345.   }
  346.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  347.   {
  348.     deviceaddress = NOR_MEMORY_ADRESS2;
  349.   }
  350.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  351.   {
  352.     deviceaddress = NOR_MEMORY_ADRESS3;
  353.   }
  354.   else /* FSMC_NORSRAM_BANK4 */
  355.   {
  356.     deviceaddress = NOR_MEMORY_ADRESS4;
  357.   }  
  358.    
  359.   /* Update the NOR controller state */
  360.   hnor->State = HAL_NOR_STATE_BUSY;
  361.  
  362.   /* Send read ID command */
  363.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  364.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  365.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
  366.  
  367.   /* Read the NOR IDs */
  368.   pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
  369.   pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
  370.   pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
  371.   pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
  372.  
  373.   /* Check the NOR controller state */
  374.   hnor->State = HAL_NOR_STATE_READY;
  375.  
  376.   /* Process unlocked */
  377.   __HAL_UNLOCK(hnor);  
  378.  
  379.   return HAL_OK;
  380. }
  381.  
  382. /**
  383.   * @brief  Returns the NOR memory to Read mode.
  384.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  385.   *                the configuration information for NOR module.
  386.   * @retval HAL status
  387.   */
  388. HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
  389. {
  390.   uint32_t deviceaddress = 0;  
  391.  
  392.   /* Process Locked */
  393.   __HAL_LOCK(hnor);
  394.  
  395.   /* Check the NOR controller state */
  396.   if(hnor->State == HAL_NOR_STATE_BUSY)
  397.   {
  398.      return HAL_BUSY;
  399.   }
  400.  
  401.   /* Select the NOR device address */
  402.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  403.   {
  404.     deviceaddress = NOR_MEMORY_ADRESS1;
  405.   }
  406.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  407.   {
  408.     deviceaddress = NOR_MEMORY_ADRESS2;
  409.   }
  410.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  411.   {
  412.     deviceaddress = NOR_MEMORY_ADRESS3;
  413.   }
  414.   else /* FSMC_NORSRAM_BANK4 */
  415.   {
  416.     deviceaddress = NOR_MEMORY_ADRESS4;
  417.   }  
  418.  
  419.   NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
  420.  
  421.   /* Check the NOR controller state */
  422.   hnor->State = HAL_NOR_STATE_READY;
  423.  
  424.   /* Process unlocked */
  425.   __HAL_UNLOCK(hnor);  
  426.  
  427.   return HAL_OK;
  428. }
  429.  
  430. /**
  431.   * @brief  Read data from NOR memory
  432.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  433.   *                the configuration information for NOR module.
  434.   * @param  pAddress: pointer to Device address
  435.   * @param  pData : pointer to read data  
  436.   * @retval HAL status
  437.   */
  438. HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
  439. {
  440.   uint32_t deviceaddress = 0;
  441.  
  442.   /* Process Locked */
  443.   __HAL_LOCK(hnor);
  444.  
  445.   /* Check the NOR controller state */
  446.   if(hnor->State == HAL_NOR_STATE_BUSY)
  447.   {
  448.      return HAL_BUSY;
  449.   }
  450.  
  451.   /* Select the NOR device address */
  452.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  453.   {
  454.     deviceaddress = NOR_MEMORY_ADRESS1;
  455.   }
  456.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  457.   {
  458.     deviceaddress = NOR_MEMORY_ADRESS2;
  459.   }
  460.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  461.   {
  462.     deviceaddress = NOR_MEMORY_ADRESS3;
  463.   }
  464.   else /* FSMC_NORSRAM_BANK4 */
  465.   {
  466.     deviceaddress = NOR_MEMORY_ADRESS4;
  467.   }
  468.    
  469.   /* Update the NOR controller state */
  470.   hnor->State = HAL_NOR_STATE_BUSY;
  471.  
  472.   /* Send read data command */
  473.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  474.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);  
  475.   NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
  476.  
  477.   /* Read the data */
  478.   *pData = *(__IO uint32_t *)(uint32_t)pAddress;
  479.  
  480.   /* Check the NOR controller state */
  481.   hnor->State = HAL_NOR_STATE_READY;
  482.  
  483.   /* Process unlocked */
  484.   __HAL_UNLOCK(hnor);
  485.  
  486.   return HAL_OK;  
  487. }
  488.  
  489. /**
  490.   * @brief  Program data to NOR memory
  491.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  492.   *                the configuration information for NOR module.
  493.   * @param  pAddress: Device address
  494.   * @param  pData : pointer to the data to write  
  495.   * @retval HAL status
  496.   */
  497. HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
  498. {
  499.   uint32_t deviceaddress = 0;
  500.  
  501.   /* Process Locked */
  502.   __HAL_LOCK(hnor);
  503.  
  504.   /* Check the NOR controller state */
  505.   if(hnor->State == HAL_NOR_STATE_BUSY)
  506.   {
  507.      return HAL_BUSY;
  508.   }
  509.  
  510.   /* Select the NOR device address */
  511.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  512.   {
  513.     deviceaddress = NOR_MEMORY_ADRESS1;
  514.   }
  515.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  516.   {
  517.     deviceaddress = NOR_MEMORY_ADRESS2;
  518.   }
  519.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  520.   {
  521.     deviceaddress = NOR_MEMORY_ADRESS3;
  522.   }
  523.   else /* FSMC_NORSRAM_BANK4 */
  524.   {
  525.     deviceaddress = NOR_MEMORY_ADRESS4;
  526.   }
  527.    
  528.   /* Update the NOR controller state */
  529.   hnor->State = HAL_NOR_STATE_BUSY;
  530.  
  531.   /* Send program data command */
  532.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  533.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  534.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
  535.  
  536.   /* Write the data */
  537.   NOR_WRITE(pAddress, *pData);
  538.  
  539.   /* Check the NOR controller state */
  540.   hnor->State = HAL_NOR_STATE_READY;
  541.  
  542.   /* Process unlocked */
  543.   __HAL_UNLOCK(hnor);
  544.  
  545.   return HAL_OK;  
  546. }
  547.  
  548. /**
  549.   * @brief  Reads a block of data from the FSMC NOR memory.
  550.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  551.   *                the configuration information for NOR module.
  552.   * @param  uwAddress: NOR memory internal address to read from.
  553.   * @param  pData: pointer to the buffer that receives the data read from the
  554.   *         NOR memory.
  555.   * @param  uwBufferSize : number of Half word to read.
  556.   * @retval HAL status
  557.   */
  558. HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
  559. {
  560.   uint32_t deviceaddress = 0;
  561.  
  562.   /* Process Locked */
  563.   __HAL_LOCK(hnor);
  564.  
  565.   /* Check the NOR controller state */
  566.   if(hnor->State == HAL_NOR_STATE_BUSY)
  567.   {
  568.      return HAL_BUSY;
  569.   }
  570.  
  571.   /* Select the NOR device address */
  572.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  573.   {
  574.     deviceaddress = NOR_MEMORY_ADRESS1;
  575.   }
  576.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  577.   {
  578.     deviceaddress = NOR_MEMORY_ADRESS2;
  579.   }
  580.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  581.   {
  582.     deviceaddress = NOR_MEMORY_ADRESS3;
  583.   }
  584.   else /* FSMC_NORSRAM_BANK4 */
  585.   {
  586.     deviceaddress = NOR_MEMORY_ADRESS4;
  587.   }  
  588.    
  589.   /* Update the NOR controller state */
  590.   hnor->State = HAL_NOR_STATE_BUSY;
  591.  
  592.   /* Send read data command */
  593.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  594.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);  
  595.   NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
  596.  
  597.   /* Read buffer */
  598.   while( uwBufferSize > 0)
  599.   {
  600.     *pData++ = *(__IO uint16_t *)uwAddress;
  601.     uwAddress += 2;
  602.     uwBufferSize--;
  603.   }
  604.  
  605.   /* Check the NOR controller state */
  606.   hnor->State = HAL_NOR_STATE_READY;
  607.  
  608.   /* Process unlocked */
  609.   __HAL_UNLOCK(hnor);
  610.  
  611.   return HAL_OK;  
  612. }
  613.  
  614. /**
  615.   * @brief  Writes a half-word buffer to the FSMC NOR memory. This function
  616.   *         must be used only with S29GL128P NOR memory.
  617.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  618.   *                the configuration information for NOR module.
  619.   * @param  uwAddress: NOR memory internal address from which the data
  620.   * @note   Some NOR memory need Address aligned to xx bytes (can be aligned to
  621.   *          64 bytes boundary for example).
  622.   * @param  pData: pointer to source data buffer.
  623.   * @param  uwBufferSize: number of Half words to write.
  624.   * @note   The maximum buffer size allowed is NOR memory dependent
  625.   *         (can be 64 Bytes max for example).
  626.   * @retval HAL status
  627.   */
  628. HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
  629. {
  630.   uint16_t * p_currentaddress = (uint16_t *)NULL;
  631.   uint16_t * p_endaddress = (uint16_t *)NULL;
  632.   uint32_t lastloadedaddress = 0, deviceaddress = 0;
  633.  
  634.   /* Process Locked */
  635.   __HAL_LOCK(hnor);
  636.  
  637.   /* Check the NOR controller state */
  638.   if(hnor->State == HAL_NOR_STATE_BUSY)
  639.   {
  640.      return HAL_BUSY;
  641.   }
  642.  
  643.   /* Select the NOR device address */
  644.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  645.   {
  646.     deviceaddress = NOR_MEMORY_ADRESS1;
  647.   }
  648.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  649.   {
  650.     deviceaddress = NOR_MEMORY_ADRESS2;
  651.   }
  652.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  653.   {
  654.     deviceaddress = NOR_MEMORY_ADRESS3;
  655.   }
  656.   else /* FSMC_NORSRAM_BANK4 */
  657.   {
  658.     deviceaddress = NOR_MEMORY_ADRESS4;
  659.   }  
  660.    
  661.   /* Update the NOR controller state */
  662.   hnor->State = HAL_NOR_STATE_BUSY;
  663.  
  664.   /* Initialize variables */
  665.   p_currentaddress  = (uint16_t*)((uint32_t)(uwAddress));
  666.   p_endaddress      = p_currentaddress + (uwBufferSize-1);
  667.   lastloadedaddress = (uint32_t)(uwAddress);
  668.  
  669.   /* Issue unlock command sequence */
  670.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  671.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  672.  
  673.   /* Write Buffer Load Command */
  674.   NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
  675.   NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
  676.  
  677.   /* Load Data into NOR Buffer */
  678.   while(p_currentaddress <= p_endaddress)
  679.   {
  680.     /* Store last loaded address & data value (for polling) */
  681.     lastloadedaddress = (uint32_t)p_currentaddress;
  682.  
  683.     NOR_WRITE(p_currentaddress, *pData++);
  684.    
  685.     p_currentaddress++;
  686.   }
  687.  
  688.   NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
  689.  
  690.   /* Check the NOR controller state */
  691.   hnor->State = HAL_NOR_STATE_READY;
  692.  
  693.   /* Process unlocked */
  694.   __HAL_UNLOCK(hnor);
  695.  
  696.   return HAL_OK;
  697.  
  698. }
  699.  
  700. /**
  701.   * @brief  Erase the specified block of the NOR memory
  702.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  703.   *                the configuration information for NOR module.
  704.   * @param  BlockAddress : Block to erase address
  705.   * @param  Address: Device address
  706.   * @retval HAL status
  707.   */
  708. HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
  709. {
  710.   uint32_t deviceaddress = 0;
  711.  
  712.   /* Process Locked */
  713.   __HAL_LOCK(hnor);
  714.  
  715.   /* Check the NOR controller state */
  716.   if(hnor->State == HAL_NOR_STATE_BUSY)
  717.   {
  718.      return HAL_BUSY;
  719.   }
  720.  
  721.   /* Select the NOR device address */
  722.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  723.   {
  724.     deviceaddress = NOR_MEMORY_ADRESS1;
  725.   }
  726.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  727.   {
  728.     deviceaddress = NOR_MEMORY_ADRESS2;
  729.   }
  730.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  731.   {
  732.     deviceaddress = NOR_MEMORY_ADRESS3;
  733.   }
  734.   else /* FSMC_NORSRAM_BANK4 */
  735.   {
  736.     deviceaddress = NOR_MEMORY_ADRESS4;
  737.   }
  738.    
  739.   /* Update the NOR controller state */
  740.   hnor->State = HAL_NOR_STATE_BUSY;
  741.  
  742.   /* Send block erase command sequence */
  743.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  744.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  745.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
  746.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
  747.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
  748.   NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
  749.  
  750.   /* Check the NOR memory status and update the controller state */
  751.   hnor->State = HAL_NOR_STATE_READY;
  752.    
  753.   /* Process unlocked */
  754.   __HAL_UNLOCK(hnor);
  755.  
  756.   return HAL_OK;
  757.  
  758. }
  759.  
  760. /**
  761.   * @brief  Erase the entire NOR chip.
  762.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  763.   *                the configuration information for NOR module.
  764.   * @param  Address : Device address  
  765.   * @retval HAL status
  766.   */
  767. HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
  768. {
  769.   uint32_t deviceaddress = 0;
  770.  
  771.   /* Process Locked */
  772.   __HAL_LOCK(hnor);
  773.  
  774.   /* Check the NOR controller state */
  775.   if(hnor->State == HAL_NOR_STATE_BUSY)
  776.   {
  777.      return HAL_BUSY;
  778.   }
  779.  
  780.   /* Select the NOR device address */
  781.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  782.   {
  783.     deviceaddress = NOR_MEMORY_ADRESS1;
  784.   }
  785.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  786.   {
  787.     deviceaddress = NOR_MEMORY_ADRESS2;
  788.   }
  789.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  790.   {
  791.     deviceaddress = NOR_MEMORY_ADRESS3;
  792.   }
  793.   else /* FSMC_NORSRAM_BANK4 */
  794.   {
  795.     deviceaddress = NOR_MEMORY_ADRESS4;
  796.   }
  797.    
  798.   /* Update the NOR controller state */
  799.   hnor->State = HAL_NOR_STATE_BUSY;  
  800.    
  801.   /* Send NOR chip erase command sequence */
  802.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  803.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  804.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
  805.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
  806.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);  
  807.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
  808.  
  809.   /* Check the NOR memory status and update the controller state */
  810.   hnor->State = HAL_NOR_STATE_READY;
  811.    
  812.   /* Process unlocked */
  813.   __HAL_UNLOCK(hnor);
  814.  
  815.   return HAL_OK;  
  816. }
  817.  
  818. /**
  819.   * @brief  Read NOR flash CFI IDs
  820.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  821.   *                the configuration information for NOR module.
  822.   * @param  pNOR_CFI : pointer to NOR CFI IDs structure  
  823.   * @retval HAL status
  824.   */
  825. HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
  826. {
  827.   uint32_t deviceaddress = 0;
  828.  
  829.   /* Process Locked */
  830.   __HAL_LOCK(hnor);
  831.  
  832.   /* Check the NOR controller state */
  833.   if(hnor->State == HAL_NOR_STATE_BUSY)
  834.   {
  835.      return HAL_BUSY;
  836.   }
  837.  
  838.   /* Select the NOR device address */
  839.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  840.   {
  841.     deviceaddress = NOR_MEMORY_ADRESS1;
  842.   }
  843.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  844.   {
  845.     deviceaddress = NOR_MEMORY_ADRESS2;
  846.   }
  847.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  848.   {
  849.     deviceaddress = NOR_MEMORY_ADRESS3;
  850.   }
  851.   else /* FSMC_NORSRAM_BANK4 */
  852.   {
  853.     deviceaddress = NOR_MEMORY_ADRESS4;
  854.   }  
  855.    
  856.   /* Update the NOR controller state */
  857.   hnor->State = HAL_NOR_STATE_BUSY;
  858.  
  859.   /* Send read CFI query command */
  860.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
  861.  
  862.   /* read the NOR CFI information */
  863.   pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
  864.   pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
  865.   pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
  866.   pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
  867.  
  868.   /* Check the NOR controller state */
  869.   hnor->State = HAL_NOR_STATE_READY;
  870.  
  871.   /* Process unlocked */
  872.   __HAL_UNLOCK(hnor);
  873.  
  874.   return HAL_OK;
  875. }
  876.  
  877. /**
  878.   * @}
  879.   */
  880.  
  881. /** @defgroup NOR_Exported_Functions_Group3 Control functions
  882.  *  @brief   management functions
  883.  *
  884. @verbatim  
  885.   ==============================================================================
  886.                         ##### NOR Control functions #####
  887.   ==============================================================================
  888.   [..]
  889.     This subsection provides a set of functions allowing to control dynamically
  890.     the NOR interface.
  891.  
  892. @endverbatim
  893.   * @{
  894.   */
  895.    
  896. /**
  897.   * @brief  Enables dynamically NOR write operation.
  898.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  899.   *                the configuration information for NOR module.
  900.   * @retval HAL status
  901.   */
  902. HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
  903. {
  904.   /* Process Locked */
  905.   __HAL_LOCK(hnor);
  906.  
  907.   /* Enable write operation */
  908.   FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
  909.  
  910.   /* Update the NOR controller state */
  911.   hnor->State = HAL_NOR_STATE_READY;
  912.  
  913.   /* Process unlocked */
  914.   __HAL_UNLOCK(hnor);
  915.  
  916.   return HAL_OK;  
  917. }
  918.  
  919. /**
  920.   * @brief  Disables dynamically NOR write operation.
  921.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  922.   *                the configuration information for NOR module.
  923.   * @retval HAL status
  924.   */
  925. HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
  926. {
  927.   /* Process Locked */
  928.   __HAL_LOCK(hnor);
  929.  
  930.   /* Update the SRAM controller state */
  931.   hnor->State = HAL_NOR_STATE_BUSY;
  932.    
  933.   /* Disable write operation */
  934.   FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
  935.  
  936.   /* Update the NOR controller state */
  937.   hnor->State = HAL_NOR_STATE_PROTECTED;
  938.  
  939.   /* Process unlocked */
  940.   __HAL_UNLOCK(hnor);
  941.  
  942.   return HAL_OK;  
  943. }
  944.  
  945. /**
  946.   * @}
  947.   */  
  948.  
  949. /** @defgroup NOR_Exported_Functions_Group4 State functions
  950.  *  @brief   Peripheral State functions
  951.  *
  952. @verbatim  
  953.   ==============================================================================
  954.                       ##### NOR State functions #####
  955.   ==============================================================================  
  956.   [..]
  957.     This subsection permits to get in run-time the status of the NOR controller
  958.     and the data flow.
  959.  
  960. @endverbatim
  961.   * @{
  962.   */
  963.  
  964. /**
  965.   * @brief  return the NOR controller state
  966.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  967.   *                the configuration information for NOR module.
  968.   * @retval NOR controller state
  969.   */
  970. HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
  971. {
  972.   return hnor->State;
  973. }
  974.  
  975. /**
  976.   * @brief  Returns the NOR operation status.
  977.   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
  978.   *                the configuration information for NOR module.  
  979.   * @param  Address: Device address
  980.   * @param  Timeout: NOR progamming Timeout
  981.   * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
  982.   *         or HAL_NOR_STATUS_TIMEOUT
  983.   */
  984. HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
  985. {
  986.   HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
  987.   uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
  988.   uint32_t tickstart = 0;
  989.  
  990.   /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
  991.   HAL_NOR_MspWait(hnor, Timeout);
  992.  
  993.   /* Get tick */
  994.   tickstart = HAL_GetTick();
  995.   while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
  996.   {
  997.     /* Check for the Timeout */
  998.     if(Timeout != HAL_MAX_DELAY)
  999.     {
  1000.       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
  1001.       {
  1002.         status = HAL_NOR_STATUS_TIMEOUT;
  1003.       }  
  1004.     }
  1005.  
  1006.     /* Read NOR status register (DQ6 and DQ5) */
  1007.     tmp_sr1 = *(__IO uint16_t *)Address;
  1008.     tmp_sr2 = *(__IO uint16_t *)Address;
  1009.  
  1010.     /* If DQ6 did not toggle between the two reads then return NOR_Success */
  1011.     if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
  1012.     {
  1013.       return HAL_NOR_STATUS_SUCCESS;
  1014.     }
  1015.    
  1016.     if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
  1017.     {
  1018.       status = HAL_NOR_STATUS_ONGOING;
  1019.     }
  1020.    
  1021.     tmp_sr1 = *(__IO uint16_t *)Address;
  1022.     tmp_sr2 = *(__IO uint16_t *)Address;
  1023.  
  1024.     /* If DQ6 did not toggle between the two reads then return NOR_Success */
  1025.     if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
  1026.     {
  1027.       return HAL_NOR_STATUS_SUCCESS;
  1028.     }
  1029.     else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
  1030.     {
  1031.       return HAL_NOR_STATUS_ERROR;
  1032.     }
  1033.   }
  1034.  
  1035.   /* Return the operation status */
  1036.   return status;
  1037. }
  1038.  
  1039. /**
  1040.   * @}
  1041.   */
  1042.  
  1043. /**
  1044.   * @}
  1045.   */
  1046. /**
  1047.   * @}
  1048.   */
  1049. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
  1050. #endif /* HAL_NOR_MODULE_ENABLED */
  1051.  
  1052. /**
  1053.   * @}
  1054.   */
  1055.  
  1056. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1057.