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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_adc_ex.c
  4.   * @author  MCD Application Team
  5.   * @brief   This file provides firmware functions to manage the following
  6.   *          functionalities of the Analog to Digital Convertor (ADC)
  7.   *          peripheral:
  8.   *           + Operation functions
  9.   *             ++ Start, stop, get result of conversions of injected
  10.   *                group, using 2 possible modes: polling, interruption.
  11.   *             ++ Multimode feature (available on devices with 2 ADCs or more)
  12.   *             ++ Calibration (ADC automatic self-calibration)
  13.   *           + Control functions
  14.   *             ++ Channels configuration on injected group
  15.   *          Other functions (generic functions) are available in file
  16.   *          "stm32f1xx_hal_adc.c".
  17.   *
  18.   @verbatim
  19.   [..]
  20.   (@) Sections "ADC peripheral features" and "How to use this driver" are
  21.       available in file of generic functions "stm32f1xx_hal_adc.c".
  22.   [..]
  23.   @endverbatim
  24.   ******************************************************************************
  25.   * @attention
  26.   *
  27.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  28.   * All rights reserved.</center></h2>
  29.   *
  30.   * This software component is licensed by ST under BSD 3-Clause license,
  31.   * the "License"; You may not use this file except in compliance with the
  32.   * License. You may obtain a copy of the License at:
  33.   *                        opensource.org/licenses/BSD-3-Clause
  34.   *
  35.   ******************************************************************************
  36.   */
  37.  
  38. /* Includes ------------------------------------------------------------------*/
  39. #include "stm32f1xx_hal.h"
  40.  
  41. /** @addtogroup STM32F1xx_HAL_Driver
  42.   * @{
  43.   */
  44.  
  45. /** @defgroup ADCEx ADCEx
  46.   * @brief ADC Extension HAL module driver
  47.   * @{
  48.   */
  49.  
  50. #ifdef HAL_ADC_MODULE_ENABLED
  51.  
  52. /* Private typedef -----------------------------------------------------------*/
  53. /* Private define ------------------------------------------------------------*/
  54. /** @defgroup ADCEx_Private_Constants ADCEx Private Constants
  55.   * @{
  56.   */
  57.  
  58.   /* Delay for ADC calibration:                                               */
  59.   /* Hardware prerequisite before starting a calibration: the ADC must have   */
  60.   /* been in power-on state for at least two ADC clock cycles.                */
  61.   /* Unit: ADC clock cycles                                                   */
  62.   #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES       2U
  63.  
  64.   /* Timeout value for ADC calibration                                        */
  65.   /* Value defined to be higher than worst cases: low clocks freq,            */
  66.   /* maximum prescaler.                                                       */
  67.   /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
  68.   /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits.    */
  69.   /* Unit: ms                                                                 */
  70.   #define ADC_CALIBRATION_TIMEOUT          10U
  71.  
  72.   /* Delay for temperature sensor stabilization time.                         */
  73.   /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
  74.   /* Unit: us                                                                 */
  75.   #define ADC_TEMPSENSOR_DELAY_US         10U
  76.  
  77. /**
  78.   * @}
  79.   */
  80.  
  81. /* Private macro -------------------------------------------------------------*/
  82. /* Private variables ---------------------------------------------------------*/
  83. /* Private function prototypes -----------------------------------------------*/
  84. /* Private functions ---------------------------------------------------------*/
  85.  
  86. /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
  87.   * @{
  88.   */
  89.  
  90. /** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions
  91.  *  @brief    Extended Extended Input and Output operation functions
  92.  *
  93. @verbatim    
  94.  ===============================================================================
  95.                       ##### IO operation functions #####
  96.  ===============================================================================
  97.     [..]  This section provides functions allowing to:
  98.       (+) Start conversion of injected group.
  99.       (+) Stop conversion of injected group.
  100.       (+) Poll for conversion complete on injected group.
  101.       (+) Get result of injected channel conversion.
  102.       (+) Start conversion of injected group and enable interruptions.
  103.       (+) Stop conversion of injected group and disable interruptions.
  104.  
  105.       (+) Start multimode and enable DMA transfer.
  106.       (+) Stop multimode and disable ADC DMA transfer.
  107.       (+) Get result of multimode conversion.
  108.  
  109.       (+) Perform the ADC self-calibration for single or differential ending.
  110.       (+) Get calibration factors for single or differential ending.
  111.       (+) Set calibration factors for single or differential ending.
  112.      
  113. @endverbatim
  114.   * @{
  115.   */
  116.  
  117. /**
  118.   * @brief  Perform an ADC automatic self-calibration
  119.   *         Calibration prerequisite: ADC must be disabled (execute this
  120.   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
  121.   *         During calibration process, ADC is enabled. ADC is let enabled at
  122.   *         the completion of this function.
  123.   * @param  hadc: ADC handle
  124.   * @retval HAL status
  125.   */
  126. HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
  127. {
  128.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  129.   uint32_t tickstart;
  130.   __IO uint32_t wait_loop_index = 0U;
  131.  
  132.   /* Check the parameters */
  133.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  134.  
  135.   /* Process locked */
  136.   __HAL_LOCK(hadc);
  137.    
  138.   /* 1. Calibration prerequisite:                                             */
  139.   /*    - ADC must be disabled for at least two ADC clock cycles in disable   */
  140.   /*      mode before ADC enable                                              */
  141.   /* Stop potential conversion on going, on regular and injected groups       */
  142.   /* Disable ADC peripheral */
  143.   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
  144.  
  145.   /* Check if ADC is effectively disabled */
  146.   if (tmp_hal_status == HAL_OK)
  147.   {
  148.     /* Set ADC state */
  149.     ADC_STATE_CLR_SET(hadc->State,
  150.                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
  151.                       HAL_ADC_STATE_BUSY_INTERNAL);
  152.    
  153.     /* Hardware prerequisite: delay before starting the calibration.          */
  154.     /*  - Computation of CPU clock cycles corresponding to ADC clock cycles.  */
  155.     /*  - Wait for the expected ADC clock cycles delay */
  156.     wait_loop_index = ((SystemCoreClock
  157.                         / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
  158.                        * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES        );
  159.  
  160.     while(wait_loop_index != 0U)
  161.     {
  162.       wait_loop_index--;
  163.     }
  164.    
  165.     /* 2. Enable the ADC peripheral */
  166.     ADC_Enable(hadc);
  167.    
  168.     /* 3. Resets ADC calibration registers */  
  169.     SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
  170.    
  171.     tickstart = HAL_GetTick();  
  172.  
  173.     /* Wait for calibration reset completion */
  174.     while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
  175.     {
  176.       if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
  177.       {
  178.         /* Update ADC state machine to error */
  179.         ADC_STATE_CLR_SET(hadc->State,
  180.                           HAL_ADC_STATE_BUSY_INTERNAL,
  181.                           HAL_ADC_STATE_ERROR_INTERNAL);
  182.        
  183.         /* Process unlocked */
  184.         __HAL_UNLOCK(hadc);
  185.        
  186.         return HAL_ERROR;
  187.       }
  188.     }
  189.    
  190.    
  191.     /* 4. Start ADC calibration */
  192.     SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
  193.    
  194.     tickstart = HAL_GetTick();  
  195.  
  196.     /* Wait for calibration completion */
  197.     while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
  198.     {
  199.       if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
  200.       {
  201.         /* Update ADC state machine to error */
  202.         ADC_STATE_CLR_SET(hadc->State,
  203.                           HAL_ADC_STATE_BUSY_INTERNAL,
  204.                           HAL_ADC_STATE_ERROR_INTERNAL);
  205.        
  206.         /* Process unlocked */
  207.         __HAL_UNLOCK(hadc);
  208.        
  209.         return HAL_ERROR;
  210.       }
  211.     }
  212.    
  213.     /* Set ADC state */
  214.     ADC_STATE_CLR_SET(hadc->State,
  215.                       HAL_ADC_STATE_BUSY_INTERNAL,
  216.                       HAL_ADC_STATE_READY);
  217.   }
  218.  
  219.   /* Process unlocked */
  220.   __HAL_UNLOCK(hadc);
  221.  
  222.   /* Return function status */
  223.   return tmp_hal_status;
  224. }
  225.  
  226. /**
  227.   * @brief  Enables ADC, starts conversion of injected group.
  228.   *         Interruptions enabled in this function: None.
  229.   * @param  hadc: ADC handle
  230.   * @retval HAL status
  231.   */
  232. HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
  233. {
  234.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  235.  
  236.   /* Check the parameters */
  237.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  238.  
  239.   /* Process locked */
  240.   __HAL_LOCK(hadc);
  241.    
  242.   /* Enable the ADC peripheral */
  243.   tmp_hal_status = ADC_Enable(hadc);
  244.  
  245.   /* Start conversion if ADC is effectively enabled */
  246.   if (tmp_hal_status == HAL_OK)
  247.   {
  248.     /* Set ADC state                                                          */
  249.     /* - Clear state bitfield related to injected group conversion results    */
  250.     /* - Set state bitfield related to injected operation                     */
  251.     ADC_STATE_CLR_SET(hadc->State,
  252.                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
  253.                       HAL_ADC_STATE_INJ_BUSY);
  254.    
  255.     /* Case of independent mode or multimode (for devices with several ADCs): */
  256.     /* Set multimode state.                                                   */
  257.     if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
  258.     {
  259.       CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  260.     }
  261.     else
  262.     {
  263.       SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  264.     }
  265.    
  266.     /* Check if a regular conversion is ongoing */
  267.     /* Note: On this device, there is no ADC error code fields related to     */
  268.     /*       conversions on group injected only. In case of conversion on     */
  269.     /*       going on group regular, no error code is reset.                  */
  270.     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
  271.     {
  272.       /* Reset ADC all error code fields */
  273.       ADC_CLEAR_ERRORCODE(hadc);
  274.     }
  275.    
  276.     /* Process unlocked */
  277.     /* Unlock before starting ADC conversions: in case of potential           */
  278.     /* interruption, to let the process to ADC IRQ Handler.                   */
  279.     __HAL_UNLOCK(hadc);
  280.    
  281.     /* Clear injected group conversion flag */
  282.     /* (To ensure of no unknown state from potential previous ADC operations) */
  283.     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
  284.        
  285.     /* Enable conversion of injected group.                                   */
  286.     /* If software start has been selected, conversion starts immediately.    */
  287.     /* If external trigger has been selected, conversion will start at next   */
  288.     /* trigger event.                                                         */
  289.     /* If automatic injected conversion is enabled, conversion will start     */
  290.     /* after next regular group conversion.                                   */
  291.     /* Case of multimode enabled (for devices with several ADCs): if ADC is   */
  292.     /* slave, ADC is enabled only (conversion is not started). If ADC is      */
  293.     /* master, ADC is enabled and conversion is started.                      */
  294.     if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
  295.     {
  296.       if (ADC_IS_SOFTWARE_START_INJECTED(hadc)     &&
  297.           ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)  )
  298.       {
  299.         /* Start ADC conversion on injected group with SW start */
  300.         SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
  301.       }
  302.       else
  303.       {
  304.         /* Start ADC conversion on injected group with external trigger */
  305.         SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
  306.       }
  307.     }
  308.   }
  309.   else
  310.   {
  311.     /* Process unlocked */
  312.     __HAL_UNLOCK(hadc);
  313.   }
  314.  
  315.   /* Return function status */
  316.   return tmp_hal_status;
  317. }
  318.  
  319. /**
  320.   * @brief  Stop conversion of injected channels. Disable ADC peripheral if
  321.   *         no regular conversion is on going.
  322.   * @note   If ADC must be disabled and if conversion is on going on
  323.   *         regular group, function HAL_ADC_Stop must be used to stop both
  324.   *         injected and regular groups, and disable the ADC.
  325.   * @note   If injected group mode auto-injection is enabled,
  326.   *         function HAL_ADC_Stop must be used.
  327.   * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
  328.   * @param  hadc: ADC handle
  329.   * @retval None
  330.   */
  331. HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
  332. {
  333.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  334.  
  335.   /* Check the parameters */
  336.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  337.  
  338.   /* Process locked */
  339.   __HAL_LOCK(hadc);
  340.    
  341.   /* Stop potential conversion and disable ADC peripheral                     */
  342.   /* Conditioned to:                                                          */
  343.   /* - No conversion on the other group (regular group) is intended to        */
  344.   /*   continue (injected and regular groups stop conversion and ADC disable  */
  345.   /*   are common)                                                            */
  346.   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
  347.   if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
  348.      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
  349.   {
  350.     /* Stop potential conversion on going, on regular and injected groups */
  351.     /* Disable ADC peripheral */
  352.     tmp_hal_status = ADC_ConversionStop_Disable(hadc);
  353.    
  354.     /* Check if ADC is effectively disabled */
  355.     if (tmp_hal_status == HAL_OK)
  356.     {
  357.       /* Set ADC state */
  358.       ADC_STATE_CLR_SET(hadc->State,
  359.                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
  360.                         HAL_ADC_STATE_READY);
  361.     }
  362.   }
  363.   else
  364.   {
  365.     /* Update ADC state machine to error */
  366.     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  367.      
  368.     tmp_hal_status = HAL_ERROR;
  369.   }
  370.  
  371.   /* Process unlocked */
  372.   __HAL_UNLOCK(hadc);
  373.  
  374.   /* Return function status */
  375.   return tmp_hal_status;
  376. }
  377.  
  378. /**
  379.   * @brief  Wait for injected group conversion to be completed.
  380.   * @param  hadc: ADC handle
  381.   * @param  Timeout: Timeout value in millisecond.
  382.   * @retval HAL status
  383.   */
  384. HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
  385. {
  386.   uint32_t tickstart;
  387.  
  388.   /* Variables for polling in case of scan mode enabled and polling for each  */
  389.   /* conversion.                                                              */
  390.   __IO uint32_t Conversion_Timeout_CPU_cycles = 0U;
  391.   uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
  392.  
  393.   /* Check the parameters */
  394.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  395.  
  396.   /* Get timeout */
  397.   tickstart = HAL_GetTick();  
  398.      
  399.   /* Polling for end of conversion: differentiation if single/sequence        */
  400.   /* conversion.                                                              */
  401.   /* For injected group, flag JEOC is set only at the end of the sequence,    */
  402.   /* not for each conversion within the sequence.                             */
  403.   /*  - If single conversion for injected group (scan mode disabled or        */
  404.   /*    InjectedNbrOfConversion ==1), flag JEOC is used to determine the      */
  405.   /*    conversion completion.                                                */
  406.   /*  - If sequence conversion for injected group (scan mode enabled and      */
  407.   /*    InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
  408.   /*    sequence.                                                             */
  409.   /*    To poll for each conversion, the maximum conversion time is computed  */
  410.   /*    from ADC conversion time (selected sampling time + conversion time of */
  411.   /*    12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on    */
  412.   /*    settings, conversion time range can be from 28 to 32256 CPU cycles).  */
  413.   /*    As flag JEOC is not set after each conversion, no timeout status can  */
  414.   /*    be set.                                                               */
  415.   if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
  416.   {
  417.     /* Wait until End of Conversion flag is raised */
  418.     while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
  419.     {
  420.       /* Check if timeout is disabled (set to infinite wait) */
  421.       if(Timeout != HAL_MAX_DELAY)
  422.       {
  423.         if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
  424.         {
  425.           /* Update ADC state machine to timeout */
  426.           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
  427.          
  428.           /* Process unlocked */
  429.           __HAL_UNLOCK(hadc);
  430.          
  431.           return HAL_TIMEOUT;
  432.         }
  433.       }
  434.     }
  435.   }
  436.   else
  437.   {
  438.     /* Replace polling by wait for maximum conversion time */
  439.     /*  - Computation of CPU clock cycles corresponding to ADC clock cycles   */
  440.     /*    and ADC maximum conversion cycles on all channels.                  */
  441.     /*  - Wait for the expected ADC clock cycles delay                        */
  442.     Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
  443.                                           / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
  444.                                          * ADC_CONVCYCLES_MAX_RANGE(hadc)                 );
  445.    
  446.     while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
  447.     {
  448.       /* Check if timeout is disabled (set to infinite wait) */
  449.       if(Timeout != HAL_MAX_DELAY)
  450.       {
  451.         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
  452.         {
  453.           /* Update ADC state machine to timeout */
  454.           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
  455.  
  456.           /* Process unlocked */
  457.           __HAL_UNLOCK(hadc);
  458.          
  459.           return HAL_TIMEOUT;
  460.         }
  461.       }
  462.       Conversion_Timeout_CPU_cycles ++;
  463.     }
  464.   }
  465.  
  466.   /* Clear injected group conversion flag */
  467.   /* Note: On STM32F1 ADC, clear regular conversion flag raised               */
  468.   /* simultaneously.                                                          */
  469.   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
  470.  
  471.   /* Update ADC state machine */
  472.   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
  473.  
  474.   /* Determine whether any further conversion upcoming on group injected      */
  475.   /* by external trigger or by automatic injected conversion                  */
  476.   /* from group regular.                                                      */
  477.   if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                     ||
  478.      (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&    
  479.      (ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
  480.       (hadc->Init.ContinuousConvMode == DISABLE)   )        )   )
  481.   {
  482.     /* Set ADC state */
  483.     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);  
  484.    
  485.     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
  486.     {
  487.       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
  488.     }
  489.   }
  490.  
  491.   /* Return ADC state */
  492.   return HAL_OK;
  493. }
  494.  
  495. /**
  496.   * @brief  Enables ADC, starts conversion of injected group with interruption.
  497.   *          - JEOC (end of conversion of injected group)
  498.   *         Each of these interruptions has its dedicated callback function.
  499.   * @param  hadc: ADC handle
  500.   * @retval HAL status.
  501.   */
  502. HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
  503. {
  504.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  505.  
  506.   /* Check the parameters */
  507.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  508.  
  509.   /* Process locked */
  510.   __HAL_LOCK(hadc);
  511.    
  512.   /* Enable the ADC peripheral */
  513.   tmp_hal_status = ADC_Enable(hadc);
  514.  
  515.   /* Start conversion if ADC is effectively enabled */
  516.   if (tmp_hal_status == HAL_OK)
  517.   {
  518.     /* Set ADC state                                                          */
  519.     /* - Clear state bitfield related to injected group conversion results    */
  520.     /* - Set state bitfield related to injected operation                     */
  521.     ADC_STATE_CLR_SET(hadc->State,
  522.                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
  523.                       HAL_ADC_STATE_INJ_BUSY);
  524.    
  525.     /* Case of independent mode or multimode (for devices with several ADCs): */
  526.     /* Set multimode state.                                                   */
  527.     if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
  528.     {
  529.       CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  530.     }
  531.     else
  532.     {
  533.       SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  534.     }
  535.    
  536.     /* Check if a regular conversion is ongoing */
  537.     /* Note: On this device, there is no ADC error code fields related to     */
  538.     /*       conversions on group injected only. In case of conversion on     */
  539.     /*       going on group regular, no error code is reset.                  */
  540.     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
  541.     {
  542.       /* Reset ADC all error code fields */
  543.       ADC_CLEAR_ERRORCODE(hadc);
  544.     }
  545.    
  546.     /* Process unlocked */
  547.     /* Unlock before starting ADC conversions: in case of potential           */
  548.     /* interruption, to let the process to ADC IRQ Handler.                   */
  549.     __HAL_UNLOCK(hadc);
  550.    
  551.     /* Clear injected group conversion flag */
  552.     /* (To ensure of no unknown state from potential previous ADC operations) */
  553.     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
  554.    
  555.     /* Enable end of conversion interrupt for injected channels */
  556.     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
  557.    
  558.     /* Start conversion of injected group if software start has been selected */
  559.     /* and if automatic injected conversion is disabled.                      */
  560.     /* If external trigger has been selected, conversion will start at next   */
  561.     /* trigger event.                                                         */
  562.     /* If automatic injected conversion is enabled, conversion will start     */
  563.     /* after next regular group conversion.                                   */
  564.     if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
  565.     {
  566.       if (ADC_IS_SOFTWARE_START_INJECTED(hadc)     &&
  567.           ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)  )
  568.       {
  569.         /* Start ADC conversion on injected group with SW start */
  570.         SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
  571.       }
  572.       else
  573.       {
  574.         /* Start ADC conversion on injected group with external trigger */
  575.         SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
  576.       }
  577.     }
  578.   }
  579.   else
  580.   {
  581.     /* Process unlocked */
  582.     __HAL_UNLOCK(hadc);
  583.   }
  584.  
  585.   /* Return function status */
  586.   return tmp_hal_status;
  587. }
  588.  
  589. /**
  590.   * @brief  Stop conversion of injected channels, disable interruption of
  591.   *         end-of-conversion. Disable ADC peripheral if no regular conversion
  592.   *         is on going.
  593.   * @note   If ADC must be disabled and if conversion is on going on
  594.   *         regular group, function HAL_ADC_Stop must be used to stop both
  595.   *         injected and regular groups, and disable the ADC.
  596.   * @note   If injected group mode auto-injection is enabled,
  597.   *         function HAL_ADC_Stop must be used.
  598.   * @param  hadc: ADC handle
  599.   * @retval None
  600.   */
  601. HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
  602. {
  603.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  604.  
  605.   /* Check the parameters */
  606.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  607.  
  608.   /* Process locked */
  609.   __HAL_LOCK(hadc);
  610.    
  611.   /* Stop potential conversion and disable ADC peripheral                     */
  612.   /* Conditioned to:                                                          */
  613.   /* - No conversion on the other group (regular group) is intended to        */
  614.   /*   continue (injected and regular groups stop conversion and ADC disable  */
  615.   /*   are common)                                                            */
  616.   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
  617.   if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
  618.      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
  619.   {
  620.     /* Stop potential conversion on going, on regular and injected groups */
  621.     /* Disable ADC peripheral */
  622.     tmp_hal_status = ADC_ConversionStop_Disable(hadc);
  623.    
  624.     /* Check if ADC is effectively disabled */
  625.     if (tmp_hal_status == HAL_OK)
  626.     {
  627.       /* Disable ADC end of conversion interrupt for injected channels */
  628.       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
  629.      
  630.       /* Set ADC state */
  631.       ADC_STATE_CLR_SET(hadc->State,
  632.                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
  633.                         HAL_ADC_STATE_READY);
  634.     }
  635.   }
  636.   else
  637.   {
  638.     /* Update ADC state machine to error */
  639.     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  640.      
  641.     tmp_hal_status = HAL_ERROR;
  642.   }
  643.  
  644.   /* Process unlocked */
  645.   __HAL_UNLOCK(hadc);
  646.  
  647.   /* Return function status */
  648.   return tmp_hal_status;
  649. }
  650.  
  651. #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
  652. /**
  653.   * @brief  Enables ADC, starts conversion of regular group and transfers result
  654.   *         through DMA.
  655.   *         Multimode must have been previously configured using
  656.   *         HAL_ADCEx_MultiModeConfigChannel() function.
  657.   *         Interruptions enabled in this function:
  658.   *          - DMA transfer complete
  659.   *          - DMA half transfer
  660.   *         Each of these interruptions has its dedicated callback function.
  661.   * @note:  On STM32F1 devices, ADC slave regular group must be configured
  662.   *         with conversion trigger ADC_SOFTWARE_START.
  663.   * @note:  ADC slave can be enabled preliminarily using single-mode  
  664.   *         HAL_ADC_Start() function.
  665.   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
  666.   * @param  pData: The destination Buffer address.
  667.   * @param  Length: The length of data to be transferred from ADC peripheral to memory.
  668.   * @retval None
  669.   */
  670. HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
  671. {
  672.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  673.   ADC_HandleTypeDef tmphadcSlave;
  674.  
  675.   /* Check the parameters */
  676.   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
  677.   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
  678.  
  679.   /* Process locked */
  680.   __HAL_LOCK(hadc);
  681.  
  682.   /* Set a temporary handle of the ADC slave associated to the ADC master     */
  683.   ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
  684.  
  685.   /* On STM32F1 devices, ADC slave regular group must be configured with      */
  686.   /* conversion trigger ADC_SOFTWARE_START.                                   */
  687.   /* Note: External trigger of ADC slave must be enabled, it is already done  */
  688.   /*       into function "HAL_ADC_Init()".                                    */
  689.   if(!ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave))  
  690.   {
  691.     /* Update ADC state machine to error */
  692.     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  693.    
  694.     /* Process unlocked */
  695.     __HAL_UNLOCK(hadc);
  696.    
  697.     return HAL_ERROR;
  698.   }
  699.  
  700.   /* Enable the ADC peripherals: master and slave (in case if not already     */
  701.   /* enabled previously)                                                      */
  702.   tmp_hal_status = ADC_Enable(hadc);
  703.   if (tmp_hal_status == HAL_OK)
  704.   {
  705.     tmp_hal_status = ADC_Enable(&tmphadcSlave);
  706.   }
  707.  
  708.   /* Start conversion if all ADCs of multimode are effectively enabled */
  709.   if (tmp_hal_status == HAL_OK)
  710.   {
  711.     /* Set ADC state (ADC master)                                             */
  712.     /* - Clear state bitfield related to regular group conversion results     */
  713.     /* - Set state bitfield related to regular operation                      */
  714.     ADC_STATE_CLR_SET(hadc->State,
  715.                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_MULTIMODE_SLAVE,
  716.                       HAL_ADC_STATE_REG_BUSY);
  717.      
  718.     /* If conversions on group regular are also triggering group injected,    */
  719.     /* update ADC state.                                                      */
  720.     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
  721.     {
  722.       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
  723.     }
  724.    
  725.     /* Process unlocked */
  726.     /* Unlock before starting ADC conversions: in case of potential           */
  727.     /* interruption, to let the process to ADC IRQ Handler.                   */
  728.     __HAL_UNLOCK(hadc);
  729.    
  730.     /* Set ADC error code to none */
  731.     ADC_CLEAR_ERRORCODE(hadc);
  732.    
  733.    
  734.     /* Set the DMA transfer complete callback */
  735.     hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
  736.        
  737.     /* Set the DMA half transfer complete callback */
  738.     hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
  739.    
  740.     /* Set the DMA error callback */
  741.     hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
  742.  
  743.    
  744.     /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
  745.     /* start (in case of SW start):                                           */
  746.    
  747.     /* Clear regular group conversion flag and overrun flag */
  748.     /* (To ensure of no unknown state from potential previous ADC operations) */
  749.     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
  750.    
  751.     /* Enable ADC DMA mode of ADC master */
  752.     SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
  753.    
  754.     /* Start the DMA channel */
  755.     HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
  756.    
  757.     /* Start conversion of regular group if software start has been selected. */
  758.     /* If external trigger has been selected, conversion will start at next   */
  759.     /* trigger event.                                                         */
  760.     /* Note: Alternate trigger for single conversion could be to force an     */
  761.     /*       additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
  762.     if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
  763.     {
  764.       /* Start ADC conversion on regular group with SW start */
  765.       SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
  766.     }
  767.     else
  768.     {
  769.       /* Start ADC conversion on regular group with external trigger */
  770.       SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
  771.     }
  772.   }
  773.   else
  774.   {
  775.     /* Process unlocked */
  776.     __HAL_UNLOCK(hadc);
  777.   }
  778.  
  779.   /* Return function status */
  780.   return tmp_hal_status;
  781. }
  782.  
  783. /**
  784.   * @brief  Stop ADC conversion of regular group (and injected channels in
  785.   *         case of auto_injection mode), disable ADC DMA transfer, disable
  786.   *         ADC peripheral.
  787.   * @note   Multimode is kept enabled after this function. To disable multimode
  788.   *         (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be
  789.   *         reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
  790.   * @note   In case of DMA configured in circular mode, function
  791.   *         HAL_ADC_Stop_DMA must be called after this function with handle of
  792.   *         ADC slave, to properly disable the DMA channel.
  793.   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
  794.   * @retval None
  795.   */
  796. HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
  797. {
  798.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  799.   ADC_HandleTypeDef tmphadcSlave;
  800.  
  801.   /* Check the parameters */
  802.   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
  803.  
  804.   /* Process locked */
  805.   __HAL_LOCK(hadc);
  806.  
  807.  
  808.   /* Stop potential conversion on going, on regular and injected groups */
  809.   /* Disable ADC master peripheral */
  810.   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
  811.  
  812.   /* Check if ADC is effectively disabled */
  813.   if(tmp_hal_status == HAL_OK)
  814.   {
  815.     /* Set a temporary handle of the ADC slave associated to the ADC master   */
  816.     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
  817.  
  818.     /* Disable ADC slave peripheral */
  819.     tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave);
  820.  
  821.     /* Check if ADC is effectively disabled */
  822.     if(tmp_hal_status != HAL_OK)
  823.     {
  824.       /* Update ADC state machine to error */
  825.       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  826.  
  827.       /* Process unlocked */
  828.       __HAL_UNLOCK(hadc);
  829.  
  830.       return HAL_ERROR;
  831.     }
  832.  
  833.     /* Disable ADC DMA mode */
  834.     CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
  835.    
  836.     /* Reset configuration of ADC DMA continuous request for dual mode */
  837.     CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD);
  838.        
  839.     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
  840.     /* while DMA transfer is on going)                                        */
  841.     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
  842.  
  843.     /* Change ADC state (ADC master) */
  844.     ADC_STATE_CLR_SET(hadc->State,
  845.                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
  846.                       HAL_ADC_STATE_READY);
  847.   }
  848.  
  849.   /* Process unlocked */
  850.   __HAL_UNLOCK(hadc);
  851.  
  852.   /* Return function status */
  853.   return tmp_hal_status;
  854. }
  855. #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
  856.  
  857. /**
  858.   * @brief  Get ADC injected group conversion result.
  859.   * @note   Reading register JDRx automatically clears ADC flag JEOC
  860.   *         (ADC group injected end of unitary conversion).
  861.   * @note   This function does not clear ADC flag JEOS
  862.   *         (ADC group injected end of sequence conversion)
  863.   *         Occurrence of flag JEOS rising:
  864.   *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
  865.   *            to flag JEOC.
  866.   *          - If sequencer is composed of several ranks, during the scan
  867.   *            sequence flag JEOC only is raised, at the end of the scan sequence
  868.   *            both flags JEOC and EOS are raised.
  869.   *         Flag JEOS must not be cleared by this function because
  870.   *         it would not be compliant with low power features
  871.   *         (feature low power auto-wait, not available on all STM32 families).
  872.   *         To clear this flag, either use function:
  873.   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
  874.   *         model polling: @ref HAL_ADCEx_InjectedPollForConversion()
  875.   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
  876.   * @param  hadc: ADC handle
  877.   * @param  InjectedRank: the converted ADC injected rank.
  878.   *          This parameter can be one of the following values:
  879.   *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
  880.   *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
  881.   *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
  882.   *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
  883.   * @retval ADC group injected conversion data
  884.   */
  885. uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
  886. {
  887.   uint32_t tmp_jdr = 0U;
  888.  
  889.   /* Check the parameters */
  890.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  891.   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
  892.  
  893.   /* Get ADC converted value */
  894.   switch(InjectedRank)
  895.   {  
  896.     case ADC_INJECTED_RANK_4:
  897.       tmp_jdr = hadc->Instance->JDR4;
  898.       break;
  899.     case ADC_INJECTED_RANK_3:
  900.       tmp_jdr = hadc->Instance->JDR3;
  901.       break;
  902.     case ADC_INJECTED_RANK_2:
  903.       tmp_jdr = hadc->Instance->JDR2;
  904.       break;
  905.     case ADC_INJECTED_RANK_1:
  906.     default:
  907.       tmp_jdr = hadc->Instance->JDR1;
  908.       break;
  909.   }
  910.  
  911.   /* Return ADC converted value */
  912.   return tmp_jdr;
  913. }
  914.  
  915. #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
  916. /**
  917.   * @brief  Returns the last ADC Master&Slave regular conversions results data
  918.   *         in the selected multi mode.
  919.   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
  920.   * @retval The converted data value.
  921.   */
  922. uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
  923. {
  924.   uint32_t tmpDR = 0U;
  925.  
  926.   /* Check the parameters */
  927.   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
  928.  
  929.   /* Check the parameters */
  930.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  931.  
  932.   /* Note: EOC flag is not cleared here by software because automatically     */
  933.   /*       cleared by hardware when reading register DR.                      */
  934.  
  935.   /* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions      */
  936.   /* only if ADC1 DMA mode is enabled.                                        */
  937.   tmpDR = hadc->Instance->DR;
  938.  
  939.   if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA))
  940.   {
  941.     tmpDR |= (ADC2->DR << 16U);
  942.   }
  943.    
  944.   /* Return ADC converted value */
  945.   return tmpDR;
  946. }
  947. #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
  948.  
  949. /**
  950.   * @brief  Injected conversion complete callback in non blocking mode
  951.   * @param  hadc: ADC handle
  952.   * @retval None
  953.   */
  954. __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
  955. {
  956.   /* Prevent unused argument(s) compilation warning */
  957.   UNUSED(hadc);
  958.   /* NOTE : This function Should not be modified, when the callback is needed,
  959.             the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
  960.   */
  961. }
  962.  
  963. /**
  964.   * @}
  965.   */
  966.  
  967. /** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
  968.   * @brief    Extended Peripheral Control functions
  969.   *
  970. @verbatim  
  971.  ===============================================================================
  972.              ##### Peripheral Control functions #####
  973.  ===============================================================================  
  974.     [..]  This section provides functions allowing to:
  975.       (+) Configure channels on injected group
  976.       (+) Configure multimode
  977.  
  978. @endverbatim
  979.   * @{
  980.   */
  981.  
  982. /**
  983.   * @brief  Configures the ADC injected group and the selected channel to be
  984.   *         linked to the injected group.
  985.   * @note   Possibility to update parameters on the fly:
  986.   *         This function initializes injected group, following calls to this
  987.   *         function can be used to reconfigure some parameters of structure
  988.   *         "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
  989.   *         The setting of these parameters is conditioned to ADC state:
  990.   *         this function must be called when ADC is not under conversion.
  991.   * @param  hadc: ADC handle
  992.   * @param  sConfigInjected: Structure of ADC injected group and ADC channel for
  993.   *         injected group.
  994.   * @retval None
  995.   */
  996. HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
  997. {
  998.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  999.   __IO uint32_t wait_loop_index = 0U;
  1000.  
  1001.   /* Check the parameters */
  1002.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  1003.   assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
  1004.   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
  1005.   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
  1006.   assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
  1007.   assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
  1008.  
  1009.   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
  1010.   {
  1011.     assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
  1012.     assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
  1013.     assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
  1014.   }
  1015.  
  1016.   /* Process locked */
  1017.   __HAL_LOCK(hadc);
  1018.  
  1019.   /* Configuration of injected group sequencer:                               */
  1020.   /* - if scan mode is disabled, injected channels sequence length is set to  */
  1021.   /*   0x00: 1 channel converted (channel on regular rank 1)                  */
  1022.   /*   Parameter "InjectedNbrOfConversion" is discarded.                      */
  1023.   /*   Note: Scan mode is present by hardware on this device and, if          */
  1024.   /*   disabled, discards automatically nb of conversions. Anyway, nb of      */
  1025.   /*   conversions is forced to 0x00 for alignment over all STM32 devices.    */
  1026.   /* - if scan mode is enabled, injected channels sequence length is set to   */
  1027.   /*   parameter "InjectedNbrOfConversion".                                   */
  1028.   if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
  1029.   {
  1030.     if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
  1031.     {
  1032.       /* Clear the old SQx bits for all injected ranks */
  1033.       MODIFY_REG(hadc->Instance->JSQR                             ,
  1034.                  ADC_JSQR_JL   |
  1035.                  ADC_JSQR_JSQ4 |
  1036.                  ADC_JSQR_JSQ3 |
  1037.                  ADC_JSQR_JSQ2 |
  1038.                  ADC_JSQR_JSQ1                                    ,
  1039.                  ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
  1040.                                   ADC_INJECTED_RANK_1,
  1041.                                   0x01U));
  1042.     }
  1043.     /* If another injected rank than rank1 was intended to be set, and could  */
  1044.     /* not due to ScanConvMode disabled, error is reported.                   */
  1045.     else
  1046.     {
  1047.       /* Update ADC state machine to error */
  1048.       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  1049.      
  1050.       tmp_hal_status = HAL_ERROR;
  1051.     }
  1052.   }
  1053.   else
  1054.   {
  1055.     /* Since injected channels rank conv. order depends on total number of   */
  1056.     /* injected conversions, selected rank must be below or equal to total   */
  1057.     /* number of injected conversions to be updated.                         */
  1058.     if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
  1059.     {
  1060.       /* Clear the old SQx bits for the selected rank */
  1061.       /* Set the SQx bits for the selected rank */
  1062.       MODIFY_REG(hadc->Instance->JSQR                                         ,
  1063.                  
  1064.                  ADC_JSQR_JL                                               |
  1065.                  ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,                        
  1066.                                   sConfigInjected->InjectedRank,        
  1067.                                   sConfigInjected->InjectedNbrOfConversion)   ,
  1068.                  
  1069.                  ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
  1070.                  ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,      
  1071.                                   sConfigInjected->InjectedRank,        
  1072.                                   sConfigInjected->InjectedNbrOfConversion)    );
  1073.     }
  1074.     else
  1075.     {
  1076.       /* Clear the old SQx bits for the selected rank */
  1077.       MODIFY_REG(hadc->Instance->JSQR                                       ,
  1078.                  
  1079.                  ADC_JSQR_JL                                               |
  1080.                  ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,                        
  1081.                                   sConfigInjected->InjectedRank,        
  1082.                                   sConfigInjected->InjectedNbrOfConversion) ,
  1083.                  
  1084.                  0x00000000U);
  1085.     }
  1086.   }
  1087.    
  1088.   /* Configuration of injected group                                          */
  1089.   /* Parameters update conditioned to ADC state:                              */
  1090.   /* Parameters that can be updated only when ADC is disabled:                */
  1091.   /*  - external trigger to start conversion                                  */
  1092.   /* Parameters update not conditioned to ADC state:                          */
  1093.   /*  - Automatic injected conversion                                         */
  1094.   /*  - Injected discontinuous mode                                           */
  1095.   /* Note: In case of ADC already enabled, caution to not launch an unwanted  */
  1096.   /*       conversion while modifying register CR2 by writing 1 to bit ADON.  */
  1097.   if (ADC_IS_ENABLE(hadc) == RESET)
  1098.   {    
  1099.     MODIFY_REG(hadc->Instance->CR2                                           ,
  1100.                ADC_CR2_JEXTSEL |
  1101.                ADC_CR2_ADON                                                  ,
  1102.                ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) );
  1103.   }
  1104.  
  1105.  
  1106.   /* Configuration of injected group                                          */
  1107.   /*  - Automatic injected conversion                                         */
  1108.   /*  - Injected discontinuous mode                                           */
  1109.  
  1110.     /* Automatic injected conversion can be enabled if injected group         */
  1111.     /* external triggers are disabled.                                        */
  1112.     if (sConfigInjected->AutoInjectedConv == ENABLE)
  1113.     {
  1114.       if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
  1115.       {
  1116.         SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
  1117.       }
  1118.       else
  1119.       {
  1120.         /* Update ADC state machine to error */
  1121.         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  1122.        
  1123.         tmp_hal_status = HAL_ERROR;
  1124.       }
  1125.     }
  1126.    
  1127.     /* Injected discontinuous can be enabled only if auto-injected mode is    */
  1128.     /* disabled.                                                              */  
  1129.     if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
  1130.     {
  1131.       if (sConfigInjected->AutoInjectedConv == DISABLE)
  1132.       {
  1133.         SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
  1134.       }
  1135.       else
  1136.       {
  1137.         /* Update ADC state machine to error */
  1138.         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  1139.        
  1140.         tmp_hal_status = HAL_ERROR;
  1141.       }
  1142.     }
  1143.  
  1144.  
  1145.   /* InjectedChannel sampling time configuration */
  1146.   /* For channels 10 to 17 */
  1147.   if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
  1148.   {
  1149.     MODIFY_REG(hadc->Instance->SMPR1                                                             ,
  1150.                ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel)                      ,
  1151.                ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
  1152.   }
  1153.   else /* For channels 0 to 9 */
  1154.   {
  1155.     MODIFY_REG(hadc->Instance->SMPR2                                                             ,
  1156.                ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel)                       ,
  1157.                ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
  1158.   }
  1159.  
  1160.   /* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor  */
  1161.   /* and VREFINT measurement path.                                            */
  1162.   if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
  1163.       (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)      )
  1164.   {
  1165.     SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
  1166.   }
  1167.  
  1168.  
  1169.   /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
  1170.   switch(sConfigInjected->InjectedRank)
  1171.   {
  1172.     case 1:
  1173.       /* Set injected channel 1 offset */
  1174.       MODIFY_REG(hadc->Instance->JOFR1,
  1175.                  ADC_JOFR1_JOFFSET1,
  1176.                  sConfigInjected->InjectedOffset);
  1177.       break;
  1178.     case 2:
  1179.       /* Set injected channel 2 offset */
  1180.       MODIFY_REG(hadc->Instance->JOFR2,
  1181.                  ADC_JOFR2_JOFFSET2,
  1182.                  sConfigInjected->InjectedOffset);
  1183.       break;
  1184.     case 3:
  1185.       /* Set injected channel 3 offset */
  1186.       MODIFY_REG(hadc->Instance->JOFR3,
  1187.                  ADC_JOFR3_JOFFSET3,
  1188.                  sConfigInjected->InjectedOffset);
  1189.       break;
  1190.     case 4:
  1191.     default:
  1192.       MODIFY_REG(hadc->Instance->JOFR4,
  1193.                  ADC_JOFR4_JOFFSET4,
  1194.                  sConfigInjected->InjectedOffset);
  1195.       break;
  1196.   }
  1197.  
  1198.   /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
  1199.   /* and VREFINT measurement path.                                            */
  1200.   if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
  1201.       (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)      )
  1202.   {
  1203.     /* For STM32F1 devices with several ADC: Only ADC1 can access internal    */
  1204.     /* measurement channels (VrefInt/TempSensor). If these channels are       */
  1205.     /* intended to be set on other ADC instances, an error is reported.       */
  1206.     if (hadc->Instance == ADC1)
  1207.     {
  1208.       if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
  1209.       {
  1210.         SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
  1211.        
  1212.         if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
  1213.         {
  1214.           /* Delay for temperature sensor stabilization time */
  1215.           /* Compute number of CPU cycles to wait for */
  1216.           wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
  1217.           while(wait_loop_index != 0U)
  1218.           {
  1219.             wait_loop_index--;
  1220.           }
  1221.         }
  1222.       }
  1223.     }
  1224.     else
  1225.     {
  1226.       /* Update ADC state machine to error */
  1227.       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  1228.      
  1229.       tmp_hal_status = HAL_ERROR;
  1230.     }
  1231.   }
  1232.  
  1233.   /* Process unlocked */
  1234.   __HAL_UNLOCK(hadc);
  1235.  
  1236.   /* Return function status */
  1237.   return tmp_hal_status;
  1238. }
  1239.  
  1240. #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
  1241. /**
  1242.   * @brief  Enable ADC multimode and configure multimode parameters
  1243.   * @note   Possibility to update parameters on the fly:
  1244.   *         This function initializes multimode parameters, following  
  1245.   *         calls to this function can be used to reconfigure some parameters
  1246.   *         of structure "ADC_MultiModeTypeDef" on the fly, without reseting
  1247.   *         the ADCs (both ADCs of the common group).
  1248.   *         The setting of these parameters is conditioned to ADC state.
  1249.   *         For parameters constraints, see comments of structure
  1250.   *         "ADC_MultiModeTypeDef".
  1251.   * @note   To change back configuration from multimode to single mode, ADC must
  1252.   *         be reset (using function HAL_ADC_Init() ).
  1253.   * @param  hadc: ADC handle
  1254.   * @param  multimode: Structure of ADC multimode configuration
  1255.   * @retval HAL status
  1256.   */
  1257. HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
  1258. {
  1259.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  1260.   ADC_HandleTypeDef tmphadcSlave;
  1261.  
  1262.   /* Check the parameters */
  1263.   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
  1264.   assert_param(IS_ADC_MODE(multimode->Mode));
  1265.  
  1266.   /* Process locked */
  1267.   __HAL_LOCK(hadc);
  1268.  
  1269.   /* Set a temporary handle of the ADC slave associated to the ADC master     */
  1270.   ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
  1271.  
  1272.   /* Parameters update conditioned to ADC state:                              */
  1273.   /* Parameters that can be updated when ADC is disabled or enabled without   */
  1274.   /* conversion on going on regular group:                                    */
  1275.   /*  - ADC master and ADC slave DMA configuration                            */
  1276.   /* Parameters that can be updated only when ADC is disabled:                */
  1277.   /*  - Multimode mode selection                                              */
  1278.   /* To optimize code, all multimode settings can be set when both ADCs of    */
  1279.   /* the common group are in state: disabled.                                 */
  1280.   if ((ADC_IS_ENABLE(hadc) == RESET)                     &&
  1281.       (ADC_IS_ENABLE(&tmphadcSlave) == RESET)            &&
  1282.       (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance))   )
  1283.   {
  1284.     MODIFY_REG(hadc->Instance->CR1,
  1285.                ADC_CR1_DUALMOD    ,
  1286.                multimode->Mode     );
  1287.   }
  1288.   /* If one of the ADC sharing the same common group is enabled, no update    */
  1289.   /* could be done on neither of the multimode structure parameters.          */
  1290.   else
  1291.   {
  1292.     /* Update ADC state machine to error */
  1293.     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  1294.    
  1295.     tmp_hal_status = HAL_ERROR;
  1296.   }
  1297.    
  1298.    
  1299.   /* Process unlocked */
  1300.   __HAL_UNLOCK(hadc);
  1301.  
  1302.   /* Return function status */
  1303.   return tmp_hal_status;
  1304. }
  1305. #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
  1306. /**
  1307.   * @}
  1308.   */  
  1309.  
  1310. /**
  1311.   * @}
  1312.   */
  1313.  
  1314. #endif /* HAL_ADC_MODULE_ENABLED */
  1315. /**
  1316.   * @}
  1317.   */
  1318.  
  1319. /**
  1320.   * @}
  1321.   */
  1322.  
  1323. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1324.