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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_adc_ex.c
  4.   * @author  MCD Application Team
  5.   * @version V1.0.1
  6.   * @date    31-July-2015
  7.   * @brief   This file provides firmware functions to manage the following
  8.   *          functionalities of the Analog to Digital Convertor (ADC)
  9.   *          peripheral:
  10.   *           + Operation functions
  11.   *             ++ Start, stop, get result of conversions of injected
  12.   *                group, using 2 possible modes: polling, interruption.
  13.   *             ++ Multimode feature (available on devices with 2 ADCs or more)
  14.   *             ++ Calibration (ADC automatic self-calibration)
  15.   *           + Control functions
  16.   *             ++ Channels configuration on injected group
  17.   *          Other functions (generic functions) are available in file
  18.   *          "stm32f1xx_hal_adc.c".
  19.   *
  20.   @verbatim
  21.   [..]
  22.   (@) Sections "ADC peripheral features" and "How to use this driver" are
  23.       available in file of generic functions "stm32f1xx_hal_adc.c".
  24.   [..]
  25.   @endverbatim
  26.   ******************************************************************************
  27.   * @attention
  28.   *
  29.   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  30.   *
  31.   * Redistribution and use in source and binary forms, with or without modification,
  32.   * are permitted provided that the following conditions are met:
  33.   *   1. Redistributions of source code must retain the above copyright notice,
  34.   *      this list of conditions and the following disclaimer.
  35.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  36.   *      this list of conditions and the following disclaimer in the documentation
  37.   *      and/or other materials provided with the distribution.
  38.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  39.   *      may be used to endorse or promote products derived from this software
  40.   *      without specific prior written permission.
  41.   *
  42.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  43.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  44.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  45.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  46.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  47.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  48.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  49.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  50.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  51.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  52.   *
  53.   ******************************************************************************  
  54.   */
  55.  
  56. /* Includes ------------------------------------------------------------------*/
  57. #include "stm32f1xx_hal.h"
  58.  
  59. /** @addtogroup STM32F1xx_HAL_Driver
  60.   * @{
  61.   */
  62.  
  63. /** @defgroup ADCEx ADCEx
  64.   * @brief ADC Extension HAL module driver
  65.   * @{
  66.   */
  67.  
  68. #ifdef HAL_ADC_MODULE_ENABLED
  69.  
  70. /* Private typedef -----------------------------------------------------------*/
  71. /* Private define ------------------------------------------------------------*/
  72. /** @defgroup ADCEx_Private_Constants ADCEx Private Constants
  73.   * @{
  74.   */
  75.  
  76.   /* Delay for ADC calibration:                                               */
  77.   /* Hardware prerequisite before starting a calibration: the ADC must have   */
  78.   /* been in power-on state for at least two ADC clock cycles.                */
  79.   /* Unit: ADC clock cycles                                                   */
  80.   #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES       ((uint32_t) 2)
  81.  
  82.   /* Timeout value for ADC calibration                                        */
  83.   /* Value defined to be higher than worst cases: low clocks freq,            */
  84.   /* maximum prescaler.                                                       */
  85.   /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
  86.   /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits.    */
  87.   /* Unit: ms                                                                 */
  88.   #define ADC_CALIBRATION_TIMEOUT         ((uint32_t) 10)
  89.  
  90.   /* Delay for temperature sensor stabilization time.                         */
  91.   /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
  92.   /* Unit: us                                                                 */
  93.   #define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 10)
  94.  
  95. /**
  96.   * @}
  97.   */
  98.  
  99. /* Private macro -------------------------------------------------------------*/
  100. /* Private variables ---------------------------------------------------------*/
  101. /* Private function prototypes -----------------------------------------------*/
  102. /* Private functions ---------------------------------------------------------*/
  103.  
  104. /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
  105.   * @{
  106.   */
  107.  
  108. /** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions
  109.  *  @brief    Extended Extended Input and Output operation functions
  110.  *
  111. @verbatim    
  112.  ===============================================================================
  113.                       ##### IO operation functions #####
  114.  ===============================================================================
  115.     [..]  This section provides functions allowing to:
  116.       (+) Start conversion of injected group.
  117.       (+) Stop conversion of injected group.
  118.       (+) Poll for conversion complete on injected group.
  119.       (+) Get result of injected channel conversion.
  120.       (+) Start conversion of injected group and enable interruptions.
  121.       (+) Stop conversion of injected group and disable interruptions.
  122.  
  123.       (+) Start multimode and enable DMA transfer.
  124.       (+) Stop multimode and disable ADC DMA transfer.
  125.       (+) Get result of multimode conversion.
  126.  
  127.       (+) Perform the ADC self-calibration for single or differential ending.
  128.       (+) Get calibration factors for single or differential ending.
  129.       (+) Set calibration factors for single or differential ending.
  130.      
  131. @endverbatim
  132.   * @{
  133.   */
  134.  
  135. /**
  136.   * @brief  Perform an ADC automatic self-calibration
  137.   *         Calibration prerequisite: ADC must be disabled (execute this
  138.   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
  139.   *         During calibration process, ADC is enabled. ADC is let enabled at
  140.   *         the completion of this function.
  141.   * @param  hadc: ADC handle
  142.   * @retval HAL status
  143.   */
  144. HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
  145. {
  146.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  147.   uint32_t tickstart;
  148.   __IO uint32_t wait_loop_index = 0;
  149.  
  150.   /* Check the parameters */
  151.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  152.  
  153.   /* Process locked */
  154.   __HAL_LOCK(hadc);
  155.    
  156.   /* 1. Calibration prerequisite:                                             */
  157.   /*    - ADC must be disabled for at least two ADC clock cycles in disable   */
  158.   /*      mode before ADC enable                                              */
  159.   /* Stop potential conversion on going, on regular and injected groups       */
  160.   /* Disable ADC peripheral */
  161.   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
  162.  
  163.   /* Check if ADC is effectively disabled */
  164.   if (tmp_hal_status == HAL_OK)
  165.   {
  166.     /* Set ADC state */
  167.     ADC_STATE_CLR_SET(hadc->State,
  168.                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
  169.                       HAL_ADC_STATE_BUSY_INTERNAL);
  170.    
  171.     /* Hardware prerequisite: delay before starting the calibration.          */
  172.     /*  - Computation of CPU clock cycles corresponding to ADC clock cycles.  */
  173.     /*  - Wait for the expected ADC clock cycles delay */
  174.     wait_loop_index = ((SystemCoreClock
  175.                         / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
  176.                        * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES        );
  177.  
  178.     while(wait_loop_index != 0)
  179.     {
  180.       wait_loop_index--;
  181.     }
  182.    
  183.     /* 2. Enable the ADC peripheral */
  184.     ADC_Enable(hadc);
  185.    
  186.     /* 3. Resets ADC calibration registers */  
  187.     SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
  188.    
  189.     tickstart = HAL_GetTick();  
  190.  
  191.     /* Wait for calibration reset completion */
  192.     while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
  193.     {
  194.       if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
  195.       {
  196.         /* Update ADC state machine to error */
  197.         ADC_STATE_CLR_SET(hadc->State,
  198.                           HAL_ADC_STATE_BUSY_INTERNAL,
  199.                           HAL_ADC_STATE_ERROR_INTERNAL);
  200.        
  201.         /* Process unlocked */
  202.         __HAL_UNLOCK(hadc);
  203.        
  204.         return HAL_ERROR;
  205.       }
  206.     }
  207.    
  208.    
  209.     /* 4. Start ADC calibration */
  210.     SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
  211.    
  212.     tickstart = HAL_GetTick();  
  213.  
  214.     /* Wait for calibration completion */
  215.     while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
  216.     {
  217.       if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
  218.       {
  219.         /* Update ADC state machine to error */
  220.         ADC_STATE_CLR_SET(hadc->State,
  221.                           HAL_ADC_STATE_BUSY_INTERNAL,
  222.                           HAL_ADC_STATE_ERROR_INTERNAL);
  223.        
  224.         /* Process unlocked */
  225.         __HAL_UNLOCK(hadc);
  226.        
  227.         return HAL_ERROR;
  228.       }
  229.     }
  230.    
  231.     /* Set ADC state */
  232.     ADC_STATE_CLR_SET(hadc->State,
  233.                       HAL_ADC_STATE_BUSY_INTERNAL,
  234.                       HAL_ADC_STATE_READY);
  235.   }
  236.  
  237.   /* Process unlocked */
  238.   __HAL_UNLOCK(hadc);
  239.  
  240.   /* Return function status */
  241.   return tmp_hal_status;
  242. }
  243.  
  244. /**
  245.   * @brief  Enables ADC, starts conversion of injected group.
  246.   *         Interruptions enabled in this function: None.
  247.   * @param  hadc: ADC handle
  248.   * @retval HAL status
  249.   */
  250. HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
  251. {
  252.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  253.  
  254.   /* Check the parameters */
  255.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  256.  
  257.   /* Process locked */
  258.   __HAL_LOCK(hadc);
  259.    
  260.   /* Enable the ADC peripheral */
  261.   tmp_hal_status = ADC_Enable(hadc);
  262.  
  263.   /* Start conversion if ADC is effectively enabled */
  264.   if (tmp_hal_status == HAL_OK)
  265.   {
  266.     /* Set ADC state                                                          */
  267.     /* - Clear state bitfield related to injected group conversion results    */
  268.     /* - Set state bitfield related to injected operation                     */
  269.     ADC_STATE_CLR_SET(hadc->State,
  270.                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
  271.                       HAL_ADC_STATE_INJ_BUSY);
  272.    
  273.     /* Case of independent mode or multimode (for devices with several ADCs): */
  274.     /* Set multimode state.                                                   */
  275.     if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
  276.     {
  277.       CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  278.     }
  279.     else
  280.     {
  281.       SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  282.     }
  283.    
  284.     /* Check if a regular conversion is ongoing */
  285.     /* Note: On this device, there is no ADC error code fields related to     */
  286.     /*       conversions on group injected only. In case of conversion on     */
  287.     /*       going on group regular, no error code is reset.                  */
  288.     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
  289.     {
  290.       /* Reset ADC all error code fields */
  291.       ADC_CLEAR_ERRORCODE(hadc);
  292.     }
  293.    
  294.     /* Process unlocked */
  295.     /* Unlock before starting ADC conversions: in case of potential           */
  296.     /* interruption, to let the process to ADC IRQ Handler.                   */
  297.     __HAL_UNLOCK(hadc);
  298.    
  299.     /* Clear injected group conversion flag */
  300.     /* (To ensure of no unknown state from potential previous ADC operations) */
  301.     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
  302.        
  303.     /* Enable conversion of injected group.                                   */
  304.     /* If software start has been selected, conversion starts immediately.    */
  305.     /* If external trigger has been selected, conversion will start at next   */
  306.     /* trigger event.                                                         */
  307.     /* If automatic injected conversion is enabled, conversion will start     */
  308.     /* after next regular group conversion.                                   */
  309.     /* Case of multimode enabled (for devices with several ADCs): if ADC is   */
  310.     /* slave, ADC is enabled only (conversion is not started). If ADC is      */
  311.     /* master, ADC is enabled and conversion is started.                      */
  312.     if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
  313.     {
  314.       if (ADC_IS_SOFTWARE_START_INJECTED(hadc)     &&
  315.           ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)  )
  316.       {
  317.         /* Start ADC conversion on injected group with SW start */
  318.         SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
  319.       }
  320.       else
  321.       {
  322.         /* Start ADC conversion on injected group with external trigger */
  323.         SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
  324.       }
  325.     }
  326.   }
  327.   else
  328.   {
  329.     /* Process unlocked */
  330.     __HAL_UNLOCK(hadc);
  331.   }
  332.  
  333.   /* Return function status */
  334.   return tmp_hal_status;
  335. }
  336.  
  337. /**
  338.   * @brief  Stop conversion of injected channels. Disable ADC peripheral if
  339.   *         no regular conversion is on going.
  340.   * @note   If ADC must be disabled and if conversion is on going on
  341.   *         regular group, function HAL_ADC_Stop must be used to stop both
  342.   *         injected and regular groups, and disable the ADC.
  343.   * @note   If injected group mode auto-injection is enabled,
  344.   *         function HAL_ADC_Stop must be used.
  345.   * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
  346.   * @param  hadc: ADC handle
  347.   * @retval None
  348.   */
  349. HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
  350. {
  351.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  352.  
  353.   /* Check the parameters */
  354.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  355.  
  356.   /* Process locked */
  357.   __HAL_LOCK(hadc);
  358.    
  359.   /* Stop potential conversion and disable ADC peripheral                     */
  360.   /* Conditioned to:                                                          */
  361.   /* - No conversion on the other group (regular group) is intended to        */
  362.   /*   continue (injected and regular groups stop conversion and ADC disable  */
  363.   /*   are common)                                                            */
  364.   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
  365.   if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
  366.      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
  367.   {
  368.     /* Stop potential conversion on going, on regular and injected groups */
  369.     /* Disable ADC peripheral */
  370.     tmp_hal_status = ADC_ConversionStop_Disable(hadc);
  371.    
  372.     /* Check if ADC is effectively disabled */
  373.     if (tmp_hal_status == HAL_OK)
  374.     {
  375.       /* Set ADC state */
  376.       ADC_STATE_CLR_SET(hadc->State,
  377.                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
  378.                         HAL_ADC_STATE_READY);
  379.     }
  380.   }
  381.   else
  382.   {
  383.     /* Update ADC state machine to error */
  384.     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  385.      
  386.     tmp_hal_status = HAL_ERROR;
  387.   }
  388.  
  389.   /* Process unlocked */
  390.   __HAL_UNLOCK(hadc);
  391.  
  392.   /* Return function status */
  393.   return tmp_hal_status;
  394. }
  395.  
  396. /**
  397.   * @brief  Wait for injected group conversion to be completed.
  398.   * @param  hadc: ADC handle
  399.   * @param  Timeout: Timeout value in millisecond.
  400.   * @retval HAL status
  401.   */
  402. HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
  403. {
  404.   uint32_t tickstart;
  405.  
  406.   /* Variables for polling in case of scan mode enabled and polling for each  */
  407.   /* conversion.                                                              */
  408.   __IO uint32_t Conversion_Timeout_CPU_cycles = 0;
  409.   uint32_t Conversion_Timeout_CPU_cycles_max = 0;
  410.  
  411.   /* Check the parameters */
  412.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  413.  
  414.   /* Get timeout */
  415.   tickstart = HAL_GetTick();  
  416.      
  417.   /* Polling for end of conversion: differentiation if single/sequence        */
  418.   /* conversion.                                                              */
  419.   /* For injected group, flag JEOC is set only at the end of the sequence,    */
  420.   /* not for each conversion within the sequence.                             */
  421.   /*  - If single conversion for injected group (scan mode disabled or        */
  422.   /*    InjectedNbrOfConversion ==1), flag JEOC is used to determine the      */
  423.   /*    conversion completion.                                                */
  424.   /*  - If sequence conversion for injected group (scan mode enabled and      */
  425.   /*    InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
  426.   /*    sequence.                                                             */
  427.   /*    To poll for each conversion, the maximum conversion time is computed  */
  428.   /*    from ADC conversion time (selected sampling time + conversion time of */
  429.   /*    12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on    */
  430.   /*    settings, conversion time range can be from 28 to 32256 CPU cycles).  */
  431.   /*    As flag JEOC is not set after each conversion, no timeout status can  */
  432.   /*    be set.                                                               */
  433.   if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
  434.   {
  435.     /* Wait until End of Conversion flag is raised */
  436.     while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
  437.     {
  438.       /* Check if timeout is disabled (set to infinite wait) */
  439.       if(Timeout != HAL_MAX_DELAY)
  440.       {
  441.         if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
  442.         {
  443.           /* Update ADC state machine to timeout */
  444.           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
  445.          
  446.           /* Process unlocked */
  447.           __HAL_UNLOCK(hadc);
  448.          
  449.           return HAL_TIMEOUT;
  450.         }
  451.       }
  452.     }
  453.   }
  454.   else
  455.   {
  456.     /* Replace polling by wait for maximum conversion time */
  457.     /*  - Computation of CPU clock cycles corresponding to ADC clock cycles   */
  458.     /*    and ADC maximum conversion cycles on all channels.                  */
  459.     /*  - Wait for the expected ADC clock cycles delay                        */
  460.     Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
  461.                                           / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
  462.                                          * ADC_CONVCYCLES_MAX_RANGE(hadc)                 );
  463.    
  464.     while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
  465.     {
  466.       /* Check if timeout is disabled (set to infinite wait) */
  467.       if(Timeout != HAL_MAX_DELAY)
  468.       {
  469.         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
  470.         {
  471.           /* Update ADC state machine to timeout */
  472.           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
  473.  
  474.           /* Process unlocked */
  475.           __HAL_UNLOCK(hadc);
  476.          
  477.           return HAL_TIMEOUT;
  478.         }
  479.       }
  480.       Conversion_Timeout_CPU_cycles ++;
  481.     }
  482.   }
  483.  
  484.   /* Clear injected group conversion flag */
  485.   /* Note: On STM32F1 ADC, clear regular conversion flag raised               */
  486.   /* simultaneously.                                                          */
  487.   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
  488.  
  489.   /* Update ADC state machine */
  490.   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
  491.  
  492.   /* Determine whether any further conversion upcoming on group injected      */
  493.   /* by external trigger or by automatic injected conversion                  */
  494.   /* from group regular.                                                      */
  495.   if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                     ||
  496.      (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&    
  497.      (ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
  498.       (hadc->Init.ContinuousConvMode == DISABLE)   )        )   )
  499.   {
  500.     /* Set ADC state */
  501.     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);  
  502.    
  503.     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
  504.     {
  505.       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
  506.     }
  507.   }
  508.  
  509.   /* Return ADC state */
  510.   return HAL_OK;
  511. }
  512.  
  513. /**
  514.   * @brief  Enables ADC, starts conversion of injected group with interruption.
  515.   *          - JEOC (end of conversion of injected group)
  516.   *         Each of these interruptions has its dedicated callback function.
  517.   * @param  hadc: ADC handle
  518.   * @retval HAL status.
  519.   */
  520. HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
  521. {
  522.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  523.  
  524.   /* Check the parameters */
  525.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  526.  
  527.   /* Process locked */
  528.   __HAL_LOCK(hadc);
  529.    
  530.   /* Enable the ADC peripheral */
  531.   tmp_hal_status = ADC_Enable(hadc);
  532.  
  533.   /* Start conversion if ADC is effectively enabled */
  534.   if (tmp_hal_status == HAL_OK)
  535.   {
  536.     /* Set ADC state                                                          */
  537.     /* - Clear state bitfield related to injected group conversion results    */
  538.     /* - Set state bitfield related to injected operation                     */
  539.     ADC_STATE_CLR_SET(hadc->State,
  540.                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
  541.                       HAL_ADC_STATE_INJ_BUSY);
  542.    
  543.     /* Case of independent mode or multimode (for devices with several ADCs): */
  544.     /* Set multimode state.                                                   */
  545.     if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
  546.     {
  547.       CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  548.     }
  549.     else
  550.     {
  551.       SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  552.     }
  553.    
  554.     /* Check if a regular conversion is ongoing */
  555.     /* Note: On this device, there is no ADC error code fields related to     */
  556.     /*       conversions on group injected only. In case of conversion on     */
  557.     /*       going on group regular, no error code is reset.                  */
  558.     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
  559.     {
  560.       /* Reset ADC all error code fields */
  561.       ADC_CLEAR_ERRORCODE(hadc);
  562.     }
  563.    
  564.     /* Process unlocked */
  565.     /* Unlock before starting ADC conversions: in case of potential           */
  566.     /* interruption, to let the process to ADC IRQ Handler.                   */
  567.     __HAL_UNLOCK(hadc);
  568.    
  569.     /* Clear injected group conversion flag */
  570.     /* (To ensure of no unknown state from potential previous ADC operations) */
  571.     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
  572.    
  573.     /* Enable end of conversion interrupt for injected channels */
  574.     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
  575.    
  576.     /* Start conversion of injected group if software start has been selected */
  577.     /* and if automatic injected conversion is disabled.                      */
  578.     /* If external trigger has been selected, conversion will start at next   */
  579.     /* trigger event.                                                         */
  580.     /* If automatic injected conversion is enabled, conversion will start     */
  581.     /* after next regular group conversion.                                   */
  582.     if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
  583.     {
  584.       if (ADC_IS_SOFTWARE_START_INJECTED(hadc)     &&
  585.           ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)  )
  586.       {
  587.         /* Start ADC conversion on injected group with SW start */
  588.         SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
  589.       }
  590.       else
  591.       {
  592.         /* Start ADC conversion on injected group with external trigger */
  593.         SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
  594.       }
  595.     }
  596.   }
  597.   else
  598.   {
  599.     /* Process unlocked */
  600.     __HAL_UNLOCK(hadc);
  601.   }
  602.  
  603.   /* Return function status */
  604.   return tmp_hal_status;
  605. }
  606.  
  607. /**
  608.   * @brief  Stop conversion of injected channels, disable interruption of
  609.   *         end-of-conversion. Disable ADC peripheral if no regular conversion
  610.   *         is on going.
  611.   * @note   If ADC must be disabled and if conversion is on going on
  612.   *         regular group, function HAL_ADC_Stop must be used to stop both
  613.   *         injected and regular groups, and disable the ADC.
  614.   * @note   If injected group mode auto-injection is enabled,
  615.   *         function HAL_ADC_Stop must be used.
  616.   * @param  hadc: ADC handle
  617.   * @retval None
  618.   */
  619. HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
  620. {
  621.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  622.  
  623.   /* Check the parameters */
  624.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  625.  
  626.   /* Process locked */
  627.   __HAL_LOCK(hadc);
  628.    
  629.   /* Stop potential conversion and disable ADC peripheral                     */
  630.   /* Conditioned to:                                                          */
  631.   /* - No conversion on the other group (regular group) is intended to        */
  632.   /*   continue (injected and regular groups stop conversion and ADC disable  */
  633.   /*   are common)                                                            */
  634.   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
  635.   if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
  636.      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
  637.   {
  638.     /* Stop potential conversion on going, on regular and injected groups */
  639.     /* Disable ADC peripheral */
  640.     tmp_hal_status = ADC_ConversionStop_Disable(hadc);
  641.    
  642.     /* Check if ADC is effectively disabled */
  643.     if (tmp_hal_status == HAL_OK)
  644.     {
  645.       /* Disable ADC end of conversion interrupt for injected channels */
  646.       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
  647.      
  648.       /* Set ADC state */
  649.       ADC_STATE_CLR_SET(hadc->State,
  650.                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
  651.                         HAL_ADC_STATE_READY);
  652.     }
  653.   }
  654.   else
  655.   {
  656.     /* Update ADC state machine to error */
  657.     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  658.      
  659.     tmp_hal_status = HAL_ERROR;
  660.   }
  661.  
  662.   /* Process unlocked */
  663.   __HAL_UNLOCK(hadc);
  664.  
  665.   /* Return function status */
  666.   return tmp_hal_status;
  667. }
  668.  
  669. #if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
  670. /**
  671.   * @brief  Enables ADC, starts conversion of regular group and transfers result
  672.   *         through DMA.
  673.   *         Multimode must have been previously configured using
  674.   *         HAL_ADCEx_MultiModeConfigChannel() function.
  675.   *         Interruptions enabled in this function:
  676.   *          - DMA transfer complete
  677.   *          - DMA half transfer
  678.   *         Each of these interruptions has its dedicated callback function.
  679.   * @note:  On STM32F1 devices, ADC slave regular group must be configured
  680.   *         with conversion trigger ADC_SOFTWARE_START.
  681.   * @note:  ADC slave can be enabled preliminarily using single-mode  
  682.   *         HAL_ADC_Start() function.
  683.   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
  684.   * @param  pData: The destination Buffer address.
  685.   * @param  Length: The length of data to be transferred from ADC peripheral to memory.
  686.   * @retval None
  687.   */
  688. HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
  689. {
  690.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  691.   ADC_HandleTypeDef tmphadcSlave;
  692.  
  693.   /* Check the parameters */
  694.   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
  695.   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
  696.  
  697.   /* Process locked */
  698.   __HAL_LOCK(hadc);
  699.  
  700.   /* Set a temporary handle of the ADC slave associated to the ADC master     */
  701.   ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
  702.  
  703.   /* On STM32F1 devices, ADC slave regular group must be configured with      */
  704.   /* conversion trigger ADC_SOFTWARE_START.                                   */
  705.   /* Note: External trigger of ADC slave must be enabled, it is already done  */
  706.   /*       into function "HAL_ADC_Init()".                                    */
  707.   if ((tmphadcSlave.Instance == NULL)                 ||
  708.       (! ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave))  )
  709.   {
  710.     /* Update ADC state machine to error */
  711.     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  712.    
  713.     /* Process unlocked */
  714.     __HAL_UNLOCK(hadc);
  715.    
  716.     return HAL_ERROR;
  717.   }
  718.  
  719.   /* Enable the ADC peripherals: master and slave (in case if not already     */
  720.   /* enabled previously)                                                      */
  721.   tmp_hal_status = ADC_Enable(hadc);
  722.   if (tmp_hal_status == HAL_OK)
  723.   {
  724.     tmp_hal_status = ADC_Enable(&tmphadcSlave);
  725.   }
  726.  
  727.   /* Start conversion if all ADCs of multimode are effectively enabled */
  728.   if (tmp_hal_status == HAL_OK)
  729.   {
  730.     /* Set ADC state (ADC master)                                             */
  731.     /* - Clear state bitfield related to regular group conversion results     */
  732.     /* - Set state bitfield related to regular operation                      */
  733.     ADC_STATE_CLR_SET(hadc->State,
  734.                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_MULTIMODE_SLAVE,
  735.                       HAL_ADC_STATE_REG_BUSY);
  736.      
  737.     /* If conversions on group regular are also triggering group injected,    */
  738.     /* update ADC state.                                                      */
  739.     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
  740.     {
  741.       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
  742.     }
  743.    
  744.     /* Process unlocked */
  745.     /* Unlock before starting ADC conversions: in case of potential           */
  746.     /* interruption, to let the process to ADC IRQ Handler.                   */
  747.     __HAL_UNLOCK(hadc);
  748.    
  749.     /* Set ADC error code to none */
  750.     ADC_CLEAR_ERRORCODE(hadc);
  751.    
  752.    
  753.     /* Set the DMA transfer complete callback */
  754.     hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
  755.        
  756.     /* Set the DMA half transfer complete callback */
  757.     hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
  758.    
  759.     /* Set the DMA error callback */
  760.     hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
  761.  
  762.    
  763.     /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
  764.     /* start (in case of SW start):                                           */
  765.    
  766.     /* Clear regular group conversion flag and overrun flag */
  767.     /* (To ensure of no unknown state from potential previous ADC operations) */
  768.     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
  769.    
  770.     /* Enable ADC DMA mode of ADC master */
  771.     SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
  772.    
  773.     /* Start the DMA channel */
  774.     HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
  775.    
  776.     /* Start conversion of regular group if software start has been selected. */
  777.     /* If external trigger has been selected, conversion will start at next   */
  778.     /* trigger event.                                                         */
  779.     /* Note: Alternate trigger for single conversion could be to force an     */
  780.     /*       additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
  781.     if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
  782.     {
  783.       /* Start ADC conversion on regular group with SW start */
  784.       SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
  785.     }
  786.     else
  787.     {
  788.       /* Start ADC conversion on regular group with external trigger */
  789.       SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
  790.     }
  791.   }
  792.   else
  793.   {
  794.     /* Process unlocked */
  795.     __HAL_UNLOCK(hadc);
  796.   }
  797.  
  798.   /* Return function status */
  799.   return tmp_hal_status;
  800. }
  801.  
  802. /**
  803.   * @brief  Stop ADC conversion of regular group (and injected channels in
  804.   *         case of auto_injection mode), disable ADC DMA transfer, disable
  805.   *         ADC peripheral.
  806.   * @note   Multimode is kept enabled after this function. To disable multimode
  807.   *         (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be
  808.   *         reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
  809.   * @note   In case of DMA configured in circular mode, function
  810.   *         HAL_ADC_Stop_DMA must be called after this function with handle of
  811.   *         ADC slave, to properly disable the DMA channel.
  812.   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
  813.   * @retval None
  814.   */
  815. HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
  816. {
  817.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  818.   ADC_HandleTypeDef tmphadcSlave;
  819.  
  820.   /* Check the parameters */
  821.   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
  822.  
  823.   /* Process locked */
  824.   __HAL_LOCK(hadc);
  825.  
  826.  
  827.   /* Stop potential conversion on going, on regular and injected groups */
  828.   /* Disable ADC master peripheral */
  829.   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
  830.  
  831.   /* Check if ADC is effectively disabled */
  832.   if (tmp_hal_status == HAL_OK)
  833.   {
  834.     /* Set a temporary handle of the ADC slave associated to the ADC master   */
  835.     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
  836.  
  837.     if (tmphadcSlave.Instance == NULL)
  838.     {
  839.       /* Update ADC state machine to error */
  840.       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
  841.      
  842.       /* Process unlocked */
  843.       __HAL_UNLOCK(hadc);
  844.      
  845.       return HAL_ERROR;
  846.     }
  847.     else
  848.     {
  849.       /* Disable ADC slave peripheral */
  850.       tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave);
  851.      
  852.       /* Check if ADC is effectively disabled */
  853.       if (tmp_hal_status != HAL_OK)
  854.       {
  855.         /* Update ADC state machine to error */
  856.         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  857.        
  858.         /* Process unlocked */
  859.         __HAL_UNLOCK(hadc);
  860.        
  861.         return HAL_ERROR;
  862.       }
  863.     }
  864.    
  865.     /* Disable ADC DMA mode */
  866.     CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
  867.    
  868.     /* Reset configuration of ADC DMA continuous request for dual mode */
  869.     CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD);
  870.        
  871.     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
  872.     /* while DMA transfer is on going)                                        */
  873.     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
  874.    
  875.    
  876.     /* Check if DMA channel effectively disabled */
  877.     if (tmp_hal_status == HAL_OK)
  878.     {
  879.       /* Change ADC state (ADC master) */
  880.       ADC_STATE_CLR_SET(hadc->State,
  881.                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
  882.                         HAL_ADC_STATE_READY);
  883.     }
  884.     else
  885.     {
  886.       /* Update ADC state machine to error */
  887.       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);    
  888.     }
  889.   }
  890.  
  891.   /* Process unlocked */
  892.   __HAL_UNLOCK(hadc);
  893.  
  894.   /* Return function status */
  895.   return tmp_hal_status;
  896. }
  897. #endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
  898.  
  899. /**
  900.   * @brief  Get ADC injected group conversion result.
  901.   * @param  hadc: ADC handle
  902.   * @param  InjectedRank: the converted ADC injected rank.
  903.   *          This parameter can be one of the following values:
  904.   *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
  905.   *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
  906.   *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
  907.   *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
  908.   * @retval None
  909.   */
  910. uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
  911. {
  912.   uint32_t tmp_jdr = 0;
  913.  
  914.   /* Check the parameters */
  915.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  916.   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
  917.    
  918.   /* Clear injected group conversion flag to have similar behaviour as        */
  919.   /* regular group: reading data register also clears end of conversion flag. */
  920.   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
  921.  
  922.   /* Get ADC converted value */
  923.   switch(InjectedRank)
  924.   {  
  925.     case ADC_INJECTED_RANK_4:
  926.       tmp_jdr = hadc->Instance->JDR4;
  927.       break;
  928.     case ADC_INJECTED_RANK_3:
  929.       tmp_jdr = hadc->Instance->JDR3;
  930.       break;
  931.     case ADC_INJECTED_RANK_2:
  932.       tmp_jdr = hadc->Instance->JDR2;
  933.       break;
  934.     case ADC_INJECTED_RANK_1:
  935.     default:
  936.       tmp_jdr = hadc->Instance->JDR1;
  937.       break;
  938.   }
  939.  
  940.   /* Return ADC converted value */
  941.   return tmp_jdr;
  942. }
  943.  
  944. #if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
  945. /**
  946.   * @brief  Returns the last ADC Master&Slave regular conversions results data
  947.   *         in the selected multi mode.
  948.   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
  949.   * @retval The converted data value.
  950.   */
  951. uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
  952. {
  953.   uint32_t tmpDR = 0;
  954.  
  955.   /* Check the parameters */
  956.   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
  957.  
  958.   /* Check the parameters */
  959.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  960.  
  961.   /* Note: EOC flag is not cleared here by software because automatically     */
  962.   /*       cleared by hardware when reading register DR.                      */
  963.  
  964.   /* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions      */
  965.   /* only if ADC1 DMA mode is enabled.                                        */
  966.   tmpDR = hadc->Instance->DR;
  967.  
  968.   if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA))
  969.   {
  970.     tmpDR |= (ADC2->DR << 16);
  971.   }
  972.    
  973.   /* Return ADC converted value */
  974.   return tmpDR;
  975. }
  976. #endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
  977.  
  978. /**
  979.   * @brief  Injected conversion complete callback in non blocking mode
  980.   * @param  hadc: ADC handle
  981.   * @retval None
  982.   */
  983. __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
  984. {
  985.   /* NOTE : This function Should not be modified, when the callback is needed,
  986.             the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
  987.   */
  988. }
  989.  
  990. /**
  991.   * @}
  992.   */
  993.  
  994. /** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
  995.   * @brief    Extended Peripheral Control functions
  996.   *
  997. @verbatim  
  998.  ===============================================================================
  999.              ##### Peripheral Control functions #####
  1000.  ===============================================================================  
  1001.     [..]  This section provides functions allowing to:
  1002.       (+) Configure channels on injected group
  1003.       (+) Configure multimode
  1004.  
  1005. @endverbatim
  1006.   * @{
  1007.   */
  1008.  
  1009. /**
  1010.   * @brief  Configures the ADC injected group and the selected channel to be
  1011.   *         linked to the injected group.
  1012.   * @note   Possibility to update parameters on the fly:
  1013.   *         This function initializes injected group, following calls to this
  1014.   *         function can be used to reconfigure some parameters of structure
  1015.   *         "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
  1016.   *         The setting of these parameters is conditioned to ADC state:
  1017.   *         this function must be called when ADC is not under conversion.
  1018.   * @param  hadc: ADC handle
  1019.   * @param  sConfigInjected: Structure of ADC injected group and ADC channel for
  1020.   *         injected group.
  1021.   * @retval None
  1022.   */
  1023. HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
  1024. {
  1025.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  1026.   __IO uint32_t wait_loop_index = 0;
  1027.  
  1028.   /* Check the parameters */
  1029.   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  1030.   assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
  1031.   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
  1032.   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
  1033.   assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
  1034.   assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
  1035.  
  1036.   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
  1037.   {
  1038.     assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
  1039.     assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
  1040.     assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
  1041.   }
  1042.  
  1043.   /* Process locked */
  1044.   __HAL_LOCK(hadc);
  1045.  
  1046.   /* Configuration of injected group sequencer:                               */
  1047.   /* - if scan mode is disabled, injected channels sequence length is set to  */
  1048.   /*   0x00: 1 channel converted (channel on regular rank 1)                  */
  1049.   /*   Parameter "InjectedNbrOfConversion" is discarded.                      */
  1050.   /*   Note: Scan mode is present by hardware on this device and, if          */
  1051.   /*   disabled, discards automatically nb of conversions. Anyway, nb of      */
  1052.   /*   conversions is forced to 0x00 for alignment over all STM32 devices.    */
  1053.   /* - if scan mode is enabled, injected channels sequence length is set to   */
  1054.   /*   parameter "InjectedNbrOfConversion".                                   */
  1055.   if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
  1056.   {
  1057.     if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
  1058.     {
  1059.       /* Clear the old SQx bits for all injected ranks */
  1060.       MODIFY_REG(hadc->Instance->JSQR                             ,
  1061.                  ADC_JSQR_JL   |
  1062.                  ADC_JSQR_JSQ4 |
  1063.                  ADC_JSQR_JSQ3 |
  1064.                  ADC_JSQR_JSQ2 |
  1065.                  ADC_JSQR_JSQ1                                    ,
  1066.                  ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
  1067.                                   ADC_INJECTED_RANK_1,
  1068.                                   0x01)                            );
  1069.     }
  1070.     /* If another injected rank than rank1 was intended to be set, and could  */
  1071.     /* not due to ScanConvMode disabled, error is reported.                   */
  1072.     else
  1073.     {
  1074.       /* Update ADC state machine to error */
  1075.       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  1076.      
  1077.       tmp_hal_status = HAL_ERROR;
  1078.     }
  1079.   }
  1080.   else
  1081.   {
  1082.     /* Since injected channels rank conv. order depends on total number of   */
  1083.     /* injected conversions, selected rank must be below or equal to total   */
  1084.     /* number of injected conversions to be updated.                         */
  1085.     if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
  1086.     {
  1087.       /* Clear the old SQx bits for the selected rank */
  1088.       /* Set the SQx bits for the selected rank */
  1089.       MODIFY_REG(hadc->Instance->JSQR                                         ,
  1090.                  
  1091.                  ADC_JSQR_JL                                               |
  1092.                  ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,                        
  1093.                                   sConfigInjected->InjectedRank,        
  1094.                                   sConfigInjected->InjectedNbrOfConversion)   ,
  1095.                  
  1096.                  ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
  1097.                  ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,      
  1098.                                   sConfigInjected->InjectedRank,        
  1099.                                   sConfigInjected->InjectedNbrOfConversion)    );
  1100.     }
  1101.     else
  1102.     {
  1103.       /* Clear the old SQx bits for the selected rank */
  1104.       MODIFY_REG(hadc->Instance->JSQR                                       ,
  1105.                  
  1106.                  ADC_JSQR_JL                                               |
  1107.                  ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,                        
  1108.                                   sConfigInjected->InjectedRank,        
  1109.                                   sConfigInjected->InjectedNbrOfConversion) ,
  1110.                  
  1111.                  0x00000000                                                  );
  1112.     }
  1113.   }
  1114.    
  1115.   /* Configuration of injected group                                          */
  1116.   /* Parameters update conditioned to ADC state:                              */
  1117.   /* Parameters that can be updated only when ADC is disabled:                */
  1118.   /*  - external trigger to start conversion                                  */
  1119.   /* Parameters update not conditioned to ADC state:                          */
  1120.   /*  - Automatic injected conversion                                         */
  1121.   /*  - Injected discontinuous mode                                           */
  1122.   /* Note: In case of ADC already enabled, caution to not launch an unwanted  */
  1123.   /*       conversion while modifying register CR2 by writing 1 to bit ADON.  */
  1124.   if (ADC_IS_ENABLE(hadc) == RESET)
  1125.   {    
  1126.     MODIFY_REG(hadc->Instance->CR2                                           ,
  1127.                ADC_CR2_JEXTSEL |
  1128.                ADC_CR2_ADON                                                  ,
  1129.                ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) );
  1130.   }
  1131.  
  1132.  
  1133.   /* Configuration of injected group                                          */
  1134.   /*  - Automatic injected conversion                                         */
  1135.   /*  - Injected discontinuous mode                                           */
  1136.  
  1137.     /* Automatic injected conversion can be enabled if injected group         */
  1138.     /* external triggers are disabled.                                        */
  1139.     if (sConfigInjected->AutoInjectedConv == ENABLE)
  1140.     {
  1141.       if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
  1142.       {
  1143.         SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
  1144.       }
  1145.       else
  1146.       {
  1147.         /* Update ADC state machine to error */
  1148.         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  1149.        
  1150.         tmp_hal_status = HAL_ERROR;
  1151.       }
  1152.     }
  1153.    
  1154.     /* Injected discontinuous can be enabled only if auto-injected mode is    */
  1155.     /* disabled.                                                              */  
  1156.     if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
  1157.     {
  1158.       if (sConfigInjected->AutoInjectedConv == DISABLE)
  1159.       {
  1160.         SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
  1161.       }
  1162.       else
  1163.       {
  1164.         /* Update ADC state machine to error */
  1165.         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  1166.        
  1167.         tmp_hal_status = HAL_ERROR;
  1168.       }
  1169.     }
  1170.  
  1171.  
  1172.   /* InjectedChannel sampling time configuration */
  1173.   /* For channels 10 to 17 */
  1174.   if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
  1175.   {
  1176.     MODIFY_REG(hadc->Instance->SMPR1                                                             ,
  1177.                ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel)                      ,
  1178.                ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
  1179.   }
  1180.   else /* For channels 0 to 9 */
  1181.   {
  1182.     MODIFY_REG(hadc->Instance->SMPR2                                                             ,
  1183.                ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel)                       ,
  1184.                ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
  1185.   }
  1186.  
  1187.   /* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor  */
  1188.   /* and VREFINT measurement path.                                            */
  1189.   if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
  1190.       (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)      )
  1191.   {
  1192.     SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
  1193.   }
  1194.  
  1195.  
  1196.   /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
  1197.   switch(sConfigInjected->InjectedRank)
  1198.   {
  1199.     case 1:
  1200.       /* Set injected channel 1 offset */
  1201.       MODIFY_REG(hadc->Instance->JOFR1,
  1202.                  ADC_JOFR1_JOFFSET1,
  1203.                  sConfigInjected->InjectedOffset);
  1204.       break;
  1205.     case 2:
  1206.       /* Set injected channel 2 offset */
  1207.       MODIFY_REG(hadc->Instance->JOFR2,
  1208.                  ADC_JOFR2_JOFFSET2,
  1209.                  sConfigInjected->InjectedOffset);
  1210.       break;
  1211.     case 3:
  1212.       /* Set injected channel 3 offset */
  1213.       MODIFY_REG(hadc->Instance->JOFR3,
  1214.                  ADC_JOFR3_JOFFSET3,
  1215.                  sConfigInjected->InjectedOffset);
  1216.       break;
  1217.     case 4:
  1218.     default:
  1219.       MODIFY_REG(hadc->Instance->JOFR4,
  1220.                  ADC_JOFR4_JOFFSET4,
  1221.                  sConfigInjected->InjectedOffset);
  1222.       break;
  1223.   }
  1224.  
  1225.   /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
  1226.   /* and VREFINT measurement path.                                            */
  1227.   if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
  1228.       (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)      )
  1229.   {
  1230.     /* For STM32F1 devices with several ADC: Only ADC1 can access internal    */
  1231.     /* measurement channels (VrefInt/TempSensor). If these channels are       */
  1232.     /* intended to be set on other ADC instances, an error is reported.       */
  1233.     if (hadc->Instance == ADC1)
  1234.     {
  1235.       if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
  1236.       {
  1237.         SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
  1238.        
  1239.         if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
  1240.         {
  1241.           /* Delay for temperature sensor stabilization time */
  1242.           /* Compute number of CPU cycles to wait for */
  1243.           wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
  1244.           while(wait_loop_index != 0)
  1245.           {
  1246.             wait_loop_index--;
  1247.           }
  1248.         }
  1249.       }
  1250.     }
  1251.     else
  1252.     {
  1253.       /* Update ADC state machine to error */
  1254.       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  1255.      
  1256.       tmp_hal_status = HAL_ERROR;
  1257.     }
  1258.   }
  1259.  
  1260.   /* Process unlocked */
  1261.   __HAL_UNLOCK(hadc);
  1262.  
  1263.   /* Return function status */
  1264.   return tmp_hal_status;
  1265. }
  1266.  
  1267. #if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
  1268. /**
  1269.   * @brief  Enable ADC multimode and configure multimode parameters
  1270.   * @note   Possibility to update parameters on the fly:
  1271.   *         This function initializes multimode parameters, following  
  1272.   *         calls to this function can be used to reconfigure some parameters
  1273.   *         of structure "ADC_MultiModeTypeDef" on the fly, without reseting
  1274.   *         the ADCs (both ADCs of the common group).
  1275.   *         The setting of these parameters is conditioned to ADC state.
  1276.   *         For parameters constraints, see comments of structure
  1277.   *         "ADC_MultiModeTypeDef".
  1278.   * @note   To change back configuration from multimode to single mode, ADC must
  1279.   *         be reset (using function HAL_ADC_Init() ).
  1280.   * @param  hadc: ADC handle
  1281.   * @param  multimode: Structure of ADC multimode configuration
  1282.   * @retval HAL status
  1283.   */
  1284. HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
  1285. {
  1286.   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  1287.   ADC_HandleTypeDef tmphadcSlave;
  1288.  
  1289.   /* Check the parameters */
  1290.   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
  1291.   assert_param(IS_ADC_MODE(multimode->Mode));
  1292.  
  1293.   /* Process locked */
  1294.   __HAL_LOCK(hadc);
  1295.  
  1296.   /* Set a temporary handle of the ADC slave associated to the ADC master     */
  1297.   ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
  1298.  
  1299.   /* Parameters update conditioned to ADC state:                              */
  1300.   /* Parameters that can be updated when ADC is disabled or enabled without   */
  1301.   /* conversion on going on regular group:                                    */
  1302.   /*  - ADC master and ADC slave DMA configuration                            */
  1303.   /* Parameters that can be updated only when ADC is disabled:                */
  1304.   /*  - Multimode mode selection                                              */
  1305.   /* To optimize code, all multimode settings can be set when both ADCs of    */
  1306.   /* the common group are in state: disabled.                                 */
  1307.   if ((ADC_IS_ENABLE(hadc) == RESET)                     &&
  1308.       (ADC_IS_ENABLE(&tmphadcSlave) == RESET)            &&
  1309.       (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance))   )
  1310.   {
  1311.     MODIFY_REG(hadc->Instance->CR1,
  1312.                ADC_CR1_DUALMOD    ,
  1313.                multimode->Mode     );
  1314.   }
  1315.   /* If one of the ADC sharing the same common group is enabled, no update    */
  1316.   /* could be done on neither of the multimode structure parameters.          */
  1317.   else
  1318.   {
  1319.     /* Update ADC state machine to error */
  1320.     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  1321.    
  1322.     tmp_hal_status = HAL_ERROR;
  1323.   }
  1324.    
  1325.    
  1326.   /* Process unlocked */
  1327.   __HAL_UNLOCK(hadc);
  1328.  
  1329.   /* Return function status */
  1330.   return tmp_hal_status;
  1331. }
  1332. #endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
  1333. /**
  1334.   * @}
  1335.   */  
  1336.  
  1337. /**
  1338.   * @}
  1339.   */
  1340.  
  1341. #endif /* HAL_ADC_MODULE_ENABLED */
  1342. /**
  1343.   * @}
  1344.   */
  1345.  
  1346. /**
  1347.   * @}
  1348.   */
  1349.  
  1350. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1351.