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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_tim.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of TIM LL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10.   * All rights reserved.</center></h2>
  11.   *
  12.   * This software component is licensed by ST under BSD 3-Clause license,
  13.   * the "License"; You may not use this file except in compliance with the
  14.   * License. You may obtain a copy of the License at:
  15.   *                        opensource.org/licenses/BSD-3-Clause
  16.   *
  17.   ******************************************************************************
  18.   */
  19.  
  20. /* Define to prevent recursive inclusion -------------------------------------*/
  21. #ifndef __STM32F1xx_LL_TIM_H
  22. #define __STM32F1xx_LL_TIM_H
  23.  
  24. #ifdef __cplusplus
  25. extern "C" {
  26. #endif
  27.  
  28. /* Includes ------------------------------------------------------------------*/
  29. #include "stm32f1xx.h"
  30.  
  31. /** @addtogroup STM32F1xx_LL_Driver
  32.   * @{
  33.   */
  34.  
  35. #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
  36.  
  37. /** @defgroup TIM_LL TIM
  38.   * @{
  39.   */
  40.  
  41. /* Private types -------------------------------------------------------------*/
  42. /* Private variables ---------------------------------------------------------*/
  43. /** @defgroup TIM_LL_Private_Variables TIM Private Variables
  44.   * @{
  45.   */
  46. static const uint8_t OFFSET_TAB_CCMRx[] =
  47. {
  48.   0x00U,   /* 0: TIMx_CH1  */
  49.   0x00U,   /* 1: TIMx_CH1N */
  50.   0x00U,   /* 2: TIMx_CH2  */
  51.   0x00U,   /* 3: TIMx_CH2N */
  52.   0x04U,   /* 4: TIMx_CH3  */
  53.   0x04U,   /* 5: TIMx_CH3N */
  54.   0x04U    /* 6: TIMx_CH4  */
  55. };
  56.  
  57. static const uint8_t SHIFT_TAB_OCxx[] =
  58. {
  59.   0U,            /* 0: OC1M, OC1FE, OC1PE */
  60.   0U,            /* 1: - NA */
  61.   8U,            /* 2: OC2M, OC2FE, OC2PE */
  62.   0U,            /* 3: - NA */
  63.   0U,            /* 4: OC3M, OC3FE, OC3PE */
  64.   0U,            /* 5: - NA */
  65.   8U             /* 6: OC4M, OC4FE, OC4PE */
  66. };
  67.  
  68. static const uint8_t SHIFT_TAB_ICxx[] =
  69. {
  70.   0U,            /* 0: CC1S, IC1PSC, IC1F */
  71.   0U,            /* 1: - NA */
  72.   8U,            /* 2: CC2S, IC2PSC, IC2F */
  73.   0U,            /* 3: - NA */
  74.   0U,            /* 4: CC3S, IC3PSC, IC3F */
  75.   0U,            /* 5: - NA */
  76.   8U             /* 6: CC4S, IC4PSC, IC4F */
  77. };
  78.  
  79. static const uint8_t SHIFT_TAB_CCxP[] =
  80. {
  81.   0U,            /* 0: CC1P */
  82.   2U,            /* 1: CC1NP */
  83.   4U,            /* 2: CC2P */
  84.   6U,            /* 3: CC2NP */
  85.   8U,            /* 4: CC3P */
  86.   10U,           /* 5: CC3NP */
  87.   12U            /* 6: CC4P */
  88. };
  89.  
  90. static const uint8_t SHIFT_TAB_OISx[] =
  91. {
  92.   0U,            /* 0: OIS1 */
  93.   1U,            /* 1: OIS1N */
  94.   2U,            /* 2: OIS2 */
  95.   3U,            /* 3: OIS2N */
  96.   4U,            /* 4: OIS3 */
  97.   5U,            /* 5: OIS3N */
  98.   6U             /* 6: OIS4 */
  99. };
  100. /**
  101.   * @}
  102.   */
  103.  
  104. /* Private constants ---------------------------------------------------------*/
  105. /** @defgroup TIM_LL_Private_Constants TIM Private Constants
  106.   * @{
  107.   */
  108.  
  109.  
  110.  
  111. /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
  112. #define DT_DELAY_1 ((uint8_t)0x7F)
  113. #define DT_DELAY_2 ((uint8_t)0x3F)
  114. #define DT_DELAY_3 ((uint8_t)0x1F)
  115. #define DT_DELAY_4 ((uint8_t)0x1F)
  116.  
  117. /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
  118. #define DT_RANGE_1 ((uint8_t)0x00)
  119. #define DT_RANGE_2 ((uint8_t)0x80)
  120. #define DT_RANGE_3 ((uint8_t)0xC0)
  121. #define DT_RANGE_4 ((uint8_t)0xE0)
  122.  
  123.  
  124. /**
  125.   * @}
  126.   */
  127.  
  128. /* Private macros ------------------------------------------------------------*/
  129. /** @defgroup TIM_LL_Private_Macros TIM Private Macros
  130.   * @{
  131.   */
  132. /** @brief  Convert channel id into channel index.
  133.   * @param  __CHANNEL__ This parameter can be one of the following values:
  134.   *         @arg @ref LL_TIM_CHANNEL_CH1
  135.   *         @arg @ref LL_TIM_CHANNEL_CH1N
  136.   *         @arg @ref LL_TIM_CHANNEL_CH2
  137.   *         @arg @ref LL_TIM_CHANNEL_CH2N
  138.   *         @arg @ref LL_TIM_CHANNEL_CH3
  139.   *         @arg @ref LL_TIM_CHANNEL_CH3N
  140.   *         @arg @ref LL_TIM_CHANNEL_CH4
  141.   * @retval none
  142.   */
  143. #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
  144.   (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
  145.    ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
  146.    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
  147.    ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
  148.    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
  149.    ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
  150.  
  151. /** @brief  Calculate the deadtime sampling period(in ps).
  152.   * @param  __TIMCLK__ timer input clock frequency (in Hz).
  153.   * @param  __CKD__ This parameter can be one of the following values:
  154.   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
  155.   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
  156.   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
  157.   * @retval none
  158.   */
  159. #define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
  160.   (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
  161.    ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
  162.    ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
  163. /**
  164.   * @}
  165.   */
  166.  
  167.  
  168. /* Exported types ------------------------------------------------------------*/
  169. #if defined(USE_FULL_LL_DRIVER)
  170. /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
  171.   * @{
  172.   */
  173.  
  174. /**
  175.   * @brief  TIM Time Base configuration structure definition.
  176.   */
  177. typedef struct
  178. {
  179.   uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
  180.                                    This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
  181.  
  182.                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
  183.  
  184.   uint32_t CounterMode;       /*!< Specifies the counter mode.
  185.                                    This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
  186.  
  187.                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
  188.  
  189.   uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
  190.                                    Auto-Reload Register at the next update event.
  191.                                    This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
  192.                                    Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
  193.  
  194.                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
  195.  
  196.   uint32_t ClockDivision;     /*!< Specifies the clock division.
  197.                                    This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
  198.  
  199.                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
  200.  
  201.   uint8_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
  202.                                    reaches zero, an update event is generated and counting restarts
  203.                                    from the RCR value (N).
  204.                                    This means in PWM mode that (N+1) corresponds to:
  205.                                       - the number of PWM periods in edge-aligned mode
  206.                                       - the number of half PWM period in center-aligned mode
  207.                                    This parameter must be a number between 0x00 and 0xFF.
  208.  
  209.                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
  210. } LL_TIM_InitTypeDef;
  211.  
  212. /**
  213.   * @brief  TIM Output Compare configuration structure definition.
  214.   */
  215. typedef struct
  216. {
  217.   uint32_t OCMode;        /*!< Specifies the output mode.
  218.                                This parameter can be a value of @ref TIM_LL_EC_OCMODE.
  219.  
  220.                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
  221.  
  222.   uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
  223.                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
  224.  
  225.                                This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
  226.  
  227.   uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
  228.                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
  229.  
  230.                                This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
  231.  
  232.   uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
  233.                                This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
  234.  
  235.                                This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
  236.  
  237.   uint32_t OCPolarity;    /*!< Specifies the output polarity.
  238.                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
  239.  
  240.                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
  241.  
  242.   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
  243.                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
  244.  
  245.                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
  246.  
  247.  
  248.   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
  249.                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
  250.  
  251.                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
  252.  
  253.   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
  254.                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
  255.  
  256.                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
  257. } LL_TIM_OC_InitTypeDef;
  258.  
  259. /**
  260.   * @brief  TIM Input Capture configuration structure definition.
  261.   */
  262.  
  263. typedef struct
  264. {
  265.  
  266.   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
  267.                                This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
  268.  
  269.                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
  270.  
  271.   uint32_t ICActiveInput; /*!< Specifies the input.
  272.                                This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
  273.  
  274.                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
  275.  
  276.   uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
  277.                                This parameter can be a value of @ref TIM_LL_EC_ICPSC.
  278.  
  279.                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
  280.  
  281.   uint32_t ICFilter;      /*!< Specifies the input capture filter.
  282.                                This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
  283.  
  284.                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
  285. } LL_TIM_IC_InitTypeDef;
  286.  
  287.  
  288. /**
  289.   * @brief  TIM Encoder interface configuration structure definition.
  290.   */
  291. typedef struct
  292. {
  293.   uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
  294.                                  This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
  295.  
  296.                                  This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
  297.  
  298.   uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
  299.                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
  300.  
  301.                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
  302.  
  303.   uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
  304.                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
  305.  
  306.                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
  307.  
  308.   uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
  309.                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
  310.  
  311.                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
  312.  
  313.   uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
  314.                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
  315.  
  316.                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
  317.  
  318.   uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
  319.                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
  320.  
  321.                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
  322.  
  323.   uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
  324.                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
  325.  
  326.                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
  327.  
  328.   uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
  329.                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
  330.  
  331.                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
  332.  
  333.   uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
  334.                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
  335.  
  336.                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
  337.  
  338. } LL_TIM_ENCODER_InitTypeDef;
  339.  
  340. /**
  341.   * @brief  TIM Hall sensor interface configuration structure definition.
  342.   */
  343. typedef struct
  344. {
  345.  
  346.   uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
  347.                                     This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
  348.  
  349.                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
  350.  
  351.   uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
  352.                                     Prescaler must be set to get a maximum counter period longer than the
  353.                                     time interval between 2 consecutive changes on the Hall inputs.
  354.                                     This parameter can be a value of @ref TIM_LL_EC_ICPSC.
  355.  
  356.                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
  357.  
  358.   uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
  359.                                     This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
  360.  
  361.                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
  362.  
  363.   uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
  364.                                     A positive pulse (TRGO event) is generated with a programmable delay every time
  365.                                     a change occurs on the Hall inputs.
  366.                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
  367.  
  368.                                     This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
  369. } LL_TIM_HALLSENSOR_InitTypeDef;
  370.  
  371. /**
  372.   * @brief  BDTR (Break and Dead Time) structure definition
  373.   */
  374. typedef struct
  375. {
  376.   uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
  377.                                       This parameter can be a value of @ref TIM_LL_EC_OSSR
  378.  
  379.                                       This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
  380.  
  381.                                       @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
  382.  
  383.   uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
  384.                                       This parameter can be a value of @ref TIM_LL_EC_OSSI
  385.  
  386.                                       This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
  387.  
  388.                                       @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
  389.  
  390.   uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
  391.                                       This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
  392.  
  393.                                       @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
  394.                                             has been written, their content is frozen until the next reset.*/
  395.  
  396.   uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
  397.                                       switching-on of the outputs.
  398.                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
  399.  
  400.                                       This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
  401.  
  402.                                       @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
  403.  
  404.   uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
  405.                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
  406.  
  407.                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
  408.  
  409.                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
  410.  
  411.   uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
  412.                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
  413.  
  414.                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
  415.  
  416.                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
  417.  
  418.   uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
  419.                                       This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
  420.  
  421.                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
  422.  
  423.                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
  424. } LL_TIM_BDTR_InitTypeDef;
  425.  
  426. /**
  427.   * @}
  428.   */
  429. #endif /* USE_FULL_LL_DRIVER */
  430.  
  431. /* Exported constants --------------------------------------------------------*/
  432. /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
  433.   * @{
  434.   */
  435.  
  436. /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
  437.   * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
  438.   * @{
  439.   */
  440. #define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
  441. #define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
  442. #define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
  443. #define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
  444. #define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
  445. #define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
  446. #define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
  447. #define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
  448. #define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
  449. #define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
  450. #define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
  451. #define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
  452. /**
  453.   * @}
  454.   */
  455.  
  456. #if defined(USE_FULL_LL_DRIVER)
  457. /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
  458.   * @{
  459.   */
  460. #define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
  461. #define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
  462. /**
  463.   * @}
  464.   */
  465.  
  466. /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
  467.   * @{
  468.   */
  469. #define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
  470. #define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
  471. /**
  472.   * @}
  473.   */
  474. #endif /* USE_FULL_LL_DRIVER */
  475.  
  476. /** @defgroup TIM_LL_EC_IT IT Defines
  477.   * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
  478.   * @{
  479.   */
  480. #define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
  481. #define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
  482. #define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
  483. #define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
  484. #define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
  485. #define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
  486. #define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
  487. #define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
  488. /**
  489.   * @}
  490.   */
  491.  
  492. /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
  493.   * @{
  494.   */
  495. #define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
  496. #define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
  497. /**
  498.   * @}
  499.   */
  500.  
  501. /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
  502.   * @{
  503.   */
  504. #define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter is not stopped at update event */
  505. #define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter stops counting at the next update event */
  506. /**
  507.   * @}
  508.   */
  509.  
  510. /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
  511.   * @{
  512.   */
  513. #define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
  514. #define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
  515. #define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
  516. #define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
  517. #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
  518. /**
  519.   * @}
  520.   */
  521.  
  522. /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
  523.   * @{
  524.   */
  525. #define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
  526. #define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
  527. #define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
  528. /**
  529.   * @}
  530.   */
  531.  
  532. /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
  533.   * @{
  534.   */
  535. #define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
  536. #define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
  537. /**
  538.   * @}
  539.   */
  540.  
  541. /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
  542.   * @{
  543.   */
  544. #define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
  545. #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
  546. /**
  547.   * @}
  548.   */
  549.  
  550. /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
  551.   * @{
  552.   */
  553. #define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
  554. #define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
  555. /**
  556.   * @}
  557.   */
  558.  
  559. /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
  560.   * @{
  561.   */
  562. #define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
  563. #define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
  564. #define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
  565. #define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
  566. /**
  567.   * @}
  568.   */
  569.  
  570. /** @defgroup TIM_LL_EC_CHANNEL Channel
  571.   * @{
  572.   */
  573. #define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
  574. #define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
  575. #define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
  576. #define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
  577. #define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
  578. #define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
  579. #define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
  580. /**
  581.   * @}
  582.   */
  583.  
  584. #if defined(USE_FULL_LL_DRIVER)
  585. /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
  586.   * @{
  587.   */
  588. #define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
  589. #define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
  590. /**
  591.   * @}
  592.   */
  593. #endif /* USE_FULL_LL_DRIVER */
  594.  
  595. /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
  596.   * @{
  597.   */
  598. #define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
  599. #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
  600. #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
  601. #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
  602. #define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
  603. #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
  604. #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
  605. #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
  606. /**
  607.   * @}
  608.   */
  609.  
  610. /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
  611.   * @{
  612.   */
  613. #define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
  614. #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
  615. /**
  616.   * @}
  617.   */
  618.  
  619. /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
  620.   * @{
  621.   */
  622. #define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
  623. #define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
  624. /**
  625.   * @}
  626.   */
  627.  
  628.  
  629. /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
  630.   * @{
  631.   */
  632. #define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
  633. #define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
  634. #define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
  635. /**
  636.   * @}
  637.   */
  638.  
  639. /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
  640.   * @{
  641.   */
  642. #define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
  643. #define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
  644. #define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
  645. #define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
  646. /**
  647.   * @}
  648.   */
  649.  
  650. /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
  651.   * @{
  652.   */
  653. #define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
  654. #define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
  655. #define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
  656. #define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
  657. #define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
  658. #define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
  659. #define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
  660. #define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
  661. #define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
  662. #define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
  663. #define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
  664. #define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
  665. #define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
  666. #define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
  667. #define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
  668. #define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
  669. /**
  670.   * @}
  671.   */
  672.  
  673. /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
  674.   * @{
  675.   */
  676. #define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
  677. #define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
  678. /**
  679.   * @}
  680.   */
  681.  
  682. /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
  683.   * @{
  684.   */
  685. #define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
  686. #define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
  687. #define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
  688. /**
  689.   * @}
  690.   */
  691.  
  692. /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
  693.   * @{
  694.   */
  695. #define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
  696. #define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
  697. #define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
  698. /**
  699.   * @}
  700.   */
  701.  
  702. /** @defgroup TIM_LL_EC_TRGO Trigger Output
  703.   * @{
  704.   */
  705. #define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
  706. #define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
  707. #define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
  708. #define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
  709. #define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
  710. #define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
  711. #define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
  712. #define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
  713. /**
  714.   * @}
  715.   */
  716.  
  717.  
  718. /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
  719.   * @{
  720.   */
  721. #define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
  722. #define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
  723. #define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
  724. #define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
  725. /**
  726.   * @}
  727.   */
  728.  
  729. /** @defgroup TIM_LL_EC_TS Trigger Selection
  730.   * @{
  731.   */
  732. #define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
  733. #define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
  734. #define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
  735. #define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
  736. #define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
  737. #define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
  738. #define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
  739. #define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
  740. /**
  741.   * @}
  742.   */
  743.  
  744. /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
  745.   * @{
  746.   */
  747. #define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
  748. #define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
  749. /**
  750.   * @}
  751.   */
  752.  
  753. /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
  754.   * @{
  755.   */
  756. #define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
  757. #define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
  758. #define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
  759. #define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
  760. /**
  761.   * @}
  762.   */
  763.  
  764. /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
  765.   * @{
  766.   */
  767. #define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
  768. #define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
  769. #define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
  770. #define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
  771. #define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
  772. #define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
  773. #define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
  774. #define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
  775. #define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
  776. #define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
  777. #define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
  778. #define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
  779. #define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
  780. #define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
  781. #define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
  782. #define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
  783. /**
  784.   * @}
  785.   */
  786.  
  787.  
  788. /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
  789.   * @{
  790.   */
  791. #define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
  792. #define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
  793. /**
  794.   * @}
  795.   */
  796.  
  797.  
  798.  
  799.  
  800. /** @defgroup TIM_LL_EC_OSSI OSSI
  801.   * @{
  802.   */
  803. #define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
  804. #define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
  805. /**
  806.   * @}
  807.   */
  808.  
  809. /** @defgroup TIM_LL_EC_OSSR OSSR
  810.   * @{
  811.   */
  812. #define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
  813. #define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
  814. /**
  815.   * @}
  816.   */
  817.  
  818.  
  819. /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
  820.   * @{
  821.   */
  822. #define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
  823. #define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
  824. #define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
  825. #define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
  826. #define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
  827. #define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
  828. #define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
  829. #define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
  830. #define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
  831. #define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
  832. #define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
  833. #define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
  834. #define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
  835. #define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
  836. #define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
  837. #define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
  838. #define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
  839. #define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
  840. /**
  841.   * @}
  842.   */
  843.  
  844. /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
  845.   * @{
  846.   */
  847. #define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
  848. #define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
  849. #define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
  850. #define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
  851. #define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
  852. #define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
  853. #define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
  854. #define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
  855. #define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
  856. #define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
  857. #define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
  858. #define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
  859. #define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
  860. #define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
  861. #define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
  862. #define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
  863. #define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
  864. #define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
  865. /**
  866.   * @}
  867.   */
  868.  
  869.  
  870. /**
  871.   * @}
  872.   */
  873.  
  874. /* Exported macro ------------------------------------------------------------*/
  875. /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
  876.   * @{
  877.   */
  878.  
  879. /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
  880.   * @{
  881.   */
  882. /**
  883.   * @brief  Write a value in TIM register.
  884.   * @param  __INSTANCE__ TIM Instance
  885.   * @param  __REG__ Register to be written
  886.   * @param  __VALUE__ Value to be written in the register
  887.   * @retval None
  888.   */
  889. #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
  890.  
  891. /**
  892.   * @brief  Read a value in TIM register.
  893.   * @param  __INSTANCE__ TIM Instance
  894.   * @param  __REG__ Register to be read
  895.   * @retval Register value
  896.   */
  897. #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
  898. /**
  899.   * @}
  900.   */
  901.  
  902. /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
  903.   * @{
  904.   */
  905.  
  906. /**
  907.   * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
  908.   * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
  909.   * @param  __TIMCLK__ timer input clock frequency (in Hz)
  910.   * @param  __CKD__ This parameter can be one of the following values:
  911.   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
  912.   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
  913.   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
  914.   * @param  __DT__ deadtime duration (in ns)
  915.   * @retval DTG[0:7]
  916.   */
  917. #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
  918.   ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \
  919.     (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
  920.     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
  921.     (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
  922.     0U)
  923.  
  924. /**
  925.   * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
  926.   * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
  927.   * @param  __TIMCLK__ timer input clock frequency (in Hz)
  928.   * @param  __CNTCLK__ counter clock frequency (in Hz)
  929.   * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
  930.   */
  931. #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
  932.   (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
  933.  
  934. /**
  935.   * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
  936.   * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
  937.   * @param  __TIMCLK__ timer input clock frequency (in Hz)
  938.   * @param  __PSC__ prescaler
  939.   * @param  __FREQ__ output signal frequency (in Hz)
  940.   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
  941.   */
  942. #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
  943.   ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
  944.  
  945. /**
  946.   * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
  947.   * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
  948.   * @param  __TIMCLK__ timer input clock frequency (in Hz)
  949.   * @param  __PSC__ prescaler
  950.   * @param  __DELAY__ timer output compare active/inactive delay (in us)
  951.   * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
  952.   */
  953. #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
  954.   ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
  955.               / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
  956.  
  957. /**
  958.   * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
  959.   * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
  960.   * @param  __TIMCLK__ timer input clock frequency (in Hz)
  961.   * @param  __PSC__ prescaler
  962.   * @param  __DELAY__ timer output compare active/inactive delay (in us)
  963.   * @param  __PULSE__ pulse duration (in us)
  964.   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
  965.   */
  966. #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
  967.   ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
  968.               + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
  969.  
  970. /**
  971.   * @brief  HELPER macro retrieving the ratio of the input capture prescaler
  972.   * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
  973.   * @param  __ICPSC__ This parameter can be one of the following values:
  974.   *         @arg @ref LL_TIM_ICPSC_DIV1
  975.   *         @arg @ref LL_TIM_ICPSC_DIV2
  976.   *         @arg @ref LL_TIM_ICPSC_DIV4
  977.   *         @arg @ref LL_TIM_ICPSC_DIV8
  978.   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
  979.   */
  980. #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
  981.   ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
  982.  
  983.  
  984. /**
  985.   * @}
  986.   */
  987.  
  988.  
  989. /**
  990.   * @}
  991.   */
  992.  
  993. /* Exported functions --------------------------------------------------------*/
  994. /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
  995.   * @{
  996.   */
  997.  
  998. /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
  999.   * @{
  1000.   */
  1001. /**
  1002.   * @brief  Enable timer counter.
  1003.   * @rmtoll CR1          CEN           LL_TIM_EnableCounter
  1004.   * @param  TIMx Timer instance
  1005.   * @retval None
  1006.   */
  1007. __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
  1008. {
  1009.   SET_BIT(TIMx->CR1, TIM_CR1_CEN);
  1010. }
  1011.  
  1012. /**
  1013.   * @brief  Disable timer counter.
  1014.   * @rmtoll CR1          CEN           LL_TIM_DisableCounter
  1015.   * @param  TIMx Timer instance
  1016.   * @retval None
  1017.   */
  1018. __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
  1019. {
  1020.   CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
  1021. }
  1022.  
  1023. /**
  1024.   * @brief  Indicates whether the timer counter is enabled.
  1025.   * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
  1026.   * @param  TIMx Timer instance
  1027.   * @retval State of bit (1 or 0).
  1028.   */
  1029. __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
  1030. {
  1031.   return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
  1032. }
  1033.  
  1034. /**
  1035.   * @brief  Enable update event generation.
  1036.   * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
  1037.   * @param  TIMx Timer instance
  1038.   * @retval None
  1039.   */
  1040. __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
  1041. {
  1042.   CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
  1043. }
  1044.  
  1045. /**
  1046.   * @brief  Disable update event generation.
  1047.   * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
  1048.   * @param  TIMx Timer instance
  1049.   * @retval None
  1050.   */
  1051. __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
  1052. {
  1053.   SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
  1054. }
  1055.  
  1056. /**
  1057.   * @brief  Indicates whether update event generation is enabled.
  1058.   * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
  1059.   * @param  TIMx Timer instance
  1060.   * @retval Inverted state of bit (0 or 1).
  1061.   */
  1062. __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
  1063. {
  1064.   return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
  1065. }
  1066.  
  1067. /**
  1068.   * @brief  Set update event source
  1069.   * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
  1070.   *       generate an update interrupt or DMA request if enabled:
  1071.   *        - Counter overflow/underflow
  1072.   *        - Setting the UG bit
  1073.   *        - Update generation through the slave mode controller
  1074.   * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
  1075.   *       overflow/underflow generates an update interrupt or DMA request if enabled.
  1076.   * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
  1077.   * @param  TIMx Timer instance
  1078.   * @param  UpdateSource This parameter can be one of the following values:
  1079.   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
  1080.   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
  1081.   * @retval None
  1082.   */
  1083. __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
  1084. {
  1085.   MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
  1086. }
  1087.  
  1088. /**
  1089.   * @brief  Get actual event update source
  1090.   * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
  1091.   * @param  TIMx Timer instance
  1092.   * @retval Returned value can be one of the following values:
  1093.   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
  1094.   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
  1095.   */
  1096. __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
  1097. {
  1098.   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
  1099. }
  1100.  
  1101. /**
  1102.   * @brief  Set one pulse mode (one shot v.s. repetitive).
  1103.   * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
  1104.   * @param  TIMx Timer instance
  1105.   * @param  OnePulseMode This parameter can be one of the following values:
  1106.   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
  1107.   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
  1108.   * @retval None
  1109.   */
  1110. __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
  1111. {
  1112.   MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
  1113. }
  1114.  
  1115. /**
  1116.   * @brief  Get actual one pulse mode.
  1117.   * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
  1118.   * @param  TIMx Timer instance
  1119.   * @retval Returned value can be one of the following values:
  1120.   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
  1121.   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
  1122.   */
  1123. __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
  1124. {
  1125.   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
  1126. }
  1127.  
  1128. /**
  1129.   * @brief  Set the timer counter counting mode.
  1130.   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
  1131.   *       check whether or not the counter mode selection feature is supported
  1132.   *       by a timer instance.
  1133.   * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  1134.   *       requires a timer reset to avoid unexpected direction
  1135.   *       due to DIR bit readonly in center aligned mode.
  1136.   * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
  1137.   *         CR1          CMS           LL_TIM_SetCounterMode
  1138.   * @param  TIMx Timer instance
  1139.   * @param  CounterMode This parameter can be one of the following values:
  1140.   *         @arg @ref LL_TIM_COUNTERMODE_UP
  1141.   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
  1142.   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
  1143.   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
  1144.   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
  1145.   * @retval None
  1146.   */
  1147. __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
  1148. {
  1149.   MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
  1150. }
  1151.  
  1152. /**
  1153.   * @brief  Get actual counter mode.
  1154.   * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
  1155.   *       check whether or not the counter mode selection feature is supported
  1156.   *       by a timer instance.
  1157.   * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
  1158.   *         CR1          CMS           LL_TIM_GetCounterMode
  1159.   * @param  TIMx Timer instance
  1160.   * @retval Returned value can be one of the following values:
  1161.   *         @arg @ref LL_TIM_COUNTERMODE_UP
  1162.   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
  1163.   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
  1164.   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
  1165.   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
  1166.   */
  1167. __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
  1168. {
  1169.   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
  1170. }
  1171.  
  1172. /**
  1173.   * @brief  Enable auto-reload (ARR) preload.
  1174.   * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
  1175.   * @param  TIMx Timer instance
  1176.   * @retval None
  1177.   */
  1178. __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
  1179. {
  1180.   SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
  1181. }
  1182.  
  1183. /**
  1184.   * @brief  Disable auto-reload (ARR) preload.
  1185.   * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
  1186.   * @param  TIMx Timer instance
  1187.   * @retval None
  1188.   */
  1189. __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
  1190. {
  1191.   CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
  1192. }
  1193.  
  1194. /**
  1195.   * @brief  Indicates whether auto-reload (ARR) preload is enabled.
  1196.   * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
  1197.   * @param  TIMx Timer instance
  1198.   * @retval State of bit (1 or 0).
  1199.   */
  1200. __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
  1201. {
  1202.   return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
  1203. }
  1204.  
  1205. /**
  1206.   * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
  1207.   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
  1208.   *       whether or not the clock division feature is supported by the timer
  1209.   *       instance.
  1210.   * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
  1211.   * @param  TIMx Timer instance
  1212.   * @param  ClockDivision This parameter can be one of the following values:
  1213.   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
  1214.   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
  1215.   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
  1216.   * @retval None
  1217.   */
  1218. __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
  1219. {
  1220.   MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
  1221. }
  1222.  
  1223. /**
  1224.   * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
  1225.   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
  1226.   *       whether or not the clock division feature is supported by the timer
  1227.   *       instance.
  1228.   * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
  1229.   * @param  TIMx Timer instance
  1230.   * @retval Returned value can be one of the following values:
  1231.   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
  1232.   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
  1233.   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
  1234.   */
  1235. __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
  1236. {
  1237.   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
  1238. }
  1239.  
  1240. /**
  1241.   * @brief  Set the counter value.
  1242.   * @rmtoll CNT          CNT           LL_TIM_SetCounter
  1243.   * @param  TIMx Timer instance
  1244.   * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
  1245.   * @retval None
  1246.   */
  1247. __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
  1248. {
  1249.   WRITE_REG(TIMx->CNT, Counter);
  1250. }
  1251.  
  1252. /**
  1253.   * @brief  Get the counter value.
  1254.   * @rmtoll CNT          CNT           LL_TIM_GetCounter
  1255.   * @param  TIMx Timer instance
  1256.   * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
  1257.   */
  1258. __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
  1259. {
  1260.   return (uint32_t)(READ_REG(TIMx->CNT));
  1261. }
  1262.  
  1263. /**
  1264.   * @brief  Get the current direction of the counter
  1265.   * @rmtoll CR1          DIR           LL_TIM_GetDirection
  1266.   * @param  TIMx Timer instance
  1267.   * @retval Returned value can be one of the following values:
  1268.   *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
  1269.   *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
  1270.   */
  1271. __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
  1272. {
  1273.   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
  1274. }
  1275.  
  1276. /**
  1277.   * @brief  Set the prescaler value.
  1278.   * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
  1279.   * @note The prescaler can be changed on the fly as this control register is buffered. The new
  1280.   *       prescaler ratio is taken into account at the next update event.
  1281.   * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
  1282.   * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
  1283.   * @param  TIMx Timer instance
  1284.   * @param  Prescaler between Min_Data=0 and Max_Data=65535
  1285.   * @retval None
  1286.   */
  1287. __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
  1288. {
  1289.   WRITE_REG(TIMx->PSC, Prescaler);
  1290. }
  1291.  
  1292. /**
  1293.   * @brief  Get the prescaler value.
  1294.   * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
  1295.   * @param  TIMx Timer instance
  1296.   * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
  1297.   */
  1298. __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
  1299. {
  1300.   return (uint32_t)(READ_REG(TIMx->PSC));
  1301. }
  1302.  
  1303. /**
  1304.   * @brief  Set the auto-reload value.
  1305.   * @note The counter is blocked while the auto-reload value is null.
  1306.   * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
  1307.   * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
  1308.   * @param  TIMx Timer instance
  1309.   * @param  AutoReload between Min_Data=0 and Max_Data=65535
  1310.   * @retval None
  1311.   */
  1312. __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
  1313. {
  1314.   WRITE_REG(TIMx->ARR, AutoReload);
  1315. }
  1316.  
  1317. /**
  1318.   * @brief  Get the auto-reload value.
  1319.   * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
  1320.   * @param  TIMx Timer instance
  1321.   * @retval Auto-reload value
  1322.   */
  1323. __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
  1324. {
  1325.   return (uint32_t)(READ_REG(TIMx->ARR));
  1326. }
  1327.  
  1328. /**
  1329.   * @brief  Set the repetition counter value.
  1330.   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
  1331.   *       whether or not a timer instance supports a repetition counter.
  1332.   * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
  1333.   * @param  TIMx Timer instance
  1334.   * @param  RepetitionCounter between Min_Data=0 and Max_Data=255
  1335.   * @retval None
  1336.   */
  1337. __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
  1338. {
  1339.   WRITE_REG(TIMx->RCR, RepetitionCounter);
  1340. }
  1341.  
  1342. /**
  1343.   * @brief  Get the repetition counter value.
  1344.   * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
  1345.   *       whether or not a timer instance supports a repetition counter.
  1346.   * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
  1347.   * @param  TIMx Timer instance
  1348.   * @retval Repetition counter value
  1349.   */
  1350. __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
  1351. {
  1352.   return (uint32_t)(READ_REG(TIMx->RCR));
  1353. }
  1354.  
  1355. /**
  1356.   * @}
  1357.   */
  1358.  
  1359. /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
  1360.   * @{
  1361.   */
  1362. /**
  1363.   * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
  1364.   * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
  1365.   *       they are updated only when a commutation event (COM) occurs.
  1366.   * @note Only on channels that have a complementary output.
  1367.   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
  1368.   *       whether or not a timer instance is able to generate a commutation event.
  1369.   * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
  1370.   * @param  TIMx Timer instance
  1371.   * @retval None
  1372.   */
  1373. __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
  1374. {
  1375.   SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
  1376. }
  1377.  
  1378. /**
  1379.   * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
  1380.   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
  1381.   *       whether or not a timer instance is able to generate a commutation event.
  1382.   * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
  1383.   * @param  TIMx Timer instance
  1384.   * @retval None
  1385.   */
  1386. __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
  1387. {
  1388.   CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
  1389. }
  1390.  
  1391. /**
  1392.   * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
  1393.   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
  1394.   *       whether or not a timer instance is able to generate a commutation event.
  1395.   * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
  1396.   * @param  TIMx Timer instance
  1397.   * @param  CCUpdateSource This parameter can be one of the following values:
  1398.   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
  1399.   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
  1400.   * @retval None
  1401.   */
  1402. __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
  1403. {
  1404.   MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
  1405. }
  1406.  
  1407. /**
  1408.   * @brief  Set the trigger of the capture/compare DMA request.
  1409.   * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
  1410.   * @param  TIMx Timer instance
  1411.   * @param  DMAReqTrigger This parameter can be one of the following values:
  1412.   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
  1413.   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
  1414.   * @retval None
  1415.   */
  1416. __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
  1417. {
  1418.   MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
  1419. }
  1420.  
  1421. /**
  1422.   * @brief  Get actual trigger of the capture/compare DMA request.
  1423.   * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
  1424.   * @param  TIMx Timer instance
  1425.   * @retval Returned value can be one of the following values:
  1426.   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
  1427.   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
  1428.   */
  1429. __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
  1430. {
  1431.   return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
  1432. }
  1433.  
  1434. /**
  1435.   * @brief  Set the lock level to freeze the
  1436.   *         configuration of several capture/compare parameters.
  1437.   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  1438.   *       the lock mechanism is supported by a timer instance.
  1439.   * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
  1440.   * @param  TIMx Timer instance
  1441.   * @param  LockLevel This parameter can be one of the following values:
  1442.   *         @arg @ref LL_TIM_LOCKLEVEL_OFF
  1443.   *         @arg @ref LL_TIM_LOCKLEVEL_1
  1444.   *         @arg @ref LL_TIM_LOCKLEVEL_2
  1445.   *         @arg @ref LL_TIM_LOCKLEVEL_3
  1446.   * @retval None
  1447.   */
  1448. __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
  1449. {
  1450.   MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
  1451. }
  1452.  
  1453. /**
  1454.   * @brief  Enable capture/compare channels.
  1455.   * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
  1456.   *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
  1457.   *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
  1458.   *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
  1459.   *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
  1460.   *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
  1461.   *         CCER         CC4E          LL_TIM_CC_EnableChannel
  1462.   * @param  TIMx Timer instance
  1463.   * @param  Channels This parameter can be a combination of the following values:
  1464.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1465.   *         @arg @ref LL_TIM_CHANNEL_CH1N
  1466.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1467.   *         @arg @ref LL_TIM_CHANNEL_CH2N
  1468.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1469.   *         @arg @ref LL_TIM_CHANNEL_CH3N
  1470.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1471.   * @retval None
  1472.   */
  1473. __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
  1474. {
  1475.   SET_BIT(TIMx->CCER, Channels);
  1476. }
  1477.  
  1478. /**
  1479.   * @brief  Disable capture/compare channels.
  1480.   * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
  1481.   *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
  1482.   *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
  1483.   *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
  1484.   *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
  1485.   *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
  1486.   *         CCER         CC4E          LL_TIM_CC_DisableChannel
  1487.   * @param  TIMx Timer instance
  1488.   * @param  Channels This parameter can be a combination of the following values:
  1489.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1490.   *         @arg @ref LL_TIM_CHANNEL_CH1N
  1491.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1492.   *         @arg @ref LL_TIM_CHANNEL_CH2N
  1493.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1494.   *         @arg @ref LL_TIM_CHANNEL_CH3N
  1495.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1496.   * @retval None
  1497.   */
  1498. __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
  1499. {
  1500.   CLEAR_BIT(TIMx->CCER, Channels);
  1501. }
  1502.  
  1503. /**
  1504.   * @brief  Indicate whether channel(s) is(are) enabled.
  1505.   * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
  1506.   *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
  1507.   *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
  1508.   *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
  1509.   *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
  1510.   *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
  1511.   *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel
  1512.   * @param  TIMx Timer instance
  1513.   * @param  Channels This parameter can be a combination of the following values:
  1514.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1515.   *         @arg @ref LL_TIM_CHANNEL_CH1N
  1516.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1517.   *         @arg @ref LL_TIM_CHANNEL_CH2N
  1518.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1519.   *         @arg @ref LL_TIM_CHANNEL_CH3N
  1520.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1521.   * @retval State of bit (1 or 0).
  1522.   */
  1523. __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
  1524. {
  1525.   return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
  1526. }
  1527.  
  1528. /**
  1529.   * @}
  1530.   */
  1531.  
  1532. /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
  1533.   * @{
  1534.   */
  1535. /**
  1536.   * @brief  Configure an output channel.
  1537.   * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
  1538.   *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
  1539.   *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
  1540.   *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
  1541.   *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
  1542.   *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
  1543.   *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
  1544.   *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
  1545.   *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
  1546.   *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
  1547.   *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
  1548.   *         CR2          OIS4          LL_TIM_OC_ConfigOutput
  1549.   * @param  TIMx Timer instance
  1550.   * @param  Channel This parameter can be one of the following values:
  1551.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1552.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1553.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1554.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1555.   * @param  Configuration This parameter must be a combination of all the following values:
  1556.   *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
  1557.   *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
  1558.   * @retval None
  1559.   */
  1560. __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
  1561. {
  1562.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1563.   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  1564.   CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
  1565.   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
  1566.              (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
  1567.   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
  1568.              (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
  1569. }
  1570.  
  1571. /**
  1572.   * @brief  Define the behavior of the output reference signal OCxREF from which
  1573.   *         OCx and OCxN (when relevant) are derived.
  1574.   * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
  1575.   *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
  1576.   *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
  1577.   *         CCMR2        OC4M          LL_TIM_OC_SetMode
  1578.   * @param  TIMx Timer instance
  1579.   * @param  Channel This parameter can be one of the following values:
  1580.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1581.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1582.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1583.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1584.   * @param  Mode This parameter can be one of the following values:
  1585.   *         @arg @ref LL_TIM_OCMODE_FROZEN
  1586.   *         @arg @ref LL_TIM_OCMODE_ACTIVE
  1587.   *         @arg @ref LL_TIM_OCMODE_INACTIVE
  1588.   *         @arg @ref LL_TIM_OCMODE_TOGGLE
  1589.   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
  1590.   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
  1591.   *         @arg @ref LL_TIM_OCMODE_PWM1
  1592.   *         @arg @ref LL_TIM_OCMODE_PWM2
  1593.   * @retval None
  1594.   */
  1595. __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
  1596. {
  1597.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1598.   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  1599.   MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),  Mode << SHIFT_TAB_OCxx[iChannel]);
  1600. }
  1601.  
  1602. /**
  1603.   * @brief  Get the output compare mode of an output channel.
  1604.   * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
  1605.   *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
  1606.   *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
  1607.   *         CCMR2        OC4M          LL_TIM_OC_GetMode
  1608.   * @param  TIMx Timer instance
  1609.   * @param  Channel This parameter can be one of the following values:
  1610.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1611.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1612.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1613.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1614.   * @retval Returned value can be one of the following values:
  1615.   *         @arg @ref LL_TIM_OCMODE_FROZEN
  1616.   *         @arg @ref LL_TIM_OCMODE_ACTIVE
  1617.   *         @arg @ref LL_TIM_OCMODE_INACTIVE
  1618.   *         @arg @ref LL_TIM_OCMODE_TOGGLE
  1619.   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
  1620.   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
  1621.   *         @arg @ref LL_TIM_OCMODE_PWM1
  1622.   *         @arg @ref LL_TIM_OCMODE_PWM2
  1623.   */
  1624. __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
  1625. {
  1626.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1627.   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  1628.   return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
  1629. }
  1630.  
  1631. /**
  1632.   * @brief  Set the polarity of an output channel.
  1633.   * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
  1634.   *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
  1635.   *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
  1636.   *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
  1637.   *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
  1638.   *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
  1639.   *         CCER         CC4P          LL_TIM_OC_SetPolarity
  1640.   * @param  TIMx Timer instance
  1641.   * @param  Channel This parameter can be one of the following values:
  1642.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1643.   *         @arg @ref LL_TIM_CHANNEL_CH1N
  1644.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1645.   *         @arg @ref LL_TIM_CHANNEL_CH2N
  1646.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1647.   *         @arg @ref LL_TIM_CHANNEL_CH3N
  1648.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1649.   * @param  Polarity This parameter can be one of the following values:
  1650.   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
  1651.   *         @arg @ref LL_TIM_OCPOLARITY_LOW
  1652.   * @retval None
  1653.   */
  1654. __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
  1655. {
  1656.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1657.   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
  1658. }
  1659.  
  1660. /**
  1661.   * @brief  Get the polarity of an output channel.
  1662.   * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
  1663.   *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
  1664.   *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
  1665.   *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
  1666.   *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
  1667.   *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
  1668.   *         CCER         CC4P          LL_TIM_OC_GetPolarity
  1669.   * @param  TIMx Timer instance
  1670.   * @param  Channel This parameter can be one of the following values:
  1671.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1672.   *         @arg @ref LL_TIM_CHANNEL_CH1N
  1673.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1674.   *         @arg @ref LL_TIM_CHANNEL_CH2N
  1675.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1676.   *         @arg @ref LL_TIM_CHANNEL_CH3N
  1677.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1678.   * @retval Returned value can be one of the following values:
  1679.   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
  1680.   *         @arg @ref LL_TIM_OCPOLARITY_LOW
  1681.   */
  1682. __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
  1683. {
  1684.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1685.   return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
  1686. }
  1687.  
  1688. /**
  1689.   * @brief  Set the IDLE state of an output channel
  1690.   * @note This function is significant only for the timer instances
  1691.   *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
  1692.   *       can be used to check whether or not a timer instance provides
  1693.   *       a break input.
  1694.   * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
  1695.   *         CR2         OIS1N         LL_TIM_OC_SetIdleState\n
  1696.   *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
  1697.   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
  1698.   *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
  1699.   *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
  1700.   *         CR2         OIS4          LL_TIM_OC_SetIdleState
  1701.   * @param  TIMx Timer instance
  1702.   * @param  Channel This parameter can be one of the following values:
  1703.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1704.   *         @arg @ref LL_TIM_CHANNEL_CH1N
  1705.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1706.   *         @arg @ref LL_TIM_CHANNEL_CH2N
  1707.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1708.   *         @arg @ref LL_TIM_CHANNEL_CH3N
  1709.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1710.   * @param  IdleState This parameter can be one of the following values:
  1711.   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
  1712.   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
  1713.   * @retval None
  1714.   */
  1715. __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
  1716. {
  1717.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1718.   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
  1719. }
  1720.  
  1721. /**
  1722.   * @brief  Get the IDLE state of an output channel
  1723.   * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
  1724.   *         CR2         OIS1N         LL_TIM_OC_GetIdleState\n
  1725.   *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
  1726.   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
  1727.   *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
  1728.   *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
  1729.   *         CR2         OIS4          LL_TIM_OC_GetIdleState
  1730.   * @param  TIMx Timer instance
  1731.   * @param  Channel This parameter can be one of the following values:
  1732.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1733.   *         @arg @ref LL_TIM_CHANNEL_CH1N
  1734.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1735.   *         @arg @ref LL_TIM_CHANNEL_CH2N
  1736.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1737.   *         @arg @ref LL_TIM_CHANNEL_CH3N
  1738.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1739.   * @retval Returned value can be one of the following values:
  1740.   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
  1741.   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
  1742.   */
  1743. __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
  1744. {
  1745.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1746.   return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
  1747. }
  1748.  
  1749. /**
  1750.   * @brief  Enable fast mode for the output channel.
  1751.   * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
  1752.   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
  1753.   *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
  1754.   *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
  1755.   *         CCMR2        OC4FE          LL_TIM_OC_EnableFast
  1756.   * @param  TIMx Timer instance
  1757.   * @param  Channel This parameter can be one of the following values:
  1758.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1759.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1760.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1761.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1762.   * @retval None
  1763.   */
  1764. __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
  1765. {
  1766.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1767.   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  1768.   SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
  1769.  
  1770. }
  1771.  
  1772. /**
  1773.   * @brief  Disable fast mode for the output channel.
  1774.   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
  1775.   *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
  1776.   *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
  1777.   *         CCMR2        OC4FE          LL_TIM_OC_DisableFast
  1778.   * @param  TIMx Timer instance
  1779.   * @param  Channel This parameter can be one of the following values:
  1780.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1781.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1782.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1783.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1784.   * @retval None
  1785.   */
  1786. __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
  1787. {
  1788.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1789.   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  1790.   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
  1791.  
  1792. }
  1793.  
  1794. /**
  1795.   * @brief  Indicates whether fast mode is enabled for the output channel.
  1796.   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
  1797.   *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
  1798.   *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
  1799.   *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
  1800.   * @param  TIMx Timer instance
  1801.   * @param  Channel This parameter can be one of the following values:
  1802.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1803.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1804.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1805.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1806.   * @retval State of bit (1 or 0).
  1807.   */
  1808. __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
  1809. {
  1810.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1811.   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  1812.   register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
  1813.   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
  1814. }
  1815.  
  1816. /**
  1817.   * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
  1818.   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
  1819.   *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
  1820.   *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
  1821.   *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload
  1822.   * @param  TIMx Timer instance
  1823.   * @param  Channel This parameter can be one of the following values:
  1824.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1825.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1826.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1827.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1828.   * @retval None
  1829.   */
  1830. __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
  1831. {
  1832.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1833.   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  1834.   SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
  1835. }
  1836.  
  1837. /**
  1838.   * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
  1839.   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
  1840.   *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
  1841.   *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
  1842.   *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload
  1843.   * @param  TIMx Timer instance
  1844.   * @param  Channel This parameter can be one of the following values:
  1845.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1846.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1847.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1848.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1849.   * @retval None
  1850.   */
  1851. __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
  1852. {
  1853.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1854.   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  1855.   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
  1856. }
  1857.  
  1858. /**
  1859.   * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
  1860.   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
  1861.   *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
  1862.   *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
  1863.   *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
  1864.   * @param  TIMx Timer instance
  1865.   * @param  Channel This parameter can be one of the following values:
  1866.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1867.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1868.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1869.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1870.   * @retval State of bit (1 or 0).
  1871.   */
  1872. __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
  1873. {
  1874.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1875.   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  1876.   register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
  1877.   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
  1878. }
  1879.  
  1880. /**
  1881.   * @brief  Enable clearing the output channel on an external event.
  1882.   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
  1883.   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
  1884.   *       or not a timer instance can clear the OCxREF signal on an external event.
  1885.   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
  1886.   *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
  1887.   *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
  1888.   *         CCMR2        OC4CE          LL_TIM_OC_EnableClear
  1889.   * @param  TIMx Timer instance
  1890.   * @param  Channel This parameter can be one of the following values:
  1891.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1892.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1893.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1894.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1895.   * @retval None
  1896.   */
  1897. __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
  1898. {
  1899.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1900.   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  1901.   SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
  1902. }
  1903.  
  1904. /**
  1905.   * @brief  Disable clearing the output channel on an external event.
  1906.   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
  1907.   *       or not a timer instance can clear the OCxREF signal on an external event.
  1908.   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
  1909.   *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
  1910.   *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
  1911.   *         CCMR2        OC4CE          LL_TIM_OC_DisableClear
  1912.   * @param  TIMx Timer instance
  1913.   * @param  Channel This parameter can be one of the following values:
  1914.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1915.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1916.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1917.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1918.   * @retval None
  1919.   */
  1920. __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
  1921. {
  1922.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1923.   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  1924.   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
  1925. }
  1926.  
  1927. /**
  1928.   * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
  1929.   * @note This function enables clearing the output channel on an external event.
  1930.   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
  1931.   * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
  1932.   *       or not a timer instance can clear the OCxREF signal on an external event.
  1933.   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
  1934.   *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
  1935.   *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
  1936.   *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
  1937.   * @param  TIMx Timer instance
  1938.   * @param  Channel This parameter can be one of the following values:
  1939.   *         @arg @ref LL_TIM_CHANNEL_CH1
  1940.   *         @arg @ref LL_TIM_CHANNEL_CH2
  1941.   *         @arg @ref LL_TIM_CHANNEL_CH3
  1942.   *         @arg @ref LL_TIM_CHANNEL_CH4
  1943.   * @retval State of bit (1 or 0).
  1944.   */
  1945. __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
  1946. {
  1947.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  1948.   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  1949.   register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
  1950.   return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
  1951. }
  1952.  
  1953. /**
  1954.   * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
  1955.   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  1956.   *       dead-time insertion feature is supported by a timer instance.
  1957.   * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
  1958.   * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
  1959.   * @param  TIMx Timer instance
  1960.   * @param  DeadTime between Min_Data=0 and Max_Data=255
  1961.   * @retval None
  1962.   */
  1963. __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
  1964. {
  1965.   MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
  1966. }
  1967.  
  1968. /**
  1969.   * @brief  Set compare value for output channel 1 (TIMx_CCR1).
  1970.   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
  1971.   *       output channel 1 is supported by a timer instance.
  1972.   * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
  1973.   * @param  TIMx Timer instance
  1974.   * @param  CompareValue between Min_Data=0 and Max_Data=65535
  1975.   * @retval None
  1976.   */
  1977. __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
  1978. {
  1979.   WRITE_REG(TIMx->CCR1, CompareValue);
  1980. }
  1981.  
  1982. /**
  1983.   * @brief  Set compare value for output channel 2 (TIMx_CCR2).
  1984.   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
  1985.   *       output channel 2 is supported by a timer instance.
  1986.   * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
  1987.   * @param  TIMx Timer instance
  1988.   * @param  CompareValue between Min_Data=0 and Max_Data=65535
  1989.   * @retval None
  1990.   */
  1991. __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
  1992. {
  1993.   WRITE_REG(TIMx->CCR2, CompareValue);
  1994. }
  1995.  
  1996. /**
  1997.   * @brief  Set compare value for output channel 3 (TIMx_CCR3).
  1998.   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
  1999.   *       output channel is supported by a timer instance.
  2000.   * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
  2001.   * @param  TIMx Timer instance
  2002.   * @param  CompareValue between Min_Data=0 and Max_Data=65535
  2003.   * @retval None
  2004.   */
  2005. __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
  2006. {
  2007.   WRITE_REG(TIMx->CCR3, CompareValue);
  2008. }
  2009.  
  2010. /**
  2011.   * @brief  Set compare value for output channel 4 (TIMx_CCR4).
  2012.   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
  2013.   *       output channel 4 is supported by a timer instance.
  2014.   * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
  2015.   * @param  TIMx Timer instance
  2016.   * @param  CompareValue between Min_Data=0 and Max_Data=65535
  2017.   * @retval None
  2018.   */
  2019. __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
  2020. {
  2021.   WRITE_REG(TIMx->CCR4, CompareValue);
  2022. }
  2023.  
  2024. /**
  2025.   * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
  2026.   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
  2027.   *       output channel 1 is supported by a timer instance.
  2028.   * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
  2029.   * @param  TIMx Timer instance
  2030.   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
  2031.   */
  2032. __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
  2033. {
  2034.   return (uint32_t)(READ_REG(TIMx->CCR1));
  2035. }
  2036.  
  2037. /**
  2038.   * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
  2039.   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
  2040.   *       output channel 2 is supported by a timer instance.
  2041.   * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
  2042.   * @param  TIMx Timer instance
  2043.   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
  2044.   */
  2045. __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
  2046. {
  2047.   return (uint32_t)(READ_REG(TIMx->CCR2));
  2048. }
  2049.  
  2050. /**
  2051.   * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
  2052.   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
  2053.   *       output channel 3 is supported by a timer instance.
  2054.   * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
  2055.   * @param  TIMx Timer instance
  2056.   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
  2057.   */
  2058. __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
  2059. {
  2060.   return (uint32_t)(READ_REG(TIMx->CCR3));
  2061. }
  2062.  
  2063. /**
  2064.   * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
  2065.   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
  2066.   *       output channel 4 is supported by a timer instance.
  2067.   * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
  2068.   * @param  TIMx Timer instance
  2069.   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
  2070.   */
  2071. __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
  2072. {
  2073.   return (uint32_t)(READ_REG(TIMx->CCR4));
  2074. }
  2075.  
  2076. /**
  2077.   * @}
  2078.   */
  2079.  
  2080. /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
  2081.   * @{
  2082.   */
  2083. /**
  2084.   * @brief  Configure input channel.
  2085.   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
  2086.   *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
  2087.   *         CCMR1        IC1F          LL_TIM_IC_Config\n
  2088.   *         CCMR1        CC2S          LL_TIM_IC_Config\n
  2089.   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
  2090.   *         CCMR1        IC2F          LL_TIM_IC_Config\n
  2091.   *         CCMR2        CC3S          LL_TIM_IC_Config\n
  2092.   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
  2093.   *         CCMR2        IC3F          LL_TIM_IC_Config\n
  2094.   *         CCMR2        CC4S          LL_TIM_IC_Config\n
  2095.   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
  2096.   *         CCMR2        IC4F          LL_TIM_IC_Config\n
  2097.   *         CCER         CC1P          LL_TIM_IC_Config\n
  2098.   *         CCER         CC1NP         LL_TIM_IC_Config\n
  2099.   *         CCER         CC2P          LL_TIM_IC_Config\n
  2100.   *         CCER         CC2NP         LL_TIM_IC_Config\n
  2101.   *         CCER         CC3P          LL_TIM_IC_Config\n
  2102.   *         CCER         CC3NP         LL_TIM_IC_Config\n
  2103.   *         CCER         CC4P          LL_TIM_IC_Config\n
  2104.   * @param  TIMx Timer instance
  2105.   * @param  Channel This parameter can be one of the following values:
  2106.   *         @arg @ref LL_TIM_CHANNEL_CH1
  2107.   *         @arg @ref LL_TIM_CHANNEL_CH2
  2108.   *         @arg @ref LL_TIM_CHANNEL_CH3
  2109.   *         @arg @ref LL_TIM_CHANNEL_CH4
  2110.   * @param  Configuration This parameter must be a combination of all the following values:
  2111.   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
  2112.   *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
  2113.   *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
  2114.   *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING
  2115.   * @retval None
  2116.   */
  2117. __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
  2118. {
  2119.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  2120.   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  2121.   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
  2122.              ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))  << SHIFT_TAB_ICxx[iChannel]);
  2123.   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
  2124.              (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
  2125. }
  2126.  
  2127. /**
  2128.   * @brief  Set the active input.
  2129.   * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
  2130.   *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
  2131.   *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
  2132.   *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
  2133.   * @param  TIMx Timer instance
  2134.   * @param  Channel This parameter can be one of the following values:
  2135.   *         @arg @ref LL_TIM_CHANNEL_CH1
  2136.   *         @arg @ref LL_TIM_CHANNEL_CH2
  2137.   *         @arg @ref LL_TIM_CHANNEL_CH3
  2138.   *         @arg @ref LL_TIM_CHANNEL_CH4
  2139.   * @param  ICActiveInput This parameter can be one of the following values:
  2140.   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
  2141.   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
  2142.   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
  2143.   * @retval None
  2144.   */
  2145. __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
  2146. {
  2147.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  2148.   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  2149.   MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
  2150. }
  2151.  
  2152. /**
  2153.   * @brief  Get the current active input.
  2154.   * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
  2155.   *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
  2156.   *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
  2157.   *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
  2158.   * @param  TIMx Timer instance
  2159.   * @param  Channel This parameter can be one of the following values:
  2160.   *         @arg @ref LL_TIM_CHANNEL_CH1
  2161.   *         @arg @ref LL_TIM_CHANNEL_CH2
  2162.   *         @arg @ref LL_TIM_CHANNEL_CH3
  2163.   *         @arg @ref LL_TIM_CHANNEL_CH4
  2164.   * @retval Returned value can be one of the following values:
  2165.   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
  2166.   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
  2167.   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
  2168.   */
  2169. __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
  2170. {
  2171.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  2172.   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  2173.   return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
  2174. }
  2175.  
  2176. /**
  2177.   * @brief  Set the prescaler of input channel.
  2178.   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
  2179.   *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
  2180.   *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
  2181.   *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
  2182.   * @param  TIMx Timer instance
  2183.   * @param  Channel This parameter can be one of the following values:
  2184.   *         @arg @ref LL_TIM_CHANNEL_CH1
  2185.   *         @arg @ref LL_TIM_CHANNEL_CH2
  2186.   *         @arg @ref LL_TIM_CHANNEL_CH3
  2187.   *         @arg @ref LL_TIM_CHANNEL_CH4
  2188.   * @param  ICPrescaler This parameter can be one of the following values:
  2189.   *         @arg @ref LL_TIM_ICPSC_DIV1
  2190.   *         @arg @ref LL_TIM_ICPSC_DIV2
  2191.   *         @arg @ref LL_TIM_ICPSC_DIV4
  2192.   *         @arg @ref LL_TIM_ICPSC_DIV8
  2193.   * @retval None
  2194.   */
  2195. __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
  2196. {
  2197.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  2198.   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  2199.   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
  2200. }
  2201.  
  2202. /**
  2203.   * @brief  Get the current prescaler value acting on an  input channel.
  2204.   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
  2205.   *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
  2206.   *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
  2207.   *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
  2208.   * @param  TIMx Timer instance
  2209.   * @param  Channel This parameter can be one of the following values:
  2210.   *         @arg @ref LL_TIM_CHANNEL_CH1
  2211.   *         @arg @ref LL_TIM_CHANNEL_CH2
  2212.   *         @arg @ref LL_TIM_CHANNEL_CH3
  2213.   *         @arg @ref LL_TIM_CHANNEL_CH4
  2214.   * @retval Returned value can be one of the following values:
  2215.   *         @arg @ref LL_TIM_ICPSC_DIV1
  2216.   *         @arg @ref LL_TIM_ICPSC_DIV2
  2217.   *         @arg @ref LL_TIM_ICPSC_DIV4
  2218.   *         @arg @ref LL_TIM_ICPSC_DIV8
  2219.   */
  2220. __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
  2221. {
  2222.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  2223.   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  2224.   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
  2225. }
  2226.  
  2227. /**
  2228.   * @brief  Set the input filter duration.
  2229.   * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
  2230.   *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
  2231.   *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
  2232.   *         CCMR2        IC4F          LL_TIM_IC_SetFilter
  2233.   * @param  TIMx Timer instance
  2234.   * @param  Channel This parameter can be one of the following values:
  2235.   *         @arg @ref LL_TIM_CHANNEL_CH1
  2236.   *         @arg @ref LL_TIM_CHANNEL_CH2
  2237.   *         @arg @ref LL_TIM_CHANNEL_CH3
  2238.   *         @arg @ref LL_TIM_CHANNEL_CH4
  2239.   * @param  ICFilter This parameter can be one of the following values:
  2240.   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
  2241.   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
  2242.   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
  2243.   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
  2244.   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
  2245.   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
  2246.   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
  2247.   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
  2248.   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
  2249.   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
  2250.   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
  2251.   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
  2252.   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
  2253.   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
  2254.   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
  2255.   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
  2256.   * @retval None
  2257.   */
  2258. __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
  2259. {
  2260.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  2261.   register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  2262.   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
  2263. }
  2264.  
  2265. /**
  2266.   * @brief  Get the input filter duration.
  2267.   * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
  2268.   *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
  2269.   *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
  2270.   *         CCMR2        IC4F          LL_TIM_IC_GetFilter
  2271.   * @param  TIMx Timer instance
  2272.   * @param  Channel This parameter can be one of the following values:
  2273.   *         @arg @ref LL_TIM_CHANNEL_CH1
  2274.   *         @arg @ref LL_TIM_CHANNEL_CH2
  2275.   *         @arg @ref LL_TIM_CHANNEL_CH3
  2276.   *         @arg @ref LL_TIM_CHANNEL_CH4
  2277.   * @retval Returned value can be one of the following values:
  2278.   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
  2279.   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
  2280.   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
  2281.   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
  2282.   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
  2283.   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
  2284.   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
  2285.   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
  2286.   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
  2287.   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
  2288.   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
  2289.   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
  2290.   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
  2291.   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
  2292.   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
  2293.   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
  2294.   */
  2295. __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
  2296. {
  2297.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  2298.   register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  2299.   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
  2300. }
  2301.  
  2302. /**
  2303.   * @brief  Set the input channel polarity.
  2304.   * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
  2305.   *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
  2306.   *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
  2307.   *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
  2308.   *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
  2309.   *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
  2310.   *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
  2311.   * @param  TIMx Timer instance
  2312.   * @param  Channel This parameter can be one of the following values:
  2313.   *         @arg @ref LL_TIM_CHANNEL_CH1
  2314.   *         @arg @ref LL_TIM_CHANNEL_CH2
  2315.   *         @arg @ref LL_TIM_CHANNEL_CH3
  2316.   *         @arg @ref LL_TIM_CHANNEL_CH4
  2317.   * @param  ICPolarity This parameter can be one of the following values:
  2318.   *         @arg @ref LL_TIM_IC_POLARITY_RISING
  2319.   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
  2320.   * @retval None
  2321.   */
  2322. __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
  2323. {
  2324.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  2325.   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
  2326.              ICPolarity << SHIFT_TAB_CCxP[iChannel]);
  2327. }
  2328.  
  2329. /**
  2330.   * @brief  Get the current input channel polarity.
  2331.   * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
  2332.   *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
  2333.   *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
  2334.   *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
  2335.   *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
  2336.   *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
  2337.   *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
  2338.   * @param  TIMx Timer instance
  2339.   * @param  Channel This parameter can be one of the following values:
  2340.   *         @arg @ref LL_TIM_CHANNEL_CH1
  2341.   *         @arg @ref LL_TIM_CHANNEL_CH2
  2342.   *         @arg @ref LL_TIM_CHANNEL_CH3
  2343.   *         @arg @ref LL_TIM_CHANNEL_CH4
  2344.   * @retval Returned value can be one of the following values:
  2345.   *         @arg @ref LL_TIM_IC_POLARITY_RISING
  2346.   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
  2347.   */
  2348. __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
  2349. {
  2350.   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
  2351.   return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
  2352.           SHIFT_TAB_CCxP[iChannel]);
  2353. }
  2354.  
  2355. /**
  2356.   * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
  2357.   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
  2358.   *       a timer instance provides an XOR input.
  2359.   * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
  2360.   * @param  TIMx Timer instance
  2361.   * @retval None
  2362.   */
  2363. __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
  2364. {
  2365.   SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
  2366. }
  2367.  
  2368. /**
  2369.   * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
  2370.   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
  2371.   *       a timer instance provides an XOR input.
  2372.   * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
  2373.   * @param  TIMx Timer instance
  2374.   * @retval None
  2375.   */
  2376. __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
  2377. {
  2378.   CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
  2379. }
  2380.  
  2381. /**
  2382.   * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
  2383.   * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
  2384.   * a timer instance provides an XOR input.
  2385.   * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
  2386.   * @param  TIMx Timer instance
  2387.   * @retval State of bit (1 or 0).
  2388.   */
  2389. __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
  2390. {
  2391.   return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
  2392. }
  2393.  
  2394. /**
  2395.   * @brief  Get captured value for input channel 1.
  2396.   * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
  2397.   *       input channel 1 is supported by a timer instance.
  2398.   * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
  2399.   * @param  TIMx Timer instance
  2400.   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
  2401.   */
  2402. __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
  2403. {
  2404.   return (uint32_t)(READ_REG(TIMx->CCR1));
  2405. }
  2406.  
  2407. /**
  2408.   * @brief  Get captured value for input channel 2.
  2409.   * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
  2410.   *       input channel 2 is supported by a timer instance.
  2411.   * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
  2412.   * @param  TIMx Timer instance
  2413.   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
  2414.   */
  2415. __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
  2416. {
  2417.   return (uint32_t)(READ_REG(TIMx->CCR2));
  2418. }
  2419.  
  2420. /**
  2421.   * @brief  Get captured value for input channel 3.
  2422.   * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
  2423.   *       input channel 3 is supported by a timer instance.
  2424.   * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
  2425.   * @param  TIMx Timer instance
  2426.   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
  2427.   */
  2428. __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
  2429. {
  2430.   return (uint32_t)(READ_REG(TIMx->CCR3));
  2431. }
  2432.  
  2433. /**
  2434.   * @brief  Get captured value for input channel 4.
  2435.   * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
  2436.   *       input channel 4 is supported by a timer instance.
  2437.   * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
  2438.   * @param  TIMx Timer instance
  2439.   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
  2440.   */
  2441. __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
  2442. {
  2443.   return (uint32_t)(READ_REG(TIMx->CCR4));
  2444. }
  2445.  
  2446. /**
  2447.   * @}
  2448.   */
  2449.  
  2450. /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
  2451.   * @{
  2452.   */
  2453. /**
  2454.   * @brief  Enable external clock mode 2.
  2455.   * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
  2456.   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
  2457.   *       whether or not a timer instance supports external clock mode2.
  2458.   * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
  2459.   * @param  TIMx Timer instance
  2460.   * @retval None
  2461.   */
  2462. __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
  2463. {
  2464.   SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
  2465. }
  2466.  
  2467. /**
  2468.   * @brief  Disable external clock mode 2.
  2469.   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
  2470.   *       whether or not a timer instance supports external clock mode2.
  2471.   * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
  2472.   * @param  TIMx Timer instance
  2473.   * @retval None
  2474.   */
  2475. __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
  2476. {
  2477.   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
  2478. }
  2479.  
  2480. /**
  2481.   * @brief  Indicate whether external clock mode 2 is enabled.
  2482.   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
  2483.   *       whether or not a timer instance supports external clock mode2.
  2484.   * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
  2485.   * @param  TIMx Timer instance
  2486.   * @retval State of bit (1 or 0).
  2487.   */
  2488. __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
  2489. {
  2490.   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
  2491. }
  2492.  
  2493. /**
  2494.   * @brief  Set the clock source of the counter clock.
  2495.   * @note when selected clock source is external clock mode 1, the timer input
  2496.   *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
  2497.   *       function. This timer input must be configured by calling
  2498.   *       the @ref LL_TIM_IC_Config() function.
  2499.   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
  2500.   *       whether or not a timer instance supports external clock mode1.
  2501.   * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
  2502.   *       whether or not a timer instance supports external clock mode2.
  2503.   * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
  2504.   *         SMCR         ECE           LL_TIM_SetClockSource
  2505.   * @param  TIMx Timer instance
  2506.   * @param  ClockSource This parameter can be one of the following values:
  2507.   *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
  2508.   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
  2509.   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
  2510.   * @retval None
  2511.   */
  2512. __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
  2513. {
  2514.   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
  2515. }
  2516.  
  2517. /**
  2518.   * @brief  Set the encoder interface mode.
  2519.   * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
  2520.   *       whether or not a timer instance supports the encoder mode.
  2521.   * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
  2522.   * @param  TIMx Timer instance
  2523.   * @param  EncoderMode This parameter can be one of the following values:
  2524.   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
  2525.   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
  2526.   *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
  2527.   * @retval None
  2528.   */
  2529. __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
  2530. {
  2531.   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
  2532. }
  2533.  
  2534. /**
  2535.   * @}
  2536.   */
  2537.  
  2538. /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
  2539.   * @{
  2540.   */
  2541. /**
  2542.   * @brief  Set the trigger output (TRGO) used for timer synchronization .
  2543.   * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
  2544.   *       whether or not a timer instance can operate as a master timer.
  2545.   * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
  2546.   * @param  TIMx Timer instance
  2547.   * @param  TimerSynchronization This parameter can be one of the following values:
  2548.   *         @arg @ref LL_TIM_TRGO_RESET
  2549.   *         @arg @ref LL_TIM_TRGO_ENABLE
  2550.   *         @arg @ref LL_TIM_TRGO_UPDATE
  2551.   *         @arg @ref LL_TIM_TRGO_CC1IF
  2552.   *         @arg @ref LL_TIM_TRGO_OC1REF
  2553.   *         @arg @ref LL_TIM_TRGO_OC2REF
  2554.   *         @arg @ref LL_TIM_TRGO_OC3REF
  2555.   *         @arg @ref LL_TIM_TRGO_OC4REF
  2556.   * @retval None
  2557.   */
  2558. __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
  2559. {
  2560.   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
  2561. }
  2562.  
  2563. /**
  2564.   * @brief  Set the synchronization mode of a slave timer.
  2565.   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
  2566.   *       a timer instance can operate as a slave timer.
  2567.   * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
  2568.   * @param  TIMx Timer instance
  2569.   * @param  SlaveMode This parameter can be one of the following values:
  2570.   *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
  2571.   *         @arg @ref LL_TIM_SLAVEMODE_RESET
  2572.   *         @arg @ref LL_TIM_SLAVEMODE_GATED
  2573.   *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
  2574.   * @retval None
  2575.   */
  2576. __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
  2577. {
  2578.   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
  2579. }
  2580.  
  2581. /**
  2582.   * @brief  Set the selects the trigger input to be used to synchronize the counter.
  2583.   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
  2584.   *       a timer instance can operate as a slave timer.
  2585.   * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
  2586.   * @param  TIMx Timer instance
  2587.   * @param  TriggerInput This parameter can be one of the following values:
  2588.   *         @arg @ref LL_TIM_TS_ITR0
  2589.   *         @arg @ref LL_TIM_TS_ITR1
  2590.   *         @arg @ref LL_TIM_TS_ITR2
  2591.   *         @arg @ref LL_TIM_TS_ITR3
  2592.   *         @arg @ref LL_TIM_TS_TI1F_ED
  2593.   *         @arg @ref LL_TIM_TS_TI1FP1
  2594.   *         @arg @ref LL_TIM_TS_TI2FP2
  2595.   *         @arg @ref LL_TIM_TS_ETRF
  2596.   * @retval None
  2597.   */
  2598. __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
  2599. {
  2600.   MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
  2601. }
  2602.  
  2603. /**
  2604.   * @brief  Enable the Master/Slave mode.
  2605.   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
  2606.   *       a timer instance can operate as a slave timer.
  2607.   * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
  2608.   * @param  TIMx Timer instance
  2609.   * @retval None
  2610.   */
  2611. __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
  2612. {
  2613.   SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
  2614. }
  2615.  
  2616. /**
  2617.   * @brief  Disable the Master/Slave mode.
  2618.   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
  2619.   *       a timer instance can operate as a slave timer.
  2620.   * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
  2621.   * @param  TIMx Timer instance
  2622.   * @retval None
  2623.   */
  2624. __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
  2625. {
  2626.   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
  2627. }
  2628.  
  2629. /**
  2630.   * @brief Indicates whether the Master/Slave mode is enabled.
  2631.   * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
  2632.   * a timer instance can operate as a slave timer.
  2633.   * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
  2634.   * @param  TIMx Timer instance
  2635.   * @retval State of bit (1 or 0).
  2636.   */
  2637. __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
  2638. {
  2639.   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
  2640. }
  2641.  
  2642. /**
  2643.   * @brief  Configure the external trigger (ETR) input.
  2644.   * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
  2645.   *       a timer instance provides an external trigger input.
  2646.   * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
  2647.   *         SMCR         ETPS          LL_TIM_ConfigETR\n
  2648.   *         SMCR         ETF           LL_TIM_ConfigETR
  2649.   * @param  TIMx Timer instance
  2650.   * @param  ETRPolarity This parameter can be one of the following values:
  2651.   *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
  2652.   *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
  2653.   * @param  ETRPrescaler This parameter can be one of the following values:
  2654.   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
  2655.   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
  2656.   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
  2657.   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
  2658.   * @param  ETRFilter This parameter can be one of the following values:
  2659.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
  2660.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
  2661.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
  2662.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
  2663.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
  2664.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
  2665.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
  2666.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
  2667.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
  2668.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
  2669.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
  2670.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
  2671.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
  2672.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
  2673.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
  2674.   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
  2675.   * @retval None
  2676.   */
  2677. __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
  2678.                                       uint32_t ETRFilter)
  2679. {
  2680.   MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
  2681. }
  2682.  
  2683. /**
  2684.   * @}
  2685.   */
  2686.  
  2687. /** @defgroup TIM_LL_EF_Break_Function Break function configuration
  2688.   * @{
  2689.   */
  2690. /**
  2691.   * @brief  Enable the break function.
  2692.   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  2693.   *       a timer instance provides a break input.
  2694.   * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
  2695.   * @param  TIMx Timer instance
  2696.   * @retval None
  2697.   */
  2698. __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
  2699. {
  2700.   __IO uint32_t tmpreg;
  2701.   SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
  2702.   /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
  2703.   tmpreg = READ_REG(TIMx->BDTR);
  2704.   (void)(tmpreg);
  2705. }
  2706.  
  2707. /**
  2708.   * @brief  Disable the break function.
  2709.   * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
  2710.   * @param  TIMx Timer instance
  2711.   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  2712.   *       a timer instance provides a break input.
  2713.   * @retval None
  2714.   */
  2715. __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
  2716. {
  2717.   __IO uint32_t tmpreg;
  2718.   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
  2719.   /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
  2720.   tmpreg = READ_REG(TIMx->BDTR);
  2721.   (void)(tmpreg);
  2722. }
  2723.  
  2724. /**
  2725.   * @brief  Configure the break input.
  2726.   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  2727.   *       a timer instance provides a break input.
  2728.   * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK
  2729.   * @param  TIMx Timer instance
  2730.   * @param  BreakPolarity This parameter can be one of the following values:
  2731.   *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
  2732.   *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
  2733.   * @retval None
  2734.   */
  2735. __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
  2736. {
  2737.   __IO uint32_t tmpreg;
  2738.   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
  2739.   /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
  2740.   tmpreg = READ_REG(TIMx->BDTR);
  2741.   (void)(tmpreg);
  2742. }
  2743.  
  2744. /**
  2745.   * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
  2746.   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  2747.   *       a timer instance provides a break input.
  2748.   * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
  2749.   *         BDTR         OSSR          LL_TIM_SetOffStates
  2750.   * @param  TIMx Timer instance
  2751.   * @param  OffStateIdle This parameter can be one of the following values:
  2752.   *         @arg @ref LL_TIM_OSSI_DISABLE
  2753.   *         @arg @ref LL_TIM_OSSI_ENABLE
  2754.   * @param  OffStateRun This parameter can be one of the following values:
  2755.   *         @arg @ref LL_TIM_OSSR_DISABLE
  2756.   *         @arg @ref LL_TIM_OSSR_ENABLE
  2757.   * @retval None
  2758.   */
  2759. __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
  2760. {
  2761.   MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
  2762. }
  2763.  
  2764. /**
  2765.   * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
  2766.   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  2767.   *       a timer instance provides a break input.
  2768.   * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
  2769.   * @param  TIMx Timer instance
  2770.   * @retval None
  2771.   */
  2772. __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
  2773. {
  2774.   SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
  2775. }
  2776.  
  2777. /**
  2778.   * @brief  Disable automatic output (MOE can be set only by software).
  2779.   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  2780.   *       a timer instance provides a break input.
  2781.   * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
  2782.   * @param  TIMx Timer instance
  2783.   * @retval None
  2784.   */
  2785. __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
  2786. {
  2787.   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
  2788. }
  2789.  
  2790. /**
  2791.   * @brief  Indicate whether automatic output is enabled.
  2792.   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  2793.   *       a timer instance provides a break input.
  2794.   * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
  2795.   * @param  TIMx Timer instance
  2796.   * @retval State of bit (1 or 0).
  2797.   */
  2798. __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
  2799. {
  2800.   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
  2801. }
  2802.  
  2803. /**
  2804.   * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
  2805.   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
  2806.   *       software and is reset in case of break or break2 event
  2807.   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  2808.   *       a timer instance provides a break input.
  2809.   * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
  2810.   * @param  TIMx Timer instance
  2811.   * @retval None
  2812.   */
  2813. __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
  2814. {
  2815.   SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
  2816. }
  2817.  
  2818. /**
  2819.   * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
  2820.   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
  2821.   *       software and is reset in case of break or break2 event.
  2822.   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  2823.   *       a timer instance provides a break input.
  2824.   * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
  2825.   * @param  TIMx Timer instance
  2826.   * @retval None
  2827.   */
  2828. __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
  2829. {
  2830.   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
  2831. }
  2832.  
  2833. /**
  2834.   * @brief  Indicates whether outputs are enabled.
  2835.   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  2836.   *       a timer instance provides a break input.
  2837.   * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
  2838.   * @param  TIMx Timer instance
  2839.   * @retval State of bit (1 or 0).
  2840.   */
  2841. __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
  2842. {
  2843.   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
  2844. }
  2845.  
  2846. /**
  2847.   * @}
  2848.   */
  2849.  
  2850. /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
  2851.   * @{
  2852.   */
  2853. /**
  2854.   * @brief  Configures the timer DMA burst feature.
  2855.   * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
  2856.   *       not a timer instance supports the DMA burst mode.
  2857.   * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
  2858.   *         DCR          DBA           LL_TIM_ConfigDMABurst
  2859.   * @param  TIMx Timer instance
  2860.   * @param  DMABurstBaseAddress This parameter can be one of the following values:
  2861.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
  2862.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
  2863.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
  2864.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
  2865.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
  2866.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
  2867.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
  2868.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
  2869.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
  2870.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
  2871.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
  2872.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
  2873.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
  2874.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
  2875.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
  2876.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
  2877.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
  2878.   *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
  2879.   * @param  DMABurstLength This parameter can be one of the following values:
  2880.   *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
  2881.   *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
  2882.   *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
  2883.   *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
  2884.   *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
  2885.   *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
  2886.   *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
  2887.   *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
  2888.   *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
  2889.   *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
  2890.   *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
  2891.   *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
  2892.   *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
  2893.   *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
  2894.   *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
  2895.   *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
  2896.   *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
  2897.   *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
  2898.   * @retval None
  2899.   */
  2900. __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
  2901. {
  2902.   MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
  2903. }
  2904.  
  2905. /**
  2906.   * @}
  2907.   */
  2908.  
  2909.  
  2910. /**
  2911.   * @}
  2912.   */
  2913.  
  2914. /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
  2915.   * @{
  2916.   */
  2917. /**
  2918.   * @brief  Clear the update interrupt flag (UIF).
  2919.   * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
  2920.   * @param  TIMx Timer instance
  2921.   * @retval None
  2922.   */
  2923. __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
  2924. {
  2925.   WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
  2926. }
  2927.  
  2928. /**
  2929.   * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
  2930.   * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
  2931.   * @param  TIMx Timer instance
  2932.   * @retval State of bit (1 or 0).
  2933.   */
  2934. __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
  2935. {
  2936.   return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
  2937. }
  2938.  
  2939. /**
  2940.   * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
  2941.   * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
  2942.   * @param  TIMx Timer instance
  2943.   * @retval None
  2944.   */
  2945. __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
  2946. {
  2947.   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
  2948. }
  2949.  
  2950. /**
  2951.   * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
  2952.   * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
  2953.   * @param  TIMx Timer instance
  2954.   * @retval State of bit (1 or 0).
  2955.   */
  2956. __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
  2957. {
  2958.   return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
  2959. }
  2960.  
  2961. /**
  2962.   * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
  2963.   * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
  2964.   * @param  TIMx Timer instance
  2965.   * @retval None
  2966.   */
  2967. __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
  2968. {
  2969.   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
  2970. }
  2971.  
  2972. /**
  2973.   * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
  2974.   * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
  2975.   * @param  TIMx Timer instance
  2976.   * @retval State of bit (1 or 0).
  2977.   */
  2978. __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
  2979. {
  2980.   return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
  2981. }
  2982.  
  2983. /**
  2984.   * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
  2985.   * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
  2986.   * @param  TIMx Timer instance
  2987.   * @retval None
  2988.   */
  2989. __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
  2990. {
  2991.   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
  2992. }
  2993.  
  2994. /**
  2995.   * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
  2996.   * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
  2997.   * @param  TIMx Timer instance
  2998.   * @retval State of bit (1 or 0).
  2999.   */
  3000. __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
  3001. {
  3002.   return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
  3003. }
  3004.  
  3005. /**
  3006.   * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
  3007.   * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
  3008.   * @param  TIMx Timer instance
  3009.   * @retval None
  3010.   */
  3011. __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
  3012. {
  3013.   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
  3014. }
  3015.  
  3016. /**
  3017.   * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
  3018.   * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
  3019.   * @param  TIMx Timer instance
  3020.   * @retval State of bit (1 or 0).
  3021.   */
  3022. __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
  3023. {
  3024.   return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
  3025. }
  3026.  
  3027. /**
  3028.   * @brief  Clear the commutation interrupt flag (COMIF).
  3029.   * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
  3030.   * @param  TIMx Timer instance
  3031.   * @retval None
  3032.   */
  3033. __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
  3034. {
  3035.   WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
  3036. }
  3037.  
  3038. /**
  3039.   * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
  3040.   * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
  3041.   * @param  TIMx Timer instance
  3042.   * @retval State of bit (1 or 0).
  3043.   */
  3044. __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
  3045. {
  3046.   return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
  3047. }
  3048.  
  3049. /**
  3050.   * @brief  Clear the trigger interrupt flag (TIF).
  3051.   * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
  3052.   * @param  TIMx Timer instance
  3053.   * @retval None
  3054.   */
  3055. __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
  3056. {
  3057.   WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
  3058. }
  3059.  
  3060. /**
  3061.   * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
  3062.   * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
  3063.   * @param  TIMx Timer instance
  3064.   * @retval State of bit (1 or 0).
  3065.   */
  3066. __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
  3067. {
  3068.   return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
  3069. }
  3070.  
  3071. /**
  3072.   * @brief  Clear the break interrupt flag (BIF).
  3073.   * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
  3074.   * @param  TIMx Timer instance
  3075.   * @retval None
  3076.   */
  3077. __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
  3078. {
  3079.   WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
  3080. }
  3081.  
  3082. /**
  3083.   * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
  3084.   * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
  3085.   * @param  TIMx Timer instance
  3086.   * @retval State of bit (1 or 0).
  3087.   */
  3088. __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
  3089. {
  3090.   return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
  3091. }
  3092.  
  3093. /**
  3094.   * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
  3095.   * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
  3096.   * @param  TIMx Timer instance
  3097.   * @retval None
  3098.   */
  3099. __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
  3100. {
  3101.   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
  3102. }
  3103.  
  3104. /**
  3105.   * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
  3106.   * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
  3107.   * @param  TIMx Timer instance
  3108.   * @retval State of bit (1 or 0).
  3109.   */
  3110. __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
  3111. {
  3112.   return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
  3113. }
  3114.  
  3115. /**
  3116.   * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
  3117.   * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
  3118.   * @param  TIMx Timer instance
  3119.   * @retval None
  3120.   */
  3121. __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
  3122. {
  3123.   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
  3124. }
  3125.  
  3126. /**
  3127.   * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
  3128.   * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
  3129.   * @param  TIMx Timer instance
  3130.   * @retval State of bit (1 or 0).
  3131.   */
  3132. __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
  3133. {
  3134.   return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
  3135. }
  3136.  
  3137. /**
  3138.   * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
  3139.   * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
  3140.   * @param  TIMx Timer instance
  3141.   * @retval None
  3142.   */
  3143. __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
  3144. {
  3145.   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
  3146. }
  3147.  
  3148. /**
  3149.   * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
  3150.   * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
  3151.   * @param  TIMx Timer instance
  3152.   * @retval State of bit (1 or 0).
  3153.   */
  3154. __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
  3155. {
  3156.   return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
  3157. }
  3158.  
  3159. /**
  3160.   * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
  3161.   * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
  3162.   * @param  TIMx Timer instance
  3163.   * @retval None
  3164.   */
  3165. __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
  3166. {
  3167.   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
  3168. }
  3169.  
  3170. /**
  3171.   * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
  3172.   * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
  3173.   * @param  TIMx Timer instance
  3174.   * @retval State of bit (1 or 0).
  3175.   */
  3176. __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
  3177. {
  3178.   return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
  3179. }
  3180.  
  3181. /**
  3182.   * @}
  3183.   */
  3184.  
  3185. /** @defgroup TIM_LL_EF_IT_Management IT-Management
  3186.   * @{
  3187.   */
  3188. /**
  3189.   * @brief  Enable update interrupt (UIE).
  3190.   * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
  3191.   * @param  TIMx Timer instance
  3192.   * @retval None
  3193.   */
  3194. __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
  3195. {
  3196.   SET_BIT(TIMx->DIER, TIM_DIER_UIE);
  3197. }
  3198.  
  3199. /**
  3200.   * @brief  Disable update interrupt (UIE).
  3201.   * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
  3202.   * @param  TIMx Timer instance
  3203.   * @retval None
  3204.   */
  3205. __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
  3206. {
  3207.   CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
  3208. }
  3209.  
  3210. /**
  3211.   * @brief  Indicates whether the update interrupt (UIE) is enabled.
  3212.   * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
  3213.   * @param  TIMx Timer instance
  3214.   * @retval State of bit (1 or 0).
  3215.   */
  3216. __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
  3217. {
  3218.   return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
  3219. }
  3220.  
  3221. /**
  3222.   * @brief  Enable capture/compare 1 interrupt (CC1IE).
  3223.   * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
  3224.   * @param  TIMx Timer instance
  3225.   * @retval None
  3226.   */
  3227. __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
  3228. {
  3229.   SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
  3230. }
  3231.  
  3232. /**
  3233.   * @brief  Disable capture/compare 1  interrupt (CC1IE).
  3234.   * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
  3235.   * @param  TIMx Timer instance
  3236.   * @retval None
  3237.   */
  3238. __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
  3239. {
  3240.   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
  3241. }
  3242.  
  3243. /**
  3244.   * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
  3245.   * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
  3246.   * @param  TIMx Timer instance
  3247.   * @retval State of bit (1 or 0).
  3248.   */
  3249. __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
  3250. {
  3251.   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
  3252. }
  3253.  
  3254. /**
  3255.   * @brief  Enable capture/compare 2 interrupt (CC2IE).
  3256.   * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
  3257.   * @param  TIMx Timer instance
  3258.   * @retval None
  3259.   */
  3260. __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
  3261. {
  3262.   SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
  3263. }
  3264.  
  3265. /**
  3266.   * @brief  Disable capture/compare 2  interrupt (CC2IE).
  3267.   * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
  3268.   * @param  TIMx Timer instance
  3269.   * @retval None
  3270.   */
  3271. __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
  3272. {
  3273.   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
  3274. }
  3275.  
  3276. /**
  3277.   * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
  3278.   * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
  3279.   * @param  TIMx Timer instance
  3280.   * @retval State of bit (1 or 0).
  3281.   */
  3282. __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
  3283. {
  3284.   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
  3285. }
  3286.  
  3287. /**
  3288.   * @brief  Enable capture/compare 3 interrupt (CC3IE).
  3289.   * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
  3290.   * @param  TIMx Timer instance
  3291.   * @retval None
  3292.   */
  3293. __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
  3294. {
  3295.   SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
  3296. }
  3297.  
  3298. /**
  3299.   * @brief  Disable capture/compare 3  interrupt (CC3IE).
  3300.   * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
  3301.   * @param  TIMx Timer instance
  3302.   * @retval None
  3303.   */
  3304. __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
  3305. {
  3306.   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
  3307. }
  3308.  
  3309. /**
  3310.   * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
  3311.   * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
  3312.   * @param  TIMx Timer instance
  3313.   * @retval State of bit (1 or 0).
  3314.   */
  3315. __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
  3316. {
  3317.   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
  3318. }
  3319.  
  3320. /**
  3321.   * @brief  Enable capture/compare 4 interrupt (CC4IE).
  3322.   * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
  3323.   * @param  TIMx Timer instance
  3324.   * @retval None
  3325.   */
  3326. __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
  3327. {
  3328.   SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
  3329. }
  3330.  
  3331. /**
  3332.   * @brief  Disable capture/compare 4  interrupt (CC4IE).
  3333.   * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
  3334.   * @param  TIMx Timer instance
  3335.   * @retval None
  3336.   */
  3337. __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
  3338. {
  3339.   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
  3340. }
  3341.  
  3342. /**
  3343.   * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
  3344.   * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
  3345.   * @param  TIMx Timer instance
  3346.   * @retval State of bit (1 or 0).
  3347.   */
  3348. __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
  3349. {
  3350.   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
  3351. }
  3352.  
  3353. /**
  3354.   * @brief  Enable commutation interrupt (COMIE).
  3355.   * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
  3356.   * @param  TIMx Timer instance
  3357.   * @retval None
  3358.   */
  3359. __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
  3360. {
  3361.   SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
  3362. }
  3363.  
  3364. /**
  3365.   * @brief  Disable commutation interrupt (COMIE).
  3366.   * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
  3367.   * @param  TIMx Timer instance
  3368.   * @retval None
  3369.   */
  3370. __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
  3371. {
  3372.   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
  3373. }
  3374.  
  3375. /**
  3376.   * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
  3377.   * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
  3378.   * @param  TIMx Timer instance
  3379.   * @retval State of bit (1 or 0).
  3380.   */
  3381. __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
  3382. {
  3383.   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
  3384. }
  3385.  
  3386. /**
  3387.   * @brief  Enable trigger interrupt (TIE).
  3388.   * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
  3389.   * @param  TIMx Timer instance
  3390.   * @retval None
  3391.   */
  3392. __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
  3393. {
  3394.   SET_BIT(TIMx->DIER, TIM_DIER_TIE);
  3395. }
  3396.  
  3397. /**
  3398.   * @brief  Disable trigger interrupt (TIE).
  3399.   * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
  3400.   * @param  TIMx Timer instance
  3401.   * @retval None
  3402.   */
  3403. __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
  3404. {
  3405.   CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
  3406. }
  3407.  
  3408. /**
  3409.   * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
  3410.   * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
  3411.   * @param  TIMx Timer instance
  3412.   * @retval State of bit (1 or 0).
  3413.   */
  3414. __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
  3415. {
  3416.   return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
  3417. }
  3418.  
  3419. /**
  3420.   * @brief  Enable break interrupt (BIE).
  3421.   * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
  3422.   * @param  TIMx Timer instance
  3423.   * @retval None
  3424.   */
  3425. __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
  3426. {
  3427.   SET_BIT(TIMx->DIER, TIM_DIER_BIE);
  3428. }
  3429.  
  3430. /**
  3431.   * @brief  Disable break interrupt (BIE).
  3432.   * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
  3433.   * @param  TIMx Timer instance
  3434.   * @retval None
  3435.   */
  3436. __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
  3437. {
  3438.   CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
  3439. }
  3440.  
  3441. /**
  3442.   * @brief  Indicates whether the break interrupt (BIE) is enabled.
  3443.   * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
  3444.   * @param  TIMx Timer instance
  3445.   * @retval State of bit (1 or 0).
  3446.   */
  3447. __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
  3448. {
  3449.   return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
  3450. }
  3451.  
  3452. /**
  3453.   * @}
  3454.   */
  3455.  
  3456. /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
  3457.   * @{
  3458.   */
  3459. /**
  3460.   * @brief  Enable update DMA request (UDE).
  3461.   * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
  3462.   * @param  TIMx Timer instance
  3463.   * @retval None
  3464.   */
  3465. __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
  3466. {
  3467.   SET_BIT(TIMx->DIER, TIM_DIER_UDE);
  3468. }
  3469.  
  3470. /**
  3471.   * @brief  Disable update DMA request (UDE).
  3472.   * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
  3473.   * @param  TIMx Timer instance
  3474.   * @retval None
  3475.   */
  3476. __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
  3477. {
  3478.   CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
  3479. }
  3480.  
  3481. /**
  3482.   * @brief  Indicates whether the update DMA request  (UDE) is enabled.
  3483.   * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
  3484.   * @param  TIMx Timer instance
  3485.   * @retval State of bit (1 or 0).
  3486.   */
  3487. __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
  3488. {
  3489.   return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
  3490. }
  3491.  
  3492. /**
  3493.   * @brief  Enable capture/compare 1 DMA request (CC1DE).
  3494.   * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
  3495.   * @param  TIMx Timer instance
  3496.   * @retval None
  3497.   */
  3498. __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
  3499. {
  3500.   SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
  3501. }
  3502.  
  3503. /**
  3504.   * @brief  Disable capture/compare 1  DMA request (CC1DE).
  3505.   * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
  3506.   * @param  TIMx Timer instance
  3507.   * @retval None
  3508.   */
  3509. __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
  3510. {
  3511.   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
  3512. }
  3513.  
  3514. /**
  3515.   * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
  3516.   * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
  3517.   * @param  TIMx Timer instance
  3518.   * @retval State of bit (1 or 0).
  3519.   */
  3520. __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
  3521. {
  3522.   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
  3523. }
  3524.  
  3525. /**
  3526.   * @brief  Enable capture/compare 2 DMA request (CC2DE).
  3527.   * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
  3528.   * @param  TIMx Timer instance
  3529.   * @retval None
  3530.   */
  3531. __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
  3532. {
  3533.   SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
  3534. }
  3535.  
  3536. /**
  3537.   * @brief  Disable capture/compare 2  DMA request (CC2DE).
  3538.   * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
  3539.   * @param  TIMx Timer instance
  3540.   * @retval None
  3541.   */
  3542. __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
  3543. {
  3544.   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
  3545. }
  3546.  
  3547. /**
  3548.   * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
  3549.   * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
  3550.   * @param  TIMx Timer instance
  3551.   * @retval State of bit (1 or 0).
  3552.   */
  3553. __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
  3554. {
  3555.   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
  3556. }
  3557.  
  3558. /**
  3559.   * @brief  Enable capture/compare 3 DMA request (CC3DE).
  3560.   * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
  3561.   * @param  TIMx Timer instance
  3562.   * @retval None
  3563.   */
  3564. __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
  3565. {
  3566.   SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
  3567. }
  3568.  
  3569. /**
  3570.   * @brief  Disable capture/compare 3  DMA request (CC3DE).
  3571.   * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
  3572.   * @param  TIMx Timer instance
  3573.   * @retval None
  3574.   */
  3575. __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
  3576. {
  3577.   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
  3578. }
  3579.  
  3580. /**
  3581.   * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
  3582.   * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
  3583.   * @param  TIMx Timer instance
  3584.   * @retval State of bit (1 or 0).
  3585.   */
  3586. __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
  3587. {
  3588.   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
  3589. }
  3590.  
  3591. /**
  3592.   * @brief  Enable capture/compare 4 DMA request (CC4DE).
  3593.   * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
  3594.   * @param  TIMx Timer instance
  3595.   * @retval None
  3596.   */
  3597. __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
  3598. {
  3599.   SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
  3600. }
  3601.  
  3602. /**
  3603.   * @brief  Disable capture/compare 4  DMA request (CC4DE).
  3604.   * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
  3605.   * @param  TIMx Timer instance
  3606.   * @retval None
  3607.   */
  3608. __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
  3609. {
  3610.   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
  3611. }
  3612.  
  3613. /**
  3614.   * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
  3615.   * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
  3616.   * @param  TIMx Timer instance
  3617.   * @retval State of bit (1 or 0).
  3618.   */
  3619. __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
  3620. {
  3621.   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
  3622. }
  3623.  
  3624. /**
  3625.   * @brief  Enable commutation DMA request (COMDE).
  3626.   * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
  3627.   * @param  TIMx Timer instance
  3628.   * @retval None
  3629.   */
  3630. __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
  3631. {
  3632.   SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
  3633. }
  3634.  
  3635. /**
  3636.   * @brief  Disable commutation DMA request (COMDE).
  3637.   * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
  3638.   * @param  TIMx Timer instance
  3639.   * @retval None
  3640.   */
  3641. __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
  3642. {
  3643.   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
  3644. }
  3645.  
  3646. /**
  3647.   * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
  3648.   * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
  3649.   * @param  TIMx Timer instance
  3650.   * @retval State of bit (1 or 0).
  3651.   */
  3652. __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
  3653. {
  3654.   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
  3655. }
  3656.  
  3657. /**
  3658.   * @brief  Enable trigger interrupt (TDE).
  3659.   * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
  3660.   * @param  TIMx Timer instance
  3661.   * @retval None
  3662.   */
  3663. __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
  3664. {
  3665.   SET_BIT(TIMx->DIER, TIM_DIER_TDE);
  3666. }
  3667.  
  3668. /**
  3669.   * @brief  Disable trigger interrupt (TDE).
  3670.   * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
  3671.   * @param  TIMx Timer instance
  3672.   * @retval None
  3673.   */
  3674. __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
  3675. {
  3676.   CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
  3677. }
  3678.  
  3679. /**
  3680.   * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
  3681.   * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
  3682.   * @param  TIMx Timer instance
  3683.   * @retval State of bit (1 or 0).
  3684.   */
  3685. __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
  3686. {
  3687.   return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
  3688. }
  3689.  
  3690. /**
  3691.   * @}
  3692.   */
  3693.  
  3694. /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
  3695.   * @{
  3696.   */
  3697. /**
  3698.   * @brief  Generate an update event.
  3699.   * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
  3700.   * @param  TIMx Timer instance
  3701.   * @retval None
  3702.   */
  3703. __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
  3704. {
  3705.   SET_BIT(TIMx->EGR, TIM_EGR_UG);
  3706. }
  3707.  
  3708. /**
  3709.   * @brief  Generate Capture/Compare 1 event.
  3710.   * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
  3711.   * @param  TIMx Timer instance
  3712.   * @retval None
  3713.   */
  3714. __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
  3715. {
  3716.   SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
  3717. }
  3718.  
  3719. /**
  3720.   * @brief  Generate Capture/Compare 2 event.
  3721.   * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
  3722.   * @param  TIMx Timer instance
  3723.   * @retval None
  3724.   */
  3725. __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
  3726. {
  3727.   SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
  3728. }
  3729.  
  3730. /**
  3731.   * @brief  Generate Capture/Compare 3 event.
  3732.   * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
  3733.   * @param  TIMx Timer instance
  3734.   * @retval None
  3735.   */
  3736. __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
  3737. {
  3738.   SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
  3739. }
  3740.  
  3741. /**
  3742.   * @brief  Generate Capture/Compare 4 event.
  3743.   * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
  3744.   * @param  TIMx Timer instance
  3745.   * @retval None
  3746.   */
  3747. __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
  3748. {
  3749.   SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
  3750. }
  3751.  
  3752. /**
  3753.   * @brief  Generate commutation event.
  3754.   * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
  3755.   * @param  TIMx Timer instance
  3756.   * @retval None
  3757.   */
  3758. __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
  3759. {
  3760.   SET_BIT(TIMx->EGR, TIM_EGR_COMG);
  3761. }
  3762.  
  3763. /**
  3764.   * @brief  Generate trigger event.
  3765.   * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
  3766.   * @param  TIMx Timer instance
  3767.   * @retval None
  3768.   */
  3769. __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
  3770. {
  3771.   SET_BIT(TIMx->EGR, TIM_EGR_TG);
  3772. }
  3773.  
  3774. /**
  3775.   * @brief  Generate break event.
  3776.   * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
  3777.   * @param  TIMx Timer instance
  3778.   * @retval None
  3779.   */
  3780. __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
  3781. {
  3782.   SET_BIT(TIMx->EGR, TIM_EGR_BG);
  3783. }
  3784.  
  3785. /**
  3786.   * @}
  3787.   */
  3788.  
  3789. #if defined(USE_FULL_LL_DRIVER)
  3790. /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
  3791.   * @{
  3792.   */
  3793.  
  3794. ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
  3795. void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
  3796. ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
  3797. void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
  3798. ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
  3799. void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  3800. ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
  3801. void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
  3802. ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
  3803. void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
  3804. ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
  3805. void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
  3806. ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
  3807. /**
  3808.   * @}
  3809.   */
  3810. #endif /* USE_FULL_LL_DRIVER */
  3811.  
  3812. /**
  3813.   * @}
  3814.   */
  3815.  
  3816. /**
  3817.   * @}
  3818.   */
  3819.  
  3820. #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14  || TIM15 || TIM16 || TIM17 */
  3821.  
  3822. /**
  3823.   * @}
  3824.   */
  3825.  
  3826. #ifdef __cplusplus
  3827. }
  3828. #endif
  3829.  
  3830. #endif /* __STM32F1xx_LL_TIM_H */
  3831. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  3832.