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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_system.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of SYSTEM LL module.
  6.   @verbatim
  7.   ==============================================================================
  8.                      ##### How to use this driver #####
  9.   ==============================================================================
  10.     [..]
  11.     The LL SYSTEM driver contains a set of generic APIs that can be
  12.     used by user:
  13.       (+) Some of the FLASH features need to be handled in the SYSTEM file.
  14.       (+) Access to DBGCMU registers
  15.       (+) Access to SYSCFG registers
  16.  
  17.   @endverbatim
  18.   ******************************************************************************
  19.   * @attention
  20.   *
  21.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  22.   *
  23.   * Redistribution and use in source and binary forms, with or without modification,
  24.   * are permitted provided that the following conditions are met:
  25.   *   1. Redistributions of source code must retain the above copyright notice,
  26.   *      this list of conditions and the following disclaimer.
  27.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  28.   *      this list of conditions and the following disclaimer in the documentation
  29.   *      and/or other materials provided with the distribution.
  30.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  31.   *      may be used to endorse or promote products derived from this software
  32.   *      without specific prior written permission.
  33.   *
  34.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  35.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  36.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  37.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  38.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  39.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  40.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  41.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  42.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  43.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  44.   *
  45.   ******************************************************************************
  46.   */
  47.  
  48. /* Define to prevent recursive inclusion -------------------------------------*/
  49. #ifndef __STM32F1xx_LL_SYSTEM_H
  50. #define __STM32F1xx_LL_SYSTEM_H
  51.  
  52. #ifdef __cplusplus
  53. extern "C" {
  54. #endif
  55.  
  56. /* Includes ------------------------------------------------------------------*/
  57. #include "stm32f1xx.h"
  58.  
  59. /** @addtogroup STM32F1xx_LL_Driver
  60.   * @{
  61.   */
  62.  
  63. #if defined (FLASH) || defined (DBGMCU)
  64.  
  65. /** @defgroup SYSTEM_LL SYSTEM
  66.   * @{
  67.   */
  68.  
  69. /* Private types -------------------------------------------------------------*/
  70. /* Private variables ---------------------------------------------------------*/
  71.  
  72. /* Private constants ---------------------------------------------------------*/
  73. /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
  74.   * @{
  75.   */
  76.  
  77. /**
  78.   * @}
  79.   */
  80.  
  81. /* Private macros ------------------------------------------------------------*/
  82.  
  83. /* Exported types ------------------------------------------------------------*/
  84. /* Exported constants --------------------------------------------------------*/
  85. /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
  86.   * @{
  87.   */
  88.  
  89.  
  90.  
  91. /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
  92.   * @{
  93.   */
  94. #define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
  95. #define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
  96. #define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
  97. #define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
  98. #define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
  99. /**
  100.   * @}
  101.   */
  102.  
  103. /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
  104.   * @{
  105.   */
  106. #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_CR_DBG_TIM2_STOP          /*!< TIM2 counter stopped when core is halted */
  107. #define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_CR_DBG_TIM3_STOP          /*!< TIM3 counter stopped when core is halted */
  108. #define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_CR_DBG_TIM4_STOP          /*!< TIM4 counter stopped when core is halted */
  109. #if defined(DBGMCU_CR_DBG_TIM5_STOP)
  110. #define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_CR_DBG_TIM5_STOP          /*!< TIM5 counter stopped when core is halted */
  111. #endif /* DBGMCU_CR_DBG_TIM5_STOP */
  112. #if defined(DBGMCU_CR_DBG_TIM6_STOP)
  113. #define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_CR_DBG_TIM6_STOP          /*!< TIM6 counter stopped when core is halted */
  114. #endif /* DBGMCU_CR_DBG_TIM6_STOP */
  115. #if defined(DBGMCU_CR_DBG_TIM7_STOP)
  116. #define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_CR_DBG_TIM7_STOP          /*!< TIM7 counter stopped when core is halted */
  117. #endif /* DBGMCU_CR_DBG_TIM7_STOP */
  118. #if defined(DBGMCU_CR_DBG_TIM12_STOP)
  119. #define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_CR_DBG_TIM12_STOP         /*!< TIM12 counter stopped when core is halted */
  120. #endif /* DBGMCU_CR_DBG_TIM12_STOP */
  121. #if defined(DBGMCU_CR_DBG_TIM13_STOP)
  122. #define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_CR_DBG_TIM13_STOP         /*!< TIM13 counter stopped when core is halted */
  123. #endif /* DBGMCU_CR_DBG_TIM13_STOP */
  124. #if defined(DBGMCU_CR_DBG_TIM14_STOP)
  125. #define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_CR_DBG_TIM14_STOP         /*!< TIM14 counter stopped when core is halted */
  126. #endif /* DBGMCU_CR_DBG_TIM14_STOP */
  127. #define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_CR_DBG_WWDG_STOP          /*!< Debug Window Watchdog stopped when Core is halted */
  128. #define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_CR_DBG_IWDG_STOP          /*!< Debug Independent Watchdog stopped when Core is halted */
  129. #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
  130. #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
  131. #define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
  132. #endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */
  133. #if defined(DBGMCU_CR_DBG_CAN1_STOP)
  134. #define LL_DBGMCU_APB1_GRP1_CAN1_STOP      DBGMCU_CR_DBG_CAN1_STOP          /*!< CAN1 debug stopped when Core is halted  */
  135. #endif /* DBGMCU_CR_DBG_CAN1_STOP */
  136. #if defined(DBGMCU_CR_DBG_CAN2_STOP)
  137. #define LL_DBGMCU_APB1_GRP1_CAN2_STOP      DBGMCU_CR_DBG_CAN2_STOP          /*!< CAN2 debug stopped when Core is halted  */
  138. #endif /* DBGMCU_CR_DBG_CAN2_STOP */
  139. /**
  140.   * @}
  141.   */
  142.  
  143. /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
  144.   * @{
  145.   */
  146. #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_CR_DBG_TIM1_STOP   /*!< TIM1 counter stopped when core is halted */
  147. #if defined(DBGMCU_CR_DBG_TIM8_STOP)
  148. #define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_CR_DBG_TIM8_STOP   /*!< TIM8 counter stopped when core is halted */
  149. #endif /* DBGMCU_CR_DBG_CAN1_STOP */
  150. #if defined(DBGMCU_CR_DBG_TIM9_STOP)
  151. #define LL_DBGMCU_APB2_GRP1_TIM9_STOP      DBGMCU_CR_DBG_TIM9_STOP   /*!< TIM9 counter stopped when core is halted */
  152. #endif /* DBGMCU_CR_DBG_TIM9_STOP */
  153. #if defined(DBGMCU_CR_DBG_TIM10_STOP)
  154. #define LL_DBGMCU_APB2_GRP1_TIM10_STOP     DBGMCU_CR_DBG_TIM10_STOP   /*!< TIM10 counter stopped when core is halted */
  155. #endif /* DBGMCU_CR_DBG_TIM10_STOP */
  156. #if defined(DBGMCU_CR_DBG_TIM11_STOP)
  157. #define LL_DBGMCU_APB2_GRP1_TIM11_STOP     DBGMCU_CR_DBG_TIM11_STOP   /*!< TIM11 counter stopped when core is halted */
  158. #endif /* DBGMCU_CR_DBG_TIM11_STOP */
  159. #if defined(DBGMCU_CR_DBG_TIM15_STOP)
  160. #define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_CR_DBG_TIM15_STOP   /*!< TIM15 counter stopped when core is halted */
  161. #endif /* DBGMCU_CR_DBG_TIM15_STOP */
  162. #if defined(DBGMCU_CR_DBG_TIM16_STOP)
  163. #define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_CR_DBG_TIM16_STOP   /*!< TIM16 counter stopped when core is halted */
  164. #endif /* DBGMCU_CR_DBG_TIM16_STOP */
  165. #if defined(DBGMCU_CR_DBG_TIM17_STOP)
  166. #define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_CR_DBG_TIM17_STOP   /*!< TIM17 counter stopped when core is halted */
  167. #endif /* DBGMCU_CR_DBG_TIM17_STOP */
  168. /**
  169.   * @}
  170.   */
  171.  
  172. /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
  173.   * @{
  174.   */
  175. #if defined(FLASH_ACR_LATENCY)
  176. #define LL_FLASH_LATENCY_0                 0x00000000U             /*!< FLASH Zero Latency cycle */
  177. #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_0     /*!< FLASH One Latency cycle */
  178. #define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_1     /*!< FLASH Two wait states */
  179. #else
  180. #endif /* FLASH_ACR_LATENCY */
  181. /**
  182.   * @}
  183.   */
  184.  
  185. /**
  186.   * @}
  187.   */
  188.  
  189. /* Exported macro ------------------------------------------------------------*/
  190.  
  191. /* Exported functions --------------------------------------------------------*/
  192. /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
  193.   * @{
  194.   */
  195.  
  196.  
  197.  
  198. /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
  199.   * @{
  200.   */
  201.  
  202. /**
  203.   * @brief  Return the device identifier
  204.   * @note For Low Density devices, the device ID is 0x412
  205.   * @note For Medium Density devices, the device ID is 0x410
  206.   * @note For High Density devices, the device ID is 0x414
  207.   * @note For XL Density devices, the device ID is 0x430
  208.   * @note For Connectivity Line devices, the device ID is 0x418
  209.   * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
  210.   * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
  211.   */
  212. __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
  213. {
  214.   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
  215. }
  216.  
  217. /**
  218.   * @brief  Return the device revision identifier
  219.   * @note This field indicates the revision of the device.
  220.           For example, it is read as revA -> 0x1000,for Low Density devices
  221.           For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
  222.           For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
  223.           For example, it is read as revA or 1 -> 0x1003,for XL Density devices
  224.           For example, it is read as revA -> 0x1000, revZ -> 0x1001 for  Connectivity line devices
  225.   * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
  226.   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
  227.   */
  228. __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
  229. {
  230.   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
  231. }
  232.  
  233. /**
  234.   * @brief  Enable the Debug Module during SLEEP mode
  235.   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
  236.   * @retval None
  237.   */
  238. __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
  239. {
  240.   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
  241. }
  242.  
  243. /**
  244.   * @brief  Disable the Debug Module during SLEEP mode
  245.   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
  246.   * @retval None
  247.   */
  248. __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
  249. {
  250.   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
  251. }
  252.  
  253. /**
  254.   * @brief  Enable the Debug Module during STOP mode
  255.   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
  256.   * @retval None
  257.   */
  258. __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
  259. {
  260.   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
  261. }
  262.  
  263. /**
  264.   * @brief  Disable the Debug Module during STOP mode
  265.   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
  266.   * @retval None
  267.   */
  268. __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
  269. {
  270.   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
  271. }
  272.  
  273. /**
  274.   * @brief  Enable the Debug Module during STANDBY mode
  275.   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
  276.   * @retval None
  277.   */
  278. __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
  279. {
  280.   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
  281. }
  282.  
  283. /**
  284.   * @brief  Disable the Debug Module during STANDBY mode
  285.   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
  286.   * @retval None
  287.   */
  288. __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
  289. {
  290.   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
  291. }
  292.  
  293. /**
  294.   * @brief  Set Trace pin assignment control
  295.   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
  296.   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
  297.   * @param  PinAssignment This parameter can be one of the following values:
  298.   *         @arg @ref LL_DBGMCU_TRACE_NONE
  299.   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
  300.   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
  301.   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
  302.   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
  303.   * @retval None
  304.   */
  305. __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
  306. {
  307.   MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
  308. }
  309.  
  310. /**
  311.   * @brief  Get Trace pin assignment control
  312.   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
  313.   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
  314.   * @retval Returned value can be one of the following values:
  315.   *         @arg @ref LL_DBGMCU_TRACE_NONE
  316.   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
  317.   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
  318.   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
  319.   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
  320.   */
  321. __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
  322. {
  323.   return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
  324. }
  325.  
  326. /**
  327.   * @brief  Freeze APB1 peripherals (group1 peripherals)
  328.   * @rmtoll DBGMCU_CR_APB1      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  329.   *         DBGMCU_CR_APB1      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  330.   *         DBGMCU_CR_APB1      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  331.   *         DBGMCU_CR_APB1      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  332.   *         DBGMCU_CR_APB1      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  333.   *         DBGMCU_CR_APB1      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  334.   *         DBGMCU_CR_APB1      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  335.   *         DBGMCU_CR_APB1      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  336.   *         DBGMCU_CR_APB1      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  337.   *         DBGMCU_CR_APB1      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  338.   *         DBGMCU_CR_APB1      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  339.   *         DBGMCU_CR_APB1      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  340.   *         DBGMCU_CR_APB1      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  341.   *         DBGMCU_CR_APB1      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  342.   *         DBGMCU_CR_APB1      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
  343.   *         DBGMCU_CR_APB1      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph
  344.   * @param  Periphs This parameter can be a combination of the following values:
  345.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
  346.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
  347.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
  348.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
  349.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
  350.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
  351.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
  352.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
  353.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
  354.   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
  355.   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
  356.   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
  357.   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
  358.   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
  359.   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
  360.   *
  361.   *         (*) value not defined in all devices.
  362.   * @retval None
  363.   */
  364. __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
  365. {
  366.   SET_BIT(DBGMCU->CR, Periphs);
  367. }
  368.  
  369. /**
  370.   * @brief  Unfreeze APB1 peripherals (group1 peripherals)
  371.   * @rmtoll DBGMCU_CR_APB1      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  372.   *         DBGMCU_CR_APB1      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  373.   *         DBGMCU_CR_APB1      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  374.   *         DBGMCU_CR_APB1      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  375.   *         DBGMCU_CR_APB1      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  376.   *         DBGMCU_CR_APB1      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  377.   *         DBGMCU_CR_APB1      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  378.   *         DBGMCU_CR_APB1      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  379.   *         DBGMCU_CR_APB1      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  380.   *         DBGMCU_CR_APB1      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  381.   *         DBGMCU_CR_APB1      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  382.   *         DBGMCU_CR_APB1      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  383.   *         DBGMCU_CR_APB1      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  384.   *         DBGMCU_CR_APB1      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  385.   *         DBGMCU_CR_APB1      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
  386.   *         DBGMCU_CR_APB1      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph
  387.   * @param  Periphs This parameter can be a combination of the following values:
  388.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
  389.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
  390.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
  391.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
  392.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
  393.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
  394.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
  395.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
  396.   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
  397.   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
  398.   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
  399.   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
  400.   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
  401.   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
  402.   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
  403.   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
  404.   *
  405.   *         (*) value not defined in all devices.
  406.   * @retval None
  407.   */
  408. __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
  409. {
  410.   CLEAR_BIT(DBGMCU->CR, Periphs);
  411. }
  412.  
  413. /**
  414.   * @brief  Freeze APB2 peripherals
  415.   * @rmtoll DBGMCU_CR_APB2      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
  416.   *         DBGMCU_CR_APB2      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
  417.   *         DBGMCU_CR_APB2      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
  418.   *         DBGMCU_CR_APB2      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
  419.   *         DBGMCU_CR_APB2      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
  420.   *         DBGMCU_CR_APB2      DBG_TIM15_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
  421.   *         DBGMCU_CR_APB2      DBG_TIM16_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
  422.   *         DBGMCU_CR_APB2      DBG_TIM17_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph
  423.   * @param  Periphs This parameter can be a combination of the following values:
  424.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
  425.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
  426.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
  427.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
  428.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
  429.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
  430.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
  431.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
  432.   *
  433.   *         (*) value not defined in all devices.
  434.   * @retval None
  435.   */
  436. __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
  437. {
  438.   SET_BIT(DBGMCU->CR, Periphs);
  439. }
  440.  
  441. /**
  442.   * @brief  Unfreeze APB2 peripherals
  443.   * @rmtoll DBGMCU_CR_APB2      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
  444.   *         DBGMCU_CR_APB2      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
  445.   *         DBGMCU_CR_APB2      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
  446.   *         DBGMCU_CR_APB2      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
  447.   *         DBGMCU_CR_APB2      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
  448.   *         DBGMCU_CR_APB2      DBG_TIM15_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
  449.   *         DBGMCU_CR_APB2      DBG_TIM16_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
  450.   *         DBGMCU_CR_APB2      DBG_TIM17_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph
  451.   * @param  Periphs This parameter can be a combination of the following values:
  452.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
  453.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
  454.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
  455.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
  456.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
  457.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
  458.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
  459.   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
  460.   *
  461.   *         (*) value not defined in all devices.
  462.   * @retval None
  463.   */
  464. __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
  465. {
  466.   CLEAR_BIT(DBGMCU->CR, Periphs);
  467. }
  468. /**
  469.   * @}
  470.   */
  471.  
  472. #if defined(FLASH_ACR_LATENCY)
  473. /** @defgroup SYSTEM_LL_EF_FLASH FLASH
  474.   * @{
  475.   */
  476.  
  477. /**
  478.   * @brief  Set FLASH Latency
  479.   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
  480.   * @param  Latency This parameter can be one of the following values:
  481.   *         @arg @ref LL_FLASH_LATENCY_0
  482.   *         @arg @ref LL_FLASH_LATENCY_1
  483.   *         @arg @ref LL_FLASH_LATENCY_2
  484.   * @retval None
  485.   */
  486. __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
  487. {
  488.   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
  489. }
  490.  
  491. /**
  492.   * @brief  Get FLASH Latency
  493.   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
  494.   * @retval Returned value can be one of the following values:
  495.   *         @arg @ref LL_FLASH_LATENCY_0
  496.   *         @arg @ref LL_FLASH_LATENCY_1
  497.   *         @arg @ref LL_FLASH_LATENCY_2
  498.   */
  499. __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
  500. {
  501.   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
  502. }
  503.  
  504. /**
  505.   * @brief  Enable Prefetch
  506.   * @rmtoll FLASH_ACR    PRFTBE        LL_FLASH_EnablePrefetch
  507.   * @retval None
  508.   */
  509. __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
  510. {
  511.   SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
  512. }
  513.  
  514. /**
  515.   * @brief  Disable Prefetch
  516.   * @rmtoll FLASH_ACR    PRFTBE        LL_FLASH_DisablePrefetch
  517.   * @retval None
  518.   */
  519. __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
  520. {
  521.   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
  522. }
  523.  
  524. /**
  525.   * @brief  Check if Prefetch buffer is enabled
  526.   * @rmtoll FLASH_ACR    PRFTBS        LL_FLASH_IsPrefetchEnabled
  527.   * @retval State of bit (1 or 0).
  528.   */
  529. __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
  530. {
  531.   return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
  532. }
  533.  
  534. #endif /* FLASH_ACR_LATENCY */
  535. /**
  536.   * @brief  Enable Flash Half Cycle Access
  537.   * @rmtoll FLASH_ACR    HLFCYA        LL_FLASH_EnableHalfCycleAccess
  538.   * @retval None
  539.   */
  540. __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
  541. {
  542.   SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
  543. }
  544.  
  545. /**
  546.   * @brief  Disable Flash Half Cycle Access
  547.   * @rmtoll FLASH_ACR    HLFCYA        LL_FLASH_DisableHalfCycleAccess
  548.   * @retval None
  549.   */
  550. __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
  551. {
  552.   CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
  553. }
  554.  
  555. /**
  556.   * @brief  Check if  Flash Half Cycle Access is enabled or not
  557.   * @rmtoll FLASH_ACR    HLFCYA        LL_FLASH_IsHalfCycleAccessEnabled
  558.   * @retval State of bit (1 or 0).
  559.   */
  560. __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
  561. {
  562.   return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
  563. }
  564.  
  565.  
  566. /**
  567.   * @}
  568.   */
  569.  
  570. /**
  571.   * @}
  572.   */
  573.  
  574. /**
  575.   * @}
  576.   */
  577.  
  578. #endif /* defined (FLASH) || defined (DBGMCU) */
  579.  
  580. /**
  581.   * @}
  582.   */
  583.  
  584. #ifdef __cplusplus
  585. }
  586. #endif
  587.  
  588. #endif /* __STM32F1xx_LL_SYSTEM_H */
  589.  
  590. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  591.