Subversion Repositories LedShow

Rev

Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_spi.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of SPI LL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10.   *
  11.   * Redistribution and use in source and binary forms, with or without modification,
  12.   * are permitted provided that the following conditions are met:
  13.   *   1. Redistributions of source code must retain the above copyright notice,
  14.   *      this list of conditions and the following disclaimer.
  15.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16.   *      this list of conditions and the following disclaimer in the documentation
  17.   *      and/or other materials provided with the distribution.
  18.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19.   *      may be used to endorse or promote products derived from this software
  20.   *      without specific prior written permission.
  21.   *
  22.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32.   *
  33.   ******************************************************************************
  34.   */
  35.  
  36. /* Define to prevent recursive inclusion -------------------------------------*/
  37. #ifndef __STM32F1xx_LL_SPI_H
  38. #define __STM32F1xx_LL_SPI_H
  39.  
  40. #ifdef __cplusplus
  41. extern "C" {
  42. #endif
  43.  
  44. /* Includes ------------------------------------------------------------------*/
  45. #include "stm32f1xx.h"
  46.  
  47. /** @addtogroup STM32F1xx_LL_Driver
  48.   * @{
  49.   */
  50.  
  51. #if defined (SPI1) || defined (SPI2) || defined (SPI3)
  52.  
  53. /** @defgroup SPI_LL SPI
  54.   * @{
  55.   */
  56.  
  57. /* Private types -------------------------------------------------------------*/
  58. /* Private variables ---------------------------------------------------------*/
  59. /* Private macros ------------------------------------------------------------*/
  60.  
  61. /* Exported types ------------------------------------------------------------*/
  62. #if defined(USE_FULL_LL_DRIVER)
  63. /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
  64.   * @{
  65.   */
  66.  
  67. /**
  68.   * @brief  SPI Init structures definition
  69.   */
  70. typedef struct
  71. {
  72.   uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
  73.                                          This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
  74.  
  75.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
  76.  
  77.   uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
  78.                                          This parameter can be a value of @ref SPI_LL_EC_MODE.
  79.  
  80.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
  81.  
  82.   uint32_t DataWidth;               /*!< Specifies the SPI data width.
  83.                                          This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
  84.  
  85.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
  86.  
  87.   uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
  88.                                          This parameter can be a value of @ref SPI_LL_EC_POLARITY.
  89.  
  90.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
  91.  
  92.   uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
  93.                                          This parameter can be a value of @ref SPI_LL_EC_PHASE.
  94.  
  95.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
  96.  
  97.   uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
  98.                                          This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
  99.  
  100.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
  101.  
  102.   uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
  103.                                          This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
  104.                                          @note The communication clock is derived from the master clock. The slave clock does not need to be set.
  105.  
  106.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
  107.  
  108.   uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
  109.                                          This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
  110.  
  111.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
  112.  
  113.   uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
  114.                                          This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
  115.  
  116.                                          This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
  117.  
  118.   uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
  119.                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
  120.  
  121.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
  122.  
  123. } LL_SPI_InitTypeDef;
  124.  
  125. /**
  126.   * @}
  127.   */
  128. #endif /* USE_FULL_LL_DRIVER */
  129.  
  130. /* Exported constants --------------------------------------------------------*/
  131. /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
  132.   * @{
  133.   */
  134.  
  135. /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
  136.   * @brief    Flags defines which can be used with LL_SPI_ReadReg function
  137.   * @{
  138.   */
  139. #define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
  140. #define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
  141. #define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
  142. #define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
  143. #define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
  144. #define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
  145. #define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
  146. /**
  147.   * @}
  148.   */
  149.  
  150. /** @defgroup SPI_LL_EC_IT IT Defines
  151.   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
  152.   * @{
  153.   */
  154. #define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
  155. #define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
  156. #define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
  157. /**
  158.   * @}
  159.   */
  160.  
  161. /** @defgroup SPI_LL_EC_MODE Operation Mode
  162.   * @{
  163.   */
  164. #define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
  165. #define LL_SPI_MODE_SLAVE                  0x00000000U                    /*!< Slave configuration   */
  166. /**
  167.   * @}
  168.   */
  169.  
  170.  
  171. /** @defgroup SPI_LL_EC_PHASE Clock Phase
  172.   * @{
  173.   */
  174. #define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
  175. #define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
  176. /**
  177.   * @}
  178.   */
  179.  
  180. /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
  181.   * @{
  182.   */
  183. #define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
  184. #define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
  185. /**
  186.   * @}
  187.   */
  188.  
  189. /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
  190.   * @{
  191.   */
  192. #define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
  193. #define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
  194. #define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
  195. #define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
  196. #define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
  197. #define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
  198. #define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
  199. #define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
  200. /**
  201.   * @}
  202.   */
  203.  
  204. /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
  205.   * @{
  206.   */
  207. #define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
  208. #define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
  209. /**
  210.   * @}
  211.   */
  212.  
  213. /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
  214.   * @{
  215.   */
  216. #define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
  217. #define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
  218. #define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
  219. #define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
  220. /**
  221.   * @}
  222.   */
  223.  
  224. /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
  225.   * @{
  226.   */
  227. #define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
  228. #define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
  229. #define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
  230. /**
  231.   * @}
  232.   */
  233.  
  234. /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
  235.   * @{
  236.   */
  237. #define LL_SPI_DATAWIDTH_8BIT              0x00000000U                       /*!< Data length for SPI transfer:  8 bits */
  238. #define LL_SPI_DATAWIDTH_16BIT             (SPI_CR1_DFF)                     /*!< Data length for SPI transfer:  16 bits */
  239. /**
  240.   * @}
  241.   */
  242. #if defined(USE_FULL_LL_DRIVER)
  243.  
  244. /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
  245.   * @{
  246.   */
  247. #define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U                       /*!< CRC calculation disabled */
  248. #define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)                   /*!< CRC calculation enabled  */
  249. /**
  250.   * @}
  251.   */
  252. #endif /* USE_FULL_LL_DRIVER */
  253.  
  254. /**
  255.   * @}
  256.   */
  257.  
  258. /* Exported macro ------------------------------------------------------------*/
  259. /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
  260.   * @{
  261.   */
  262.  
  263. /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
  264.   * @{
  265.   */
  266.  
  267. /**
  268.   * @brief  Write a value in SPI register
  269.   * @param  __INSTANCE__ SPI Instance
  270.   * @param  __REG__ Register to be written
  271.   * @param  __VALUE__ Value to be written in the register
  272.   * @retval None
  273.   */
  274. #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  275.  
  276. /**
  277.   * @brief  Read a value in SPI register
  278.   * @param  __INSTANCE__ SPI Instance
  279.   * @param  __REG__ Register to be read
  280.   * @retval Register value
  281.   */
  282. #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  283. /**
  284.   * @}
  285.   */
  286.  
  287. /**
  288.   * @}
  289.   */
  290.  
  291. /* Exported functions --------------------------------------------------------*/
  292. /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
  293.   * @{
  294.   */
  295.  
  296. /** @defgroup SPI_LL_EF_Configuration Configuration
  297.   * @{
  298.   */
  299.  
  300. /**
  301.   * @brief  Enable SPI peripheral
  302.   * @rmtoll CR1          SPE           LL_SPI_Enable
  303.   * @param  SPIx SPI Instance
  304.   * @retval None
  305.   */
  306. __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
  307. {
  308.   SET_BIT(SPIx->CR1, SPI_CR1_SPE);
  309. }
  310.  
  311. /**
  312.   * @brief  Disable SPI peripheral
  313.   * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
  314.   * @rmtoll CR1          SPE           LL_SPI_Disable
  315.   * @param  SPIx SPI Instance
  316.   * @retval None
  317.   */
  318. __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
  319. {
  320.   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
  321. }
  322.  
  323. /**
  324.   * @brief  Check if SPI peripheral is enabled
  325.   * @rmtoll CR1          SPE           LL_SPI_IsEnabled
  326.   * @param  SPIx SPI Instance
  327.   * @retval State of bit (1 or 0).
  328.   */
  329. __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
  330. {
  331.   return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
  332. }
  333.  
  334. /**
  335.   * @brief  Set SPI operation mode to Master or Slave
  336.   * @note   This bit should not be changed when communication is ongoing.
  337.   * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
  338.   *         CR1          SSI           LL_SPI_SetMode
  339.   * @param  SPIx SPI Instance
  340.   * @param  Mode This parameter can be one of the following values:
  341.   *         @arg @ref LL_SPI_MODE_MASTER
  342.   *         @arg @ref LL_SPI_MODE_SLAVE
  343.   * @retval None
  344.   */
  345. __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
  346. {
  347.   MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
  348. }
  349.  
  350. /**
  351.   * @brief  Get SPI operation mode (Master or Slave)
  352.   * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
  353.   *         CR1          SSI           LL_SPI_GetMode
  354.   * @param  SPIx SPI Instance
  355.   * @retval Returned value can be one of the following values:
  356.   *         @arg @ref LL_SPI_MODE_MASTER
  357.   *         @arg @ref LL_SPI_MODE_SLAVE
  358.   */
  359. __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
  360. {
  361.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
  362. }
  363.  
  364.  
  365. /**
  366.   * @brief  Set clock phase
  367.   * @note   This bit should not be changed when communication is ongoing.
  368.   *         This bit is not used in SPI TI mode.
  369.   * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
  370.   * @param  SPIx SPI Instance
  371.   * @param  ClockPhase This parameter can be one of the following values:
  372.   *         @arg @ref LL_SPI_PHASE_1EDGE
  373.   *         @arg @ref LL_SPI_PHASE_2EDGE
  374.   * @retval None
  375.   */
  376. __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
  377. {
  378.   MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
  379. }
  380.  
  381. /**
  382.   * @brief  Get clock phase
  383.   * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
  384.   * @param  SPIx SPI Instance
  385.   * @retval Returned value can be one of the following values:
  386.   *         @arg @ref LL_SPI_PHASE_1EDGE
  387.   *         @arg @ref LL_SPI_PHASE_2EDGE
  388.   */
  389. __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
  390. {
  391.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
  392. }
  393.  
  394. /**
  395.   * @brief  Set clock polarity
  396.   * @note   This bit should not be changed when communication is ongoing.
  397.   *         This bit is not used in SPI TI mode.
  398.   * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
  399.   * @param  SPIx SPI Instance
  400.   * @param  ClockPolarity This parameter can be one of the following values:
  401.   *         @arg @ref LL_SPI_POLARITY_LOW
  402.   *         @arg @ref LL_SPI_POLARITY_HIGH
  403.   * @retval None
  404.   */
  405. __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
  406. {
  407.   MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
  408. }
  409.  
  410. /**
  411.   * @brief  Get clock polarity
  412.   * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
  413.   * @param  SPIx SPI Instance
  414.   * @retval Returned value can be one of the following values:
  415.   *         @arg @ref LL_SPI_POLARITY_LOW
  416.   *         @arg @ref LL_SPI_POLARITY_HIGH
  417.   */
  418. __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
  419. {
  420.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
  421. }
  422.  
  423. /**
  424.   * @brief  Set baud rate prescaler
  425.   * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
  426.   * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
  427.   * @param  SPIx SPI Instance
  428.   * @param  BaudRate This parameter can be one of the following values:
  429.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
  430.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
  431.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
  432.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
  433.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
  434.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
  435.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
  436.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
  437.   * @retval None
  438.   */
  439. __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
  440. {
  441.   MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
  442. }
  443.  
  444. /**
  445.   * @brief  Get baud rate prescaler
  446.   * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
  447.   * @param  SPIx SPI Instance
  448.   * @retval Returned value can be one of the following values:
  449.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
  450.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
  451.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
  452.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
  453.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
  454.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
  455.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
  456.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
  457.   */
  458. __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
  459. {
  460.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
  461. }
  462.  
  463. /**
  464.   * @brief  Set transfer bit order
  465.   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
  466.   * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
  467.   * @param  SPIx SPI Instance
  468.   * @param  BitOrder This parameter can be one of the following values:
  469.   *         @arg @ref LL_SPI_LSB_FIRST
  470.   *         @arg @ref LL_SPI_MSB_FIRST
  471.   * @retval None
  472.   */
  473. __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
  474. {
  475.   MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
  476. }
  477.  
  478. /**
  479.   * @brief  Get transfer bit order
  480.   * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
  481.   * @param  SPIx SPI Instance
  482.   * @retval Returned value can be one of the following values:
  483.   *         @arg @ref LL_SPI_LSB_FIRST
  484.   *         @arg @ref LL_SPI_MSB_FIRST
  485.   */
  486. __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
  487. {
  488.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
  489. }
  490.  
  491. /**
  492.   * @brief  Set transfer direction mode
  493.   * @note   For Half-Duplex mode, Rx Direction is set by default.
  494.   *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
  495.   * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
  496.   *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
  497.   *         CR1          BIDIOE        LL_SPI_SetTransferDirection
  498.   * @param  SPIx SPI Instance
  499.   * @param  TransferDirection This parameter can be one of the following values:
  500.   *         @arg @ref LL_SPI_FULL_DUPLEX
  501.   *         @arg @ref LL_SPI_SIMPLEX_RX
  502.   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
  503.   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
  504.   * @retval None
  505.   */
  506. __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
  507. {
  508.   MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
  509. }
  510.  
  511. /**
  512.   * @brief  Get transfer direction mode
  513.   * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
  514.   *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
  515.   *         CR1          BIDIOE        LL_SPI_GetTransferDirection
  516.   * @param  SPIx SPI Instance
  517.   * @retval Returned value can be one of the following values:
  518.   *         @arg @ref LL_SPI_FULL_DUPLEX
  519.   *         @arg @ref LL_SPI_SIMPLEX_RX
  520.   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
  521.   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
  522.   */
  523. __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
  524. {
  525.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
  526. }
  527.  
  528. /**
  529.   * @brief  Set frame data width
  530.   * @rmtoll CR1          DFF           LL_SPI_SetDataWidth
  531.   * @param  SPIx SPI Instance
  532.   * @param  DataWidth This parameter can be one of the following values:
  533.   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
  534.   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
  535.   * @retval None
  536.   */
  537. __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
  538. {
  539.   MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
  540. }
  541.  
  542. /**
  543.   * @brief  Get frame data width
  544.   * @rmtoll CR1          DFF           LL_SPI_GetDataWidth
  545.   * @param  SPIx SPI Instance
  546.   * @retval Returned value can be one of the following values:
  547.   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
  548.   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
  549.   */
  550. __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
  551. {
  552.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
  553. }
  554.  
  555. /**
  556.   * @}
  557.   */
  558.  
  559. /** @defgroup SPI_LL_EF_CRC_Management CRC Management
  560.   * @{
  561.   */
  562.  
  563. /**
  564.   * @brief  Enable CRC
  565.   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  566.   * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
  567.   * @param  SPIx SPI Instance
  568.   * @retval None
  569.   */
  570. __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
  571. {
  572.   SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
  573. }
  574.  
  575. /**
  576.   * @brief  Disable CRC
  577.   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  578.   * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
  579.   * @param  SPIx SPI Instance
  580.   * @retval None
  581.   */
  582. __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
  583. {
  584.   CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
  585. }
  586.  
  587. /**
  588.   * @brief  Check if CRC is enabled
  589.   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  590.   * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
  591.   * @param  SPIx SPI Instance
  592.   * @retval State of bit (1 or 0).
  593.   */
  594. __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
  595. {
  596.   return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
  597. }
  598.  
  599. /**
  600.   * @brief  Set CRCNext to transfer CRC on the line
  601.   * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
  602.   * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
  603.   * @param  SPIx SPI Instance
  604.   * @retval None
  605.   */
  606. __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
  607. {
  608.   SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
  609. }
  610.  
  611. /**
  612.   * @brief  Set polynomial for CRC calculation
  613.   * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
  614.   * @param  SPIx SPI Instance
  615.   * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  616.   * @retval None
  617.   */
  618. __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
  619. {
  620.   WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
  621. }
  622.  
  623. /**
  624.   * @brief  Get polynomial for CRC calculation
  625.   * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
  626.   * @param  SPIx SPI Instance
  627.   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  628.   */
  629. __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
  630. {
  631.   return (uint32_t)(READ_REG(SPIx->CRCPR));
  632. }
  633.  
  634. /**
  635.   * @brief  Get Rx CRC
  636.   * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
  637.   * @param  SPIx SPI Instance
  638.   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  639.   */
  640. __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
  641. {
  642.   return (uint32_t)(READ_REG(SPIx->RXCRCR));
  643. }
  644.  
  645. /**
  646.   * @brief  Get Tx CRC
  647.   * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
  648.   * @param  SPIx SPI Instance
  649.   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  650.   */
  651. __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
  652. {
  653.   return (uint32_t)(READ_REG(SPIx->TXCRCR));
  654. }
  655.  
  656. /**
  657.   * @}
  658.   */
  659.  
  660. /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
  661.   * @{
  662.   */
  663.  
  664. /**
  665.   * @brief  Set NSS mode
  666.   * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
  667.   * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
  668.   * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
  669.   * @param  SPIx SPI Instance
  670.   * @param  NSS This parameter can be one of the following values:
  671.   *         @arg @ref LL_SPI_NSS_SOFT
  672.   *         @arg @ref LL_SPI_NSS_HARD_INPUT
  673.   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
  674.   * @retval None
  675.   */
  676. __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
  677. {
  678.   MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
  679.   MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
  680. }
  681.  
  682. /**
  683.   * @brief  Get NSS mode
  684.   * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
  685.   * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
  686.   * @param  SPIx SPI Instance
  687.   * @retval Returned value can be one of the following values:
  688.   *         @arg @ref LL_SPI_NSS_SOFT
  689.   *         @arg @ref LL_SPI_NSS_HARD_INPUT
  690.   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
  691.   */
  692. __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
  693. {
  694.   register uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
  695.   register uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
  696.   return (Ssm | Ssoe);
  697. }
  698.  
  699. /**
  700.   * @}
  701.   */
  702.  
  703. /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
  704.   * @{
  705.   */
  706.  
  707. /**
  708.   * @brief  Check if Rx buffer is not empty
  709.   * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
  710.   * @param  SPIx SPI Instance
  711.   * @retval State of bit (1 or 0).
  712.   */
  713. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
  714. {
  715.   return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
  716. }
  717.  
  718. /**
  719.   * @brief  Check if Tx buffer is empty
  720.   * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
  721.   * @param  SPIx SPI Instance
  722.   * @retval State of bit (1 or 0).
  723.   */
  724. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
  725. {
  726.   return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
  727. }
  728.  
  729. /**
  730.   * @brief  Get CRC error flag
  731.   * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
  732.   * @param  SPIx SPI Instance
  733.   * @retval State of bit (1 or 0).
  734.   */
  735. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
  736. {
  737.   return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
  738. }
  739.  
  740. /**
  741.   * @brief  Get mode fault error flag
  742.   * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
  743.   * @param  SPIx SPI Instance
  744.   * @retval State of bit (1 or 0).
  745.   */
  746. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
  747. {
  748.   return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
  749. }
  750.  
  751. /**
  752.   * @brief  Get overrun error flag
  753.   * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
  754.   * @param  SPIx SPI Instance
  755.   * @retval State of bit (1 or 0).
  756.   */
  757. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
  758. {
  759.   return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
  760. }
  761.  
  762. /**
  763.   * @brief  Get busy flag
  764.   * @note   The BSY flag is cleared under any one of the following conditions:
  765.   * -When the SPI is correctly disabled
  766.   * -When a fault is detected in Master mode (MODF bit set to 1)
  767.   * -In Master mode, when it finishes a data transmission and no new data is ready to be
  768.   * sent
  769.   * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
  770.   * each data transfer.
  771.   * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
  772.   * @param  SPIx SPI Instance
  773.   * @retval State of bit (1 or 0).
  774.   */
  775. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
  776. {
  777.   return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
  778. }
  779.  
  780.  
  781. /**
  782.   * @brief  Clear CRC error flag
  783.   * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
  784.   * @param  SPIx SPI Instance
  785.   * @retval None
  786.   */
  787. __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
  788. {
  789.   CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
  790. }
  791.  
  792. /**
  793.   * @brief  Clear mode fault error flag
  794.   * @note   Clearing this flag is done by a read access to the SPIx_SR
  795.   *         register followed by a write access to the SPIx_CR1 register
  796.   * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
  797.   * @param  SPIx SPI Instance
  798.   * @retval None
  799.   */
  800. __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
  801. {
  802.   __IO uint32_t tmpreg;
  803.   tmpreg = SPIx->SR;
  804.   (void) tmpreg;
  805.   tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
  806.   (void) tmpreg;
  807. }
  808.  
  809. /**
  810.   * @brief  Clear overrun error flag
  811.   * @note   Clearing this flag is done by a read access to the SPIx_DR
  812.   *         register followed by a read access to the SPIx_SR register
  813.   * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
  814.   * @param  SPIx SPI Instance
  815.   * @retval None
  816.   */
  817. __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
  818. {
  819.   __IO uint32_t tmpreg;
  820.   tmpreg = SPIx->DR;
  821.   (void) tmpreg;
  822.   tmpreg = SPIx->SR;
  823.   (void) tmpreg;
  824. }
  825.  
  826.  
  827. /**
  828.   * @}
  829.   */
  830.  
  831. /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
  832.   * @{
  833.   */
  834.  
  835. /**
  836.   * @brief  Enable error interrupt
  837.   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
  838.   * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
  839.   * @param  SPIx SPI Instance
  840.   * @retval None
  841.   */
  842. __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
  843. {
  844.   SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
  845. }
  846.  
  847. /**
  848.   * @brief  Enable Rx buffer not empty interrupt
  849.   * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
  850.   * @param  SPIx SPI Instance
  851.   * @retval None
  852.   */
  853. __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
  854. {
  855.   SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
  856. }
  857.  
  858. /**
  859.   * @brief  Enable Tx buffer empty interrupt
  860.   * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
  861.   * @param  SPIx SPI Instance
  862.   * @retval None
  863.   */
  864. __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
  865. {
  866.   SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
  867. }
  868.  
  869. /**
  870.   * @brief  Disable error interrupt
  871.   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
  872.   * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
  873.   * @param  SPIx SPI Instance
  874.   * @retval None
  875.   */
  876. __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
  877. {
  878.   CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
  879. }
  880.  
  881. /**
  882.   * @brief  Disable Rx buffer not empty interrupt
  883.   * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
  884.   * @param  SPIx SPI Instance
  885.   * @retval None
  886.   */
  887. __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
  888. {
  889.   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
  890. }
  891.  
  892. /**
  893.   * @brief  Disable Tx buffer empty interrupt
  894.   * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
  895.   * @param  SPIx SPI Instance
  896.   * @retval None
  897.   */
  898. __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
  899. {
  900.   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
  901. }
  902.  
  903. /**
  904.   * @brief  Check if error interrupt is enabled
  905.   * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
  906.   * @param  SPIx SPI Instance
  907.   * @retval State of bit (1 or 0).
  908.   */
  909. __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
  910. {
  911.   return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
  912. }
  913.  
  914. /**
  915.   * @brief  Check if Rx buffer not empty interrupt is enabled
  916.   * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
  917.   * @param  SPIx SPI Instance
  918.   * @retval State of bit (1 or 0).
  919.   */
  920. __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
  921. {
  922.   return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
  923. }
  924.  
  925. /**
  926.   * @brief  Check if Tx buffer empty interrupt
  927.   * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
  928.   * @param  SPIx SPI Instance
  929.   * @retval State of bit (1 or 0).
  930.   */
  931. __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
  932. {
  933.   return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
  934. }
  935.  
  936. /**
  937.   * @}
  938.   */
  939.  
  940. /** @defgroup SPI_LL_EF_DMA_Management DMA Management
  941.   * @{
  942.   */
  943.  
  944. /**
  945.   * @brief  Enable DMA Rx
  946.   * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
  947.   * @param  SPIx SPI Instance
  948.   * @retval None
  949.   */
  950. __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
  951. {
  952.   SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
  953. }
  954.  
  955. /**
  956.   * @brief  Disable DMA Rx
  957.   * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
  958.   * @param  SPIx SPI Instance
  959.   * @retval None
  960.   */
  961. __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
  962. {
  963.   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
  964. }
  965.  
  966. /**
  967.   * @brief  Check if DMA Rx is enabled
  968.   * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
  969.   * @param  SPIx SPI Instance
  970.   * @retval State of bit (1 or 0).
  971.   */
  972. __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
  973. {
  974.   return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
  975. }
  976.  
  977. /**
  978.   * @brief  Enable DMA Tx
  979.   * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
  980.   * @param  SPIx SPI Instance
  981.   * @retval None
  982.   */
  983. __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
  984. {
  985.   SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
  986. }
  987.  
  988. /**
  989.   * @brief  Disable DMA Tx
  990.   * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
  991.   * @param  SPIx SPI Instance
  992.   * @retval None
  993.   */
  994. __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
  995. {
  996.   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
  997. }
  998.  
  999. /**
  1000.   * @brief  Check if DMA Tx is enabled
  1001.   * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
  1002.   * @param  SPIx SPI Instance
  1003.   * @retval State of bit (1 or 0).
  1004.   */
  1005. __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
  1006. {
  1007.   return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
  1008. }
  1009.  
  1010. /**
  1011.   * @brief  Get the data register address used for DMA transfer
  1012.   * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
  1013.   * @param  SPIx SPI Instance
  1014.   * @retval Address of data register
  1015.   */
  1016. __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
  1017. {
  1018.   return (uint32_t) & (SPIx->DR);
  1019. }
  1020.  
  1021. /**
  1022.   * @}
  1023.   */
  1024.  
  1025. /** @defgroup SPI_LL_EF_DATA_Management DATA Management
  1026.   * @{
  1027.   */
  1028.  
  1029. /**
  1030.   * @brief  Read 8-Bits in the data register
  1031.   * @rmtoll DR           DR            LL_SPI_ReceiveData8
  1032.   * @param  SPIx SPI Instance
  1033.   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
  1034.   */
  1035. __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
  1036. {
  1037.   return (uint8_t)(READ_REG(SPIx->DR));
  1038. }
  1039.  
  1040. /**
  1041.   * @brief  Read 16-Bits in the data register
  1042.   * @rmtoll DR           DR            LL_SPI_ReceiveData16
  1043.   * @param  SPIx SPI Instance
  1044.   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
  1045.   */
  1046. __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
  1047. {
  1048.   return (uint16_t)(READ_REG(SPIx->DR));
  1049. }
  1050.  
  1051. /**
  1052.   * @brief  Write 8-Bits in the data register
  1053.   * @rmtoll DR           DR            LL_SPI_TransmitData8
  1054.   * @param  SPIx SPI Instance
  1055.   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
  1056.   * @retval None
  1057.   */
  1058. __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
  1059. {
  1060.   SPIx->DR = TxData;
  1061. }
  1062.  
  1063. /**
  1064.   * @brief  Write 16-Bits in the data register
  1065.   * @rmtoll DR           DR            LL_SPI_TransmitData16
  1066.   * @param  SPIx SPI Instance
  1067.   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
  1068.   * @retval None
  1069.   */
  1070. __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
  1071. {
  1072.   SPIx->DR = TxData;
  1073. }
  1074.  
  1075. /**
  1076.   * @}
  1077.   */
  1078. #if defined(USE_FULL_LL_DRIVER)
  1079. /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
  1080.   * @{
  1081.   */
  1082.  
  1083. ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
  1084. ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
  1085. void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
  1086.  
  1087. /**
  1088.   * @}
  1089.   */
  1090. #endif /* USE_FULL_LL_DRIVER */
  1091. /**
  1092.   * @}
  1093.   */
  1094.  
  1095. /**
  1096.   * @}
  1097.   */
  1098.  
  1099. #if defined(SPI_I2S_SUPPORT)
  1100. /** @defgroup I2S_LL I2S
  1101.   * @{
  1102.   */
  1103.  
  1104. /* Private variables ---------------------------------------------------------*/
  1105. /* Private constants ---------------------------------------------------------*/
  1106. /* Private macros ------------------------------------------------------------*/
  1107.  
  1108. /* Exported types ------------------------------------------------------------*/
  1109. #if defined(USE_FULL_LL_DRIVER)
  1110. /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
  1111.   * @{
  1112.   */
  1113.  
  1114. /**
  1115.   * @brief  I2S Init structure definition
  1116.   */
  1117.  
  1118. typedef struct
  1119. {
  1120.   uint32_t Mode;                    /*!< Specifies the I2S operating mode.
  1121.                                          This parameter can be a value of @ref I2S_LL_EC_MODE
  1122.  
  1123.                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
  1124.  
  1125.   uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
  1126.                                          This parameter can be a value of @ref I2S_LL_EC_STANDARD
  1127.  
  1128.                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
  1129.  
  1130.  
  1131.   uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
  1132.                                          This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
  1133.  
  1134.                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
  1135.  
  1136.  
  1137.   uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
  1138.                                          This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
  1139.  
  1140.                                          This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
  1141.  
  1142.  
  1143.   uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
  1144.                                          This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
  1145.  
  1146.                                          Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
  1147.                                          and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
  1148.  
  1149.  
  1150.   uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
  1151.                                          This parameter can be a value of @ref I2S_LL_EC_POLARITY
  1152.  
  1153.                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
  1154.  
  1155. } LL_I2S_InitTypeDef;
  1156.  
  1157. /**
  1158.   * @}
  1159.   */
  1160. #endif /*USE_FULL_LL_DRIVER*/
  1161.  
  1162. /* Exported constants --------------------------------------------------------*/
  1163. /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
  1164.   * @{
  1165.   */
  1166.  
  1167. /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
  1168.   * @brief    Flags defines which can be used with LL_I2S_ReadReg function
  1169.   * @{
  1170.   */
  1171. #define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
  1172. #define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
  1173. #define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
  1174. #define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
  1175. #define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
  1176. #define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
  1177. /**
  1178.   * @}
  1179.   */
  1180.  
  1181. /** @defgroup SPI_LL_EC_IT IT Defines
  1182.   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
  1183.   * @{
  1184.   */
  1185. #define LL_I2S_CR2_RXNEIE                  LL_SPI_CR2_RXNEIE         /*!< Rx buffer not empty interrupt enable */
  1186. #define LL_I2S_CR2_TXEIE                   LL_SPI_CR2_TXEIE          /*!< Tx buffer empty interrupt enable     */
  1187. #define LL_I2S_CR2_ERRIE                   LL_SPI_CR2_ERRIE          /*!< Error interrupt enable               */
  1188. /**
  1189.   * @}
  1190.   */
  1191.  
  1192. /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
  1193.   * @{
  1194.   */
  1195. #define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel lenght 16bit */
  1196. #define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel lenght 32bit */
  1197. #define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel lenght 32bit */
  1198. #define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel lenght 32bit */
  1199. /**
  1200.   * @}
  1201.   */
  1202.  
  1203. /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
  1204.   * @{
  1205.   */
  1206. #define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low level  */
  1207. #define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
  1208. /**
  1209.   * @}
  1210.   */
  1211.  
  1212. /** @defgroup I2S_LL_EC_STANDARD I2s Standard
  1213.   * @{
  1214.   */
  1215. #define LL_I2S_STANDARD_PHILIPS            0x00000000U                                                         /*!< I2S standard philips                      */
  1216. #define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
  1217. #define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
  1218. #define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
  1219. #define LL_I2S_STANDARD_PCM_LONG           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization  */
  1220. /**
  1221.   * @}
  1222.   */
  1223.  
  1224. /** @defgroup I2S_LL_EC_MODE Operation Mode
  1225.   * @{
  1226.   */
  1227. #define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave Tx configuration  */
  1228. #define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
  1229. #define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
  1230. #define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
  1231. /**
  1232.   * @}
  1233.   */
  1234.  
  1235. /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
  1236.   * @{
  1237.   */
  1238. #define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
  1239. #define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
  1240. /**
  1241.   * @}
  1242.   */
  1243.  
  1244. #if defined(USE_FULL_LL_DRIVER)
  1245.  
  1246. /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
  1247.   * @{
  1248.   */
  1249. #define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is disabled */
  1250. #define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
  1251. /**
  1252.   * @}
  1253.   */
  1254.  
  1255. /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
  1256.   * @{
  1257.   */
  1258.  
  1259. #define LL_I2S_AUDIOFREQ_192K              192000U      /*!< Audio Frequency configuration 192000 Hz       */
  1260. #define LL_I2S_AUDIOFREQ_96K               96000U       /*!< Audio Frequency configuration  96000 Hz       */
  1261. #define LL_I2S_AUDIOFREQ_48K               48000U       /*!< Audio Frequency configuration  48000 Hz       */
  1262. #define LL_I2S_AUDIOFREQ_44K               44100U       /*!< Audio Frequency configuration  44100 Hz       */
  1263. #define LL_I2S_AUDIOFREQ_32K               32000U       /*!< Audio Frequency configuration  32000 Hz       */
  1264. #define LL_I2S_AUDIOFREQ_22K               22050U       /*!< Audio Frequency configuration  22050 Hz       */
  1265. #define LL_I2S_AUDIOFREQ_16K               16000U       /*!< Audio Frequency configuration  16000 Hz       */
  1266. #define LL_I2S_AUDIOFREQ_11K               11025U       /*!< Audio Frequency configuration  11025 Hz       */
  1267. #define LL_I2S_AUDIOFREQ_8K                8000U        /*!< Audio Frequency configuration   8000 Hz       */
  1268. #define LL_I2S_AUDIOFREQ_DEFAULT           2U           /*!< Audio Freq not specified. Register I2SDIV = 2 */
  1269. /**
  1270.   * @}
  1271.   */
  1272. #endif /* USE_FULL_LL_DRIVER */
  1273.  
  1274. /**
  1275.   * @}
  1276.   */
  1277.  
  1278. /* Exported macro ------------------------------------------------------------*/
  1279. /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
  1280.   * @{
  1281.   */
  1282.  
  1283. /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
  1284.   * @{
  1285.   */
  1286.  
  1287. /**
  1288.   * @brief  Write a value in I2S register
  1289.   * @param  __INSTANCE__ I2S Instance
  1290.   * @param  __REG__ Register to be written
  1291.   * @param  __VALUE__ Value to be written in the register
  1292.   * @retval None
  1293.   */
  1294. #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  1295.  
  1296. /**
  1297.   * @brief  Read a value in I2S register
  1298.   * @param  __INSTANCE__ I2S Instance
  1299.   * @param  __REG__ Register to be read
  1300.   * @retval Register value
  1301.   */
  1302. #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  1303. /**
  1304.   * @}
  1305.   */
  1306.  
  1307. /**
  1308.   * @}
  1309.   */
  1310.  
  1311.  
  1312. /* Exported functions --------------------------------------------------------*/
  1313.  
  1314. /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
  1315.   * @{
  1316.   */
  1317.  
  1318. /** @defgroup I2S_LL_EF_Configuration Configuration
  1319.   * @{
  1320.   */
  1321.  
  1322. /**
  1323.   * @brief  Select I2S mode and Enable I2S peripheral
  1324.   * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
  1325.   *         I2SCFGR      I2SE          LL_I2S_Enable
  1326.   * @param  SPIx SPI Instance
  1327.   * @retval None
  1328.   */
  1329. __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
  1330. {
  1331.   SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
  1332. }
  1333.  
  1334. /**
  1335.   * @brief  Disable I2S peripheral
  1336.   * @rmtoll I2SCFGR      I2SE          LL_I2S_Disable
  1337.   * @param  SPIx SPI Instance
  1338.   * @retval None
  1339.   */
  1340. __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
  1341. {
  1342.   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
  1343. }
  1344.  
  1345. /**
  1346.   * @brief  Check if I2S peripheral is enabled
  1347.   * @rmtoll I2SCFGR      I2SE          LL_I2S_IsEnabled
  1348.   * @param  SPIx SPI Instance
  1349.   * @retval State of bit (1 or 0).
  1350.   */
  1351. __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
  1352. {
  1353.   return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
  1354. }
  1355.  
  1356. /**
  1357.   * @brief  Set I2S data frame length
  1358.   * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
  1359.   *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat
  1360.   * @param  SPIx SPI Instance
  1361.   * @param  DataFormat This parameter can be one of the following values:
  1362.   *         @arg @ref LL_I2S_DATAFORMAT_16B
  1363.   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
  1364.   *         @arg @ref LL_I2S_DATAFORMAT_24B
  1365.   *         @arg @ref LL_I2S_DATAFORMAT_32B
  1366.   * @retval None
  1367.   */
  1368. __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
  1369. {
  1370.   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
  1371. }
  1372.  
  1373. /**
  1374.   * @brief  Get I2S data frame length
  1375.   * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
  1376.   *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat
  1377.   * @param  SPIx SPI Instance
  1378.   * @retval Returned value can be one of the following values:
  1379.   *         @arg @ref LL_I2S_DATAFORMAT_16B
  1380.   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
  1381.   *         @arg @ref LL_I2S_DATAFORMAT_24B
  1382.   *         @arg @ref LL_I2S_DATAFORMAT_32B
  1383.   */
  1384. __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
  1385. {
  1386.   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
  1387. }
  1388.  
  1389. /**
  1390.   * @brief  Set I2S clock polarity
  1391.   * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
  1392.   * @param  SPIx SPI Instance
  1393.   * @param  ClockPolarity This parameter can be one of the following values:
  1394.   *         @arg @ref LL_I2S_POLARITY_LOW
  1395.   *         @arg @ref LL_I2S_POLARITY_HIGH
  1396.   * @retval None
  1397.   */
  1398. __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
  1399. {
  1400.   SET_BIT(SPIx->I2SCFGR, ClockPolarity);
  1401. }
  1402.  
  1403. /**
  1404.   * @brief  Get I2S clock polarity
  1405.   * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
  1406.   * @param  SPIx SPI Instance
  1407.   * @retval Returned value can be one of the following values:
  1408.   *         @arg @ref LL_I2S_POLARITY_LOW
  1409.   *         @arg @ref LL_I2S_POLARITY_HIGH
  1410.   */
  1411. __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
  1412. {
  1413.   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
  1414. }
  1415.  
  1416. /**
  1417.   * @brief  Set I2S standard protocol
  1418.   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
  1419.   *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
  1420.   * @param  SPIx SPI Instance
  1421.   * @param  Standard This parameter can be one of the following values:
  1422.   *         @arg @ref LL_I2S_STANDARD_PHILIPS
  1423.   *         @arg @ref LL_I2S_STANDARD_MSB
  1424.   *         @arg @ref LL_I2S_STANDARD_LSB
  1425.   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
  1426.   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
  1427.   * @retval None
  1428.   */
  1429. __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
  1430. {
  1431.   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
  1432. }
  1433.  
  1434. /**
  1435.   * @brief  Get I2S standard protocol
  1436.   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
  1437.   *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
  1438.   * @param  SPIx SPI Instance
  1439.   * @retval Returned value can be one of the following values:
  1440.   *         @arg @ref LL_I2S_STANDARD_PHILIPS
  1441.   *         @arg @ref LL_I2S_STANDARD_MSB
  1442.   *         @arg @ref LL_I2S_STANDARD_LSB
  1443.   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
  1444.   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
  1445.   */
  1446. __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
  1447. {
  1448.   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
  1449. }
  1450.  
  1451. /**
  1452.   * @brief  Set I2S transfer mode
  1453.   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
  1454.   * @param  SPIx SPI Instance
  1455.   * @param  Mode This parameter can be one of the following values:
  1456.   *         @arg @ref LL_I2S_MODE_SLAVE_TX
  1457.   *         @arg @ref LL_I2S_MODE_SLAVE_RX
  1458.   *         @arg @ref LL_I2S_MODE_MASTER_TX
  1459.   *         @arg @ref LL_I2S_MODE_MASTER_RX
  1460.   * @retval None
  1461.   */
  1462. __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
  1463. {
  1464.   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
  1465. }
  1466.  
  1467. /**
  1468.   * @brief  Get I2S transfer mode
  1469.   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
  1470.   * @param  SPIx SPI Instance
  1471.   * @retval Returned value can be one of the following values:
  1472.   *         @arg @ref LL_I2S_MODE_SLAVE_TX
  1473.   *         @arg @ref LL_I2S_MODE_SLAVE_RX
  1474.   *         @arg @ref LL_I2S_MODE_MASTER_TX
  1475.   *         @arg @ref LL_I2S_MODE_MASTER_RX
  1476.   */
  1477. __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
  1478. {
  1479.   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
  1480. }
  1481.  
  1482. /**
  1483.   * @brief  Set I2S linear prescaler
  1484.   * @rmtoll I2SPR        I2SDIV        LL_I2S_SetPrescalerLinear
  1485.   * @param  SPIx SPI Instance
  1486.   * @param  PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
  1487.   * @retval None
  1488.   */
  1489. __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
  1490. {
  1491.   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
  1492. }
  1493.  
  1494. /**
  1495.   * @brief  Get I2S linear prescaler
  1496.   * @rmtoll I2SPR        I2SDIV        LL_I2S_GetPrescalerLinear
  1497.   * @param  SPIx SPI Instance
  1498.   * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
  1499.   */
  1500. __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
  1501. {
  1502.   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
  1503. }
  1504.  
  1505. /**
  1506.   * @brief  Set I2S parity prescaler
  1507.   * @rmtoll I2SPR        ODD           LL_I2S_SetPrescalerParity
  1508.   * @param  SPIx SPI Instance
  1509.   * @param  PrescalerParity This parameter can be one of the following values:
  1510.   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
  1511.   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
  1512.   * @retval None
  1513.   */
  1514. __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
  1515. {
  1516.   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
  1517. }
  1518.  
  1519. /**
  1520.   * @brief  Get I2S parity prescaler
  1521.   * @rmtoll I2SPR        ODD           LL_I2S_GetPrescalerParity
  1522.   * @param  SPIx SPI Instance
  1523.   * @retval Returned value can be one of the following values:
  1524.   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
  1525.   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
  1526.   */
  1527. __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
  1528. {
  1529.   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
  1530. }
  1531.  
  1532. /**
  1533.   * @brief  Enable the master clock ouput (Pin MCK)
  1534.   * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
  1535.   * @param  SPIx SPI Instance
  1536.   * @retval None
  1537.   */
  1538. __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
  1539. {
  1540.   SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
  1541. }
  1542.  
  1543. /**
  1544.   * @brief  Disable the master clock ouput (Pin MCK)
  1545.   * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
  1546.   * @param  SPIx SPI Instance
  1547.   * @retval None
  1548.   */
  1549. __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
  1550. {
  1551.   CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
  1552. }
  1553.  
  1554. /**
  1555.   * @brief  Check if the master clock ouput (Pin MCK) is enabled
  1556.   * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
  1557.   * @param  SPIx SPI Instance
  1558.   * @retval State of bit (1 or 0).
  1559.   */
  1560. __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
  1561. {
  1562.   return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
  1563. }
  1564.  
  1565. /**
  1566.   * @}
  1567.   */
  1568.  
  1569. /** @defgroup I2S_LL_EF_FLAG FLAG Management
  1570.   * @{
  1571.   */
  1572.  
  1573. /**
  1574.   * @brief  Check if Rx buffer is not empty
  1575.   * @rmtoll SR           RXNE          LL_I2S_IsActiveFlag_RXNE
  1576.   * @param  SPIx SPI Instance
  1577.   * @retval State of bit (1 or 0).
  1578.   */
  1579. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
  1580. {
  1581.   return LL_SPI_IsActiveFlag_RXNE(SPIx);
  1582. }
  1583.  
  1584. /**
  1585.   * @brief  Check if Tx buffer is empty
  1586.   * @rmtoll SR           TXE           LL_I2S_IsActiveFlag_TXE
  1587.   * @param  SPIx SPI Instance
  1588.   * @retval State of bit (1 or 0).
  1589.   */
  1590. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
  1591. {
  1592.   return LL_SPI_IsActiveFlag_TXE(SPIx);
  1593. }
  1594.  
  1595. /**
  1596.   * @brief  Get busy flag
  1597.   * @rmtoll SR           BSY           LL_I2S_IsActiveFlag_BSY
  1598.   * @param  SPIx SPI Instance
  1599.   * @retval State of bit (1 or 0).
  1600.   */
  1601. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
  1602. {
  1603.   return LL_SPI_IsActiveFlag_BSY(SPIx);
  1604. }
  1605.  
  1606. /**
  1607.   * @brief  Get overrun error flag
  1608.   * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
  1609.   * @param  SPIx SPI Instance
  1610.   * @retval State of bit (1 or 0).
  1611.   */
  1612. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
  1613. {
  1614.   return LL_SPI_IsActiveFlag_OVR(SPIx);
  1615. }
  1616.  
  1617. /**
  1618.   * @brief  Get underrun error flag
  1619.   * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
  1620.   * @param  SPIx SPI Instance
  1621.   * @retval State of bit (1 or 0).
  1622.   */
  1623. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
  1624. {
  1625.   return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
  1626. }
  1627.  
  1628. /**
  1629.   * @brief  Get channel side flag.
  1630.   * @note   0: Channel Left has to be transmitted or has been received\n
  1631.   *         1: Channel Right has to be transmitted or has been received\n
  1632.   *         It has no significance in PCM mode.
  1633.   * @rmtoll SR           CHSIDE        LL_I2S_IsActiveFlag_CHSIDE
  1634.   * @param  SPIx SPI Instance
  1635.   * @retval State of bit (1 or 0).
  1636.   */
  1637. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
  1638. {
  1639.   return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
  1640. }
  1641.  
  1642. /**
  1643.   * @brief  Clear overrun error flag
  1644.   * @rmtoll SR           OVR           LL_I2S_ClearFlag_OVR
  1645.   * @param  SPIx SPI Instance
  1646.   * @retval None
  1647.   */
  1648. __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
  1649. {
  1650.   LL_SPI_ClearFlag_OVR(SPIx);
  1651. }
  1652.  
  1653. /**
  1654.   * @brief  Clear underrun error flag
  1655.   * @rmtoll SR           UDR           LL_I2S_ClearFlag_UDR
  1656.   * @param  SPIx SPI Instance
  1657.   * @retval None
  1658.   */
  1659. __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
  1660. {
  1661.   __IO uint32_t tmpreg;
  1662.   tmpreg = SPIx->SR;
  1663.   (void)tmpreg;
  1664. }
  1665.  
  1666. /**
  1667.   * @}
  1668.   */
  1669.  
  1670. /** @defgroup I2S_LL_EF_IT Interrupt Management
  1671.   * @{
  1672.   */
  1673.  
  1674. /**
  1675.   * @brief  Enable error IT
  1676.   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
  1677.   * @rmtoll CR2          ERRIE         LL_I2S_EnableIT_ERR
  1678.   * @param  SPIx SPI Instance
  1679.   * @retval None
  1680.   */
  1681. __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
  1682. {
  1683.   LL_SPI_EnableIT_ERR(SPIx);
  1684. }
  1685.  
  1686. /**
  1687.   * @brief  Enable Rx buffer not empty IT
  1688.   * @rmtoll CR2          RXNEIE        LL_I2S_EnableIT_RXNE
  1689.   * @param  SPIx SPI Instance
  1690.   * @retval None
  1691.   */
  1692. __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
  1693. {
  1694.   LL_SPI_EnableIT_RXNE(SPIx);
  1695. }
  1696.  
  1697. /**
  1698.   * @brief  Enable Tx buffer empty IT
  1699.   * @rmtoll CR2          TXEIE         LL_I2S_EnableIT_TXE
  1700.   * @param  SPIx SPI Instance
  1701.   * @retval None
  1702.   */
  1703. __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
  1704. {
  1705.   LL_SPI_EnableIT_TXE(SPIx);
  1706. }
  1707.  
  1708. /**
  1709.   * @brief  Disable error IT
  1710.   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
  1711.   * @rmtoll CR2          ERRIE         LL_I2S_DisableIT_ERR
  1712.   * @param  SPIx SPI Instance
  1713.   * @retval None
  1714.   */
  1715. __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
  1716. {
  1717.   LL_SPI_DisableIT_ERR(SPIx);
  1718. }
  1719.  
  1720. /**
  1721.   * @brief  Disable Rx buffer not empty IT
  1722.   * @rmtoll CR2          RXNEIE        LL_I2S_DisableIT_RXNE
  1723.   * @param  SPIx SPI Instance
  1724.   * @retval None
  1725.   */
  1726. __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
  1727. {
  1728.   LL_SPI_DisableIT_RXNE(SPIx);
  1729. }
  1730.  
  1731. /**
  1732.   * @brief  Disable Tx buffer empty IT
  1733.   * @rmtoll CR2          TXEIE         LL_I2S_DisableIT_TXE
  1734.   * @param  SPIx SPI Instance
  1735.   * @retval None
  1736.   */
  1737. __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
  1738. {
  1739.   LL_SPI_DisableIT_TXE(SPIx);
  1740. }
  1741.  
  1742. /**
  1743.   * @brief  Check if ERR IT is enabled
  1744.   * @rmtoll CR2          ERRIE         LL_I2S_IsEnabledIT_ERR
  1745.   * @param  SPIx SPI Instance
  1746.   * @retval State of bit (1 or 0).
  1747.   */
  1748. __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
  1749. {
  1750.   return LL_SPI_IsEnabledIT_ERR(SPIx);
  1751. }
  1752.  
  1753. /**
  1754.   * @brief  Check if RXNE IT is enabled
  1755.   * @rmtoll CR2          RXNEIE        LL_I2S_IsEnabledIT_RXNE
  1756.   * @param  SPIx SPI Instance
  1757.   * @retval State of bit (1 or 0).
  1758.   */
  1759. __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
  1760. {
  1761.   return LL_SPI_IsEnabledIT_RXNE(SPIx);
  1762. }
  1763.  
  1764. /**
  1765.   * @brief  Check if TXE IT is enabled
  1766.   * @rmtoll CR2          TXEIE         LL_I2S_IsEnabledIT_TXE
  1767.   * @param  SPIx SPI Instance
  1768.   * @retval State of bit (1 or 0).
  1769.   */
  1770. __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
  1771. {
  1772.   return LL_SPI_IsEnabledIT_TXE(SPIx);
  1773. }
  1774.  
  1775. /**
  1776.   * @}
  1777.   */
  1778.  
  1779. /** @defgroup I2S_LL_EF_DMA DMA Management
  1780.   * @{
  1781.   */
  1782.  
  1783. /**
  1784.   * @brief  Enable DMA Rx
  1785.   * @rmtoll CR2          RXDMAEN       LL_I2S_EnableDMAReq_RX
  1786.   * @param  SPIx SPI Instance
  1787.   * @retval None
  1788.   */
  1789. __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
  1790. {
  1791.   LL_SPI_EnableDMAReq_RX(SPIx);
  1792. }
  1793.  
  1794. /**
  1795.   * @brief  Disable DMA Rx
  1796.   * @rmtoll CR2          RXDMAEN       LL_I2S_DisableDMAReq_RX
  1797.   * @param  SPIx SPI Instance
  1798.   * @retval None
  1799.   */
  1800. __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
  1801. {
  1802.   LL_SPI_DisableDMAReq_RX(SPIx);
  1803. }
  1804.  
  1805. /**
  1806.   * @brief  Check if DMA Rx is enabled
  1807.   * @rmtoll CR2          RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
  1808.   * @param  SPIx SPI Instance
  1809.   * @retval State of bit (1 or 0).
  1810.   */
  1811. __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
  1812. {
  1813.   return LL_SPI_IsEnabledDMAReq_RX(SPIx);
  1814. }
  1815.  
  1816. /**
  1817.   * @brief  Enable DMA Tx
  1818.   * @rmtoll CR2          TXDMAEN       LL_I2S_EnableDMAReq_TX
  1819.   * @param  SPIx SPI Instance
  1820.   * @retval None
  1821.   */
  1822. __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
  1823. {
  1824.   LL_SPI_EnableDMAReq_TX(SPIx);
  1825. }
  1826.  
  1827. /**
  1828.   * @brief  Disable DMA Tx
  1829.   * @rmtoll CR2          TXDMAEN       LL_I2S_DisableDMAReq_TX
  1830.   * @param  SPIx SPI Instance
  1831.   * @retval None
  1832.   */
  1833. __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
  1834. {
  1835.   LL_SPI_DisableDMAReq_TX(SPIx);
  1836. }
  1837.  
  1838. /**
  1839.   * @brief  Check if DMA Tx is enabled
  1840.   * @rmtoll CR2          TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
  1841.   * @param  SPIx SPI Instance
  1842.   * @retval State of bit (1 or 0).
  1843.   */
  1844. __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
  1845. {
  1846.   return LL_SPI_IsEnabledDMAReq_TX(SPIx);
  1847. }
  1848.  
  1849. /**
  1850.   * @}
  1851.   */
  1852.  
  1853. /** @defgroup I2S_LL_EF_DATA DATA Management
  1854.   * @{
  1855.   */
  1856.  
  1857. /**
  1858.   * @brief  Read 16-Bits in data register
  1859.   * @rmtoll DR           DR            LL_I2S_ReceiveData16
  1860.   * @param  SPIx SPI Instance
  1861.   * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
  1862.   */
  1863. __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
  1864. {
  1865.   return LL_SPI_ReceiveData16(SPIx);
  1866. }
  1867.  
  1868. /**
  1869.   * @brief  Write 16-Bits in data register
  1870.   * @rmtoll DR           DR            LL_I2S_TransmitData16
  1871.   * @param  SPIx SPI Instance
  1872.   * @param  TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
  1873.   * @retval None
  1874.   */
  1875. __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
  1876. {
  1877.   LL_SPI_TransmitData16(SPIx, TxData);
  1878. }
  1879.  
  1880. /**
  1881.   * @}
  1882.   */
  1883.  
  1884. #if defined(USE_FULL_LL_DRIVER)
  1885. /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
  1886.   * @{
  1887.   */
  1888.  
  1889. ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
  1890. ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
  1891. void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
  1892. void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
  1893.  
  1894. /**
  1895.   * @}
  1896.   */
  1897. #endif /* USE_FULL_LL_DRIVER */
  1898.  
  1899. /**
  1900.   * @}
  1901.   */
  1902.  
  1903. /**
  1904.   * @}
  1905.   */
  1906. #endif /* SPI_I2S_SUPPORT */
  1907.  
  1908. #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
  1909.  
  1910. /**
  1911.   * @}
  1912.   */
  1913.  
  1914. #ifdef __cplusplus
  1915. }
  1916. #endif
  1917.  
  1918. #endif /* __STM32F1xx_LL_SPI_H */
  1919.  
  1920. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1921.