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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_sdmmc.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of SDMMC HAL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * Copyright (c) 2016 STMicroelectronics.
  10.   * All rights reserved.
  11.   *
  12.   * This software is licensed under terms that can be found in the LICENSE file
  13.   * in the root directory of this software component.
  14.   * If no LICENSE file comes with this software, it is provided AS-IS.
  15.   *
  16.   ******************************************************************************
  17.   */
  18.  
  19. /* Define to prevent recursive inclusion -------------------------------------*/
  20. #ifndef STM32F1xx_LL_SDMMC_H
  21. #define STM32F1xx_LL_SDMMC_H
  22.  
  23. #ifdef __cplusplus
  24.  extern "C" {
  25. #endif
  26.  
  27. #if defined(SDIO)
  28.  
  29. /* Includes ------------------------------------------------------------------*/
  30. #include "stm32f1xx_hal_def.h"
  31.  
  32. /** @addtogroup STM32F1xx_Driver
  33.   * @{
  34.   */
  35.  
  36. /** @addtogroup SDMMC_LL
  37.   * @{
  38.   */
  39.  
  40. /* Exported types ------------------------------------------------------------*/
  41. /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
  42.   * @{
  43.   */
  44.  
  45. /**
  46.   * @brief  SDMMC Configuration Structure definition  
  47.   */
  48. typedef struct
  49. {
  50.   uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
  51.                                       This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
  52.  
  53.   uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is
  54.                                       enabled or disabled.
  55.                                       This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
  56.  
  57.   uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or
  58.                                       disabled when the bus is idle.
  59.                                       This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
  60.  
  61.   uint32_t BusWide;              /*!< Specifies the SDMMC bus width.
  62.                                       This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
  63.  
  64.   uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
  65.                                       This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
  66.  
  67.   uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.
  68.                                       This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  
  69.  
  70. }SDIO_InitTypeDef;
  71.  
  72.  
  73. /**
  74.   * @brief  SDMMC Command Control structure
  75.   */
  76. typedef struct                                                                                            
  77. {
  78.   uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent
  79.                                      to a card as part of a command message. If a command
  80.                                      contains an argument, it must be loaded into this register
  81.                                      before writing the command to the command register.              */
  82.  
  83.   uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
  84.                                      Max_Data = 64                                                    */
  85.  
  86.   uint32_t Response;            /*!< Specifies the SDMMC response type.
  87.                                      This parameter can be a value of @ref SDMMC_LL_Response_Type         */
  88.  
  89.   uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is
  90.                                      enabled or disabled.
  91.                                      This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
  92.  
  93.   uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)
  94.                                      is enabled or disabled.
  95.                                      This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
  96. }SDIO_CmdInitTypeDef;
  97.  
  98.  
  99. /**
  100.   * @brief  SDMMC Data Control structure
  101.   */
  102. typedef struct
  103. {
  104.   uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
  105.  
  106.   uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
  107.  
  108.   uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
  109.                                      This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
  110.  
  111.   uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
  112.                                      is a read or write.
  113.                                      This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
  114.  
  115.   uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
  116.                                      This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
  117.  
  118.   uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)
  119.                                      is enabled or disabled.
  120.                                      This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
  121. }SDIO_DataInitTypeDef;
  122.  
  123. /**
  124.   * @}
  125.   */
  126.  
  127. /* Exported constants --------------------------------------------------------*/
  128. /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
  129.   * @{
  130.   */
  131. #define SDMMC_ERROR_NONE                                0x00000000U    /*!< No error                                                      */
  132. #define SDMMC_ERROR_CMD_CRC_FAIL                        0x00000001U    /*!< Command response received (but CRC check failed)              */
  133. #define SDMMC_ERROR_DATA_CRC_FAIL                       0x00000002U    /*!< Data block sent/received (CRC check failed)                   */
  134. #define SDMMC_ERROR_CMD_RSP_TIMEOUT                     0x00000004U    /*!< Command response timeout                                      */
  135. #define SDMMC_ERROR_DATA_TIMEOUT                        0x00000008U    /*!< Data timeout                                                  */
  136. #define SDMMC_ERROR_TX_UNDERRUN                         0x00000010U    /*!< Transmit FIFO underrun                                        */
  137. #define SDMMC_ERROR_RX_OVERRUN                          0x00000020U    /*!< Receive FIFO overrun                                          */
  138. #define SDMMC_ERROR_ADDR_MISALIGNED                     0x00000040U    /*!< Misaligned address                                            */
  139. #define SDMMC_ERROR_BLOCK_LEN_ERR                       0x00000080U    /*!< Transferred block length is not allowed for the card or the
  140.                                                                             number of transferred bytes does not match the block length   */
  141. #define SDMMC_ERROR_ERASE_SEQ_ERR                       0x00000100U    /*!< An error in the sequence of erase command occurs              */
  142. #define SDMMC_ERROR_BAD_ERASE_PARAM                     0x00000200U    /*!< An invalid selection for erase groups                         */
  143. #define SDMMC_ERROR_WRITE_PROT_VIOLATION                0x00000400U    /*!< Attempt to program a write protect block                      */
  144. #define SDMMC_ERROR_LOCK_UNLOCK_FAILED                  0x00000800U    /*!< Sequence or password error has been detected in unlock
  145.                                                                             command or if there was an attempt to access a locked card    */
  146. #define SDMMC_ERROR_COM_CRC_FAILED                      0x00001000U    /*!< CRC check of the previous command failed                      */
  147. #define SDMMC_ERROR_ILLEGAL_CMD                         0x00002000U    /*!< Command is not legal for the card state                       */
  148. #define SDMMC_ERROR_CARD_ECC_FAILED                     0x00004000U    /*!< Card internal ECC was applied but failed to correct the data  */
  149. #define SDMMC_ERROR_CC_ERR                              0x00008000U    /*!< Internal card controller error                                */
  150. #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR                 0x00010000U    /*!< General or unknown error                                      */
  151. #define SDMMC_ERROR_STREAM_READ_UNDERRUN                0x00020000U    /*!< The card could not sustain data reading in stream rmode       */
  152. #define SDMMC_ERROR_STREAM_WRITE_OVERRUN                0x00040000U    /*!< The card could not sustain data programming in stream mode    */
  153. #define SDMMC_ERROR_CID_CSD_OVERWRITE                   0x00080000U    /*!< CID/CSD overwrite error                                       */
  154. #define SDMMC_ERROR_WP_ERASE_SKIP                       0x00100000U    /*!< Only partial address space was erased                         */
  155. #define SDMMC_ERROR_CARD_ECC_DISABLED                   0x00200000U    /*!< Command has been executed without using internal ECC          */
  156. #define SDMMC_ERROR_ERASE_RESET                         0x00400000U    /*!< Erase sequence was cleared before executing because an out
  157.                                                                             of erase sequence command was received                        */
  158. #define SDMMC_ERROR_AKE_SEQ_ERR                         0x00800000U    /*!< Error in sequence of authentication                           */
  159. #define SDMMC_ERROR_INVALID_VOLTRANGE                   0x01000000U    /*!< Error in case of invalid voltage range                        */
  160. #define SDMMC_ERROR_ADDR_OUT_OF_RANGE                   0x02000000U    /*!< Error when addressed block is out of range                    */
  161. #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE              0x04000000U    /*!< Error when command request is not applicable                  */
  162. #define SDMMC_ERROR_INVALID_PARAMETER                   0x08000000U    /*!< the used parameter is not valid                               */
  163. #define SDMMC_ERROR_UNSUPPORTED_FEATURE                 0x10000000U    /*!< Error when feature is not insupported                         */
  164. #define SDMMC_ERROR_BUSY                                0x20000000U    /*!< Error when transfer process is busy                           */
  165. #define SDMMC_ERROR_DMA                                 0x40000000U    /*!< Error while DMA transfer                                      */
  166. #define SDMMC_ERROR_TIMEOUT                             0x80000000U    /*!< Timeout error                                                 */
  167.  
  168. /**
  169.   * @brief SDMMC Commands Index
  170.   */
  171. #define SDMMC_CMD_GO_IDLE_STATE                                 0U    /*!< Resets the SD memory card.                                                               */
  172. #define SDMMC_CMD_SEND_OP_COND                                  1U    /*!< Sends host capacity support information and activates the card's initialization process. */
  173. #define SDMMC_CMD_ALL_SEND_CID                                  2U    /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
  174. #define SDMMC_CMD_SET_REL_ADDR                                  3U    /*!< Asks the card to publish a new relative address (RCA).                                   */
  175. #define SDMMC_CMD_SET_DSR                                       4U    /*!< Programs the DSR of all cards.                                                           */
  176. #define SDMMC_CMD_SDMMC_SEN_OP_COND                             5U    /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
  177.                                                                            operating condition register (OCR) content in the response on the CMD line.              */
  178. #define SDMMC_CMD_HS_SWITCH                                     6U    /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
  179. #define SDMMC_CMD_SEL_DESEL_CARD                                7U    /*!< Selects the card by its own relative address and gets deselected by any other address    */
  180. #define SDMMC_CMD_HS_SEND_EXT_CSD                               8U    /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
  181.                                                                            and asks the card whether card supports voltage.                                         */
  182. #define SDMMC_CMD_SEND_CSD                                      9U    /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
  183. #define SDMMC_CMD_SEND_CID                                      10U   /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
  184. #define SDMMC_CMD_READ_DAT_UNTIL_STOP                           11U   /*!< SD card doesn't support it.                                                              */
  185. #define SDMMC_CMD_STOP_TRANSMISSION                             12U   /*!< Forces the card to stop transmission.                                                    */
  186. #define SDMMC_CMD_SEND_STATUS                                   13U   /*!< Addressed card sends its status register.                                                */
  187. #define SDMMC_CMD_HS_BUSTEST_READ                               14U   /*!< Reserved                                                                                 */
  188. #define SDMMC_CMD_GO_INACTIVE_STATE                             15U   /*!< Sends an addressed card into the inactive state.                                         */
  189. #define SDMMC_CMD_SET_BLOCKLEN                                  16U   /*!< Sets the block length (in bytes for SDSC) for all following block commands
  190.                                                                            (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
  191.                                                                            for SDHS and SDXC.                                                                       */
  192. #define SDMMC_CMD_READ_SINGLE_BLOCK                             17U   /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
  193.                                                                            fixed 512 bytes in case of SDHC and SDXC.                                                */
  194. #define SDMMC_CMD_READ_MULT_BLOCK                               18U   /*!< Continuously transfers data blocks from card to host until interrupted by
  195.                                                                            STOP_TRANSMISSION command.                                                               */
  196. #define SDMMC_CMD_HS_BUSTEST_WRITE                              19U   /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
  197. #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                          20U   /*!< Speed class control command.                                                             */
  198. #define SDMMC_CMD_SET_BLOCK_COUNT                               23U   /*!< Specify block count for CMD18 and CMD25.                                                 */
  199. #define SDMMC_CMD_WRITE_SINGLE_BLOCK                            24U   /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
  200.                                                                            fixed 512 bytes in case of SDHC and SDXC.                                                */
  201. #define SDMMC_CMD_WRITE_MULT_BLOCK                              25U   /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
  202. #define SDMMC_CMD_PROG_CID                                      26U   /*!< Reserved for manufacturers.                                                              */
  203. #define SDMMC_CMD_PROG_CSD                                      27U   /*!< Programming of the programmable bits of the CSD.                                         */
  204. #define SDMMC_CMD_SET_WRITE_PROT                                28U   /*!< Sets the write protection bit of the addressed group.                                    */
  205. #define SDMMC_CMD_CLR_WRITE_PROT                                29U   /*!< Clears the write protection bit of the addressed group.                                  */
  206. #define SDMMC_CMD_SEND_WRITE_PROT                               30U   /*!< Asks the card to send the status of the write protection bits.                           */
  207. #define SDMMC_CMD_SD_ERASE_GRP_START                            32U   /*!< Sets the address of the first write block to be erased. (For SD card only).              */
  208. #define SDMMC_CMD_SD_ERASE_GRP_END                              33U   /*!< Sets the address of the last write block of the continuous range to be erased.           */
  209. #define SDMMC_CMD_ERASE_GRP_START                               35U   /*!< Sets the address of the first write block to be erased. Reserved for each command
  210.                                                                            system set by switch function command (CMD6).                                            */
  211. #define SDMMC_CMD_ERASE_GRP_END                                 36U   /*!< Sets the address of the last write block of the continuous range to be erased.
  212.                                                                            Reserved for each command system set by switch function command (CMD6).                  */
  213. #define SDMMC_CMD_ERASE                                         38U   /*!< Reserved for SD security applications.                                                   */
  214. #define SDMMC_CMD_FAST_IO                                       39U   /*!< SD card doesn't support it (Reserved).                                                   */
  215. #define SDMMC_CMD_GO_IRQ_STATE                                  40U   /*!< SD card doesn't support it (Reserved).                                                   */
  216. #define SDMMC_CMD_LOCK_UNLOCK                                   42U   /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
  217.                                                                            the SET_BLOCK_LEN command.                                                               */
  218. #define SDMMC_CMD_APP_CMD                                       55U   /*!< Indicates to the card that the next command is an application specific command rather
  219.                                                                            than a standard command.                                                                 */
  220. #define SDMMC_CMD_GEN_CMD                                       56U   /*!< Used either to transfer a data block to the card or to get a data block from the card
  221.                                                                            for general purpose/application specific commands.                                       */
  222. #define SDMMC_CMD_NO_CMD                                        64U   /*!< No command                                                                               */
  223.  
  224. /**
  225.   * @brief Following commands are SD Card Specific commands.
  226.   *        SDMMC_APP_CMD should be sent before sending these commands.
  227.   */
  228. #define SDMMC_CMD_APP_SD_SET_BUSWIDTH                           6U    /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
  229.                                                                             widths are given in SCR register.                                                       */
  230. #define SDMMC_CMD_SD_APP_STATUS                                 13U   /*!< (ACMD13) Sends the SD status.                                                            */
  231. #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS                  22U   /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
  232.                                                                            32bit+CRC data block.                                                                    */
  233. #define SDMMC_CMD_SD_APP_OP_COND                                41U   /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
  234.                                                                            send its operating condition register (OCR) content in the response on the CMD line.     */
  235. #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT                    42U   /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */
  236. #define SDMMC_CMD_SD_APP_SEND_SCR                               51U   /*!< Reads the SD Configuration Register (SCR).                                               */
  237. #define SDMMC_CMD_SDMMC_RW_DIRECT                               52U   /*!< For SD I/O card only, reserved for security specification.                               */
  238. #define SDMMC_CMD_SDMMC_RW_EXTENDED                             53U   /*!< For SD I/O card only, reserved for security specification.                               */
  239.  
  240. /**
  241.   * @brief Following commands are SD Card Specific security commands.
  242.   *        SDMMC_CMD_APP_CMD should be sent before sending these commands.
  243.   */
  244. #define SDMMC_CMD_SD_APP_GET_MKB                                43U
  245. #define SDMMC_CMD_SD_APP_GET_MID                                44U
  246. #define SDMMC_CMD_SD_APP_SET_CER_RN1                            45U
  247. #define SDMMC_CMD_SD_APP_GET_CER_RN2                            46U
  248. #define SDMMC_CMD_SD_APP_SET_CER_RES2                           47U
  249. #define SDMMC_CMD_SD_APP_GET_CER_RES1                           48U
  250. #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK             18U
  251. #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK            25U
  252. #define SDMMC_CMD_SD_APP_SECURE_ERASE                           38U
  253. #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA                     49U
  254. #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB                       48U
  255.  
  256. /**
  257.   * @brief  Masks for errors Card Status R1 (OCR Register)
  258.   */
  259. #define SDMMC_OCR_ADDR_OUT_OF_RANGE                   0x80000000U
  260. #define SDMMC_OCR_ADDR_MISALIGNED                     0x40000000U
  261. #define SDMMC_OCR_BLOCK_LEN_ERR                       0x20000000U
  262. #define SDMMC_OCR_ERASE_SEQ_ERR                       0x10000000U
  263. #define SDMMC_OCR_BAD_ERASE_PARAM                     0x08000000U
  264. #define SDMMC_OCR_WRITE_PROT_VIOLATION                0x04000000U
  265. #define SDMMC_OCR_LOCK_UNLOCK_FAILED                  0x01000000U
  266. #define SDMMC_OCR_COM_CRC_FAILED                      0x00800000U
  267. #define SDMMC_OCR_ILLEGAL_CMD                         0x00400000U
  268. #define SDMMC_OCR_CARD_ECC_FAILED                     0x00200000U
  269. #define SDMMC_OCR_CC_ERROR                            0x00100000U
  270. #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR               0x00080000U
  271. #define SDMMC_OCR_STREAM_READ_UNDERRUN                0x00040000U
  272. #define SDMMC_OCR_STREAM_WRITE_OVERRUN                0x00020000U
  273. #define SDMMC_OCR_CID_CSD_OVERWRITE                   0x00010000U
  274. #define SDMMC_OCR_WP_ERASE_SKIP                       0x00008000U
  275. #define SDMMC_OCR_CARD_ECC_DISABLED                   0x00004000U
  276. #define SDMMC_OCR_ERASE_RESET                         0x00002000U
  277. #define SDMMC_OCR_AKE_SEQ_ERROR                       0x00000008U
  278. #define SDMMC_OCR_ERRORBITS                           0xFDFFE008U
  279.  
  280. /**
  281.   * @brief  Masks for R6 Response
  282.   */
  283. #define SDMMC_R6_GENERAL_UNKNOWN_ERROR                0x00002000U
  284. #define SDMMC_R6_ILLEGAL_CMD                          0x00004000U
  285. #define SDMMC_R6_COM_CRC_FAILED                       0x00008000U
  286.  
  287. #define SDMMC_VOLTAGE_WINDOW_SD                       0x80100000U
  288. #define SDMMC_HIGH_CAPACITY                           0x40000000U
  289. #define SDMMC_STD_CAPACITY                            0x00000000U
  290. #define SDMMC_CHECK_PATTERN                           0x000001AAU
  291. #define SD_SWITCH_1_8V_CAPACITY                       0x01000000U
  292.  
  293. #define SDMMC_MAX_VOLT_TRIAL                          0x0000FFFFU
  294.  
  295. #define SDMMC_MAX_TRIAL                               0x0000FFFFU
  296.  
  297. #define SDMMC_ALLZERO                                 0x00000000U
  298.  
  299. #define SDMMC_WIDE_BUS_SUPPORT                        0x00040000U
  300. #define SDMMC_SINGLE_BUS_SUPPORT                      0x00010000U
  301. #define SDMMC_CARD_LOCKED                             0x02000000U
  302.  
  303. #ifndef SDMMC_DATATIMEOUT
  304. #define SDMMC_DATATIMEOUT                             0xFFFFFFFFU
  305. #endif /* SDMMC_DATATIMEOUT */
  306.  
  307. #define SDMMC_0TO7BITS                                0x000000FFU
  308. #define SDMMC_8TO15BITS                               0x0000FF00U
  309. #define SDMMC_16TO23BITS                              0x00FF0000U
  310. #define SDMMC_24TO31BITS                              0xFF000000U
  311. #define SDMMC_MAX_DATA_LENGTH                         0x01FFFFFFU
  312.  
  313. #define SDMMC_HALFFIFO                                0x00000008U
  314. #define SDMMC_HALFFIFOBYTES                           0x00000020U
  315.  
  316. /**
  317.   * @brief  Command Class supported
  318.   */
  319. #define SDIO_CCCC_ERASE                       0x00000020U
  320.  
  321. #define SDIO_CMDTIMEOUT                       5000U         /* Command send and response timeout */
  322. #define SDIO_MAXERASETIMEOUT                  63000U        /* Max erase Timeout 63 s            */
  323. #define SDIO_STOPTRANSFERTIMEOUT              100000000U    /* Timeout for STOP TRANSMISSION command */
  324.  
  325. /** @defgroup SDIO_LL_Clock_Edge Clock Edge
  326.   * @{
  327.   */
  328. #define SDIO_CLOCK_EDGE_RISING               0x00000000U
  329. #define SDIO_CLOCK_EDGE_FALLING              SDIO_CLKCR_NEGEDGE
  330.  
  331. #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
  332.                                           ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
  333. /**
  334.   * @}
  335.   */
  336.  
  337. /** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
  338.   * @{
  339.   */
  340. #define SDIO_CLOCK_BYPASS_DISABLE             0x00000000U
  341. #define SDIO_CLOCK_BYPASS_ENABLE              SDIO_CLKCR_BYPASS  
  342.  
  343. #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
  344.                                               ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
  345. /**
  346.   * @}
  347.   */
  348.  
  349. /** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
  350.   * @{
  351.   */
  352. #define SDIO_CLOCK_POWER_SAVE_DISABLE         0x00000000U
  353. #define SDIO_CLOCK_POWER_SAVE_ENABLE          SDIO_CLKCR_PWRSAV
  354.  
  355. #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
  356.                                                 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
  357. /**
  358.   * @}
  359.   */
  360.  
  361. /** @defgroup SDIO_LL_Bus_Wide Bus Width
  362.   * @{
  363.   */
  364. #define SDIO_BUS_WIDE_1B                      0x00000000U
  365. #define SDIO_BUS_WIDE_4B                      SDIO_CLKCR_WIDBUS_0
  366. #define SDIO_BUS_WIDE_8B                      SDIO_CLKCR_WIDBUS_1
  367.  
  368. #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
  369.                                         ((WIDE) == SDIO_BUS_WIDE_4B) || \
  370.                                         ((WIDE) == SDIO_BUS_WIDE_8B))
  371. /**
  372.   * @}
  373.   */
  374.  
  375. /** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
  376.   * @{
  377.   */
  378. #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    0x00000000U
  379. #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     SDIO_CLKCR_HWFC_EN
  380.  
  381. #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
  382.                                                         ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
  383. /**
  384.   * @}
  385.   */
  386.  
  387. /** @defgroup SDIO_LL_Clock_Division Clock Division
  388.   * @{
  389.   */
  390. #define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFFU)
  391. /**
  392.   * @}
  393.   */  
  394.    
  395. /** @defgroup SDIO_LL_Command_Index Command Index
  396.   * @{
  397.   */
  398. #define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40U)
  399. /**
  400.   * @}
  401.   */
  402.  
  403. /** @defgroup SDIO_LL_Response_Type Response Type
  404.   * @{
  405.   */
  406. #define SDIO_RESPONSE_NO                    0x00000000U
  407. #define SDIO_RESPONSE_SHORT                 SDIO_CMD_WAITRESP_0
  408. #define SDIO_RESPONSE_LONG                  SDIO_CMD_WAITRESP
  409.  
  410. #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO)    || \
  411.                                             ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
  412.                                             ((RESPONSE) == SDIO_RESPONSE_LONG))
  413. /**
  414.   * @}
  415.   */
  416.  
  417. /** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
  418.   * @{
  419.   */
  420. #define SDIO_WAIT_NO                        0x00000000U
  421. #define SDIO_WAIT_IT                        SDIO_CMD_WAITINT
  422. #define SDIO_WAIT_PEND                      SDIO_CMD_WAITPEND
  423.  
  424. #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
  425.                                     ((WAIT) == SDIO_WAIT_IT) || \
  426.                                     ((WAIT) == SDIO_WAIT_PEND))
  427. /**
  428.   * @}
  429.   */
  430.  
  431. /** @defgroup SDIO_LL_CPSM_State CPSM State
  432.   * @{
  433.   */
  434. #define SDIO_CPSM_DISABLE                   0x00000000U
  435. #define SDIO_CPSM_ENABLE                    SDIO_CMD_CPSMEN
  436.  
  437. #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
  438.                                     ((CPSM) == SDIO_CPSM_ENABLE))
  439. /**
  440.   * @}
  441.   */  
  442.  
  443. /** @defgroup SDIO_LL_Response_Registers Response Register
  444.   * @{
  445.   */
  446. #define SDIO_RESP1                          0x00000000U
  447. #define SDIO_RESP2                          0x00000004U
  448. #define SDIO_RESP3                          0x00000008U
  449. #define SDIO_RESP4                          0x0000000CU
  450.  
  451. #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
  452.                                     ((RESP) == SDIO_RESP2) || \
  453.                                     ((RESP) == SDIO_RESP3) || \
  454.                                     ((RESP) == SDIO_RESP4))
  455. /**
  456.   * @}
  457.   */
  458.  
  459. /** @defgroup SDIO_LL_Data_Length Data Length
  460.   * @{
  461.   */
  462. #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
  463. /**
  464.   * @}
  465.   */
  466.  
  467. /** @defgroup SDIO_LL_Data_Block_Size  Data Block Size
  468.   * @{
  469.   */
  470. #define SDIO_DATABLOCK_SIZE_1B               0x00000000U
  471. #define SDIO_DATABLOCK_SIZE_2B               SDIO_DCTRL_DBLOCKSIZE_0
  472. #define SDIO_DATABLOCK_SIZE_4B               SDIO_DCTRL_DBLOCKSIZE_1
  473. #define SDIO_DATABLOCK_SIZE_8B               (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
  474. #define SDIO_DATABLOCK_SIZE_16B              SDIO_DCTRL_DBLOCKSIZE_2
  475. #define SDIO_DATABLOCK_SIZE_32B              (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)
  476. #define SDIO_DATABLOCK_SIZE_64B              (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
  477. #define SDIO_DATABLOCK_SIZE_128B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
  478. #define SDIO_DATABLOCK_SIZE_256B             SDIO_DCTRL_DBLOCKSIZE_3
  479. #define SDIO_DATABLOCK_SIZE_512B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)
  480. #define SDIO_DATABLOCK_SIZE_1024B            (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
  481. #define SDIO_DATABLOCK_SIZE_2048B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
  482. #define SDIO_DATABLOCK_SIZE_4096B            (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
  483. #define SDIO_DATABLOCK_SIZE_8192B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
  484. #define SDIO_DATABLOCK_SIZE_16384B           (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
  485.  
  486. #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \
  487.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
  488.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \
  489.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \
  490.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \
  491.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \
  492.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \
  493.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \
  494.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \
  495.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \
  496.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
  497.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
  498.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
  499.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
  500.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
  501. /**
  502.   * @}
  503.   */
  504.  
  505. /** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
  506.   * @{
  507.   */
  508. #define SDIO_TRANSFER_DIR_TO_CARD            0x00000000U
  509. #define SDIO_TRANSFER_DIR_TO_SDIO    SDIO_DCTRL_DTDIR
  510.  
  511. #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
  512.                                            ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
  513. /**
  514.   * @}
  515.   */
  516.  
  517. /** @defgroup SDIO_LL_Transfer_Type Transfer Type
  518.   * @{
  519.   */
  520. #define SDIO_TRANSFER_MODE_BLOCK             0x00000000U
  521. #define SDIO_TRANSFER_MODE_STREAM            SDIO_DCTRL_DTMODE
  522.  
  523. #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
  524.                                              ((MODE) == SDIO_TRANSFER_MODE_STREAM))
  525. /**
  526.   * @}
  527.   */
  528.  
  529. /** @defgroup SDIO_LL_DPSM_State DPSM State
  530.   * @{
  531.   */
  532. #define SDIO_DPSM_DISABLE                    0x00000000U
  533. #define SDIO_DPSM_ENABLE                     SDIO_DCTRL_DTEN
  534.  
  535. #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
  536.                                     ((DPSM) == SDIO_DPSM_ENABLE))
  537. /**
  538.   * @}
  539.   */
  540.  
  541. /** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
  542.   * @{
  543.   */
  544. #define SDIO_READ_WAIT_MODE_DATA2                0x00000000U
  545. #define SDIO_READ_WAIT_MODE_CLK                  (SDIO_DCTRL_RWMOD)
  546.  
  547. #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
  548.                                              ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
  549. /**
  550.   * @}
  551.   */  
  552.  
  553. /** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
  554.   * @{
  555.   */
  556. #define SDIO_IT_CCRCFAIL                    SDIO_MASK_CCRCFAILIE
  557. #define SDIO_IT_DCRCFAIL                    SDIO_MASK_DCRCFAILIE
  558. #define SDIO_IT_CTIMEOUT                    SDIO_MASK_CTIMEOUTIE
  559. #define SDIO_IT_DTIMEOUT                    SDIO_MASK_DTIMEOUTIE
  560. #define SDIO_IT_TXUNDERR                    SDIO_MASK_TXUNDERRIE
  561. #define SDIO_IT_RXOVERR                     SDIO_MASK_RXOVERRIE
  562. #define SDIO_IT_CMDREND                     SDIO_MASK_CMDRENDIE
  563. #define SDIO_IT_CMDSENT                     SDIO_MASK_CMDSENTIE
  564. #define SDIO_IT_DATAEND                     SDIO_MASK_DATAENDIE
  565. #define SDIO_IT_STBITERR                    SDIO_MASK_STBITERRIE
  566. #define SDIO_IT_DBCKEND                     SDIO_MASK_DBCKENDIE
  567. #define SDIO_IT_CMDACT                      SDIO_MASK_CMDACTIE
  568. #define SDIO_IT_TXACT                       SDIO_MASK_TXACTIE
  569. #define SDIO_IT_RXACT                       SDIO_MASK_RXACTIE
  570. #define SDIO_IT_TXFIFOHE                    SDIO_MASK_TXFIFOHEIE
  571. #define SDIO_IT_RXFIFOHF                    SDIO_MASK_RXFIFOHFIE
  572. #define SDIO_IT_TXFIFOF                     SDIO_MASK_TXFIFOFIE
  573. #define SDIO_IT_RXFIFOF                     SDIO_MASK_RXFIFOFIE
  574. #define SDIO_IT_TXFIFOE                     SDIO_MASK_TXFIFOEIE
  575. #define SDIO_IT_RXFIFOE                     SDIO_MASK_RXFIFOEIE
  576. #define SDIO_IT_TXDAVL                      SDIO_MASK_TXDAVLIE
  577. #define SDIO_IT_RXDAVL                      SDIO_MASK_RXDAVLIE
  578. #define SDIO_IT_SDIOIT                      SDIO_MASK_SDIOITIE
  579. #define SDIO_IT_CEATAEND                    SDIO_MASK_CEATAENDIE
  580. /**
  581.   * @}
  582.   */
  583.  
  584. /** @defgroup SDIO_LL_Flags Flags
  585.   * @{
  586.   */
  587. #define SDIO_FLAG_CCRCFAIL                  SDIO_STA_CCRCFAIL
  588. #define SDIO_FLAG_DCRCFAIL                  SDIO_STA_DCRCFAIL
  589. #define SDIO_FLAG_CTIMEOUT                  SDIO_STA_CTIMEOUT
  590. #define SDIO_FLAG_DTIMEOUT                  SDIO_STA_DTIMEOUT
  591. #define SDIO_FLAG_TXUNDERR                  SDIO_STA_TXUNDERR
  592. #define SDIO_FLAG_RXOVERR                   SDIO_STA_RXOVERR
  593. #define SDIO_FLAG_CMDREND                   SDIO_STA_CMDREND
  594. #define SDIO_FLAG_CMDSENT                   SDIO_STA_CMDSENT
  595. #define SDIO_FLAG_DATAEND                   SDIO_STA_DATAEND
  596. #define SDIO_FLAG_STBITERR                  SDIO_STA_STBITERR
  597. #define SDIO_FLAG_DBCKEND                   SDIO_STA_DBCKEND
  598. #define SDIO_FLAG_CMDACT                    SDIO_STA_CMDACT
  599. #define SDIO_FLAG_TXACT                     SDIO_STA_TXACT
  600. #define SDIO_FLAG_RXACT                     SDIO_STA_RXACT
  601. #define SDIO_FLAG_TXFIFOHE                  SDIO_STA_TXFIFOHE
  602. #define SDIO_FLAG_RXFIFOHF                  SDIO_STA_RXFIFOHF
  603. #define SDIO_FLAG_TXFIFOF                   SDIO_STA_TXFIFOF
  604. #define SDIO_FLAG_RXFIFOF                   SDIO_STA_RXFIFOF
  605. #define SDIO_FLAG_TXFIFOE                   SDIO_STA_TXFIFOE
  606. #define SDIO_FLAG_RXFIFOE                   SDIO_STA_RXFIFOE
  607. #define SDIO_FLAG_TXDAVL                    SDIO_STA_TXDAVL
  608. #define SDIO_FLAG_RXDAVL                    SDIO_STA_RXDAVL
  609. #define SDIO_FLAG_SDIOIT                    SDIO_STA_SDIOIT
  610. #define SDIO_FLAG_CEATAEND                  SDIO_STA_CEATAEND
  611. #define SDIO_STATIC_FLAGS                   ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
  612.                                                          SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR  |\
  613.                                                          SDIO_FLAG_CMDREND  | SDIO_FLAG_CMDSENT  | SDIO_FLAG_DATAEND  |\
  614.                                                          SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT))  
  615.  
  616. #define SDIO_STATIC_CMD_FLAGS               ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\
  617.                                                          SDIO_FLAG_CMDSENT))
  618.  
  619. #define SDIO_STATIC_DATA_FLAGS              ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\
  620.                                                          SDIO_FLAG_RXOVERR  | SDIO_FLAG_DATAEND  | SDIO_FLAG_DBCKEND))
  621. /**
  622.   * @}
  623.   */
  624.  
  625. /**
  626.   * @}
  627.   */
  628.  
  629. /* Exported macro ------------------------------------------------------------*/
  630. /** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
  631.   * @{
  632.   */
  633.  
  634. /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
  635.   * @{
  636.   */
  637. /* ------------ SDIO registers bit address in the alias region -------------- */
  638. #define SDIO_OFFSET               (SDIO_BASE - PERIPH_BASE)
  639.  
  640. /* --- CLKCR Register ---*/
  641. /* Alias word address of CLKEN bit */
  642. #define CLKCR_OFFSET              (SDIO_OFFSET + 0x04U)
  643. #define CLKEN_BITNUMBER           0x08U
  644. #define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
  645.  
  646. /* --- CMD Register ---*/
  647. /* Alias word address of SDIOSUSPEND bit */
  648. #define CMD_OFFSET                (SDIO_OFFSET + 0x0CU)
  649. #define SDIOSUSPEND_BITNUMBER     0x0BU
  650. #define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
  651.  
  652. /* Alias word address of ENCMDCOMPL bit */
  653. #define ENCMDCOMPL_BITNUMBER      0x0CU
  654. #define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
  655.  
  656. /* Alias word address of NIEN bit */
  657. #define NIEN_BITNUMBER            0x0DU
  658. #define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
  659.  
  660. /* Alias word address of ATACMD bit */
  661. #define ATACMD_BITNUMBER          0x0EU
  662. #define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
  663.  
  664. /* --- DCTRL Register ---*/
  665. /* Alias word address of DMAEN bit */
  666. #define DCTRL_OFFSET              (SDIO_OFFSET + 0x2CU)
  667. #define DMAEN_BITNUMBER           0x03U
  668. #define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
  669.  
  670. /* Alias word address of RWSTART bit */
  671. #define RWSTART_BITNUMBER         0x08U
  672. #define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
  673.  
  674. /* Alias word address of RWSTOP bit */
  675. #define RWSTOP_BITNUMBER          0x09U
  676. #define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
  677.  
  678. /* Alias word address of RWMOD bit */
  679. #define RWMOD_BITNUMBER           0x0AU
  680. #define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
  681.  
  682. /* Alias word address of SDIOEN bit */
  683. #define SDIOEN_BITNUMBER          0x0BU
  684. #define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
  685. /**
  686.   * @}
  687.   */
  688.  
  689. /** @defgroup SDIO_LL_Register Bits And Addresses Definitions
  690.   * @brief SDIO_LL registers bit address in the alias region
  691.   * @{
  692.   */
  693. /* ---------------------- SDIO registers bit mask --------------------------- */
  694. /* --- CLKCR Register ---*/
  695. /* CLKCR register clear mask */
  696. #define CLKCR_CLEAR_MASK         ((uint32_t)(SDIO_CLKCR_CLKDIV  | SDIO_CLKCR_PWRSAV |\
  697.                                              SDIO_CLKCR_BYPASS  | SDIO_CLKCR_WIDBUS |\
  698.                                              SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
  699.  
  700. /* --- DCTRL Register ---*/
  701. /* SDIO DCTRL Clear Mask */
  702. #define DCTRL_CLEAR_MASK         ((uint32_t)(SDIO_DCTRL_DTEN    | SDIO_DCTRL_DTDIR |\
  703.                                              SDIO_DCTRL_DTMODE  | SDIO_DCTRL_DBLOCKSIZE))
  704.  
  705. /* --- CMD Register ---*/
  706. /* CMD Register clear mask */
  707. #define CMD_CLEAR_MASK           ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
  708.                                              SDIO_CMD_WAITINT  | SDIO_CMD_WAITPEND |\
  709.                                              SDIO_CMD_CPSMEN   | SDIO_CMD_SDIOSUSPEND))
  710.  
  711. /* SDIO Initialization Frequency (400KHz max) */
  712. #define SDIO_INIT_CLK_DIV     ((uint8_t)0x76)    /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
  713.  
  714. /* SDIO Data Transfer Frequency (25MHz max) */
  715. #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4)
  716. /**
  717.   * @}
  718.   */
  719.  
  720. /** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
  721.  *  @brief macros to handle interrupts and specific clock configurations
  722.  * @{
  723.  */
  724.  
  725. /**
  726.   * @brief  Enable the SDIO device.
  727.   * @param  __INSTANCE__: SDIO Instance  
  728.   * @retval None
  729.   */
  730. #define __SDIO_ENABLE(__INSTANCE__)  (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
  731.  
  732. /**
  733.   * @brief  Disable the SDIO device.
  734.   * @param  __INSTANCE__: SDIO Instance  
  735.   * @retval None
  736.   */
  737. #define __SDIO_DISABLE(__INSTANCE__)  (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
  738.  
  739. /**
  740.   * @brief  Enable the SDIO DMA transfer.
  741.   * @param  __INSTANCE__: SDIO Instance  
  742.   * @retval None
  743.   */
  744. #define __SDIO_DMA_ENABLE(__INSTANCE__)  (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
  745.  
  746. /**
  747.   * @brief  Disable the SDIO DMA transfer.
  748.   * @param  __INSTANCE__: SDIO Instance  
  749.   * @retval None
  750.   */
  751. #define __SDIO_DMA_DISABLE(__INSTANCE__)  (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
  752.  
  753. /**
  754.   * @brief  Enable the SDIO device interrupt.
  755.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  756.   * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
  757.   *         This parameter can be one or a combination of the following values:
  758.   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  759.   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  760.   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
  761.   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
  762.   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  763.   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
  764.   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
  765.   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
  766.   *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
  767.   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
  768.   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
  769.   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
  770.   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
  771.   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  772.   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  773.   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
  774.   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
  775.   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
  776.   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
  777.   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
  778.   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
  779.   *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
  780.   * @retval None
  781.   */
  782. #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
  783.  
  784. /**
  785.   * @brief  Disable the SDIO device interrupt.
  786.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  787.   * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
  788.   *          This parameter can be one or a combination of the following values:
  789.   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  790.   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  791.   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
  792.   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
  793.   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  794.   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
  795.   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
  796.   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
  797.   *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
  798.   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
  799.   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
  800.   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
  801.   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
  802.   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  803.   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  804.   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
  805.   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
  806.   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
  807.   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
  808.   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
  809.   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
  810.   *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt  
  811.   * @retval None
  812.   */
  813. #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
  814.  
  815. /**
  816.   * @brief  Checks whether the specified SDIO flag is set or not.
  817.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  818.   * @param  __FLAG__: specifies the flag to check.
  819.   *          This parameter can be one of the following values:
  820.   *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
  821.   *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  822.   *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
  823.   *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
  824.   *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
  825.   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
  826.   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
  827.   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
  828.   *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
  829.   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
  830.   *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
  831.   *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
  832.   *            @arg SDIO_FLAG_RXACT:    Data receive in progress
  833.   *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
  834.   *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
  835.   *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
  836.   *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
  837.   *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
  838.   *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
  839.   *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
  840.   *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
  841.   *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
  842.   * @retval The new state of SDIO_FLAG (SET or RESET).
  843.   */
  844. #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
  845.  
  846.  
  847. /**
  848.   * @brief  Clears the SDIO pending flags.
  849.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  850.   * @param  __FLAG__: specifies the flag to clear.  
  851.   *          This parameter can be one or a combination of the following values:
  852.   *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
  853.   *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  854.   *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
  855.   *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
  856.   *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
  857.   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
  858.   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
  859.   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
  860.   *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
  861.   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
  862.   *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
  863.   * @retval None
  864.   */
  865. #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))
  866.  
  867. /**
  868.   * @brief  Checks whether the specified SDIO interrupt has occurred or not.
  869.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  870.   * @param  __INTERRUPT__: specifies the SDIO interrupt source to check.
  871.   *          This parameter can be one of the following values:
  872.   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  873.   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  874.   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
  875.   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
  876.   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  877.   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
  878.   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
  879.   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
  880.   *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
  881.   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
  882.   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
  883.   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
  884.   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
  885.   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  886.   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  887.   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
  888.   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
  889.   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
  890.   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
  891.   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
  892.   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
  893.   *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
  894.   * @retval The new state of SDIO_IT (SET or RESET).
  895.   */
  896. #define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
  897.  
  898. /**
  899.   * @brief  Clears the SDIO's interrupt pending bits.
  900.   * @param  __INSTANCE__ : Pointer to SDIO register base
  901.   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
  902.   *          This parameter can be one or a combination of the following values:
  903.   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  904.   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  905.   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
  906.   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
  907.   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  908.   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
  909.   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
  910.   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
  911.   *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
  912.   *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
  913.   * @retval None
  914.   */
  915. #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))
  916.  
  917. /**
  918.   * @brief  Enable Start the SD I/O Read Wait operation.
  919.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  920.   * @retval None
  921.   */
  922. #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
  923.  
  924. /**
  925.   * @brief  Disable Start the SD I/O Read Wait operations.
  926.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  927.   * @retval None
  928.   */
  929. #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
  930.  
  931. /**
  932.   * @brief  Enable Start the SD I/O Read Wait operation.
  933.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  934.   * @retval None
  935.   */
  936. #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
  937.  
  938. /**
  939.   * @brief  Disable Stop the SD I/O Read Wait operations.
  940.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  941.   * @retval None
  942.   */
  943. #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
  944.  
  945. /**
  946.   * @brief  Enable the SD I/O Mode Operation.
  947.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  948.   * @retval None
  949.   */
  950. #define __SDIO_OPERATION_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
  951.  
  952. /**
  953.   * @brief  Disable the SD I/O Mode Operation.
  954.   * @param  __INSTANCE__ : Pointer to SDIO register base
  955.   * @retval None
  956.   */
  957. #define __SDIO_OPERATION_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
  958.  
  959. /**
  960.   * @brief  Enable the SD I/O Suspend command sending.
  961.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  962.   * @retval None
  963.   */
  964. #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
  965.  
  966. /**
  967.   * @brief  Disable the SD I/O Suspend command sending.
  968.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  969.   * @retval None
  970.   */
  971. #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
  972.  
  973. /**
  974.   * @brief  Enable the command completion signal.
  975.   * @retval None
  976.   */    
  977. #define __SDIO_CEATA_CMD_COMPLETION_ENABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
  978.  
  979. /**
  980.   * @brief  Disable the command completion signal.
  981.   * @retval None
  982.   */  
  983. #define __SDIO_CEATA_CMD_COMPLETION_DISABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
  984.  
  985. /**
  986.   * @brief  Enable the CE-ATA interrupt.
  987.   * @retval None
  988.   */    
  989. #define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
  990.  
  991. /**
  992.   * @brief  Disable the CE-ATA interrupt.
  993.   * @retval None
  994.   */  
  995. #define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
  996.  
  997. /**
  998.   * @brief  Enable send CE-ATA command (CMD61).
  999.   * @retval None
  1000.   */  
  1001. #define __SDIO_CEATA_SENDCMD_ENABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
  1002.  
  1003. /**
  1004.   * @brief  Disable send CE-ATA command (CMD61).
  1005.   * @retval None
  1006.   */  
  1007. #define __SDIO_CEATA_SENDCMD_DISABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
  1008.    
  1009. /**
  1010.   * @}
  1011.   */
  1012.  
  1013. /**
  1014.   * @}
  1015.   */  
  1016.  
  1017. /* Exported functions --------------------------------------------------------*/
  1018. /** @addtogroup SDMMC_LL_Exported_Functions
  1019.   * @{
  1020.   */
  1021.  
  1022. /* Initialization/de-initialization functions  **********************************/
  1023. /** @addtogroup HAL_SDMMC_LL_Group1
  1024.   * @{
  1025.   */
  1026. HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
  1027. /**
  1028.   * @}
  1029.   */
  1030.  
  1031. /* I/O operation functions  *****************************************************/
  1032. /** @addtogroup HAL_SDMMC_LL_Group2
  1033.   * @{
  1034.   */
  1035. uint32_t          SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
  1036. HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
  1037. /**
  1038.   * @}
  1039.   */
  1040.  
  1041. /* Peripheral Control functions  ************************************************/
  1042. /** @addtogroup HAL_SDMMC_LL_Group3
  1043.   * @{
  1044.   */
  1045. HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
  1046. HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
  1047. uint32_t          SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
  1048.  
  1049. /* Command path state machine (CPSM) management functions */
  1050. HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);
  1051. uint8_t           SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
  1052. uint32_t          SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
  1053.  
  1054. /* Data path state machine (DPSM) management functions */
  1055. HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
  1056. uint32_t          SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
  1057. uint32_t          SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
  1058.  
  1059. /* SDMMC Cards mode management functions */
  1060. HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
  1061. /**
  1062.   * @}
  1063.   */
  1064.  
  1065. /* SDMMC Commands management functions */
  1066. /** @addtogroup HAL_SDMMC_LL_Group4
  1067.   * @{
  1068.   */
  1069. uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
  1070. uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
  1071. uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
  1072. uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
  1073. uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
  1074. uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
  1075. uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
  1076. uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
  1077. uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
  1078. uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
  1079. uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
  1080. uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
  1081. uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
  1082. uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
  1083. uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
  1084. uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
  1085. uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
  1086. uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
  1087. uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
  1088. uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
  1089. uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
  1090. uint32_t SDMMC_CmdSetRelAddMmc(SDIO_TypeDef *SDIOx, uint16_t RCA);
  1091. uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
  1092. uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
  1093. uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
  1094. uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
  1095. uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
  1096. /**
  1097.   * @}
  1098.   */
  1099.  
  1100. /* SDMMC Responses management functions *****************************************/
  1101. /** @addtogroup HAL_SDMMC_LL_Group5
  1102.   * @{
  1103.   */
  1104. uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout);
  1105. uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx);
  1106. uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx);
  1107. uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA);
  1108. uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx);
  1109. /**
  1110.   * @}
  1111.   */
  1112.  
  1113. /**
  1114.   * @}
  1115.   */
  1116.  
  1117. /**
  1118.   * @}
  1119.   */
  1120.  
  1121. /**
  1122.   * @}
  1123.   */
  1124.  
  1125. #endif /* SDIO */
  1126.  
  1127. #ifdef __cplusplus
  1128. }
  1129. #endif
  1130.  
  1131. #endif /* STM32F1xx_LL_SDMMC_H */
  1132.