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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_sdmmc.h
  4.   * @author  MCD Application Team
  5.   * @version V1.0.1
  6.   * @date    31-July-2015
  7.   * @brief   Header file of low layer SDMMC HAL module.
  8.   ******************************************************************************
  9.   * @attention
  10.   *
  11.   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  12.   *
  13.   * Redistribution and use in source and binary forms, with or without modification,
  14.   * are permitted provided that the following conditions are met:
  15.   *   1. Redistributions of source code must retain the above copyright notice,
  16.   *      this list of conditions and the following disclaimer.
  17.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18.   *      this list of conditions and the following disclaimer in the documentation
  19.   *      and/or other materials provided with the distribution.
  20.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21.   *      may be used to endorse or promote products derived from this software
  22.   *      without specific prior written permission.
  23.   *
  24.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34.   *
  35.   ******************************************************************************
  36.   */
  37.  
  38. /* Define to prevent recursive inclusion -------------------------------------*/
  39. #ifndef __stm32f1xx_LL_SD_H
  40. #define __stm32f1xx_LL_SD_H
  41.  
  42. #if defined(STM32F103xE) || defined(STM32F103xG)
  43.  
  44. #ifdef __cplusplus
  45.  extern "C" {
  46. #endif
  47.  
  48. /* Includes ------------------------------------------------------------------*/
  49. #include "stm32f1xx_hal_def.h"
  50.  
  51. /** @addtogroup STM32F1xx_HAL_Driver
  52.   * @{
  53.   */
  54.  
  55. /** @addtogroup SDMMC_LL
  56.   * @{
  57.   */
  58.  
  59. /* Exported types ------------------------------------------------------------*/
  60. /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
  61.   * @{
  62.   */
  63.  
  64. /**
  65.   * @brief  SDMMC Configuration Structure definition  
  66.   */
  67. typedef struct
  68. {
  69.   uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
  70.                                       This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
  71.  
  72.   uint32_t ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
  73.                                       enabled or disabled.
  74.                                       This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
  75.  
  76.   uint32_t ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
  77.                                       disabled when the bus is idle.
  78.                                       This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
  79.  
  80.   uint32_t BusWide;              /*!< Specifies the SDIO bus width.
  81.                                       This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
  82.  
  83.   uint32_t HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
  84.                                       This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
  85.  
  86.   uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDIO controller.
  87.                                       This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  
  88.  
  89. }SDIO_InitTypeDef;
  90.  
  91.  
  92. /**
  93.   * @brief  SDIO Command Control structure
  94.   */
  95. typedef struct                                                                                            
  96. {
  97.   uint32_t Argument;            /*!< Specifies the SDIO command argument which is sent
  98.                                      to a card as part of a command message. If a command
  99.                                      contains an argument, it must be loaded into this register
  100.                                      before writing the command to the command register.              */
  101.  
  102.   uint32_t CmdIndex;            /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
  103.                                      Max_Data = 64                                                    */
  104.  
  105.   uint32_t Response;            /*!< Specifies the SDIO response type.
  106.                                      This parameter can be a value of @ref SDMMC_LL_Response_Type         */
  107.  
  108.   uint32_t WaitForInterrupt;    /*!< Specifies whether SDIO wait for interrupt request is
  109.                                      enabled or disabled.
  110.                                      This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
  111.  
  112.   uint32_t CPSM;                /*!< Specifies whether SDIO Command path state machine (CPSM)
  113.                                      is enabled or disabled.
  114.                                      This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
  115. }SDIO_CmdInitTypeDef;
  116.  
  117.  
  118. /**
  119.   * @brief  SDIO Data Control structure
  120.   */
  121. typedef struct
  122. {
  123.   uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
  124.  
  125.   uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
  126.  
  127.   uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
  128.                                      This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
  129.  
  130.   uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
  131.                                      is a read or write.
  132.                                      This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
  133.  
  134.   uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
  135.                                      This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
  136.  
  137.   uint32_t DPSM;                /*!< Specifies whether SDIO Data path state machine (DPSM)
  138.                                      is enabled or disabled.
  139.                                      This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
  140. }SDIO_DataInitTypeDef;
  141.  
  142. /**
  143.   * @}
  144.   */
  145.  
  146. /* Exported constants --------------------------------------------------------*/
  147. /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
  148.   * @{
  149.   */
  150.  
  151. /** @defgroup SDMMC_LL_Clock_Edge Clock Edge
  152.   * @{
  153.   */
  154. #define SDIO_CLOCK_EDGE_RISING               ((uint32_t)0x00000000)
  155. #define SDIO_CLOCK_EDGE_FALLING              SDIO_CLKCR_NEGEDGE
  156.  
  157. #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
  158.                                   ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
  159. /**
  160.   * @}
  161.   */
  162.  
  163. /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
  164.   * @{
  165.   */
  166. #define SDIO_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000)
  167. #define SDIO_CLOCK_BYPASS_ENABLE              SDIO_CLKCR_BYPASS  
  168.  
  169. #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
  170.                                       ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
  171. /**
  172.   * @}
  173.   */
  174.  
  175. /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
  176.   * @{
  177.   */
  178. #define SDIO_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000)
  179. #define SDIO_CLOCK_POWER_SAVE_ENABLE          SDIO_CLKCR_PWRSAV
  180.  
  181. #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
  182.                                         ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
  183. /**
  184.   * @}
  185.   */
  186.  
  187. /** @defgroup SDMMC_LL_Bus_Wide Bus Width
  188.   * @{
  189.   */
  190. #define SDIO_BUS_WIDE_1B                      ((uint32_t)0x00000000)
  191. #define SDIO_BUS_WIDE_4B                      SDIO_CLKCR_WIDBUS_0
  192. #define SDIO_BUS_WIDE_8B                      SDIO_CLKCR_WIDBUS_1
  193.  
  194. #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
  195.                                 ((WIDE) == SDIO_BUS_WIDE_4B) || \
  196.                                 ((WIDE) == SDIO_BUS_WIDE_8B))
  197. /**
  198.   * @}
  199.   */
  200.  
  201. /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
  202.   * @{
  203.   */
  204. #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000)
  205. #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     SDIO_CLKCR_HWFC_EN
  206.  
  207. #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
  208.                                                 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
  209. /**
  210.   * @}
  211.   */
  212.  
  213. /** @defgroup SDMMC_LL_Clock_Division Clock Division
  214.   * @{
  215.   */
  216. #define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFF)
  217. /**
  218.   * @}
  219.   */  
  220.    
  221. /** @defgroup SDMMC_LL_Command_Index Command Index
  222.   * @{
  223.   */
  224. #define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
  225. /**
  226.   * @}
  227.   */
  228.  
  229. /** @defgroup SDMMC_LL_Response_Type Response Type
  230.   * @{
  231.   */
  232. #define SDIO_RESPONSE_NO                    ((uint32_t)0x00000000)
  233. #define SDIO_RESPONSE_SHORT                 SDIO_CMD_WAITRESP_0
  234. #define SDIO_RESPONSE_LONG                  SDIO_CMD_WAITRESP
  235.  
  236. #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO)    || \
  237.                                     ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
  238.                                     ((RESPONSE) == SDIO_RESPONSE_LONG))
  239. /**
  240.   * @}
  241.   */
  242.  
  243. /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
  244.   * @{
  245.   */
  246. #define SDIO_WAIT_NO                        ((uint32_t)0x00000000)
  247. #define SDIO_WAIT_IT                        SDIO_CMD_WAITINT
  248. #define SDIO_WAIT_PEND                      SDIO_CMD_WAITPEND
  249.  
  250. #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
  251.                             ((WAIT) == SDIO_WAIT_IT) || \
  252.                             ((WAIT) == SDIO_WAIT_PEND))
  253. /**
  254.   * @}
  255.   */
  256.  
  257. /** @defgroup SDMMC_LL_CPSM_State CPSM State
  258.   * @{
  259.   */
  260. #define SDIO_CPSM_DISABLE                   ((uint32_t)0x00000000)
  261. #define SDIO_CPSM_ENABLE                    SDIO_CMD_CPSMEN
  262.  
  263. #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
  264.                             ((CPSM) == SDIO_CPSM_ENABLE))
  265. /**
  266.   * @}
  267.   */  
  268.  
  269. /** @defgroup SDMMC_LL_Response_Registers Response Register
  270.   * @{
  271.   */
  272. #define SDIO_RESP1                          ((uint32_t)0x00000000)
  273. #define SDIO_RESP2                          ((uint32_t)0x00000004)
  274. #define SDIO_RESP3                          ((uint32_t)0x00000008)
  275. #define SDIO_RESP4                          ((uint32_t)0x0000000C)
  276.  
  277. #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
  278.                             ((RESP) == SDIO_RESP2) || \
  279.                             ((RESP) == SDIO_RESP3) || \
  280.                             ((RESP) == SDIO_RESP4))
  281. /**
  282.   * @}
  283.   */
  284.  
  285. /** @defgroup SDMMC_LL_Data_Length Data Lenght
  286.   * @{
  287.   */
  288. #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
  289. /**
  290.   * @}
  291.   */
  292.  
  293. /** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size
  294.   * @{
  295.   */
  296. #define SDIO_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000)
  297. #define SDIO_DATABLOCK_SIZE_2B               SDIO_DCTRL_DBLOCKSIZE_0
  298. #define SDIO_DATABLOCK_SIZE_4B               SDIO_DCTRL_DBLOCKSIZE_1
  299. #define SDIO_DATABLOCK_SIZE_8B               (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
  300. #define SDIO_DATABLOCK_SIZE_16B              SDIO_DCTRL_DBLOCKSIZE_2
  301. #define SDIO_DATABLOCK_SIZE_32B              (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)
  302. #define SDIO_DATABLOCK_SIZE_64B              (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
  303. #define SDIO_DATABLOCK_SIZE_128B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
  304. #define SDIO_DATABLOCK_SIZE_256B             SDIO_DCTRL_DBLOCKSIZE_3
  305. #define SDIO_DATABLOCK_SIZE_512B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)
  306. #define SDIO_DATABLOCK_SIZE_1024B            (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
  307. #define SDIO_DATABLOCK_SIZE_2048B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
  308. #define SDIO_DATABLOCK_SIZE_4096B            (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
  309. #define SDIO_DATABLOCK_SIZE_8192B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
  310. #define SDIO_DATABLOCK_SIZE_16384B           (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
  311.  
  312. #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \
  313.                                   ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
  314.                                   ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \
  315.                                   ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \
  316.                                   ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \
  317.                                   ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \
  318.                                   ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \
  319.                                   ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \
  320.                                   ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \
  321.                                   ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \
  322.                                   ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
  323.                                   ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
  324.                                   ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
  325.                                   ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
  326.                                   ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
  327. /**
  328.   * @}
  329.   */
  330.  
  331. /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
  332.   * @{
  333.   */
  334. #define SDIO_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000)
  335. #define SDIO_TRANSFER_DIR_TO_SDIO            SDIO_DCTRL_DTDIR
  336.  
  337. #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
  338.                                    ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
  339. /**
  340.   * @}
  341.   */
  342.  
  343. /** @defgroup SDMMC_LL_Transfer_Type Transfer Type
  344.   * @{
  345.   */
  346. #define SDIO_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000)
  347. #define SDIO_TRANSFER_MODE_STREAM            SDIO_DCTRL_DTMODE
  348.  
  349. #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
  350.                                      ((MODE) == SDIO_TRANSFER_MODE_STREAM))
  351. /**
  352.   * @}
  353.   */
  354.  
  355. /** @defgroup SDMMC_LL_DPSM_State DPSM State
  356.   * @{
  357.   */
  358. #define SDIO_DPSM_DISABLE                    ((uint32_t)0x00000000)
  359. #define SDIO_DPSM_ENABLE                     SDIO_DCTRL_DTEN
  360.  
  361. #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
  362.                             ((DPSM) == SDIO_DPSM_ENABLE))
  363. /**
  364.   * @}
  365.   */
  366.  
  367. /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
  368.   * @{
  369.   */
  370. #define SDIO_READ_WAIT_MODE_DATA2                ((uint32_t)0x00000000)
  371. #define SDIO_READ_WAIT_MODE_CLK                  (SDIO_DCTRL_RWMOD)
  372.  
  373. #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
  374.                                      ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
  375. /**
  376.   * @}
  377.   */  
  378.  
  379. /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
  380.   * @{
  381.   */
  382. #define SDIO_IT_CCRCFAIL                    SDIO_STA_CCRCFAIL
  383. #define SDIO_IT_DCRCFAIL                    SDIO_STA_DCRCFAIL
  384. #define SDIO_IT_CTIMEOUT                    SDIO_STA_CTIMEOUT
  385. #define SDIO_IT_DTIMEOUT                    SDIO_STA_DTIMEOUT
  386. #define SDIO_IT_TXUNDERR                    SDIO_STA_TXUNDERR
  387. #define SDIO_IT_RXOVERR                     SDIO_STA_RXOVERR
  388. #define SDIO_IT_CMDREND                     SDIO_STA_CMDREND
  389. #define SDIO_IT_CMDSENT                     SDIO_STA_CMDSENT
  390. #define SDIO_IT_DATAEND                     SDIO_STA_DATAEND
  391. #define SDIO_IT_STBITERR                    SDIO_STA_STBITERR
  392. #define SDIO_IT_DBCKEND                     SDIO_STA_DBCKEND
  393. #define SDIO_IT_CMDACT                      SDIO_STA_CMDACT
  394. #define SDIO_IT_TXACT                       SDIO_STA_TXACT
  395. #define SDIO_IT_RXACT                       SDIO_STA_RXACT
  396. #define SDIO_IT_TXFIFOHE                    SDIO_STA_TXFIFOHE
  397. #define SDIO_IT_RXFIFOHF                    SDIO_STA_RXFIFOHF
  398. #define SDIO_IT_TXFIFOF                     SDIO_STA_TXFIFOF
  399. #define SDIO_IT_RXFIFOF                     SDIO_STA_RXFIFOF
  400. #define SDIO_IT_TXFIFOE                     SDIO_STA_TXFIFOE
  401. #define SDIO_IT_RXFIFOE                     SDIO_STA_RXFIFOE
  402. #define SDIO_IT_TXDAVL                      SDIO_STA_TXDAVL
  403. #define SDIO_IT_RXDAVL                      SDIO_STA_RXDAVL
  404. #define SDIO_IT_SDIOIT                      SDIO_STA_SDIOIT
  405. #define SDIO_IT_CEATAEND                    SDIO_STA_CEATAEND
  406.  
  407. /**
  408.   * @}
  409.   */
  410.  
  411. /** @defgroup SDMMC_LL_Flags Flags
  412.   * @{
  413.   */
  414. #define SDIO_FLAG_CCRCFAIL                  SDIO_STA_CCRCFAIL
  415. #define SDIO_FLAG_DCRCFAIL                  SDIO_STA_DCRCFAIL
  416. #define SDIO_FLAG_CTIMEOUT                  SDIO_STA_CTIMEOUT
  417. #define SDIO_FLAG_DTIMEOUT                  SDIO_STA_DTIMEOUT
  418. #define SDIO_FLAG_TXUNDERR                  SDIO_STA_TXUNDERR
  419. #define SDIO_FLAG_RXOVERR                   SDIO_STA_RXOVERR
  420. #define SDIO_FLAG_CMDREND                   SDIO_STA_CMDREND
  421. #define SDIO_FLAG_CMDSENT                   SDIO_STA_CMDSENT
  422. #define SDIO_FLAG_DATAEND                   SDIO_STA_DATAEND
  423. #define SDIO_FLAG_STBITERR                  SDIO_STA_STBITERR
  424. #define SDIO_FLAG_DBCKEND                   SDIO_STA_DBCKEND
  425. #define SDIO_FLAG_CMDACT                    SDIO_STA_CMDACT
  426. #define SDIO_FLAG_TXACT                     SDIO_STA_TXACT
  427. #define SDIO_FLAG_RXACT                     SDIO_STA_RXACT
  428. #define SDIO_FLAG_TXFIFOHE                  SDIO_STA_TXFIFOHE
  429. #define SDIO_FLAG_RXFIFOHF                  SDIO_STA_RXFIFOHF
  430. #define SDIO_FLAG_TXFIFOF                   SDIO_STA_TXFIFOF
  431. #define SDIO_FLAG_RXFIFOF                   SDIO_STA_RXFIFOF
  432. #define SDIO_FLAG_TXFIFOE                   SDIO_STA_TXFIFOE
  433. #define SDIO_FLAG_RXFIFOE                   SDIO_STA_RXFIFOE
  434. #define SDIO_FLAG_TXDAVL                    SDIO_STA_TXDAVL
  435. #define SDIO_FLAG_RXDAVL                    SDIO_STA_RXDAVL
  436. #define SDIO_FLAG_SDIOIT                    SDIO_STA_SDIOIT
  437. #define SDIO_FLAG_CEATAEND                  SDIO_STA_CEATAEND
  438.  
  439. /**
  440.   * @}
  441.   */
  442.  
  443. /**
  444.   * @}
  445.   */
  446.  
  447. /* Exported macro ------------------------------------------------------------*/
  448. /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
  449.   * @{
  450.   */
  451.  
  452. /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
  453.   * @brief SDMMC_LL registers bit address in the alias region
  454.   * @{
  455.   */
  456.  
  457. /* ---------------------- SDIO registers bit mask --------------------------- */
  458. /* --- CLKCR Register ---*/
  459. /* CLKCR register clear mask */
  460. #define CLKCR_CLEAR_MASK         ((uint32_t)(SDIO_CLKCR_CLKDIV  | SDIO_CLKCR_PWRSAV |\
  461.                                              SDIO_CLKCR_BYPASS  | SDIO_CLKCR_WIDBUS |\
  462.                                              SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
  463.  
  464. /* --- DCTRL Register ---*/
  465. /* SDIO DCTRL Clear Mask */
  466. #define DCTRL_CLEAR_MASK         ((uint32_t)(SDIO_DCTRL_DTEN    | SDIO_DCTRL_DTDIR |\
  467.                                              SDIO_DCTRL_DTMODE  | SDIO_DCTRL_DBLOCKSIZE))
  468.  
  469. /* --- CMD Register ---*/
  470. /* CMD Register clear mask */
  471. #define CMD_CLEAR_MASK           ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
  472.                                              SDIO_CMD_WAITINT  | SDIO_CMD_WAITPEND |\
  473.                                              SDIO_CMD_CPSMEN   | SDIO_CMD_SDIOSUSPEND))
  474.  
  475. /* SDIO RESP Registers Address */
  476. #define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
  477.  
  478. /* SDIO Intialization Frequency (400KHz max) */
  479. #define SDIO_INIT_CLK_DIV ((uint8_t)0xC3)
  480.  
  481. /* SDIO Data Transfer Frequency */
  482. #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x9)
  483.  
  484. /**
  485.   * @}
  486.   */
  487.  
  488. /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
  489.   * @brief macros to handle interrupts and specific clock configurations
  490.   * @{
  491.   */
  492.  
  493. /**
  494.   * @brief  Enable the SDIO device.
  495.   * @param  __INSTANCE__: SDIO Instance  
  496.   * @retval None
  497.   */
  498. #define __SDIO_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR |= SDIO_CLKCR_CLKEN)
  499.  
  500. /**
  501.   * @brief  Disable the SDIO device.
  502.   * @param  __INSTANCE__: SDIO Instance  
  503.   * @retval None
  504.   */
  505. #define __SDIO_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR &= ~SDIO_CLKCR_CLKEN)
  506.  
  507. /**
  508.   * @brief  Enable the SDIO DMA transfer.
  509.   * @param  None  
  510.   * @retval None
  511.   */
  512. #define __SDIO_DMA_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_DMAEN)
  513. /**
  514.   * @brief  Disable the SDIO DMA transfer.
  515.   * @param  None  
  516.   * @retval None
  517.   */
  518. #define __SDIO_DMA_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_DMAEN)
  519.  
  520. /**
  521.   * @brief  Enable the SDIO device interrupt.
  522.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  523.   * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
  524.   *         This parameter can be one or a combination of the following values:
  525.   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  526.   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  527.   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
  528.   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
  529.   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  530.   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
  531.   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
  532.   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
  533.   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
  534.   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
  535.   *                                   bus mode interrupt
  536.   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
  537.   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
  538.   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
  539.   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
  540.   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  541.   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  542.   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
  543.   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
  544.   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
  545.   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
  546.   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
  547.   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
  548.   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
  549.   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt    
  550.   * @retval None
  551.   */
  552. #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
  553.  
  554. /**
  555.   * @brief  Disable the SDIO device interrupt.
  556.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  557.   * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
  558.   *          This parameter can be one or a combination of the following values:
  559.   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  560.   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  561.   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
  562.   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
  563.   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  564.   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
  565.   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
  566.   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
  567.   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
  568.   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
  569.   *                                   bus mode interrupt
  570.   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
  571.   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
  572.   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
  573.   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
  574.   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  575.   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  576.   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
  577.   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
  578.   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
  579.   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
  580.   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
  581.   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
  582.   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
  583.   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt    
  584.   * @retval None
  585.   */
  586. #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
  587.  
  588. /**
  589.   * @brief  Checks whether the specified SDIO flag is set or not.
  590.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  591.   * @param  __FLAG__: specifies the flag to check.
  592.   *          This parameter can be one of the following values:
  593.   *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
  594.   *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  595.   *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
  596.   *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
  597.   *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
  598.   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
  599.   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
  600.   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
  601.   *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
  602.   *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
  603.   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
  604.   *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
  605.   *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
  606.   *            @arg SDIO_FLAG_RXACT:    Data receive in progress
  607.   *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
  608.   *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
  609.   *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
  610.   *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
  611.   *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
  612.   *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
  613.   *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
  614.   *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
  615.   *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
  616.   *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
  617.   * @retval The new state of SDIO_FLAG (SET or RESET).
  618.   */
  619. #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)   (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
  620.  
  621.  
  622. /**
  623.   * @brief  Clears the SDIO pending flags.
  624.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  625.   * @param  __FLAG__: specifies the flag to clear.  
  626.   *          This parameter can be one or a combination of the following values:
  627.   *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
  628.   *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  629.   *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
  630.   *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
  631.   *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
  632.   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
  633.   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
  634.   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
  635.   *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
  636.   *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
  637.   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
  638.   *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
  639.   *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
  640.   * @retval None
  641.   */
  642. #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)   ((__INSTANCE__)->ICR = (__FLAG__))
  643.  
  644. /**
  645.   * @brief  Checks whether the specified SDIO interrupt has occurred or not.
  646.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  647.   * @param  __INTERRUPT__: specifies the SDIO interrupt source to check.
  648.   *          This parameter can be one of the following values:
  649.   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  650.   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  651.   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
  652.   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
  653.   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  654.   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
  655.   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
  656.   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
  657.   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
  658.   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
  659.   *                                   bus mode interrupt
  660.   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
  661.   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
  662.   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
  663.   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
  664.   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  665.   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  666.   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
  667.   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
  668.   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
  669.   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
  670.   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
  671.   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
  672.   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
  673.   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
  674.   * @retval The new state of SDIO_IT (SET or RESET).
  675.   */
  676. #define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)   (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
  677.  
  678. /**
  679.   * @brief  Clears the SDIO's interrupt pending bits.
  680.   * @param  __INSTANCE__ : Pointer to SDIO register base
  681.   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
  682.   *          This parameter can be one or a combination of the following values:
  683.   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  684.   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  685.   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
  686.   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
  687.   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  688.   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
  689.   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
  690.   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
  691.   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
  692.   *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
  693.   *                                   bus mode interrupt
  694.   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
  695.   *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
  696.   * @retval None
  697.   */
  698. #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->ICR = (__INTERRUPT__))
  699.  
  700. /**
  701.   * @brief  Enable Start the SD I/O Read Wait operation.
  702.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  703.   * @retval None
  704.   */  
  705. #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_RWSTART)
  706.  
  707. /**
  708.   * @brief  Disable Start the SD I/O Read Wait operations.
  709.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  710.   * @retval None
  711.   */  
  712. #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_RWSTART)
  713.  
  714. /**
  715.   * @brief  Enable Start the SD I/O Read Wait operation.
  716.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  717.   * @retval None
  718.   */  
  719. #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_RWSTOP)
  720.  
  721. /**
  722.   * @brief  Disable Stop the SD I/O Read Wait operations.
  723.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  724.   * @retval None
  725.   */  
  726. #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_RWSTOP)
  727.  
  728. /**
  729.   * @brief  Enable the SD I/O Mode Operation.
  730.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  731.   * @retval None
  732.   */  
  733. #define __SDIO_OPERATION_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_SDIOEN)
  734.  
  735. /**
  736.   * @brief  Disable the SD I/O Mode Operation.
  737.   * @param  __INSTANCE__ : Pointer to SDIO register base
  738.   * @retval None
  739.   */  
  740. #define __SDIO_OPERATION_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_SDIOEN)
  741.  
  742. /**
  743.   * @brief  Enable the SD I/O Suspend command sending.
  744.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  745.   * @retval None
  746.   */  
  747. #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDIO_CMD_SDIOSUSPEND)
  748.  
  749. /**
  750.   * @brief  Disable the SD I/O Suspend command sending.
  751.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  752.   * @retval None
  753.   */  
  754. #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDIO_CMD_SDIOSUSPEND)
  755.    
  756. /**
  757.   * @brief  Enable the command completion signal.
  758.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  759.   * @retval None
  760.   */    
  761. #define __SDIO_CEATA_CMD_COMPLETION_ENABLE(__INSTANCE__)   ((__INSTANCE__)->CMD |= SDIO_CMD_ENCMDCOMPL)
  762.  
  763. /**
  764.   * @brief  Disable the command completion signal.
  765.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  766.   * @retval None
  767.   */  
  768. #define __SDIO_CEATA_CMD_COMPLETION_DISABLE(__INSTANCE__)   ((__INSTANCE__)->CMD &= ~SDIO_CMD_ENCMDCOMPL)
  769.  
  770. /**
  771.   * @brief  Enable the CE-ATA interrupt.
  772.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  773.   * @retval None
  774.   */    
  775. #define __SDIO_CEATA_ENABLE_IT(__INSTANCE__)   ((__INSTANCE__)->CMD &= ~SDIO_CMD_NIEN)
  776.  
  777. /**
  778.   * @brief  Disable the CE-ATA interrupt.
  779.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  780.   * @retval None
  781.   */  
  782. #define __SDIO_CEATA_DISABLE_IT(__INSTANCE__)   ((__INSTANCE__)->CMD |= SDIO_CMD_NIEN)
  783.  
  784. /**
  785.   * @brief  Enable send CE-ATA command (CMD61).
  786.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  787.   * @retval None
  788.   */  
  789. #define __SDIO_CEATA_SENDCMD_ENABLE(__INSTANCE__)   ((__INSTANCE__)->CMD |= SDIO_CMD_CEATACMD)
  790.  
  791. /**
  792.   * @brief  Disable send CE-ATA command (CMD61).
  793.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  794.   * @retval None
  795.   */  
  796. #define __SDIO_CEATA_SENDCMD_DISABLE(__INSTANCE__)   ((__INSTANCE__)->CMD &= ~SDIO_CMD_CEATACMD)
  797.  
  798. /**
  799.   * @}
  800.   */
  801.  
  802. /**
  803.   * @}
  804.   */
  805.  
  806. /* Exported functions --------------------------------------------------------*/
  807. /** @addtogroup SDMMC_LL_Exported_Functions
  808.   * @{
  809.   */
  810.  
  811. /* Initialization/de-initialization functions  **********************************/
  812. /** @addtogroup HAL_SDMMC_LL_Group1
  813.   * @{
  814.   */
  815. HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
  816. /**
  817.   * @}
  818.   */
  819.  
  820. /* I/O operation functions  *****************************************************/
  821. /** @addtogroup HAL_SDMMC_LL_Group2
  822.   * @{
  823.   */
  824. /* Blocking mode: Polling */
  825. uint32_t          SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
  826. HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
  827. /**
  828.   * @}
  829.   */
  830.  
  831. /* Peripheral Control functions  ************************************************/
  832. /** @addtogroup HAL_SDMMC_LL_Group3
  833.   * @{
  834.   */
  835. HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
  836. HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
  837. uint32_t          SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
  838.  
  839. /* Command path state machine (CPSM) management functions */
  840. HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);
  841. uint8_t           SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
  842. uint32_t          SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
  843.  
  844. /* Data path state machine (DPSM) management functions */
  845. HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
  846. uint32_t          SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
  847. uint32_t          SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
  848.  
  849. /* SDIO Cards mode management functions */
  850. HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
  851.  
  852. /**
  853.   * @}
  854.   */
  855.  
  856. /**
  857.   * @}
  858.   */
  859.  
  860. /**
  861.   * @}
  862.   */
  863.  
  864. /**
  865.   * @}
  866.   */
  867.  
  868. #ifdef __cplusplus
  869. }
  870. #endif
  871.  
  872. #endif /* STM32F103xE || STM32F103xG */
  873.  
  874. #endif /* __stm32f1xx_LL_SD_H */
  875.  
  876. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  877.