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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_sdmmc.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of SDMMC HAL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
  10.   * All rights reserved.</center></h2>
  11.   *
  12.   * This software component is licensed by ST under BSD 3-Clause license,
  13.   * the "License"; You may not use this file except in compliance with the
  14.   * License. You may obtain a copy of the License at:
  15.   *                       opensource.org/licenses/BSD-3-Clause
  16.   *
  17.   ******************************************************************************
  18.   */
  19.  
  20. /* Define to prevent recursive inclusion -------------------------------------*/
  21. #ifndef STM32F1xx_LL_SDMMC_H
  22. #define STM32F1xx_LL_SDMMC_H
  23.  
  24. #ifdef __cplusplus
  25.  extern "C" {
  26. #endif
  27.  
  28. #if defined(SDIO)
  29.  
  30. /* Includes ------------------------------------------------------------------*/
  31. #include "stm32f1xx_hal_def.h"
  32.  
  33. /** @addtogroup STM32F1xx_Driver
  34.   * @{
  35.   */
  36.  
  37. /** @addtogroup SDMMC_LL
  38.   * @{
  39.   */
  40.  
  41. /* Exported types ------------------------------------------------------------*/
  42. /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
  43.   * @{
  44.   */
  45.  
  46. /**
  47.   * @brief  SDMMC Configuration Structure definition  
  48.   */
  49. typedef struct
  50. {
  51.   uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
  52.                                       This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
  53.  
  54.   uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is
  55.                                       enabled or disabled.
  56.                                       This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
  57.  
  58.   uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or
  59.                                       disabled when the bus is idle.
  60.                                       This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
  61.  
  62.   uint32_t BusWide;              /*!< Specifies the SDMMC bus width.
  63.                                       This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
  64.  
  65.   uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
  66.                                       This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
  67.  
  68.   uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.
  69.                                       This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  
  70.  
  71. }SDIO_InitTypeDef;
  72.  
  73.  
  74. /**
  75.   * @brief  SDMMC Command Control structure
  76.   */
  77. typedef struct                                                                                            
  78. {
  79.   uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent
  80.                                      to a card as part of a command message. If a command
  81.                                      contains an argument, it must be loaded into this register
  82.                                      before writing the command to the command register.              */
  83.  
  84.   uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
  85.                                      Max_Data = 64                                                    */
  86.  
  87.   uint32_t Response;            /*!< Specifies the SDMMC response type.
  88.                                      This parameter can be a value of @ref SDMMC_LL_Response_Type         */
  89.  
  90.   uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is
  91.                                      enabled or disabled.
  92.                                      This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
  93.  
  94.   uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)
  95.                                      is enabled or disabled.
  96.                                      This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
  97. }SDIO_CmdInitTypeDef;
  98.  
  99.  
  100. /**
  101.   * @brief  SDMMC Data Control structure
  102.   */
  103. typedef struct
  104. {
  105.   uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
  106.  
  107.   uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
  108.  
  109.   uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
  110.                                      This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
  111.  
  112.   uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
  113.                                      is a read or write.
  114.                                      This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
  115.  
  116.   uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
  117.                                      This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
  118.  
  119.   uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)
  120.                                      is enabled or disabled.
  121.                                      This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
  122. }SDIO_DataInitTypeDef;
  123.  
  124. /**
  125.   * @}
  126.   */
  127.  
  128. /* Exported constants --------------------------------------------------------*/
  129. /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
  130.   * @{
  131.   */
  132. #define SDMMC_ERROR_NONE                                0x00000000U    /*!< No error                                                      */
  133. #define SDMMC_ERROR_CMD_CRC_FAIL                        0x00000001U    /*!< Command response received (but CRC check failed)              */
  134. #define SDMMC_ERROR_DATA_CRC_FAIL                       0x00000002U    /*!< Data block sent/received (CRC check failed)                   */
  135. #define SDMMC_ERROR_CMD_RSP_TIMEOUT                     0x00000004U    /*!< Command response timeout                                      */
  136. #define SDMMC_ERROR_DATA_TIMEOUT                        0x00000008U    /*!< Data timeout                                                  */
  137. #define SDMMC_ERROR_TX_UNDERRUN                         0x00000010U    /*!< Transmit FIFO underrun                                        */
  138. #define SDMMC_ERROR_RX_OVERRUN                          0x00000020U    /*!< Receive FIFO overrun                                          */
  139. #define SDMMC_ERROR_ADDR_MISALIGNED                     0x00000040U    /*!< Misaligned address                                            */
  140. #define SDMMC_ERROR_BLOCK_LEN_ERR                       0x00000080U    /*!< Transferred block length is not allowed for the card or the
  141.                                                                             number of transferred bytes does not match the block length   */
  142. #define SDMMC_ERROR_ERASE_SEQ_ERR                       0x00000100U    /*!< An error in the sequence of erase command occurs              */
  143. #define SDMMC_ERROR_BAD_ERASE_PARAM                     0x00000200U    /*!< An invalid selection for erase groups                         */
  144. #define SDMMC_ERROR_WRITE_PROT_VIOLATION                0x00000400U    /*!< Attempt to program a write protect block                      */
  145. #define SDMMC_ERROR_LOCK_UNLOCK_FAILED                  0x00000800U    /*!< Sequence or password error has been detected in unlock
  146.                                                                             command or if there was an attempt to access a locked card    */
  147. #define SDMMC_ERROR_COM_CRC_FAILED                      0x00001000U    /*!< CRC check of the previous command failed                      */
  148. #define SDMMC_ERROR_ILLEGAL_CMD                         0x00002000U    /*!< Command is not legal for the card state                       */
  149. #define SDMMC_ERROR_CARD_ECC_FAILED                     0x00004000U    /*!< Card internal ECC was applied but failed to correct the data  */
  150. #define SDMMC_ERROR_CC_ERR                              0x00008000U    /*!< Internal card controller error                                */
  151. #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR                 0x00010000U    /*!< General or unknown error                                      */
  152. #define SDMMC_ERROR_STREAM_READ_UNDERRUN                0x00020000U    /*!< The card could not sustain data reading in stream rmode       */
  153. #define SDMMC_ERROR_STREAM_WRITE_OVERRUN                0x00040000U    /*!< The card could not sustain data programming in stream mode    */
  154. #define SDMMC_ERROR_CID_CSD_OVERWRITE                   0x00080000U    /*!< CID/CSD overwrite error                                       */
  155. #define SDMMC_ERROR_WP_ERASE_SKIP                       0x00100000U    /*!< Only partial address space was erased                         */
  156. #define SDMMC_ERROR_CARD_ECC_DISABLED                   0x00200000U    /*!< Command has been executed without using internal ECC          */
  157. #define SDMMC_ERROR_ERASE_RESET                         0x00400000U    /*!< Erase sequence was cleared before executing because an out
  158.                                                                             of erase sequence command was received                        */
  159. #define SDMMC_ERROR_AKE_SEQ_ERR                         0x00800000U    /*!< Error in sequence of authentication                           */
  160. #define SDMMC_ERROR_INVALID_VOLTRANGE                   0x01000000U    /*!< Error in case of invalid voltage range                        */
  161. #define SDMMC_ERROR_ADDR_OUT_OF_RANGE                   0x02000000U    /*!< Error when addressed block is out of range                    */
  162. #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE              0x04000000U    /*!< Error when command request is not applicable                  */
  163. #define SDMMC_ERROR_INVALID_PARAMETER                   0x08000000U    /*!< the used parameter is not valid                               */
  164. #define SDMMC_ERROR_UNSUPPORTED_FEATURE                 0x10000000U    /*!< Error when feature is not insupported                         */
  165. #define SDMMC_ERROR_BUSY                                0x20000000U    /*!< Error when transfer process is busy                           */
  166. #define SDMMC_ERROR_DMA                                 0x40000000U    /*!< Error while DMA transfer                                      */
  167. #define SDMMC_ERROR_TIMEOUT                             0x80000000U    /*!< Timeout error                                                 */
  168.  
  169. /**
  170.   * @brief SDMMC Commands Index
  171.   */
  172. #define SDMMC_CMD_GO_IDLE_STATE                                 0U    /*!< Resets the SD memory card.                                                               */
  173. #define SDMMC_CMD_SEND_OP_COND                                  1U    /*!< Sends host capacity support information and activates the card's initialization process. */
  174. #define SDMMC_CMD_ALL_SEND_CID                                  2U    /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
  175. #define SDMMC_CMD_SET_REL_ADDR                                  3U    /*!< Asks the card to publish a new relative address (RCA).                                   */
  176. #define SDMMC_CMD_SET_DSR                                       4U    /*!< Programs the DSR of all cards.                                                           */
  177. #define SDMMC_CMD_SDMMC_SEN_OP_COND                             5U    /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
  178.                                                                            operating condition register (OCR) content in the response on the CMD line.              */
  179. #define SDMMC_CMD_HS_SWITCH                                     6U    /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
  180. #define SDMMC_CMD_SEL_DESEL_CARD                                7U    /*!< Selects the card by its own relative address and gets deselected by any other address    */
  181. #define SDMMC_CMD_HS_SEND_EXT_CSD                               8U    /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
  182.                                                                            and asks the card whether card supports voltage.                                         */
  183. #define SDMMC_CMD_SEND_CSD                                      9U    /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
  184. #define SDMMC_CMD_SEND_CID                                      10U   /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
  185. #define SDMMC_CMD_READ_DAT_UNTIL_STOP                           11U   /*!< SD card doesn't support it.                                                              */
  186. #define SDMMC_CMD_STOP_TRANSMISSION                             12U   /*!< Forces the card to stop transmission.                                                    */
  187. #define SDMMC_CMD_SEND_STATUS                                   13U   /*!< Addressed card sends its status register.                                                */
  188. #define SDMMC_CMD_HS_BUSTEST_READ                               14U   /*!< Reserved                                                                                 */
  189. #define SDMMC_CMD_GO_INACTIVE_STATE                             15U   /*!< Sends an addressed card into the inactive state.                                         */
  190. #define SDMMC_CMD_SET_BLOCKLEN                                  16U   /*!< Sets the block length (in bytes for SDSC) for all following block commands
  191.                                                                            (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
  192.                                                                            for SDHS and SDXC.                                                                       */
  193. #define SDMMC_CMD_READ_SINGLE_BLOCK                             17U   /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
  194.                                                                            fixed 512 bytes in case of SDHC and SDXC.                                                */
  195. #define SDMMC_CMD_READ_MULT_BLOCK                               18U   /*!< Continuously transfers data blocks from card to host until interrupted by
  196.                                                                            STOP_TRANSMISSION command.                                                               */
  197. #define SDMMC_CMD_HS_BUSTEST_WRITE                              19U   /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
  198. #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                          20U   /*!< Speed class control command.                                                             */
  199. #define SDMMC_CMD_SET_BLOCK_COUNT                               23U   /*!< Specify block count for CMD18 and CMD25.                                                 */
  200. #define SDMMC_CMD_WRITE_SINGLE_BLOCK                            24U   /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
  201.                                                                            fixed 512 bytes in case of SDHC and SDXC.                                                */
  202. #define SDMMC_CMD_WRITE_MULT_BLOCK                              25U   /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
  203. #define SDMMC_CMD_PROG_CID                                      26U   /*!< Reserved for manufacturers.                                                              */
  204. #define SDMMC_CMD_PROG_CSD                                      27U   /*!< Programming of the programmable bits of the CSD.                                         */
  205. #define SDMMC_CMD_SET_WRITE_PROT                                28U   /*!< Sets the write protection bit of the addressed group.                                    */
  206. #define SDMMC_CMD_CLR_WRITE_PROT                                29U   /*!< Clears the write protection bit of the addressed group.                                  */
  207. #define SDMMC_CMD_SEND_WRITE_PROT                               30U   /*!< Asks the card to send the status of the write protection bits.                           */
  208. #define SDMMC_CMD_SD_ERASE_GRP_START                            32U   /*!< Sets the address of the first write block to be erased. (For SD card only).              */
  209. #define SDMMC_CMD_SD_ERASE_GRP_END                              33U   /*!< Sets the address of the last write block of the continuous range to be erased.           */
  210. #define SDMMC_CMD_ERASE_GRP_START                               35U   /*!< Sets the address of the first write block to be erased. Reserved for each command
  211.                                                                            system set by switch function command (CMD6).                                            */
  212. #define SDMMC_CMD_ERASE_GRP_END                                 36U   /*!< Sets the address of the last write block of the continuous range to be erased.
  213.                                                                            Reserved for each command system set by switch function command (CMD6).                  */
  214. #define SDMMC_CMD_ERASE                                         38U   /*!< Reserved for SD security applications.                                                   */
  215. #define SDMMC_CMD_FAST_IO                                       39U   /*!< SD card doesn't support it (Reserved).                                                   */
  216. #define SDMMC_CMD_GO_IRQ_STATE                                  40U   /*!< SD card doesn't support it (Reserved).                                                   */
  217. #define SDMMC_CMD_LOCK_UNLOCK                                   42U   /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
  218.                                                                            the SET_BLOCK_LEN command.                                                               */
  219. #define SDMMC_CMD_APP_CMD                                       55U   /*!< Indicates to the card that the next command is an application specific command rather
  220.                                                                            than a standard command.                                                                 */
  221. #define SDMMC_CMD_GEN_CMD                                       56U   /*!< Used either to transfer a data block to the card or to get a data block from the card
  222.                                                                            for general purpose/application specific commands.                                       */
  223. #define SDMMC_CMD_NO_CMD                                        64U   /*!< No command                                                                               */
  224.  
  225. /**
  226.   * @brief Following commands are SD Card Specific commands.
  227.   *        SDMMC_APP_CMD should be sent before sending these commands.
  228.   */
  229. #define SDMMC_CMD_APP_SD_SET_BUSWIDTH                           6U    /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
  230.                                                                             widths are given in SCR register.                                                       */
  231. #define SDMMC_CMD_SD_APP_STATUS                                 13U   /*!< (ACMD13) Sends the SD status.                                                            */
  232. #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS                  22U   /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
  233.                                                                            32bit+CRC data block.                                                                    */
  234. #define SDMMC_CMD_SD_APP_OP_COND                                41U   /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
  235.                                                                            send its operating condition register (OCR) content in the response on the CMD line.     */
  236. #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT                    42U   /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */
  237. #define SDMMC_CMD_SD_APP_SEND_SCR                               51U   /*!< Reads the SD Configuration Register (SCR).                                               */
  238. #define SDMMC_CMD_SDMMC_RW_DIRECT                               52U   /*!< For SD I/O card only, reserved for security specification.                               */
  239. #define SDMMC_CMD_SDMMC_RW_EXTENDED                             53U   /*!< For SD I/O card only, reserved for security specification.                               */
  240.  
  241. /**
  242.   * @brief Following commands are SD Card Specific security commands.
  243.   *        SDMMC_CMD_APP_CMD should be sent before sending these commands.
  244.   */
  245. #define SDMMC_CMD_SD_APP_GET_MKB                                43U
  246. #define SDMMC_CMD_SD_APP_GET_MID                                44U
  247. #define SDMMC_CMD_SD_APP_SET_CER_RN1                            45U
  248. #define SDMMC_CMD_SD_APP_GET_CER_RN2                            46U
  249. #define SDMMC_CMD_SD_APP_SET_CER_RES2                           47U
  250. #define SDMMC_CMD_SD_APP_GET_CER_RES1                           48U
  251. #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK             18U
  252. #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK            25U
  253. #define SDMMC_CMD_SD_APP_SECURE_ERASE                           38U
  254. #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA                     49U
  255. #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB                       48U
  256.  
  257. /**
  258.   * @brief  Masks for errors Card Status R1 (OCR Register)
  259.   */
  260. #define SDMMC_OCR_ADDR_OUT_OF_RANGE                   0x80000000U
  261. #define SDMMC_OCR_ADDR_MISALIGNED                     0x40000000U
  262. #define SDMMC_OCR_BLOCK_LEN_ERR                       0x20000000U
  263. #define SDMMC_OCR_ERASE_SEQ_ERR                       0x10000000U
  264. #define SDMMC_OCR_BAD_ERASE_PARAM                     0x08000000U
  265. #define SDMMC_OCR_WRITE_PROT_VIOLATION                0x04000000U
  266. #define SDMMC_OCR_LOCK_UNLOCK_FAILED                  0x01000000U
  267. #define SDMMC_OCR_COM_CRC_FAILED                      0x00800000U
  268. #define SDMMC_OCR_ILLEGAL_CMD                         0x00400000U
  269. #define SDMMC_OCR_CARD_ECC_FAILED                     0x00200000U
  270. #define SDMMC_OCR_CC_ERROR                            0x00100000U
  271. #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR               0x00080000U
  272. #define SDMMC_OCR_STREAM_READ_UNDERRUN                0x00040000U
  273. #define SDMMC_OCR_STREAM_WRITE_OVERRUN                0x00020000U
  274. #define SDMMC_OCR_CID_CSD_OVERWRITE                   0x00010000U
  275. #define SDMMC_OCR_WP_ERASE_SKIP                       0x00008000U
  276. #define SDMMC_OCR_CARD_ECC_DISABLED                   0x00004000U
  277. #define SDMMC_OCR_ERASE_RESET                         0x00002000U
  278. #define SDMMC_OCR_AKE_SEQ_ERROR                       0x00000008U
  279. #define SDMMC_OCR_ERRORBITS                           0xFDFFE008U
  280.  
  281. /**
  282.   * @brief  Masks for R6 Response
  283.   */
  284. #define SDMMC_R6_GENERAL_UNKNOWN_ERROR                0x00002000U
  285. #define SDMMC_R6_ILLEGAL_CMD                          0x00004000U
  286. #define SDMMC_R6_COM_CRC_FAILED                       0x00008000U
  287.  
  288. #define SDMMC_VOLTAGE_WINDOW_SD                       0x80100000U
  289. #define SDMMC_HIGH_CAPACITY                           0x40000000U
  290. #define SDMMC_STD_CAPACITY                            0x00000000U
  291. #define SDMMC_CHECK_PATTERN                           0x000001AAU
  292. #define SD_SWITCH_1_8V_CAPACITY                       0x01000000U
  293.  
  294. #define SDMMC_MAX_VOLT_TRIAL                          0x0000FFFFU
  295.  
  296. #define SDMMC_MAX_TRIAL                               0x0000FFFFU
  297.  
  298. #define SDMMC_ALLZERO                                 0x00000000U
  299.  
  300. #define SDMMC_WIDE_BUS_SUPPORT                        0x00040000U
  301. #define SDMMC_SINGLE_BUS_SUPPORT                      0x00010000U
  302. #define SDMMC_CARD_LOCKED                             0x02000000U
  303.  
  304. #ifndef SDMMC_DATATIMEOUT
  305. #define SDMMC_DATATIMEOUT                             0xFFFFFFFFU
  306. #endif /* SDMMC_DATATIMEOUT */
  307.  
  308. #define SDMMC_0TO7BITS                                0x000000FFU
  309. #define SDMMC_8TO15BITS                               0x0000FF00U
  310. #define SDMMC_16TO23BITS                              0x00FF0000U
  311. #define SDMMC_24TO31BITS                              0xFF000000U
  312. #define SDMMC_MAX_DATA_LENGTH                         0x01FFFFFFU
  313.  
  314. #define SDMMC_HALFFIFO                                0x00000008U
  315. #define SDMMC_HALFFIFOBYTES                           0x00000020U
  316.  
  317. /**
  318.   * @brief  Command Class supported
  319.   */
  320. #define SDIO_CCCC_ERASE                       0x00000020U
  321.  
  322. #define SDIO_CMDTIMEOUT                       5000U         /* Command send and response timeout */
  323. #define SDIO_MAXERASETIMEOUT                  63000U        /* Max erase Timeout 63 s            */
  324. #define SDIO_STOPTRANSFERTIMEOUT              100000000U    /* Timeout for STOP TRANSMISSION command */
  325.  
  326. /** @defgroup SDIO_LL_Clock_Edge Clock Edge
  327.   * @{
  328.   */
  329. #define SDIO_CLOCK_EDGE_RISING               0x00000000U
  330. #define SDIO_CLOCK_EDGE_FALLING              SDIO_CLKCR_NEGEDGE
  331.  
  332. #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
  333.                                           ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
  334. /**
  335.   * @}
  336.   */
  337.  
  338. /** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
  339.   * @{
  340.   */
  341. #define SDIO_CLOCK_BYPASS_DISABLE             0x00000000U
  342. #define SDIO_CLOCK_BYPASS_ENABLE              SDIO_CLKCR_BYPASS  
  343.  
  344. #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
  345.                                               ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
  346. /**
  347.   * @}
  348.   */
  349.  
  350. /** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
  351.   * @{
  352.   */
  353. #define SDIO_CLOCK_POWER_SAVE_DISABLE         0x00000000U
  354. #define SDIO_CLOCK_POWER_SAVE_ENABLE          SDIO_CLKCR_PWRSAV
  355.  
  356. #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
  357.                                                 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
  358. /**
  359.   * @}
  360.   */
  361.  
  362. /** @defgroup SDIO_LL_Bus_Wide Bus Width
  363.   * @{
  364.   */
  365. #define SDIO_BUS_WIDE_1B                      0x00000000U
  366. #define SDIO_BUS_WIDE_4B                      SDIO_CLKCR_WIDBUS_0
  367. #define SDIO_BUS_WIDE_8B                      SDIO_CLKCR_WIDBUS_1
  368.  
  369. #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
  370.                                         ((WIDE) == SDIO_BUS_WIDE_4B) || \
  371.                                         ((WIDE) == SDIO_BUS_WIDE_8B))
  372. /**
  373.   * @}
  374.   */
  375.  
  376. /** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
  377.   * @{
  378.   */
  379. #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    0x00000000U
  380. #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     SDIO_CLKCR_HWFC_EN
  381.  
  382. #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
  383.                                                         ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
  384. /**
  385.   * @}
  386.   */
  387.  
  388. /** @defgroup SDIO_LL_Clock_Division Clock Division
  389.   * @{
  390.   */
  391. #define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFFU)
  392. /**
  393.   * @}
  394.   */  
  395.    
  396. /** @defgroup SDIO_LL_Command_Index Command Index
  397.   * @{
  398.   */
  399. #define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40U)
  400. /**
  401.   * @}
  402.   */
  403.  
  404. /** @defgroup SDIO_LL_Response_Type Response Type
  405.   * @{
  406.   */
  407. #define SDIO_RESPONSE_NO                    0x00000000U
  408. #define SDIO_RESPONSE_SHORT                 SDIO_CMD_WAITRESP_0
  409. #define SDIO_RESPONSE_LONG                  SDIO_CMD_WAITRESP
  410.  
  411. #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO)    || \
  412.                                             ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
  413.                                             ((RESPONSE) == SDIO_RESPONSE_LONG))
  414. /**
  415.   * @}
  416.   */
  417.  
  418. /** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
  419.   * @{
  420.   */
  421. #define SDIO_WAIT_NO                        0x00000000U
  422. #define SDIO_WAIT_IT                        SDIO_CMD_WAITINT
  423. #define SDIO_WAIT_PEND                      SDIO_CMD_WAITPEND
  424.  
  425. #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
  426.                                     ((WAIT) == SDIO_WAIT_IT) || \
  427.                                     ((WAIT) == SDIO_WAIT_PEND))
  428. /**
  429.   * @}
  430.   */
  431.  
  432. /** @defgroup SDIO_LL_CPSM_State CPSM State
  433.   * @{
  434.   */
  435. #define SDIO_CPSM_DISABLE                   0x00000000U
  436. #define SDIO_CPSM_ENABLE                    SDIO_CMD_CPSMEN
  437.  
  438. #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
  439.                                     ((CPSM) == SDIO_CPSM_ENABLE))
  440. /**
  441.   * @}
  442.   */  
  443.  
  444. /** @defgroup SDIO_LL_Response_Registers Response Register
  445.   * @{
  446.   */
  447. #define SDIO_RESP1                          0x00000000U
  448. #define SDIO_RESP2                          0x00000004U
  449. #define SDIO_RESP3                          0x00000008U
  450. #define SDIO_RESP4                          0x0000000CU
  451.  
  452. #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
  453.                                     ((RESP) == SDIO_RESP2) || \
  454.                                     ((RESP) == SDIO_RESP3) || \
  455.                                     ((RESP) == SDIO_RESP4))
  456. /**
  457.   * @}
  458.   */
  459.  
  460. /** @defgroup SDIO_LL_Data_Length Data Length
  461.   * @{
  462.   */
  463. #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
  464. /**
  465.   * @}
  466.   */
  467.  
  468. /** @defgroup SDIO_LL_Data_Block_Size  Data Block Size
  469.   * @{
  470.   */
  471. #define SDIO_DATABLOCK_SIZE_1B               0x00000000U
  472. #define SDIO_DATABLOCK_SIZE_2B               SDIO_DCTRL_DBLOCKSIZE_0
  473. #define SDIO_DATABLOCK_SIZE_4B               SDIO_DCTRL_DBLOCKSIZE_1
  474. #define SDIO_DATABLOCK_SIZE_8B               (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
  475. #define SDIO_DATABLOCK_SIZE_16B              SDIO_DCTRL_DBLOCKSIZE_2
  476. #define SDIO_DATABLOCK_SIZE_32B              (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)
  477. #define SDIO_DATABLOCK_SIZE_64B              (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
  478. #define SDIO_DATABLOCK_SIZE_128B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
  479. #define SDIO_DATABLOCK_SIZE_256B             SDIO_DCTRL_DBLOCKSIZE_3
  480. #define SDIO_DATABLOCK_SIZE_512B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)
  481. #define SDIO_DATABLOCK_SIZE_1024B            (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
  482. #define SDIO_DATABLOCK_SIZE_2048B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
  483. #define SDIO_DATABLOCK_SIZE_4096B            (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
  484. #define SDIO_DATABLOCK_SIZE_8192B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
  485. #define SDIO_DATABLOCK_SIZE_16384B           (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
  486.  
  487. #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \
  488.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
  489.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \
  490.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \
  491.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \
  492.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \
  493.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \
  494.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \
  495.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \
  496.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \
  497.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
  498.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
  499.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
  500.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
  501.                                           ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
  502. /**
  503.   * @}
  504.   */
  505.  
  506. /** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
  507.   * @{
  508.   */
  509. #define SDIO_TRANSFER_DIR_TO_CARD            0x00000000U
  510. #define SDIO_TRANSFER_DIR_TO_SDIO    SDIO_DCTRL_DTDIR
  511.  
  512. #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
  513.                                            ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
  514. /**
  515.   * @}
  516.   */
  517.  
  518. /** @defgroup SDIO_LL_Transfer_Type Transfer Type
  519.   * @{
  520.   */
  521. #define SDIO_TRANSFER_MODE_BLOCK             0x00000000U
  522. #define SDIO_TRANSFER_MODE_STREAM            SDIO_DCTRL_DTMODE
  523.  
  524. #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
  525.                                              ((MODE) == SDIO_TRANSFER_MODE_STREAM))
  526. /**
  527.   * @}
  528.   */
  529.  
  530. /** @defgroup SDIO_LL_DPSM_State DPSM State
  531.   * @{
  532.   */
  533. #define SDIO_DPSM_DISABLE                    0x00000000U
  534. #define SDIO_DPSM_ENABLE                     SDIO_DCTRL_DTEN
  535.  
  536. #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
  537.                                     ((DPSM) == SDIO_DPSM_ENABLE))
  538. /**
  539.   * @}
  540.   */
  541.  
  542. /** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
  543.   * @{
  544.   */
  545. #define SDIO_READ_WAIT_MODE_DATA2                0x00000000U
  546. #define SDIO_READ_WAIT_MODE_CLK                  (SDIO_DCTRL_RWMOD)
  547.  
  548. #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
  549.                                              ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
  550. /**
  551.   * @}
  552.   */  
  553.  
  554. /** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
  555.   * @{
  556.   */
  557. #define SDIO_IT_CCRCFAIL                    SDIO_MASK_CCRCFAILIE
  558. #define SDIO_IT_DCRCFAIL                    SDIO_MASK_DCRCFAILIE
  559. #define SDIO_IT_CTIMEOUT                    SDIO_MASK_CTIMEOUTIE
  560. #define SDIO_IT_DTIMEOUT                    SDIO_MASK_DTIMEOUTIE
  561. #define SDIO_IT_TXUNDERR                    SDIO_MASK_TXUNDERRIE
  562. #define SDIO_IT_RXOVERR                     SDIO_MASK_RXOVERRIE
  563. #define SDIO_IT_CMDREND                     SDIO_MASK_CMDRENDIE
  564. #define SDIO_IT_CMDSENT                     SDIO_MASK_CMDSENTIE
  565. #define SDIO_IT_DATAEND                     SDIO_MASK_DATAENDIE
  566. #define SDIO_IT_STBITERR                    SDIO_MASK_STBITERRIE
  567. #define SDIO_IT_DBCKEND                     SDIO_MASK_DBCKENDIE
  568. #define SDIO_IT_CMDACT                      SDIO_MASK_CMDACTIE
  569. #define SDIO_IT_TXACT                       SDIO_MASK_TXACTIE
  570. #define SDIO_IT_RXACT                       SDIO_MASK_RXACTIE
  571. #define SDIO_IT_TXFIFOHE                    SDIO_MASK_TXFIFOHEIE
  572. #define SDIO_IT_RXFIFOHF                    SDIO_MASK_RXFIFOHFIE
  573. #define SDIO_IT_TXFIFOF                     SDIO_MASK_TXFIFOFIE
  574. #define SDIO_IT_RXFIFOF                     SDIO_MASK_RXFIFOFIE
  575. #define SDIO_IT_TXFIFOE                     SDIO_MASK_TXFIFOEIE
  576. #define SDIO_IT_RXFIFOE                     SDIO_MASK_RXFIFOEIE
  577. #define SDIO_IT_TXDAVL                      SDIO_MASK_TXDAVLIE
  578. #define SDIO_IT_RXDAVL                      SDIO_MASK_RXDAVLIE
  579. #define SDIO_IT_SDIOIT                      SDIO_MASK_SDIOITIE
  580. #define SDIO_IT_CEATAEND                    SDIO_MASK_CEATAENDIE
  581. /**
  582.   * @}
  583.   */
  584.  
  585. /** @defgroup SDIO_LL_Flags Flags
  586.   * @{
  587.   */
  588. #define SDIO_FLAG_CCRCFAIL                  SDIO_STA_CCRCFAIL
  589. #define SDIO_FLAG_DCRCFAIL                  SDIO_STA_DCRCFAIL
  590. #define SDIO_FLAG_CTIMEOUT                  SDIO_STA_CTIMEOUT
  591. #define SDIO_FLAG_DTIMEOUT                  SDIO_STA_DTIMEOUT
  592. #define SDIO_FLAG_TXUNDERR                  SDIO_STA_TXUNDERR
  593. #define SDIO_FLAG_RXOVERR                   SDIO_STA_RXOVERR
  594. #define SDIO_FLAG_CMDREND                   SDIO_STA_CMDREND
  595. #define SDIO_FLAG_CMDSENT                   SDIO_STA_CMDSENT
  596. #define SDIO_FLAG_DATAEND                   SDIO_STA_DATAEND
  597. #define SDIO_FLAG_STBITERR                  SDIO_STA_STBITERR
  598. #define SDIO_FLAG_DBCKEND                   SDIO_STA_DBCKEND
  599. #define SDIO_FLAG_CMDACT                    SDIO_STA_CMDACT
  600. #define SDIO_FLAG_TXACT                     SDIO_STA_TXACT
  601. #define SDIO_FLAG_RXACT                     SDIO_STA_RXACT
  602. #define SDIO_FLAG_TXFIFOHE                  SDIO_STA_TXFIFOHE
  603. #define SDIO_FLAG_RXFIFOHF                  SDIO_STA_RXFIFOHF
  604. #define SDIO_FLAG_TXFIFOF                   SDIO_STA_TXFIFOF
  605. #define SDIO_FLAG_RXFIFOF                   SDIO_STA_RXFIFOF
  606. #define SDIO_FLAG_TXFIFOE                   SDIO_STA_TXFIFOE
  607. #define SDIO_FLAG_RXFIFOE                   SDIO_STA_RXFIFOE
  608. #define SDIO_FLAG_TXDAVL                    SDIO_STA_TXDAVL
  609. #define SDIO_FLAG_RXDAVL                    SDIO_STA_RXDAVL
  610. #define SDIO_FLAG_SDIOIT                    SDIO_STA_SDIOIT
  611. #define SDIO_FLAG_CEATAEND                  SDIO_STA_CEATAEND
  612. #define SDIO_STATIC_FLAGS                   ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
  613.                                                          SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR  |\
  614.                                                          SDIO_FLAG_CMDREND  | SDIO_FLAG_CMDSENT  | SDIO_FLAG_DATAEND  |\
  615.                                                          SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT))  
  616.  
  617. #define SDIO_STATIC_CMD_FLAGS               ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\
  618.                                                          SDIO_FLAG_CMDSENT))
  619.  
  620. #define SDIO_STATIC_DATA_FLAGS              ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\
  621.                                                          SDIO_FLAG_RXOVERR  | SDIO_FLAG_DATAEND  | SDIO_FLAG_DBCKEND))
  622. /**
  623.   * @}
  624.   */
  625.  
  626. /**
  627.   * @}
  628.   */
  629.  
  630. /* Exported macro ------------------------------------------------------------*/
  631. /** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
  632.   * @{
  633.   */
  634.  
  635. /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
  636.   * @{
  637.   */
  638. /* ------------ SDIO registers bit address in the alias region -------------- */
  639. #define SDIO_OFFSET               (SDIO_BASE - PERIPH_BASE)
  640.  
  641. /* --- CLKCR Register ---*/
  642. /* Alias word address of CLKEN bit */
  643. #define CLKCR_OFFSET              (SDIO_OFFSET + 0x04U)
  644. #define CLKEN_BITNUMBER           0x08U
  645. #define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
  646.  
  647. /* --- CMD Register ---*/
  648. /* Alias word address of SDIOSUSPEND bit */
  649. #define CMD_OFFSET                (SDIO_OFFSET + 0x0CU)
  650. #define SDIOSUSPEND_BITNUMBER     0x0BU
  651. #define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
  652.  
  653. /* Alias word address of ENCMDCOMPL bit */
  654. #define ENCMDCOMPL_BITNUMBER      0x0CU
  655. #define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
  656.  
  657. /* Alias word address of NIEN bit */
  658. #define NIEN_BITNUMBER            0x0DU
  659. #define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
  660.  
  661. /* Alias word address of ATACMD bit */
  662. #define ATACMD_BITNUMBER          0x0EU
  663. #define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
  664.  
  665. /* --- DCTRL Register ---*/
  666. /* Alias word address of DMAEN bit */
  667. #define DCTRL_OFFSET              (SDIO_OFFSET + 0x2CU)
  668. #define DMAEN_BITNUMBER           0x03U
  669. #define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
  670.  
  671. /* Alias word address of RWSTART bit */
  672. #define RWSTART_BITNUMBER         0x08U
  673. #define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
  674.  
  675. /* Alias word address of RWSTOP bit */
  676. #define RWSTOP_BITNUMBER          0x09U
  677. #define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
  678.  
  679. /* Alias word address of RWMOD bit */
  680. #define RWMOD_BITNUMBER           0x0AU
  681. #define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
  682.  
  683. /* Alias word address of SDIOEN bit */
  684. #define SDIOEN_BITNUMBER          0x0BU
  685. #define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
  686. /**
  687.   * @}
  688.   */
  689.  
  690. /** @defgroup SDIO_LL_Register Bits And Addresses Definitions
  691.   * @brief SDIO_LL registers bit address in the alias region
  692.   * @{
  693.   */
  694. /* ---------------------- SDIO registers bit mask --------------------------- */
  695. /* --- CLKCR Register ---*/
  696. /* CLKCR register clear mask */
  697. #define CLKCR_CLEAR_MASK         ((uint32_t)(SDIO_CLKCR_CLKDIV  | SDIO_CLKCR_PWRSAV |\
  698.                                              SDIO_CLKCR_BYPASS  | SDIO_CLKCR_WIDBUS |\
  699.                                              SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
  700.  
  701. /* --- DCTRL Register ---*/
  702. /* SDIO DCTRL Clear Mask */
  703. #define DCTRL_CLEAR_MASK         ((uint32_t)(SDIO_DCTRL_DTEN    | SDIO_DCTRL_DTDIR |\
  704.                                              SDIO_DCTRL_DTMODE  | SDIO_DCTRL_DBLOCKSIZE))
  705.  
  706. /* --- CMD Register ---*/
  707. /* CMD Register clear mask */
  708. #define CMD_CLEAR_MASK           ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
  709.                                              SDIO_CMD_WAITINT  | SDIO_CMD_WAITPEND |\
  710.                                              SDIO_CMD_CPSMEN   | SDIO_CMD_SDIOSUSPEND))
  711.  
  712. /* SDIO Initialization Frequency (400KHz max) */
  713. #define SDIO_INIT_CLK_DIV     ((uint8_t)0x76)    /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
  714.  
  715. /* SDIO Data Transfer Frequency (25MHz max) */
  716. #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4)
  717. /**
  718.   * @}
  719.   */
  720.  
  721. /** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
  722.  *  @brief macros to handle interrupts and specific clock configurations
  723.  * @{
  724.  */
  725.  
  726. /**
  727.   * @brief  Enable the SDIO device.
  728.   * @param  __INSTANCE__: SDIO Instance  
  729.   * @retval None
  730.   */
  731. #define __SDIO_ENABLE(__INSTANCE__)  (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
  732.  
  733. /**
  734.   * @brief  Disable the SDIO device.
  735.   * @param  __INSTANCE__: SDIO Instance  
  736.   * @retval None
  737.   */
  738. #define __SDIO_DISABLE(__INSTANCE__)  (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
  739.  
  740. /**
  741.   * @brief  Enable the SDIO DMA transfer.
  742.   * @param  __INSTANCE__: SDIO Instance  
  743.   * @retval None
  744.   */
  745. #define __SDIO_DMA_ENABLE(__INSTANCE__)  (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
  746.  
  747. /**
  748.   * @brief  Disable the SDIO DMA transfer.
  749.   * @param  __INSTANCE__: SDIO Instance  
  750.   * @retval None
  751.   */
  752. #define __SDIO_DMA_DISABLE(__INSTANCE__)  (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
  753.  
  754. /**
  755.   * @brief  Enable the SDIO device interrupt.
  756.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  757.   * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
  758.   *         This parameter can be one or a combination of the following values:
  759.   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  760.   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  761.   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
  762.   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
  763.   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  764.   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
  765.   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
  766.   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
  767.   *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
  768.   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
  769.   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
  770.   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
  771.   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
  772.   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  773.   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  774.   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
  775.   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
  776.   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
  777.   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
  778.   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
  779.   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
  780.   *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
  781.   * @retval None
  782.   */
  783. #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
  784.  
  785. /**
  786.   * @brief  Disable the SDIO device interrupt.
  787.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  788.   * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
  789.   *          This parameter can be one or a combination of the following values:
  790.   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  791.   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  792.   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
  793.   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
  794.   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  795.   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
  796.   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
  797.   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
  798.   *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
  799.   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
  800.   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
  801.   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
  802.   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
  803.   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  804.   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  805.   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
  806.   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
  807.   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
  808.   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
  809.   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
  810.   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
  811.   *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt  
  812.   * @retval None
  813.   */
  814. #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
  815.  
  816. /**
  817.   * @brief  Checks whether the specified SDIO flag is set or not.
  818.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  819.   * @param  __FLAG__: specifies the flag to check.
  820.   *          This parameter can be one of the following values:
  821.   *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
  822.   *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  823.   *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
  824.   *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
  825.   *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
  826.   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
  827.   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
  828.   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
  829.   *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
  830.   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
  831.   *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
  832.   *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
  833.   *            @arg SDIO_FLAG_RXACT:    Data receive in progress
  834.   *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
  835.   *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
  836.   *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
  837.   *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
  838.   *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
  839.   *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
  840.   *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
  841.   *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
  842.   *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
  843.   * @retval The new state of SDIO_FLAG (SET or RESET).
  844.   */
  845. #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
  846.  
  847.  
  848. /**
  849.   * @brief  Clears the SDIO pending flags.
  850.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  851.   * @param  __FLAG__: specifies the flag to clear.  
  852.   *          This parameter can be one or a combination of the following values:
  853.   *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
  854.   *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
  855.   *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
  856.   *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
  857.   *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
  858.   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
  859.   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
  860.   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
  861.   *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
  862.   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
  863.   *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
  864.   * @retval None
  865.   */
  866. #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))
  867.  
  868. /**
  869.   * @brief  Checks whether the specified SDIO interrupt has occurred or not.
  870.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  871.   * @param  __INTERRUPT__: specifies the SDIO interrupt source to check.
  872.   *          This parameter can be one of the following values:
  873.   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  874.   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  875.   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
  876.   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
  877.   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  878.   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
  879.   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
  880.   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
  881.   *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
  882.   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
  883.   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
  884.   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
  885.   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
  886.   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
  887.   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
  888.   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
  889.   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
  890.   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
  891.   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
  892.   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
  893.   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
  894.   *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
  895.   * @retval The new state of SDIO_IT (SET or RESET).
  896.   */
  897. #define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
  898.  
  899. /**
  900.   * @brief  Clears the SDIO's interrupt pending bits.
  901.   * @param  __INSTANCE__ : Pointer to SDIO register base
  902.   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
  903.   *          This parameter can be one or a combination of the following values:
  904.   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
  905.   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
  906.   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
  907.   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
  908.   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
  909.   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
  910.   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
  911.   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
  912.   *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
  913.   *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
  914.   * @retval None
  915.   */
  916. #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))
  917.  
  918. /**
  919.   * @brief  Enable Start the SD I/O Read Wait operation.
  920.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  921.   * @retval None
  922.   */
  923. #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
  924.  
  925. /**
  926.   * @brief  Disable Start the SD I/O Read Wait operations.
  927.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  928.   * @retval None
  929.   */
  930. #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
  931.  
  932. /**
  933.   * @brief  Enable Start the SD I/O Read Wait operation.
  934.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  935.   * @retval None
  936.   */
  937. #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
  938.  
  939. /**
  940.   * @brief  Disable Stop the SD I/O Read Wait operations.
  941.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  942.   * @retval None
  943.   */
  944. #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
  945.  
  946. /**
  947.   * @brief  Enable the SD I/O Mode Operation.
  948.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  949.   * @retval None
  950.   */
  951. #define __SDIO_OPERATION_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
  952.  
  953. /**
  954.   * @brief  Disable the SD I/O Mode Operation.
  955.   * @param  __INSTANCE__ : Pointer to SDIO register base
  956.   * @retval None
  957.   */
  958. #define __SDIO_OPERATION_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
  959.  
  960. /**
  961.   * @brief  Enable the SD I/O Suspend command sending.
  962.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  963.   * @retval None
  964.   */
  965. #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
  966.  
  967. /**
  968.   * @brief  Disable the SD I/O Suspend command sending.
  969.   * @param  __INSTANCE__ : Pointer to SDIO register base  
  970.   * @retval None
  971.   */
  972. #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
  973.  
  974. /**
  975.   * @brief  Enable the command completion signal.
  976.   * @retval None
  977.   */    
  978. #define __SDIO_CEATA_CMD_COMPLETION_ENABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
  979.  
  980. /**
  981.   * @brief  Disable the command completion signal.
  982.   * @retval None
  983.   */  
  984. #define __SDIO_CEATA_CMD_COMPLETION_DISABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
  985.  
  986. /**
  987.   * @brief  Enable the CE-ATA interrupt.
  988.   * @retval None
  989.   */    
  990. #define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
  991.  
  992. /**
  993.   * @brief  Disable the CE-ATA interrupt.
  994.   * @retval None
  995.   */  
  996. #define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
  997.  
  998. /**
  999.   * @brief  Enable send CE-ATA command (CMD61).
  1000.   * @retval None
  1001.   */  
  1002. #define __SDIO_CEATA_SENDCMD_ENABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
  1003.  
  1004. /**
  1005.   * @brief  Disable send CE-ATA command (CMD61).
  1006.   * @retval None
  1007.   */  
  1008. #define __SDIO_CEATA_SENDCMD_DISABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
  1009.    
  1010. /**
  1011.   * @}
  1012.   */
  1013.  
  1014. /**
  1015.   * @}
  1016.   */  
  1017.  
  1018. /* Exported functions --------------------------------------------------------*/
  1019. /** @addtogroup SDMMC_LL_Exported_Functions
  1020.   * @{
  1021.   */
  1022.  
  1023. /* Initialization/de-initialization functions  **********************************/
  1024. /** @addtogroup HAL_SDMMC_LL_Group1
  1025.   * @{
  1026.   */
  1027. HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
  1028. /**
  1029.   * @}
  1030.   */
  1031.  
  1032. /* I/O operation functions  *****************************************************/
  1033. /** @addtogroup HAL_SDMMC_LL_Group2
  1034.   * @{
  1035.   */
  1036. uint32_t          SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
  1037. HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
  1038. /**
  1039.   * @}
  1040.   */
  1041.  
  1042. /* Peripheral Control functions  ************************************************/
  1043. /** @addtogroup HAL_SDMMC_LL_Group3
  1044.   * @{
  1045.   */
  1046. HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
  1047. HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
  1048. uint32_t          SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
  1049.  
  1050. /* Command path state machine (CPSM) management functions */
  1051. HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);
  1052. uint8_t           SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
  1053. uint32_t          SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
  1054.  
  1055. /* Data path state machine (DPSM) management functions */
  1056. HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
  1057. uint32_t          SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
  1058. uint32_t          SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
  1059.  
  1060. /* SDMMC Cards mode management functions */
  1061. HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
  1062.  
  1063. /* SDMMC Commands management functions */
  1064. uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
  1065. uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
  1066. uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
  1067. uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
  1068. uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
  1069. uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
  1070. uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
  1071. uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
  1072. uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
  1073. uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
  1074. uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
  1075. uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
  1076. uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
  1077. uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
  1078. uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
  1079. uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
  1080. uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
  1081. uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
  1082. uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
  1083. uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
  1084. uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
  1085. uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
  1086. uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
  1087. uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
  1088. uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
  1089. uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
  1090.  
  1091. /**
  1092.   * @}
  1093.   */
  1094.  
  1095. /**
  1096.   * @}
  1097.   */
  1098.  
  1099. /**
  1100.   * @}
  1101.   */
  1102.  
  1103. /**
  1104.   * @}
  1105.   */
  1106.  
  1107. #endif /* SDIO */
  1108.  
  1109. #ifdef __cplusplus
  1110. }
  1111. #endif
  1112.  
  1113. #endif /* STM32F1xx_LL_SDMMC_H */
  1114.  
  1115. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1116.