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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_fsmc.h
  4.   * @author  MCD Application Team
  5.   * @version V1.0.4
  6.   * @date    29-April-2016
  7.   * @brief   Header file of FSMC HAL module.
  8.   ******************************************************************************
  9.   * @attention
  10.   *
  11.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  12.   *
  13.   * Redistribution and use in source and binary forms, with or without modification,
  14.   * are permitted provided that the following conditions are met:
  15.   *   1. Redistributions of source code must retain the above copyright notice,
  16.   *      this list of conditions and the following disclaimer.
  17.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18.   *      this list of conditions and the following disclaimer in the documentation
  19.   *      and/or other materials provided with the distribution.
  20.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21.   *      may be used to endorse or promote products derived from this software
  22.   *      without specific prior written permission.
  23.   *
  24.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34.   *
  35.   ******************************************************************************
  36.   */
  37.  
  38. /* Define to prevent recursive inclusion -------------------------------------*/
  39. #ifndef __STM32F1xx_LL_FSMC_H
  40. #define __STM32F1xx_LL_FSMC_H
  41.  
  42. #ifdef __cplusplus
  43. extern "C" {
  44. #endif
  45.  
  46. /* Includes ------------------------------------------------------------------*/
  47. #include "stm32f1xx_hal_def.h"
  48.  
  49. /** @addtogroup STM32F1xx_HAL_Driver
  50.   * @{
  51.   */
  52.  
  53. #if defined(FSMC_BANK1)
  54.  
  55. /** @addtogroup FSMC_LL
  56.   * @{
  57.   */
  58.  
  59. /** @addtogroup FSMC_LL_Private_Macros
  60.   * @{
  61.   */
  62.  
  63. #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
  64.                                         ((__BANK__) == FSMC_NORSRAM_BANK2) || \
  65.                                         ((__BANK__) == FSMC_NORSRAM_BANK3) || \
  66.                                         ((__BANK__) == FSMC_NORSRAM_BANK4))
  67.  
  68. #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
  69.                               ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
  70.  
  71. #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
  72.                                     ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
  73.                                     ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
  74.  
  75. #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
  76.                                                  ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
  77.                                                  ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
  78.  
  79. #define IS_FSMC_WRITE_BURST(__BURST__)          (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
  80.                                                 ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
  81.  
  82. #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
  83.                                        ((__MODE__) == FSMC_ACCESS_MODE_B) || \
  84.                                        ((__MODE__) == FSMC_ACCESS_MODE_C) || \
  85.                                        ((__MODE__) == FSMC_ACCESS_MODE_D))
  86.  
  87. #define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \
  88.                                 ((__BANK__) == FSMC_NAND_BANK3))
  89.  
  90. #define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
  91.                                       ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
  92.  
  93. #define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
  94.                                          ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
  95.  
  96. #define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
  97.                                  ((__STATE__) == FSMC_NAND_ECC_ENABLE))
  98.  
  99. #define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
  100.                                    ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
  101.                                    ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
  102.                                    ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
  103.                                    ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
  104.                                    ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
  105.  
  106. /** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time
  107.   * @{
  108.   */
  109. #define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
  110. /**
  111.   * @}
  112.   */
  113.  
  114. /** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time
  115.   * @{
  116.   */
  117. #define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255)
  118. /**
  119.   * @}
  120.   */
  121.  
  122. /** @defgroup FSMC_Setup_Time FSMC_Setup_Time
  123.   * @{
  124.   */
  125. #define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255)
  126. /**
  127.   * @}
  128.   */
  129.  
  130. /** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time
  131.   * @{
  132.   */
  133. #define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255)
  134. /**
  135.   * @}
  136.   */
  137.  
  138. /** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time
  139.   * @{
  140.   */
  141. #define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255)
  142. /**
  143.   * @}
  144.   */
  145.  
  146. /** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time
  147.   * @{
  148.   */
  149. #define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255)
  150. /**
  151.   * @}
  152.   */
  153.  
  154. /** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
  155.   * @{
  156.   */
  157.  
  158. #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
  159.  
  160. /**
  161.   * @}
  162.   */
  163.  
  164. /** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
  165.   * @{
  166.   */
  167.  
  168. #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
  169.  
  170. /**
  171.   * @}
  172.   */
  173.  
  174. /** @defgroup FSMC_NAND_Device_Instance FSMC NAND Device Instance
  175.   * @{
  176.   */
  177. #define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
  178. /**
  179.   * @}
  180.   */
  181.  
  182. /** @defgroup FSMC_PCCARD_Device_Instance FSMC PCCARD Device Instance
  183.   * @{
  184.   */
  185. #define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
  186.  
  187. /**
  188.   * @}
  189.   */
  190. #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
  191.                                       ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
  192.  
  193. #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
  194.                                              ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
  195.  
  196. #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
  197.                                      ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
  198.  
  199. #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
  200.                                                 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
  201.  
  202. #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
  203.                                                 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
  204.  
  205. #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
  206.                                           ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
  207.  
  208. #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
  209.                                          ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
  210.  
  211. #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
  212.                                      ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
  213.  
  214. #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
  215.  
  216. /** @defgroup FSMC_Data_Latency FSMC Data Latency
  217.   * @{
  218.   */
  219. #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
  220. /**
  221.   * @}
  222.   */
  223.  
  224. /** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
  225.   * @{
  226.   */
  227. #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
  228. /**
  229.   * @}
  230.   */
  231.  
  232. /** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
  233.   * @{
  234.   */
  235. #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
  236. /**
  237.   * @}
  238.   */
  239.  
  240. /** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
  241.   * @{
  242.   */
  243. #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
  244. /**
  245.   * @}
  246.   */
  247.  
  248. /** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
  249.   * @{
  250.   */
  251. #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
  252. /**
  253.   * @}
  254.   */
  255.  
  256. /**
  257.   * @}
  258.   */
  259.  
  260. /* Exported typedef ----------------------------------------------------------*/
  261.  
  262. /** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types
  263.   * @{
  264.   */
  265.  
  266. #define FSMC_NORSRAM_TypeDef            FSMC_Bank1_TypeDef
  267. #define FSMC_NORSRAM_EXTENDED_TypeDef   FSMC_Bank1E_TypeDef
  268. #define FSMC_NAND_TypeDef               FSMC_Bank2_3_TypeDef
  269. #define FSMC_PCCARD_TypeDef             FSMC_Bank4_TypeDef
  270.  
  271. #define FSMC_NORSRAM_DEVICE             FSMC_Bank1
  272. #define FSMC_NORSRAM_EXTENDED_DEVICE    FSMC_Bank1E
  273. #define FSMC_NAND_DEVICE                FSMC_Bank2_3
  274. #define FSMC_PCCARD_DEVICE              FSMC_Bank4
  275.  
  276. /**
  277.   * @brief  FSMC_NORSRAM Configuration Structure definition
  278.   */
  279. typedef struct
  280. {
  281.   uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
  282.                                               This parameter can be a value of @ref FSMC_NORSRAM_Bank                     */
  283.  
  284.   uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
  285.                                               multiplexed on the data bus or not.
  286.                                               This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing    */
  287.  
  288.   uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
  289.                                               the corresponding memory device.
  290.                                               This parameter can be a value of @ref FSMC_Memory_Type                      */
  291.  
  292.   uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
  293.                                               This parameter can be a value of @ref FSMC_NORSRAM_Data_Width               */
  294.  
  295.   uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
  296.                                               valid only with synchronous burst Flash memories.
  297.                                               This parameter can be a value of @ref FSMC_Burst_Access_Mode                */
  298.  
  299.   uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
  300.                                               the Flash memory in burst mode.
  301.                                               This parameter can be a value of @ref FSMC_Wait_Signal_Polarity             */
  302.  
  303.   uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
  304.                                               memory, valid only when accessing Flash memories in burst mode.
  305.                                               This parameter can be a value of @ref FSMC_Wrap_Mode                        */
  306.  
  307.   uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
  308.                                               clock cycle before the wait state or during the wait state,
  309.                                               valid only when accessing memories in burst mode.
  310.                                               This parameter can be a value of @ref FSMC_Wait_Timing                      */
  311.  
  312.   uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FSMC.
  313.                                               This parameter can be a value of @ref FSMC_Write_Operation                  */
  314.  
  315.   uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
  316.                                               signal, valid for Flash memory access in burst mode.
  317.                                               This parameter can be a value of @ref FSMC_Wait_Signal                      */
  318.  
  319.   uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
  320.                                               This parameter can be a value of @ref FSMC_Extended_Mode                    */
  321.  
  322.   uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
  323.                                               valid only with asynchronous Flash memories.
  324.                                               This parameter can be a value of @ref FSMC_AsynchronousWait                 */
  325.  
  326.   uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
  327.                                               This parameter can be a value of @ref FSMC_Write_Burst                      */
  328.  
  329. }FSMC_NORSRAM_InitTypeDef;
  330.  
  331. /**
  332.   * @brief  FSMC_NORSRAM Timing parameters structure definition
  333.   */
  334. typedef struct
  335. {
  336.   uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
  337.                                               the duration of the address setup time.
  338.                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
  339.                                               @note This parameter is not used with synchronous NOR Flash memories.      */
  340.  
  341.   uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
  342.                                               the duration of the address hold time.
  343.                                               This parameter can be a value between Min_Data = 1 and Max_Data = 15.
  344.                                               @note This parameter is not used with synchronous NOR Flash memories.      */
  345.  
  346.   uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
  347.                                               the duration of the data setup time.
  348.                                               This parameter can be a value between Min_Data = 1 and Max_Data = 255.
  349.                                               @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
  350.                                               NOR Flash memories.                                                        */
  351.  
  352.   uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
  353.                                               the duration of the bus turnaround.
  354.                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
  355.                                               @note This parameter is only used for multiplexed NOR Flash memories.      */
  356.  
  357.   uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
  358.                                               HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
  359.                                               @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
  360.                                               accesses.                                                                  */
  361.  
  362.   uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
  363.                                               to the memory before getting the first data.
  364.                                               The parameter value depends on the memory type as shown below:
  365.                                               - It must be set to 0 in case of a CRAM
  366.                                               - It is don't care in asynchronous NOR, SRAM or ROM accesses
  367.                                               - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
  368.                                                 with synchronous burst mode enable                                       */
  369.  
  370.   uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
  371.                                               This parameter can be a value of @ref FSMC_Access_Mode                      */
  372.  
  373. }FSMC_NORSRAM_TimingTypeDef;
  374.  
  375. #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
  376. /**
  377.   * @brief  FSMC_NAND Configuration Structure definition
  378.   */
  379. typedef struct
  380. {
  381.   uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
  382.                                         This parameter can be a value of @ref FSMC_NAND_Bank                    */
  383.  
  384.   uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
  385.                                         This parameter can be any value of @ref FSMC_Wait_feature               */
  386.  
  387.   uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
  388.                                         This parameter can be any value of @ref FSMC_NAND_Data_Width            */
  389.  
  390.   uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
  391.                                         This parameter can be any value of @ref FSMC_ECC                        */
  392.  
  393.   uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
  394.                                         This parameter can be any value of @ref FSMC_ECC_Page_Size              */
  395.  
  396.   uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
  397.                                         delay between CLE low and RE low.
  398.                                         This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
  399.  
  400.   uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
  401.                                         delay between ALE low and RE low.
  402.                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
  403.  
  404. }FSMC_NAND_InitTypeDef;
  405.  
  406. /**
  407.   * @brief  FSMC_NAND_PCCARD Timing parameters structure definition
  408.   */
  409. typedef struct
  410. {
  411.   uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
  412.                                       the command assertion for NAND-Flash read or write access
  413.                                       to common/Attribute or I/O memory space (depending on
  414.                                       the memory space timing to be configured).
  415.                                       This parameter can be a value between Min_Data = 0 and Max_Data = 255    */
  416.  
  417.   uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
  418.                                       command for NAND-Flash read or write access to
  419.                                       common/Attribute or I/O memory space (depending on the
  420.                                       memory space timing to be configured).
  421.                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
  422.  
  423.   uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
  424.                                       (and data for write access) after the command de-assertion
  425.                                       for NAND-Flash read or write access to common/Attribute
  426.                                       or I/O memory space (depending on the memory space timing
  427.                                       to be configured).
  428.                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
  429.  
  430.   uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
  431.                                       data bus is kept in HiZ after the start of a NAND-Flash
  432.                                       write access to common/Attribute or I/O memory space (depending
  433.                                       on the memory space timing to be configured).
  434.                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
  435.  
  436. }FSMC_NAND_PCC_TimingTypeDef;
  437.  
  438. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  439. #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
  440. /**
  441.   * @brief  FSMC_NAND Configuration Structure definition
  442.   */
  443. typedef struct
  444. {
  445.   uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the PCCARD Memory device.
  446.                                         This parameter can be any value of @ref FSMC_Wait_feature               */
  447.  
  448.   uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
  449.                                         delay between CLE low and RE low.
  450.                                         This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
  451.  
  452.   uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
  453.                                         delay between ALE low and RE low.
  454.                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
  455.  
  456. }FSMC_PCCARD_InitTypeDef;
  457.  
  458. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  459. /**
  460.   * @}
  461.   */
  462.  
  463. /* Exported constants --------------------------------------------------------*/
  464.  
  465. /** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants
  466.   * @{
  467.   */
  468.  
  469. /** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
  470.   * @{
  471.   */
  472.  
  473. /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
  474.   * @{
  475.   */
  476. #define FSMC_NORSRAM_BANK1                       ((uint32_t)0x00000000)
  477. #define FSMC_NORSRAM_BANK2                       ((uint32_t)0x00000002)
  478. #define FSMC_NORSRAM_BANK3                       ((uint32_t)0x00000004)
  479. #define FSMC_NORSRAM_BANK4                       ((uint32_t)0x00000006)
  480.  
  481. /**
  482.   * @}
  483.   */
  484.  
  485. /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
  486.   * @{
  487.   */
  488.  
  489. #define FSMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
  490. #define FSMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)FSMC_BCRx_MUXEN)
  491.  
  492. /**
  493.   * @}
  494.   */
  495.  
  496. /** @defgroup FSMC_Memory_Type FSMC Memory Type
  497.   * @{
  498.   */
  499.  
  500. #define FSMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)
  501. #define FSMC_MEMORY_TYPE_PSRAM                   ((uint32_t)FSMC_BCRx_MTYP_0)
  502. #define FSMC_MEMORY_TYPE_NOR                     ((uint32_t)FSMC_BCRx_MTYP_1)
  503.  
  504. /**
  505.   * @}
  506.   */
  507.  
  508. /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
  509.   * @{
  510.   */
  511.  
  512. #define FSMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
  513. #define FSMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)FSMC_BCRx_MWID_0)
  514. #define FSMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)FSMC_BCRx_MWID_1)
  515.  
  516. /**
  517.   * @}
  518.   */
  519.  
  520. /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
  521.   * @{
  522.   */
  523.  
  524. #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)FSMC_BCRx_FACCEN)
  525. #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)
  526. /**
  527.   * @}
  528.   */
  529.  
  530. /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
  531.   * @{
  532.   */
  533.  
  534. #define FSMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000)
  535. #define FSMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)FSMC_BCRx_BURSTEN)
  536.  
  537. /**
  538.   * @}
  539.   */
  540.  
  541.  
  542. /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
  543.   * @{
  544.   */
  545.  
  546. #define FSMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
  547. #define FSMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)FSMC_BCRx_WAITPOL)
  548.  
  549. /**
  550.   * @}
  551.   */
  552.  
  553. /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
  554.   * @{
  555.   */
  556.  
  557. #define FSMC_WRAP_MODE_DISABLE                   ((uint32_t)0x00000000)
  558. #define FSMC_WRAP_MODE_ENABLE                    ((uint32_t)FSMC_BCRx_WRAPMOD)
  559.  
  560. /**
  561.   * @}
  562.   */
  563.  
  564. /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
  565.   * @{
  566.   */
  567.  
  568. #define FSMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
  569. #define FSMC_WAIT_TIMING_DURING_WS               ((uint32_t)FSMC_BCRx_WAITCFG)
  570.  
  571. /**
  572.   * @}
  573.   */
  574.  
  575. /** @defgroup FSMC_Write_Operation FSMC Write Operation
  576.   * @{
  577.   */
  578.  
  579. #define FSMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
  580. #define FSMC_WRITE_OPERATION_ENABLE              ((uint32_t)FSMC_BCRx_WREN)
  581.  
  582. /**
  583.   * @}
  584.   */
  585.  
  586. /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
  587.   * @{
  588.   */
  589.  
  590. #define FSMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
  591. #define FSMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)FSMC_BCRx_WAITEN)
  592.  
  593. /**
  594.   * @}
  595.   */
  596.  
  597. /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
  598.   * @{
  599.   */
  600.  
  601. #define FSMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
  602. #define FSMC_EXTENDED_MODE_ENABLE                ((uint32_t)FSMC_BCRx_EXTMOD)
  603.  
  604. /**
  605.   * @}
  606.   */
  607.  
  608. /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
  609.   * @{
  610.   */
  611.  
  612. #define FSMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
  613. #define FSMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)FSMC_BCRx_ASYNCWAIT)
  614.  
  615. /**
  616.   * @}
  617.   */
  618.  
  619. /** @defgroup FSMC_Write_Burst FSMC Write Burst
  620.   * @{
  621.   */
  622.  
  623. #define FSMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
  624. #define FSMC_WRITE_BURST_ENABLE                  ((uint32_t)FSMC_BCRx_CBURSTRW)
  625.  
  626. /**
  627.   * @}
  628.   */
  629.  
  630. /** @defgroup FSMC_Access_Mode FSMC Access Mode
  631.   * @{
  632.   */
  633.  
  634. #define FSMC_ACCESS_MODE_A                        ((uint32_t)0x00000000)
  635. #define FSMC_ACCESS_MODE_B                        ((uint32_t)FSMC_BTRx_ACCMOD_0)
  636. #define FSMC_ACCESS_MODE_C                        ((uint32_t)FSMC_BTRx_ACCMOD_1)
  637. #define FSMC_ACCESS_MODE_D                        ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1))
  638.  
  639. /**
  640.   * @}
  641.   */
  642.  
  643. /**
  644.   * @}
  645.   */
  646.  
  647. #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
  648. /** @defgroup FSMC_NAND_Controller FSMC NAND and PCCARD Controller
  649.   * @{
  650.   */
  651.  
  652. /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
  653.   * @{
  654.   */
  655. #define FSMC_NAND_BANK2                          ((uint32_t)0x00000010)
  656. #define FSMC_NAND_BANK3                          ((uint32_t)0x00000100)
  657.  
  658. /**
  659.   * @}
  660.   */
  661.  
  662. /** @defgroup FSMC_Wait_feature FSMC Wait feature
  663.   * @{
  664.   */
  665. #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000)
  666. #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE            ((uint32_t)FSMC_PCRx_PWAITEN)
  667.  
  668. /**
  669.   * @}
  670.   */
  671.  
  672. /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
  673.   * @{
  674.   */
  675. #define FSMC_PCR_MEMORY_TYPE_PCCARD        ((uint32_t)0x00000000)
  676. #define FSMC_PCR_MEMORY_TYPE_NAND          ((uint32_t)FSMC_PCRx_PTYP)
  677. /**
  678.   * @}
  679.   */
  680.  
  681. /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
  682.   * @{
  683.   */
  684. #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000)
  685. #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16               ((uint32_t)FSMC_PCRx_PWID_0)
  686.  
  687. /**
  688.   * @}
  689.   */
  690.  
  691. /** @defgroup FSMC_ECC FSMC NAND ECC
  692.   * @{
  693.   */
  694. #define FSMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000)
  695. #define FSMC_NAND_ECC_ENABLE                     ((uint32_t)FSMC_PCRx_ECCEN)
  696.  
  697. /**
  698.   * @}
  699.   */
  700.  
  701. /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
  702.   * @{
  703.   */
  704. #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000)
  705. #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)FSMC_PCRx_ECCPS_0)
  706. #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)FSMC_PCRx_ECCPS_1)
  707. #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_1)
  708. #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)FSMC_PCRx_ECCPS_2)
  709. #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_2)
  710.  
  711. /**
  712.   * @}
  713.   */
  714.  
  715. /** @defgroup FSMC_Interrupt_definition FSMC Interrupt definition
  716.   * @brief FSMC Interrupt definition
  717.   * @{
  718.   */
  719. #define FSMC_IT_RISING_EDGE                ((uint32_t)FSMC_SRx_IREN)
  720. #define FSMC_IT_LEVEL                      ((uint32_t)FSMC_SRx_ILEN)
  721. #define FSMC_IT_FALLING_EDGE               ((uint32_t)FSMC_SRx_IFEN)
  722.  
  723. /**
  724.   * @}
  725.   */
  726.  
  727. /** @defgroup FSMC_Flag_definition FSMC Flag definition
  728.   * @brief FSMC Flag definition
  729.   * @{
  730.   */
  731. #define FSMC_FLAG_RISING_EDGE                    ((uint32_t)FSMC_SRx_IRS)
  732. #define FSMC_FLAG_LEVEL                          ((uint32_t)FSMC_SRx_ILS)
  733. #define FSMC_FLAG_FALLING_EDGE                   ((uint32_t)FSMC_SRx_IFS)
  734. #define FSMC_FLAG_FEMPT                          ((uint32_t)FSMC_SRx_FEMPT)
  735.  
  736. /**
  737.   * @}
  738.   */
  739.  
  740. /**
  741.   * @}
  742.   */
  743. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  744.  
  745. /**
  746.   * @}
  747.   */
  748.  
  749. /* Exported macro ------------------------------------------------------------*/
  750.  
  751. /** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros
  752.   * @{
  753.   */
  754.  
  755. /** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros
  756.  *  @brief macros to handle NOR device enable/disable and read/write operations
  757.  *  @{
  758.  */
  759.  
  760. /**
  761.   * @brief  Enable the NORSRAM device access.
  762.   * @param  __INSTANCE__ FSMC_NORSRAM Instance
  763.   * @param  __BANK__ FSMC_NORSRAM Bank
  764.   * @retval none
  765.   */
  766. #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
  767.  
  768. /**
  769.   * @brief  Disable the NORSRAM device access.
  770.   * @param  __INSTANCE__ FSMC_NORSRAM Instance
  771.   * @param  __BANK__ FSMC_NORSRAM Bank
  772.   * @retval none
  773.   */
  774. #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
  775.  
  776. /**
  777.   * @}
  778.   */
  779.  
  780. #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
  781. /** @defgroup FSMC_NAND_Macros FSMC NAND Macros
  782.  *  @brief macros to handle NAND device enable/disable
  783.  *  @{
  784.  */
  785.  
  786. /**
  787.   * @brief  Enable the NAND device access.
  788.   * @param  __INSTANCE__ FSMC_NAND Instance
  789.   * @param  __BANK__ FSMC_NAND Bank
  790.   * @retval None
  791.   */
  792. #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__)  (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
  793.                                                     SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
  794.  
  795. /**
  796.   * @brief  Disable the NAND device access.
  797.   * @param  __INSTANCE__ FSMC_NAND Instance
  798.   * @param  __BANK__ FSMC_NAND Bank
  799.   * @retval None
  800.   */
  801. #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
  802.                                                    CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
  803.  
  804. /**
  805.   * @}
  806.   */
  807.  
  808. /** @defgroup FSMC_PCCARD_Macros FSMC PCCARD Macros
  809.  *  @brief macros to handle PCCARD read/write operations
  810.  *  @{
  811.  */
  812.  
  813. /**
  814.   * @brief  Enable the PCCARD device access.
  815.   * @param  __INSTANCE__ FSMC_PCCARD Instance
  816.   * @retval None
  817.   */
  818. #define __FSMC_PCCARD_ENABLE(__INSTANCE__)  SET_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
  819.  
  820. /**
  821.   * @brief  Disable the PCCARD device access.
  822.   * @param  __INSTANCE__ FSMC_PCCARD Instance
  823.   * @retval None
  824.   */
  825. #define __FSMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
  826. /**
  827.   * @}
  828.   */
  829.  
  830. /** @defgroup FSMC_Interrupt FSMC Interrupt
  831.  *  @brief macros to handle FSMC interrupts
  832.  * @{
  833.  */
  834.  
  835. /**
  836.   * @brief  Enable the NAND device interrupt.
  837.   * @param  __INSTANCE__  FSMC_NAND Instance
  838.   * @param  __BANK__      FSMC_NAND Bank
  839.   * @param  __INTERRUPT__ FSMC_NAND interrupt
  840.   *         This parameter can be any combination of the following values:
  841.   *            @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
  842.   *            @arg FSMC_IT_LEVEL Interrupt level.
  843.   *            @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
  844.   * @retval None
  845.   */
  846. #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
  847.                                                                                                         SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
  848.  
  849. /**
  850.   * @brief  Disable the NAND device interrupt.
  851.   * @param  __INSTANCE__  FSMC_NAND Instance
  852.   * @param  __BANK__      FSMC_NAND Bank
  853.   * @param  __INTERRUPT__ FSMC_NAND interrupt
  854.   *         This parameter can be any combination of the following values:
  855.   *            @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
  856.   *            @arg FSMC_IT_LEVEL Interrupt level.
  857.   *            @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
  858.   * @retval None
  859.   */
  860. #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
  861.                                                                                                          CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
  862.  
  863. /**
  864.   * @brief  Get flag status of the NAND device.
  865.   * @param  __INSTANCE__ FSMC_NAND Instance
  866.   * @param  __BANK__     FSMC_NAND Bank
  867.   * @param  __FLAG__ FSMC_NAND flag
  868.   *         This parameter can be any combination of the following values:
  869.   *            @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
  870.   *            @arg FSMC_FLAG_LEVEL Interrupt level edge flag.
  871.   *            @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
  872.   *            @arg FSMC_FLAG_FEMPT FIFO empty flag.
  873.   * @retval The state of FLAG (SET or RESET).
  874.   */
  875. #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
  876.                                                                                                    (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
  877.  
  878. /**
  879.   * @brief  Clear flag status of the NAND device.
  880.   * @param  __INSTANCE__ FSMC_NAND Instance
  881.   * @param  __BANK__     FSMC_NAND Bank
  882.   * @param  __FLAG__ FSMC_NAND flag
  883.   *         This parameter can be any combination of the following values:
  884.   *            @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
  885.   *            @arg FSMC_FLAG_LEVEL Interrupt level edge flag.
  886.   *            @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
  887.   *            @arg FSMC_FLAG_FEMPT FIFO empty flag.
  888.   * @retval None
  889.   */
  890. #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
  891.                                                                                                     CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
  892.  
  893. /**
  894.   * @brief  Enable the PCCARD device interrupt.
  895.   * @param  __INSTANCE__ FSMC_PCCARD Instance
  896.   * @param  __INTERRUPT__ FSMC_PCCARD interrupt
  897.   *         This parameter can be any combination of the following values:
  898.   *            @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
  899.   *            @arg FSMC_IT_LEVEL Interrupt level.
  900.   *            @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
  901.   * @retval None
  902.   */
  903. #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
  904.  
  905. /**
  906.   * @brief  Disable the PCCARD device interrupt.
  907.   * @param  __INSTANCE__ FSMC_PCCARD Instance
  908.   * @param  __INTERRUPT__ FSMC_PCCARD interrupt
  909.   *         This parameter can be any combination of the following values:
  910.   *            @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
  911.   *            @arg FSMC_IT_LEVEL Interrupt level.
  912.   *            @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
  913.   * @retval None
  914.   */
  915. #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
  916.  
  917. /**
  918.   * @brief  Get flag status of the PCCARD device.
  919.   * @param  __INSTANCE__ FSMC_PCCARD Instance
  920.   * @param  __FLAG__ FSMC_PCCARD flag
  921.   *         This parameter can be any combination of the following values:
  922.   *            @arg  FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
  923.   *            @arg  FSMC_FLAG_LEVEL Interrupt level edge flag.
  924.   *            @arg  FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
  925.   *            @arg  FSMC_FLAG_FEMPT FIFO empty flag.
  926.   * @retval The state of FLAG (SET or RESET).
  927.   */
  928. #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
  929.  
  930. /**
  931.   * @brief  Clear flag status of the PCCARD device.
  932.   * @param  __INSTANCE__ FSMC_PCCARD Instance
  933.   * @param  __FLAG__ FSMC_PCCARD flag
  934.   *         This parameter can be any combination of the following values:
  935.   *            @arg  FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
  936.   *            @arg  FSMC_FLAG_LEVEL Interrupt level edge flag.
  937.   *            @arg  FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
  938.   *            @arg  FSMC_FLAG_FEMPT FIFO empty flag.
  939.   * @retval None
  940.   */
  941. #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__)  CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
  942.  
  943. /**
  944.   * @}
  945.   */
  946.  
  947. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  948.  
  949. /**
  950.   * @}
  951.   */
  952.  
  953. /* Exported functions --------------------------------------------------------*/
  954.  
  955. /** @addtogroup FSMC_LL_Exported_Functions
  956.  *  @{
  957.  */
  958.  
  959. /** @addtogroup FSMC_NORSRAM
  960.  *  @{
  961.  */
  962.  
  963. /** @addtogroup FSMC_NORSRAM_Group1
  964.  *  @{
  965.  */
  966.  
  967. /* FSMC_NORSRAM Controller functions ******************************************/
  968. /* Initialization/de-initialization functions */
  969. HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
  970. HAL_StatusTypeDef  FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
  971. HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
  972. HAL_StatusTypeDef  FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
  973.  
  974. /**
  975.   * @}
  976.   */
  977.  
  978. /** @addtogroup FSMC_NORSRAM_Group2
  979.  *  @{
  980.  */
  981.  
  982. /* FSMC_NORSRAM Control functions */
  983. HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
  984. HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
  985.  
  986. /**
  987.   * @}
  988.   */
  989.  
  990. /**
  991.   * @}
  992.   */
  993.  
  994. #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
  995. /** @addtogroup FSMC_NAND
  996.  *  @{
  997.  */
  998.  
  999. /* FSMC_NAND Controller functions **********************************************/
  1000. /* Initialization/de-initialization functions */
  1001. /** @addtogroup FSMC_NAND_Exported_Functions_Group1
  1002.  *  @{
  1003.  */
  1004.  
  1005. HAL_StatusTypeDef  FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
  1006. HAL_StatusTypeDef  FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
  1007. HAL_StatusTypeDef  FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
  1008. HAL_StatusTypeDef  FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
  1009.  
  1010. /**
  1011.   * @}
  1012.   */
  1013.  
  1014. /* FSMC_NAND Control functions */
  1015. /** @addtogroup FSMC_NAND_Exported_Functions_Group2
  1016.  *  @{
  1017.  */
  1018.  
  1019. HAL_StatusTypeDef  FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
  1020. HAL_StatusTypeDef  FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
  1021. HAL_StatusTypeDef  FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
  1022.  
  1023. /**
  1024.   * @}
  1025.   */
  1026.  
  1027. /**
  1028.   * @}
  1029.   */
  1030.  
  1031. /** @addtogroup FSMC_PCCARD
  1032.  *  @{
  1033.  */
  1034.  
  1035. /* FSMC_PCCARD Controller functions ********************************************/
  1036. /* Initialization/de-initialization functions */
  1037. /** @addtogroup FSMC_PCCARD_Exported_Functions_Group1
  1038.  *  @{
  1039.  */
  1040.  
  1041. HAL_StatusTypeDef  FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
  1042. HAL_StatusTypeDef  FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
  1043. HAL_StatusTypeDef  FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
  1044. HAL_StatusTypeDef  FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
  1045. HAL_StatusTypeDef  FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
  1046.  
  1047. /**
  1048.   * @}
  1049.   */
  1050.  
  1051. /**
  1052.   * @}
  1053.   */
  1054.  
  1055. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  1056. /**
  1057.   * @}
  1058.   */
  1059.  
  1060. /**
  1061.   * @}
  1062.   */
  1063.  
  1064. #endif /* FSMC_BANK1 */
  1065.  
  1066. /**
  1067.   * @}
  1068.   */
  1069.  
  1070. #ifdef __cplusplus
  1071. }
  1072. #endif
  1073.  
  1074. #endif /* __STM32F1xx_LL_FSMC_H */
  1075.  
  1076. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1077.  
  1078.