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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_fsmc.h
  4.   * @author  MCD Application Team
  5.   * @version V1.0.1
  6.   * @date    31-July-2015
  7.   * @brief   Header file of FSMC HAL module.
  8.   ******************************************************************************
  9.   * @attention
  10.   *
  11.   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  12.   *
  13.   * Redistribution and use in source and binary forms, with or without modification,
  14.   * are permitted provided that the following conditions are met:
  15.   *   1. Redistributions of source code must retain the above copyright notice,
  16.   *      this list of conditions and the following disclaimer.
  17.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18.   *      this list of conditions and the following disclaimer in the documentation
  19.   *      and/or other materials provided with the distribution.
  20.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21.   *      may be used to endorse or promote products derived from this software
  22.   *      without specific prior written permission.
  23.   *
  24.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34.   *
  35.   ******************************************************************************
  36.   */
  37.  
  38. /* Define to prevent recursive inclusion -------------------------------------*/
  39. #ifndef __STM32F1xx_LL_FSMC_H
  40. #define __STM32F1xx_LL_FSMC_H
  41.  
  42. #ifdef __cplusplus
  43.  extern "C" {
  44. #endif
  45.  
  46. /* Includes ------------------------------------------------------------------*/
  47. #include "stm32f1xx_hal_def.h"
  48.  
  49. /** @addtogroup STM32F1xx_HAL_Driver
  50.   * @{
  51.   */
  52.  
  53. #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
  54.  
  55. /** @addtogroup FSMC_LL
  56.   * @{
  57.   */
  58.  
  59. /** @addtogroup FSMC_LL_Private_Macros
  60.   * @{
  61.   */
  62.  
  63. #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
  64.                                         ((__BANK__) == FSMC_NORSRAM_BANK2) || \
  65.                                         ((__BANK__) == FSMC_NORSRAM_BANK3) || \
  66.                                         ((__BANK__) == FSMC_NORSRAM_BANK4))
  67.  
  68. #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
  69.                               ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
  70.  
  71. #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
  72.                                     ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
  73.                                     ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
  74.  
  75. #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
  76.                                                  ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
  77.                                                  ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
  78.  
  79. #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
  80.                                        ((__MODE__) == FSMC_ACCESS_MODE_B) || \
  81.                                        ((__MODE__) == FSMC_ACCESS_MODE_C) || \
  82.                                        ((__MODE__) == FSMC_ACCESS_MODE_D))
  83.  
  84. #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
  85.                                 ((BANK) == FSMC_NAND_BANK3))
  86.  
  87. #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
  88.                                       ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
  89.  
  90. #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
  91.                                          ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
  92.                                          
  93. #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
  94.                                  ((STATE) == FSMC_NAND_ECC_ENABLE))
  95.                                  
  96. #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
  97.                                    ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
  98.                                    ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
  99.                                    ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
  100.                                    ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
  101.                                    ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
  102. /** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time
  103.   * @{
  104.   */
  105. #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
  106. /**
  107.   * @}
  108.   */
  109.  
  110. /** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time
  111.   * @{
  112.   */
  113. #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
  114. /**
  115.   * @}
  116.   */
  117.  
  118. /** @defgroup FSMC_Setup_Time FSMC_Setup_Time
  119.   * @{
  120.   */
  121. #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
  122. /**
  123.   * @}
  124.   */
  125.  
  126. /** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time
  127.   * @{
  128.   */
  129. #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
  130. /**
  131.   * @}
  132.   */
  133.  
  134. /** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time
  135.   * @{
  136.   */
  137. #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
  138. /**
  139.   * @}
  140.   */
  141.  
  142. /** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time
  143.   * @{
  144.   */
  145. #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
  146. /**
  147.   * @}
  148.   */  
  149.    
  150. /** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
  151.   * @{
  152.   */
  153.  
  154. #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
  155.  
  156. /**
  157.   * @}
  158.   */
  159.  
  160. /** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
  161.   * @{
  162.   */
  163.  
  164. #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
  165.  
  166. /**
  167.   * @}
  168.   */
  169.  
  170. /** @defgroup FSMC_NAND_Device_Instance FSMC_NAND_Device_Instance
  171.   * @{
  172.   */
  173. #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
  174. /**
  175.   * @}
  176.   */  
  177.  
  178. /** @defgroup FSMC_PCCARD_Device_Instance FSMC_PCCARD_Device_Instance
  179.   * @{
  180.   */
  181. #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
  182.  
  183. /**
  184.   * @}
  185.   */
  186.  
  187. #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
  188.                                       ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
  189.  
  190. #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
  191.                                              ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
  192.  
  193. #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
  194.                                      ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
  195.  
  196. #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
  197.                                                 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
  198.  
  199. #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
  200.                                                 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))                        
  201.  
  202. #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
  203.                                           ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
  204.  
  205. #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
  206.                                          ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
  207.  
  208. #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
  209.                                      ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
  210.  
  211. #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
  212.  
  213. /** @defgroup FSMC_Data_Latency FSMC Data Latency
  214.   * @{
  215.   */
  216.  
  217. #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
  218. /**
  219.   * @}
  220.   */  
  221.  
  222. #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
  223.                                         ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
  224. /** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
  225.   * @{
  226.   */
  227.  
  228. #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
  229. /**
  230.   * @}
  231.   */
  232.  
  233. /** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
  234.   * @{
  235.   */
  236.  
  237. #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
  238. /**
  239.   * @}
  240.   */
  241.  
  242. /** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
  243.   * @{
  244.   */
  245.  
  246. #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
  247. /**
  248.   * @}
  249.   */
  250.  
  251. /** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
  252.   * @{
  253.   */
  254.  
  255. #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
  256. /**
  257.   * @}
  258.   */
  259.  
  260. /**
  261.   * @}
  262.   */
  263.  
  264. /* Exported typedef ----------------------------------------------------------*/
  265.  
  266. /** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types
  267.   * @{
  268.   */
  269.  
  270. #define FSMC_NORSRAM_TypeDef            FSMC_Bank1_TypeDef
  271. #define FSMC_NORSRAM_EXTENDED_TypeDef   FSMC_Bank1E_TypeDef
  272. #define FSMC_NAND_TypeDef               FSMC_Bank2_3_TypeDef
  273. #define FSMC_PCCARD_TypeDef             FSMC_Bank4_TypeDef
  274.  
  275. #define FSMC_NORSRAM_DEVICE             FSMC_Bank1            
  276. #define FSMC_NORSRAM_EXTENDED_DEVICE    FSMC_Bank1E  
  277. #define FSMC_NAND_DEVICE                FSMC_Bank2_3            
  278. #define FSMC_PCCARD_DEVICE              FSMC_Bank4            
  279.  
  280. /**
  281.   * @brief  FSMC_NORSRAM Configuration Structure definition  
  282.   */
  283. typedef struct
  284. {
  285.   uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
  286.                                               This parameter can be a value of @ref FSMC_NORSRAM_Bank                     */  
  287.                                                    
  288.   uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
  289.                                               multiplexed on the data bus or not.
  290.                                               This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing    */
  291.  
  292.   uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
  293.                                               the corresponding memory device.
  294.                                               This parameter can be a value of @ref FSMC_Memory_Type                      */
  295.                                              
  296.   uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
  297.                                               This parameter can be a value of @ref FSMC_NORSRAM_Data_Width               */
  298.  
  299.   uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
  300.                                               valid only with synchronous burst Flash memories.
  301.                                               This parameter can be a value of @ref FSMC_Burst_Access_Mode                */
  302.                                                
  303.   uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
  304.                                               the Flash memory in burst mode.
  305.                                               This parameter can be a value of @ref FSMC_Wait_Signal_Polarity             */
  306.  
  307.   uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
  308.                                               memory, valid only when accessing Flash memories in burst mode.
  309.                                               This parameter can be a value of @ref FSMC_Wrap_Mode                        */
  310.  
  311.   uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
  312.                                               clock cycle before the wait state or during the wait state,
  313.                                               valid only when accessing memories in burst mode.
  314.                                               This parameter can be a value of @ref FSMC_Wait_Timing                      */
  315.  
  316.   uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FSMC.
  317.                                               This parameter can be a value of @ref FSMC_Write_Operation                  */
  318.  
  319.   uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
  320.                                               signal, valid for Flash memory access in burst mode.
  321.                                               This parameter can be a value of @ref FSMC_Wait_Signal                      */
  322.  
  323.   uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
  324.                                               This parameter can be a value of @ref FSMC_Extended_Mode                    */
  325.  
  326.   uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
  327.                                               valid only with asynchronous Flash memories.
  328.                                               This parameter can be a value of @ref FSMC_AsynchronousWait                 */
  329.  
  330.   uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
  331.                                               This parameter can be a value of @ref FSMC_Write_Burst                      */                                    
  332.  
  333. }FSMC_NORSRAM_InitTypeDef;
  334.  
  335.  
  336. /**
  337.   * @brief  FSMC_NORSRAM Timing parameters structure definition  
  338.   */
  339. typedef struct
  340. {
  341.   uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
  342.                                               the duration of the address setup time.
  343.                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
  344.                                               @note This parameter is not used with synchronous NOR Flash memories.      */
  345.  
  346.   uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
  347.                                               the duration of the address hold time.
  348.                                               This parameter can be a value between Min_Data = 1 and Max_Data = 15.
  349.                                               @note This parameter is not used with synchronous NOR Flash memories.      */
  350.  
  351.   uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
  352.                                               the duration of the data setup time.
  353.                                               This parameter can be a value between Min_Data = 1 and Max_Data = 255.
  354.                                               @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
  355.                                               NOR Flash memories.                                                        */
  356.  
  357.   uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
  358.                                               the duration of the bus turnaround.
  359.                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
  360.                                               @note This parameter is only used for multiplexed NOR Flash memories.      */
  361.  
  362.   uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
  363.                                               HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
  364.                                               @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
  365.                                               accesses.                                                                  */
  366.  
  367.   uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
  368.                                               to the memory before getting the first data.
  369.                                               The parameter value depends on the memory type as shown below:
  370.                                               - It must be set to 0 in case of a CRAM
  371.                                               - It is don't care in asynchronous NOR, SRAM or ROM accesses
  372.                                               - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
  373.                                                 with synchronous burst mode enable                                       */
  374.  
  375.   uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
  376.                                               This parameter can be a value of @ref FSMC_Access_Mode                      */
  377.  
  378. }FSMC_NORSRAM_TimingTypeDef;
  379.  
  380. #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  381. /**
  382.   * @brief  FSMC_NAND Configuration Structure definition  
  383.   */
  384. typedef struct
  385. {
  386.   uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
  387.                                         This parameter can be a value of @ref FSMC_NAND_Bank                    */          
  388.  
  389.   uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
  390.                                         This parameter can be any value of @ref FSMC_Wait_feature               */
  391.  
  392.   uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
  393.                                         This parameter can be any value of @ref FSMC_NAND_Data_Width            */
  394.  
  395.   uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
  396.                                         This parameter can be any value of @ref FSMC_ECC                        */
  397.  
  398.   uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
  399.                                         This parameter can be any value of @ref FSMC_ECC_Page_Size              */
  400.  
  401.   uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
  402.                                         delay between CLE low and RE low.
  403.                                         This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
  404.  
  405.   uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
  406.                                         delay between ALE low and RE low.
  407.                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
  408.                                      
  409. }FSMC_NAND_InitTypeDef;  
  410.  
  411. /**
  412.   * @brief  FSMC_NAND_PCCARD Timing parameters structure definition
  413.   */
  414. typedef struct
  415. {
  416.   uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
  417.                                       the command assertion for NAND-Flash read or write access
  418.                                       to common/Attribute or I/O memory space (depending on
  419.                                       the memory space timing to be configured).
  420.                                       This parameter can be a value between Min_Data = 0 and Max_Data = 255    */
  421.  
  422.   uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
  423.                                       command for NAND-Flash read or write access to
  424.                                       common/Attribute or I/O memory space (depending on the
  425.                                       memory space timing to be configured).
  426.                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
  427.  
  428.   uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
  429.                                       (and data for write access) after the command de-assertion
  430.                                       for NAND-Flash read or write access to common/Attribute
  431.                                       or I/O memory space (depending on the memory space timing
  432.                                       to be configured).
  433.                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
  434.  
  435.   uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
  436.                                       data bus is kept in HiZ after the start of a NAND-Flash
  437.                                       write access to common/Attribute or I/O memory space (depending
  438.                                       on the memory space timing to be configured).
  439.                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
  440.  
  441. }FSMC_NAND_PCC_TimingTypeDef;
  442.  
  443. /**
  444.   * @brief  FSMC_NAND Configuration Structure definition  
  445.   */
  446. typedef struct
  447. {
  448.   uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the PCCARD Memory device.
  449.                                         This parameter can be any value of @ref FSMC_Wait_feature               */
  450.  
  451.   uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
  452.                                         delay between CLE low and RE low.
  453.                                         This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
  454.  
  455.   uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
  456.                                         delay between ALE low and RE low.
  457.                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
  458.                                      
  459. }FSMC_PCCARD_InitTypeDef;  
  460.  
  461. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  462. /**
  463.   * @}
  464.   */
  465.  
  466. /* Exported constants --------------------------------------------------------*/
  467.  
  468. /** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants
  469.   * @{
  470.   */
  471.  
  472. /** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
  473.   * @{
  474.   */
  475.  
  476. /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
  477.   * @{
  478.   */
  479. #define FSMC_NORSRAM_BANK1                       ((uint32_t)0x00000000)
  480. #define FSMC_NORSRAM_BANK2                       ((uint32_t)0x00000002)
  481. #define FSMC_NORSRAM_BANK3                       ((uint32_t)0x00000004)
  482. #define FSMC_NORSRAM_BANK4                       ((uint32_t)0x00000006)
  483.  
  484. /**
  485.   * @}
  486.   */
  487.  
  488. /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
  489.   * @{
  490.   */
  491.  
  492. #define FSMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
  493. #define FSMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)FSMC_BCRx_MUXEN)
  494.  
  495. /**
  496.   * @}
  497.   */
  498.  
  499. /** @defgroup FSMC_Memory_Type FSMC Memory Type
  500.   * @{
  501.   */
  502.  
  503. #define FSMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)
  504. #define FSMC_MEMORY_TYPE_PSRAM                   ((uint32_t)FSMC_BCRx_MTYP_0)
  505. #define FSMC_MEMORY_TYPE_NOR                     ((uint32_t)FSMC_BCRx_MTYP_1)
  506.  
  507.  
  508. /**
  509.   * @}
  510.   */
  511.  
  512. /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
  513.   * @{
  514.   */
  515.  
  516. #define FSMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
  517. #define FSMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)FSMC_BCRx_MWID_0)
  518. #define FSMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)FSMC_BCRx_MWID_1)
  519.  
  520. /**
  521.   * @}
  522.   */
  523.  
  524. /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
  525.   * @{
  526.   */
  527.  
  528. #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)FSMC_BCRx_FACCEN)
  529. #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)
  530. /**
  531.   * @}
  532.   */
  533.  
  534. /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
  535.   * @{
  536.   */
  537.  
  538. #define FSMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000)
  539. #define FSMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)FSMC_BCRx_BURSTEN)
  540.  
  541. /**
  542.   * @}
  543.   */
  544.    
  545.  
  546. /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
  547.   * @{
  548.   */
  549.  
  550. #define FSMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
  551. #define FSMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)FSMC_BCRx_WAITPOL)
  552.  
  553. /**
  554.   * @}
  555.   */
  556.  
  557. /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
  558.   * @{
  559.   */
  560.  
  561. #define FSMC_WRAP_MODE_DISABLE                   ((uint32_t)0x00000000)
  562. #define FSMC_WRAP_MODE_ENABLE                    ((uint32_t)FSMC_BCRx_WRAPMOD)
  563.  
  564. /**
  565.   * @}
  566.   */
  567.  
  568. /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
  569.   * @{
  570.   */
  571.  
  572. #define FSMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
  573. #define FSMC_WAIT_TIMING_DURING_WS               ((uint32_t)FSMC_BCRx_WAITCFG)
  574.  
  575. /**
  576.   * @}
  577.   */
  578.  
  579. /** @defgroup FSMC_Write_Operation FSMC Write Operation
  580.   * @{
  581.   */
  582.  
  583. #define FSMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
  584. #define FSMC_WRITE_OPERATION_ENABLE              ((uint32_t)FSMC_BCRx_WREN)
  585.  
  586. /**
  587.   * @}
  588.   */
  589.  
  590. /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
  591.   * @{
  592.   */
  593.  
  594. #define FSMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
  595. #define FSMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)FSMC_BCRx_WAITEN)
  596.  
  597. /**
  598.   * @}
  599.   */
  600.  
  601. /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
  602.   * @{
  603.   */
  604.  
  605. #define FSMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
  606. #define FSMC_EXTENDED_MODE_ENABLE                ((uint32_t)FSMC_BCRx_EXTMOD)
  607.  
  608. /**
  609.   * @}
  610.   */
  611.  
  612. /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
  613.   * @{
  614.   */
  615.  
  616. #define FSMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
  617. #define FSMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)FSMC_BCRx_ASYNCWAIT)
  618.  
  619. /**
  620.   * @}
  621.   */  
  622.  
  623. /** @defgroup FSMC_Write_Burst FSMC Write Burst
  624.   * @{
  625.   */
  626.  
  627. #define FSMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
  628. #define FSMC_WRITE_BURST_ENABLE                  ((uint32_t)FSMC_BCRx_CBURSTRW)
  629.  
  630. /**
  631.   * @}
  632.   */
  633.  
  634. /** @defgroup FSMC_Access_Mode FSMC Access Mode
  635.   * @{
  636.   */
  637.  
  638. #define FSMC_ACCESS_MODE_A                        ((uint32_t)0x00000000)
  639. #define FSMC_ACCESS_MODE_B                        ((uint32_t)FSMC_BTRx_ACCMOD_0)
  640. #define FSMC_ACCESS_MODE_C                        ((uint32_t)FSMC_BTRx_ACCMOD_1)
  641. #define FSMC_ACCESS_MODE_D                        ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1))
  642.  
  643. /**
  644.   * @}
  645.   */
  646.    
  647.  
  648. /**
  649.   * @}
  650.   */
  651.  
  652. #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  653. /** @defgroup FSMC_NAND_Controller FSMC NAND and PCCARD Controller
  654.   * @{
  655.   */
  656.  
  657. /** @defgroup FSMC_NAND_Bank FSMC_NAND_Bank
  658.   * @{
  659.   */  
  660. #define FSMC_NAND_BANK2                          ((uint32_t)0x00000010)
  661. #define FSMC_NAND_BANK3                          ((uint32_t)0x00000100)
  662.  
  663. /**
  664.   * @}
  665.   */
  666.  
  667. /** @defgroup FSMC_Wait_feature FSMC_Wait_feature
  668.   * @{
  669.   */
  670. #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000)
  671. #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE            ((uint32_t)0x00000002)
  672.  
  673. /**
  674.   * @}
  675.   */
  676.  
  677. /** @defgroup FSMC_PCR_Memory_Type FSMC_PCR_Memory_Type
  678.   * @{
  679.   */
  680. #define FSMC_PCR_MEMORY_TYPE_PCCARD        ((uint32_t)0x00000000)
  681. #define FSMC_PCR_MEMORY_TYPE_NAND          ((uint32_t)FSMC_PCRx_PTYP)
  682. /**
  683.   * @}
  684.   */
  685.  
  686. /** @defgroup FSMC_NAND_Data_Width FSMC_NAND_Data_Width
  687.   * @{
  688.   */
  689. #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000)
  690. #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16               ((uint32_t)FSMC_PCRx_PWID_0)
  691.  
  692. /**
  693.   * @}
  694.   */
  695.  
  696. /** @defgroup FSMC_ECC FSMC_ECC
  697.   * @{
  698.   */
  699. #define FSMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000)
  700. #define FSMC_NAND_ECC_ENABLE                     ((uint32_t)FSMC_PCRx_ECCEN)
  701.  
  702. /**
  703.   * @}
  704.   */
  705.  
  706. /** @defgroup FSMC_ECC_Page_Size FSMC_ECC_Page_Size
  707.   * @{
  708.   */
  709. #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000)
  710. #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)FSMC_PCRx_ECCPS_0)
  711. #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)FSMC_PCRx_ECCPS_1)
  712. #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_1)
  713. #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)FSMC_PCRx_ECCPS_2)
  714. #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_2)
  715.  
  716. /**
  717.   * @}
  718.   */
  719.  
  720. /** @defgroup FSMC_Interrupt_definition FSMC_Interrupt_definition
  721.   * @brief FSMC Interrupt definition
  722.   * @{
  723.   */  
  724. #define FSMC_IT_RISING_EDGE                ((uint32_t)FSMC_SRx_IREN)
  725. #define FSMC_IT_LEVEL                      ((uint32_t)FSMC_SRx_ILEN)
  726. #define FSMC_IT_FALLING_EDGE               ((uint32_t)FSMC_SRx_IFEN)
  727.  
  728. /**
  729.   * @}
  730.   */
  731.    
  732. /** @defgroup FSMC_Flag_definition FSMC_Flag_definition
  733.   * @brief FSMC Flag definition
  734.   * @{
  735.   */
  736. #define FSMC_FLAG_RISING_EDGE                    ((uint32_t)FSMC_SRx_IRS)
  737. #define FSMC_FLAG_LEVEL                          ((uint32_t)FSMC_SRx_ILS)
  738. #define FSMC_FLAG_FALLING_EDGE                   ((uint32_t)FSMC_SRx_IFS)
  739. #define FSMC_FLAG_FEMPT                          ((uint32_t)FSMC_SRx_FEMPT)
  740.  
  741. /**
  742.   * @}
  743.   */
  744.  
  745. /**
  746.   * @}
  747.   */
  748. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  749.  
  750. /**
  751.   * @}
  752.   */
  753.  
  754. /* Exported macro ------------------------------------------------------------*/
  755.  
  756. /** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros
  757.   * @{
  758.   */
  759.  
  760. /** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros
  761.  *  @brief macros to handle NOR device enable/disable and read/write operations
  762.  *  @{
  763.  */
  764.  
  765. /**
  766.   * @brief  Enable the NORSRAM device access.
  767.   * @param  __INSTANCE__: FSMC_NORSRAM Instance
  768.   * @param  __BANK__: FSMC_NORSRAM Bank    
  769.   * @retval none
  770.   */
  771. #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
  772.  
  773. /**
  774.   * @brief  Disable the NORSRAM device access.
  775.   * @param  __INSTANCE__: FSMC_NORSRAM Instance
  776.   * @param  __BANK__: FSMC_NORSRAM Bank  
  777.   * @retval none
  778.   */
  779. #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
  780.  
  781. /**
  782.   * @}
  783.   */
  784.  
  785. #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  786. /** @defgroup FSMC_NAND_Macros FSMC_NAND_Macros
  787.  *  @brief macros to handle NAND device enable/disable
  788.  *  @{
  789.  */
  790.  
  791. /**
  792.   * @brief  Enable the NAND device access.
  793.   * @param  __INSTANCE__: FSMC_NAND Instance
  794.   * @param  __BANK__: FSMC_NAND Bank    
  795.   * @retval None
  796.   */  
  797. #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__)  (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
  798.                                                     SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))                                        
  799.  
  800. /**
  801.   * @brief  Disable the NAND device access.
  802.   * @param  __INSTANCE__: FSMC_NAND Instance
  803.   * @param  __BANK__: FSMC_NAND Bank  
  804.   * @retval None
  805.   */                                          
  806. #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
  807.                                                    CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))                                                                                
  808. /**
  809.   * @}
  810.   */
  811.  
  812. /** @defgroup FSMC_PCCARD_Macros FSMC_PCCARD_Macros
  813.  *  @brief macros to handle SRAM read/write operations
  814.  *  @{
  815.  */
  816.  
  817. /**
  818.   * @brief  Enable the PCCARD device access.
  819.   * @param  __INSTANCE__: FSMC_PCCARD Instance  
  820.   * @retval None
  821.   */
  822. #define __FSMC_PCCARD_ENABLE(__INSTANCE__)  SET_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
  823.  
  824. /**
  825.   * @brief  Disable the PCCARD device access.
  826.   * @param  __INSTANCE__: FSMC_PCCARD Instance    
  827.   * @retval None
  828.   */
  829. #define __FSMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
  830. /**
  831.   * @}
  832.   */
  833.  
  834. /** @defgroup FSMC_Interrupt FSMC_Interrupt
  835.  *  @brief macros to handle FSMC interrupts
  836.  * @{
  837.  */
  838.  
  839. /**
  840.   * @brief  Enable the NAND device interrupt.
  841.   * @param  __INSTANCE__:  FSMC_NAND Instance
  842.   * @param  __BANK__:      FSMC_NAND Bank    
  843.   * @param  __INTERRUPT__: FSMC_NAND interrupt
  844.   *         This parameter can be any combination of the following values:
  845.   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
  846.   *            @arg FSMC_IT_LEVEL: Interrupt level.
  847.   *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.      
  848.   * @retval None
  849.   */  
  850. #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
  851.                                                                                                         SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
  852.  
  853. /**
  854.   * @brief  Disable the NAND device interrupt.
  855.   * @param  __INSTANCE__:  FSMC_NAND Instance
  856.   * @param  __BANK__:      FSMC_NAND Bank    
  857.   * @param  __INTERRUPT__: FSMC_NAND interrupt
  858.   *         This parameter can be any combination of the following values:
  859.   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
  860.   *            @arg FSMC_IT_LEVEL: Interrupt level.
  861.   *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.  
  862.   * @retval None
  863.   */
  864. #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
  865.                                                                                                          CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
  866.                                                                                                                              
  867. /**
  868.   * @brief  Get flag status of the NAND device.
  869.   * @param  __INSTANCE__: FSMC_NAND Instance
  870.   * @param  __BANK__:     FSMC_NAND Bank      
  871.   * @param  __FLAG__: FSMC_NAND flag
  872.   *         This parameter can be any combination of the following values:
  873.   *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
  874.   *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
  875.   *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
  876.   *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.  
  877.   * @retval The state of FLAG (SET or RESET).
  878.   */
  879. #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
  880.                                                                                                    (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
  881. /**
  882.   * @brief  Clear flag status of the NAND device.
  883.   * @param  __INSTANCE__: FSMC_NAND Instance  
  884.   * @param  __BANK__:     FSMC_NAND Bank  
  885.   * @param  __FLAG__: FSMC_NAND flag
  886.   *         This parameter can be any combination of the following values:
  887.   *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
  888.   *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
  889.   *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
  890.   *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.  
  891.   * @retval None
  892.   */
  893. #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
  894.                                                                                                     CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
  895. /**
  896.   * @brief  Enable the PCCARD device interrupt.
  897.   * @param  __INSTANCE__: FSMC_PCCARD Instance  
  898.   * @param  __INTERRUPT__: FSMC_PCCARD interrupt
  899.   *         This parameter can be any combination of the following values:
  900.   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
  901.   *            @arg FSMC_IT_LEVEL: Interrupt level.
  902.   *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.      
  903.   * @retval None
  904.   */
  905. #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
  906.  
  907. /**
  908.   * @brief  Disable the PCCARD device interrupt.
  909.   * @param  __INSTANCE__: FSMC_PCCARD Instance  
  910.   * @param  __INTERRUPT__: FSMC_PCCARD interrupt
  911.   *         This parameter can be any combination of the following values:
  912.   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
  913.   *            @arg FSMC_IT_LEVEL: Interrupt level.
  914.   *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.      
  915.   * @retval None
  916.   */
  917. #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
  918.  
  919. /**
  920.   * @brief  Get flag status of the PCCARD device.
  921.   * @param  __INSTANCE__: FSMC_PCCARD Instance  
  922.   * @param  __FLAG__: FSMC_PCCARD flag
  923.   *         This parameter can be any combination of the following values:
  924.   *            @arg  FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
  925.   *            @arg  FSMC_FLAG_LEVEL: Interrupt level edge flag.
  926.   *            @arg  FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
  927.   *            @arg  FSMC_FLAG_FEMPT: FIFO empty flag.  
  928.   * @retval The state of FLAG (SET or RESET).
  929.   */
  930. #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
  931.  
  932. /**
  933.   * @brief  Clear flag status of the PCCARD device.
  934.   * @param  __INSTANCE__: FSMC_PCCARD Instance  
  935.   * @param  __FLAG__: FSMC_PCCARD flag
  936.   *         This parameter can be any combination of the following values:
  937.   *            @arg  FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
  938.   *            @arg  FSMC_FLAG_LEVEL: Interrupt level edge flag.
  939.   *            @arg  FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
  940.   *            @arg  FSMC_FLAG_FEMPT: FIFO empty flag.  
  941.   * @retval None
  942.   */
  943. #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__)  CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
  944.  
  945. /**
  946.   * @}
  947.   */
  948.  
  949. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  950.  
  951. /**
  952.   * @}
  953.   */
  954.  
  955. /* Exported functions --------------------------------------------------------*/
  956.  
  957. /** @addtogroup FSMC_LL_Exported_Functions
  958.  *  @{
  959.  */
  960.  
  961. /** @addtogroup FSMC_NORSRAM
  962.  *  @{
  963.  */
  964.  
  965. /** @addtogroup FSMC_NORSRAM_Group1
  966.  *  @{
  967.  */
  968.  
  969. /* FSMC_NORSRAM Controller functions ******************************************/
  970. /* Initialization/de-initialization functions */
  971. HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
  972. HAL_StatusTypeDef  FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
  973. HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
  974. HAL_StatusTypeDef  FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
  975.  
  976. /**
  977.   * @}
  978.   */
  979.  
  980. /** @addtogroup FSMC_NORSRAM_Group2
  981.  *  @{
  982.  */
  983.  
  984. /* FSMC_NORSRAM Control functions */
  985. HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
  986. HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
  987.  
  988. /**
  989.   * @}
  990.   */
  991.  
  992. /**
  993.   * @}
  994.   */
  995.  
  996. #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  997. /** @addtogroup FSMC_NAND
  998.  *  @{
  999.  */
  1000.  
  1001. /* FSMC_NAND Controller functions **********************************************/
  1002. /* Initialization/de-initialization functions */
  1003. /** @addtogroup FSMC_NAND_Exported_Functions_Group1
  1004.  *  @{
  1005.  */
  1006.  
  1007. HAL_StatusTypeDef  FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
  1008. HAL_StatusTypeDef  FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
  1009. HAL_StatusTypeDef  FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
  1010. HAL_StatusTypeDef  FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
  1011.  
  1012. /**
  1013.   * @}
  1014.   */
  1015.  
  1016. /* FSMC_NAND Control functions */
  1017. /** @addtogroup FSMC_NAND_Exported_Functions_Group2
  1018.  *  @{
  1019.  */
  1020.  
  1021. HAL_StatusTypeDef  FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
  1022. HAL_StatusTypeDef  FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
  1023. HAL_StatusTypeDef  FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
  1024.  
  1025. /**
  1026.   * @}
  1027.   */
  1028.  
  1029. /**
  1030.   * @}
  1031.   */
  1032.  
  1033. /** @addtogroup FSMC_PCCARD
  1034.  *  @{
  1035.  */
  1036.  
  1037. /* FSMC_PCCARD Controller functions ********************************************/
  1038. /* Initialization/de-initialization functions */
  1039. /** @addtogroup FSMC_PCCARD_Exported_Functions_Group1
  1040.  *  @{
  1041.  */
  1042.  
  1043. HAL_StatusTypeDef  FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
  1044. HAL_StatusTypeDef  FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
  1045. HAL_StatusTypeDef  FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
  1046. HAL_StatusTypeDef  FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
  1047. HAL_StatusTypeDef  FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
  1048.  
  1049. /**
  1050.   * @}
  1051.   */
  1052.  
  1053. /**
  1054.   * @}
  1055.   */
  1056.  
  1057. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  1058.  
  1059. /**
  1060.   * @}
  1061.   */
  1062.  
  1063. /**
  1064.   * @}
  1065.   */
  1066.  
  1067. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
  1068.  
  1069. /**
  1070.   * @}
  1071.   */
  1072.  
  1073. #ifdef __cplusplus
  1074. }
  1075. #endif
  1076.  
  1077. #endif /* __STM32F1xx_LL_FSMC_H */
  1078.  
  1079. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1080.  
  1081.