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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_fsmc.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of FSMC HAL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10.   * All rights reserved.</center></h2>
  11.   *
  12.   * This software component is licensed by ST under BSD 3-Clause license,
  13.   * the "License"; You may not use this file except in compliance with the
  14.   * License. You may obtain a copy of the License at:
  15.   *                       opensource.org/licenses/BSD-3-Clause
  16.   *
  17.   ******************************************************************************
  18.   */
  19.  
  20. /* Define to prevent recursive inclusion -------------------------------------*/
  21. #ifndef STM32F1xx_LL_FSMC_H
  22. #define STM32F1xx_LL_FSMC_H
  23.  
  24. #ifdef __cplusplus
  25. extern "C" {
  26. #endif
  27.  
  28. /* Includes ------------------------------------------------------------------*/
  29. #include "stm32f1xx_hal_def.h"
  30.  
  31. /** @addtogroup STM32F1xx_HAL_Driver
  32.   * @{
  33.   */
  34.  
  35. /** @addtogroup FSMC_LL
  36.   * @{
  37.   */
  38.  
  39. /** @addtogroup FSMC_LL_Private_Macros
  40.   * @{
  41.   */
  42. #if defined(FSMC_BANK1)
  43.  
  44. #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
  45.                                        ((__BANK__) == FSMC_NORSRAM_BANK2) || \
  46.                                        ((__BANK__) == FSMC_NORSRAM_BANK3) || \
  47.                                        ((__BANK__) == FSMC_NORSRAM_BANK4))
  48. #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
  49.                              ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
  50. #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
  51.                                    ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
  52.                                    ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
  53. #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
  54.                                                 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
  55.                                                 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
  56. #define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \
  57.                                    ((__SIZE__) == FSMC_PAGE_SIZE_128) || \
  58.                                    ((__SIZE__) == FSMC_PAGE_SIZE_256) || \
  59.                                    ((__SIZE__) == FSMC_PAGE_SIZE_512) || \
  60.                                    ((__SIZE__) == FSMC_PAGE_SIZE_1024))
  61. #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
  62.                                       ((__MODE__) == FSMC_ACCESS_MODE_B) || \
  63.                                       ((__MODE__) == FSMC_ACCESS_MODE_C) || \
  64.                                       ((__MODE__) == FSMC_ACCESS_MODE_D))
  65. #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
  66.                                      ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
  67. #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
  68.                                             ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
  69. #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
  70.                                              ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
  71. #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
  72.                                                ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
  73. #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
  74.                                                ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
  75. #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
  76.                                          ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
  77. #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
  78.                                         ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
  79. #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
  80.                                     ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
  81. #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
  82. #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
  83.                                        ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
  84. #define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
  85.                                             ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
  86. #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
  87. #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
  88. #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
  89. #define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
  90. #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
  91. #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
  92. #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
  93. #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
  94.  
  95. #endif /* FSMC_BANK1 */
  96. #if defined(FSMC_BANK3)
  97.  
  98. #define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3)
  99. #define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
  100.                                                    ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
  101. #define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
  102.                                                       ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
  103. #define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
  104.                                      ((__STATE__) == FSMC_NAND_ECC_ENABLE))
  105.  
  106. #define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
  107.                                        ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
  108.                                        ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
  109.                                        ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
  110.                                        ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
  111.                                        ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
  112. #define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
  113. #define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
  114. #define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
  115. #define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
  116. #define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
  117. #define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
  118. #define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
  119.  
  120. #endif /* FSMC_BANK3 */
  121. #if defined(FSMC_BANK4)
  122. #define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
  123.  
  124. #endif /* FSMC_BANK4 */
  125.  
  126. /**
  127.   * @}
  128.   */
  129.  
  130. /* Exported typedef ----------------------------------------------------------*/
  131.  
  132. /** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types
  133.   * @{
  134.   */
  135.  
  136. #if defined(FSMC_BANK1)
  137. #define FSMC_NORSRAM_TypeDef            FSMC_Bank1_TypeDef
  138. #define FSMC_NORSRAM_EXTENDED_TypeDef   FSMC_Bank1E_TypeDef
  139. #endif /* FSMC_BANK1 */
  140. #if defined(FSMC_BANK3)
  141. #define FSMC_NAND_TypeDef               FSMC_Bank2_3_TypeDef
  142. #endif /* FSMC_BANK3 */
  143. #if defined(FSMC_BANK4)
  144. #define FSMC_PCCARD_TypeDef             FSMC_Bank4_TypeDef
  145. #endif /* FSMC_BANK4 */
  146.  
  147. #if defined(FSMC_BANK1)
  148. #define FSMC_NORSRAM_DEVICE             FSMC_Bank1
  149. #define FSMC_NORSRAM_EXTENDED_DEVICE    FSMC_Bank1E
  150. #endif /* FSMC_BANK1 */
  151. #if defined(FSMC_BANK3)
  152. #define FSMC_NAND_DEVICE                FSMC_Bank2_3
  153. #endif /* FSMC_BANK3 */
  154. #if defined(FSMC_BANK4)
  155. #define FSMC_PCCARD_DEVICE              FSMC_Bank4
  156. #endif /* FSMC_BANK4 */
  157.  
  158. #if defined(FSMC_BANK1)
  159. /**
  160.   * @brief  FSMC NORSRAM Configuration Structure definition
  161.   */
  162. typedef struct
  163. {
  164.   uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
  165.                                               This parameter can be a value of @ref FSMC_NORSRAM_Bank                  */
  166.  
  167.   uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
  168.                                               multiplexed on the data bus or not.
  169.                                               This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
  170.  
  171.   uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
  172.                                               the corresponding memory device.
  173.                                               This parameter can be a value of @ref FSMC_Memory_Type                   */
  174.  
  175.   uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
  176.                                               This parameter can be a value of @ref FSMC_NORSRAM_Data_Width            */
  177.  
  178.   uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
  179.                                               valid only with synchronous burst Flash memories.
  180.                                               This parameter can be a value of @ref FSMC_Burst_Access_Mode             */
  181.  
  182.   uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
  183.                                               the Flash memory in burst mode.
  184.                                               This parameter can be a value of @ref FSMC_Wait_Signal_Polarity          */
  185.  
  186.   uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
  187.                                               memory, valid only when accessing Flash memories in burst mode.
  188.                                               This parameter can be a value of @ref FSMC_Wrap_Mode                     */
  189.  
  190.   uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
  191.                                               clock cycle before the wait state or during the wait state,
  192.                                               valid only when accessing memories in burst mode.
  193.                                               This parameter can be a value of @ref FSMC_Wait_Timing                   */
  194.  
  195.   uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FSMC.
  196.                                               This parameter can be a value of @ref FSMC_Write_Operation               */
  197.  
  198.   uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
  199.                                               signal, valid for Flash memory access in burst mode.
  200.                                               This parameter can be a value of @ref FSMC_Wait_Signal                   */
  201.  
  202.   uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
  203.                                               This parameter can be a value of @ref FSMC_Extended_Mode                 */
  204.  
  205.   uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
  206.                                               valid only with asynchronous Flash memories.
  207.                                               This parameter can be a value of @ref FSMC_AsynchronousWait              */
  208.  
  209.   uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
  210.                                               This parameter can be a value of @ref FSMC_Write_Burst                   */
  211.  
  212.  
  213.   uint32_t PageSize;                     /*!< Specifies the memory page size.
  214.                                               This parameter can be a value of @ref FSMC_Page_Size                     */
  215. } FSMC_NORSRAM_InitTypeDef;
  216.  
  217. /**
  218.   * @brief  FSMC NORSRAM Timing parameters structure definition
  219.   */
  220. typedef struct
  221. {
  222.   uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
  223.                                               the duration of the address setup time.
  224.                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
  225.                                               @note This parameter is not used with synchronous NOR Flash memories.   */
  226.  
  227.   uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
  228.                                               the duration of the address hold time.
  229.                                               This parameter can be a value between Min_Data = 1 and Max_Data = 15.
  230.                                               @note This parameter is not used with synchronous NOR Flash memories.   */
  231.  
  232.   uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
  233.                                               the duration of the data setup time.
  234.                                               This parameter can be a value between Min_Data = 1 and Max_Data = 255.
  235.                                               @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
  236.                                               NOR Flash memories.                                                     */
  237.  
  238.   uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
  239.                                               the duration of the bus turnaround.
  240.                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
  241.                                               @note This parameter is only used for multiplexed NOR Flash memories.   */
  242.  
  243.   uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
  244.                                               HCLK cycles. This parameter can be a value between Min_Data = 2 and
  245.                                               Max_Data = 16.
  246.                                               @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
  247.                                               accesses.                                                               */
  248.  
  249.   uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
  250.                                               to the memory before getting the first data.
  251.                                               The parameter value depends on the memory type as shown below:
  252.                                               - It must be set to 0 in case of a CRAM
  253.                                               - It is don't care in asynchronous NOR, SRAM or ROM accesses
  254.                                               - It may assume a value between Min_Data = 2 and Max_Data = 17
  255.                                                 in NOR Flash memories with synchronous burst mode enable              */
  256.  
  257.   uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
  258.                                               This parameter can be a value of @ref FSMC_Access_Mode                   */
  259. } FSMC_NORSRAM_TimingTypeDef;
  260. #endif /* FSMC_BANK1 */
  261.  
  262. #if defined(FSMC_BANK3)
  263. /**
  264.   * @brief  FSMC NAND Configuration Structure definition
  265.   */
  266. typedef struct
  267. {
  268.   uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
  269.                                         This parameter can be a value of @ref FSMC_NAND_Bank                  */
  270.  
  271.   uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
  272.                                         This parameter can be any value of @ref FSMC_Wait_feature             */
  273.  
  274.   uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
  275.                                         This parameter can be any value of @ref FSMC_NAND_Data_Width          */
  276.  
  277.   uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
  278.                                         This parameter can be any value of @ref FSMC_ECC                      */
  279.  
  280.   uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
  281.                                         This parameter can be any value of @ref FSMC_ECC_Page_Size            */
  282.  
  283.   uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
  284.                                         delay between CLE low and RE low.
  285.                                         This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
  286.  
  287.   uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
  288.                                         delay between ALE low and RE low.
  289.                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
  290. } FSMC_NAND_InitTypeDef;
  291. #endif
  292.  
  293. #if defined(FSMC_BANK3) || defined(FSMC_BANK4)
  294. /**
  295.   * @brief  FSMC NAND Timing parameters structure definition
  296.   */
  297. typedef struct
  298. {
  299.   uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
  300.                                       the command assertion for NAND-Flash read or write access
  301.                                       to common/Attribute or I/O memory space (depending on
  302.                                       the memory space timing to be configured).
  303.                                       This parameter can be a value between Min_Data = 0 and Max_Data = 254    */
  304.  
  305.   uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
  306.                                       command for NAND-Flash read or write access to
  307.                                       common/Attribute or I/O memory space (depending on the
  308.                                       memory space timing to be configured).
  309.                                       This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
  310.  
  311.   uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
  312.                                       (and data for write access) after the command de-assertion
  313.                                       for NAND-Flash read or write access to common/Attribute
  314.                                       or I/O memory space (depending on the memory space timing
  315.                                       to be configured).
  316.                                       This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
  317.  
  318.   uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
  319.                                       data bus is kept in HiZ after the start of a NAND-Flash
  320.                                       write access to common/Attribute or I/O memory space (depending
  321.                                       on the memory space timing to be configured).
  322.                                       This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
  323. } FSMC_NAND_PCC_TimingTypeDef;
  324. #endif /* FSMC_BANK3 */
  325.  
  326. #if defined(FSMC_BANK4)
  327. /**
  328.   * @brief FSMC PCCARD Configuration Structure definition
  329.   */
  330. typedef struct
  331. {
  332.   uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the PCCARD Memory device.
  333.                                         This parameter can be any value of @ref FSMC_Wait_feature      */
  334.  
  335.   uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
  336.                                         delay between CLE low and RE low.
  337.                                         This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
  338.  
  339.   uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
  340.                                         delay between ALE low and RE low.
  341.                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
  342. }FSMC_PCCARD_InitTypeDef;
  343. #endif
  344.  
  345. /**
  346.   * @}
  347.   */
  348.  
  349. /* Exported constants --------------------------------------------------------*/
  350. /** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants
  351.   * @{
  352.   */
  353. #if defined(FSMC_BANK1)
  354.  
  355. /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
  356.   * @{
  357.   */
  358.  
  359. /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
  360.   * @{
  361.   */
  362. #define FSMC_NORSRAM_BANK1                       (0x00000000U)
  363. #define FSMC_NORSRAM_BANK2                       (0x00000002U)
  364. #define FSMC_NORSRAM_BANK3                       (0x00000004U)
  365. #define FSMC_NORSRAM_BANK4                       (0x00000006U)
  366. /**
  367.   * @}
  368.   */
  369.  
  370. /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
  371.   * @{
  372.   */
  373. #define FSMC_DATA_ADDRESS_MUX_DISABLE            (0x00000000U)
  374. #define FSMC_DATA_ADDRESS_MUX_ENABLE             (0x00000002U)
  375. /**
  376.   * @}
  377.   */
  378.  
  379. /** @defgroup FSMC_Memory_Type FSMC Memory Type
  380.   * @{
  381.   */
  382. #define FSMC_MEMORY_TYPE_SRAM                    (0x00000000U)
  383. #define FSMC_MEMORY_TYPE_PSRAM                   (0x00000004U)
  384. #define FSMC_MEMORY_TYPE_NOR                     (0x00000008U)
  385. /**
  386.   * @}
  387.   */
  388.  
  389. /** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width
  390.   * @{
  391.   */
  392. #define FSMC_NORSRAM_MEM_BUS_WIDTH_8             (0x00000000U)
  393. #define FSMC_NORSRAM_MEM_BUS_WIDTH_16            (0x00000010U)
  394. #define FSMC_NORSRAM_MEM_BUS_WIDTH_32            (0x00000020U)
  395. /**
  396.   * @}
  397.   */
  398.  
  399. /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
  400.   * @{
  401.   */
  402. #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE         (0x00000040U)
  403. #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        (0x00000000U)
  404. /**
  405.   * @}
  406.   */
  407.  
  408. /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
  409.   * @{
  410.   */
  411. #define FSMC_BURST_ACCESS_MODE_DISABLE           (0x00000000U)
  412. #define FSMC_BURST_ACCESS_MODE_ENABLE            (0x00000100U)
  413. /**
  414.   * @}
  415.   */
  416.  
  417. /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
  418.   * @{
  419.   */
  420. #define FSMC_WAIT_SIGNAL_POLARITY_LOW            (0x00000000U)
  421. #define FSMC_WAIT_SIGNAL_POLARITY_HIGH           (0x00000200U)
  422. /**
  423.   * @}
  424.   */
  425.  
  426. /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
  427.   * @{
  428.   */
  429. #define FSMC_WRAP_MODE_DISABLE                   (0x00000000U)
  430. #define FSMC_WRAP_MODE_ENABLE                    (0x00000400U)
  431. /**
  432.   * @}
  433.   */
  434.  
  435. /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
  436.   * @{
  437.   */
  438. #define FSMC_WAIT_TIMING_BEFORE_WS               (0x00000000U)
  439. #define FSMC_WAIT_TIMING_DURING_WS               (0x00000800U)
  440. /**
  441.   * @}
  442.   */
  443.  
  444. /** @defgroup FSMC_Write_Operation FSMC Write Operation
  445.   * @{
  446.   */
  447. #define FSMC_WRITE_OPERATION_DISABLE             (0x00000000U)
  448. #define FSMC_WRITE_OPERATION_ENABLE              (0x00001000U)
  449. /**
  450.   * @}
  451.   */
  452.  
  453. /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
  454.   * @{
  455.   */
  456. #define FSMC_WAIT_SIGNAL_DISABLE                 (0x00000000U)
  457. #define FSMC_WAIT_SIGNAL_ENABLE                  (0x00002000U)
  458. /**
  459.   * @}
  460.   */
  461.  
  462. /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
  463.   * @{
  464.   */
  465. #define FSMC_EXTENDED_MODE_DISABLE               (0x00000000U)
  466. #define FSMC_EXTENDED_MODE_ENABLE                (0x00004000U)
  467. /**
  468.   * @}
  469.   */
  470.  
  471. /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
  472.   * @{
  473.   */
  474. #define FSMC_ASYNCHRONOUS_WAIT_DISABLE           (0x00000000U)
  475. #define FSMC_ASYNCHRONOUS_WAIT_ENABLE            (0x00008000U)
  476. /**
  477.   * @}
  478.   */
  479.  
  480. /** @defgroup FSMC_Page_Size FSMC Page Size
  481.   * @{
  482.   */
  483. #define FSMC_PAGE_SIZE_NONE                      (0x00000000U)
  484. #define FSMC_PAGE_SIZE_128                       (0x00010000U)
  485. #define FSMC_PAGE_SIZE_256                       (0x00020000U)
  486. #define FSMC_PAGE_SIZE_512                       (0x00030000U)
  487. #define FSMC_PAGE_SIZE_1024                      (0x00040000U)
  488. /**
  489.   * @}
  490.   */
  491.  
  492. /** @defgroup FSMC_Write_Burst FSMC Write Burst
  493.   * @{
  494.   */
  495. #define FSMC_WRITE_BURST_DISABLE                 (0x00000000U)
  496. #define FSMC_WRITE_BURST_ENABLE                  (0x00080000U)
  497. /**
  498.   * @}
  499.   */
  500.  
  501. /** @defgroup FSMC_Continous_Clock FSMC Continuous Clock
  502.   * @{
  503.   */
  504. #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY          (0x00000000U)
  505. #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC         (0x00100000U)
  506. /**
  507.   * @}
  508.   */
  509.  
  510. /** @defgroup FSMC_Access_Mode FSMC Access Mode
  511.   * @{
  512.   */
  513. #define FSMC_ACCESS_MODE_A                       (0x00000000U)
  514. #define FSMC_ACCESS_MODE_B                       (0x10000000U)
  515. #define FSMC_ACCESS_MODE_C                       (0x20000000U)
  516. #define FSMC_ACCESS_MODE_D                       (0x30000000U)
  517. /**
  518.   * @}
  519.   */
  520.  
  521. /**
  522.   * @}
  523.   */
  524. #endif /* FSMC_BANK1 */
  525.  
  526. #if defined(FSMC_BANK3) || defined(FSMC_BANK4)
  527.  
  528. /** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller
  529.   * @{
  530.   */
  531. /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
  532.   * @{
  533.   */
  534. #define FSMC_NAND_BANK2                          (0x00000010U)
  535. #define FSMC_NAND_BANK3                          (0x00000100U)
  536. /**
  537.   * @}
  538.   */
  539.  
  540. /** @defgroup FSMC_Wait_feature FSMC Wait feature
  541.   * @{
  542.   */
  543. #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE       (0x00000000U)
  544. #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE        (0x00000002U)
  545. /**
  546.   * @}
  547.   */
  548.  
  549. /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
  550.   * @{
  551.   */
  552. #if defined(FSMC_BANK4)
  553. #define FSMC_PCR_MEMORY_TYPE_PCCARD              (0x00000000U)
  554. #endif
  555. #define FSMC_PCR_MEMORY_TYPE_NAND                (0x00000008U)
  556. /**
  557.   * @}
  558.   */
  559.  
  560. /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
  561.   * @{
  562.   */
  563. #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8            (0x00000000U)
  564. #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16           (0x00000010U)
  565. /**
  566.   * @}
  567.   */
  568.  
  569. /** @defgroup FSMC_ECC FSMC ECC
  570.   * @{
  571.   */
  572. #define FSMC_NAND_ECC_DISABLE                    (0x00000000U)
  573. #define FSMC_NAND_ECC_ENABLE                     (0x00000040U)
  574. /**
  575.   * @}
  576.   */
  577.  
  578. /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
  579.   * @{
  580.   */
  581. #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE          (0x00000000U)
  582. #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE          (0x00020000U)
  583. #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE         (0x00040000U)
  584. #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE         (0x00060000U)
  585. #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE         (0x00080000U)
  586. #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE         (0x000A0000U)
  587. /**
  588.   * @}
  589.   */
  590.  
  591. /**
  592.   * @}
  593.   */
  594. #endif /* FSMC_BANK3 */
  595.  
  596.  
  597. /** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition
  598.   * @{
  599.   */
  600. #if defined(FSMC_BANK3) || defined(FSMC_BANK4)
  601. #define FSMC_IT_RISING_EDGE                      (0x00000008U)
  602. #define FSMC_IT_LEVEL                            (0x00000010U)
  603. #define FSMC_IT_FALLING_EDGE                     (0x00000020U)
  604. #endif /* FSMC_BANK3 */
  605. /**
  606.   * @}
  607.   */
  608.  
  609. /** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition
  610.   * @{
  611.   */
  612. #if defined(FSMC_BANK3) || defined(FSMC_BANK4)
  613. #define FSMC_FLAG_RISING_EDGE                    (0x00000001U)
  614. #define FSMC_FLAG_LEVEL                          (0x00000002U)
  615. #define FSMC_FLAG_FALLING_EDGE                   (0x00000004U)
  616. #define FSMC_FLAG_FEMPT                          (0x00000040U)
  617. #endif /* FSMC_BANK3 */
  618. /**
  619.   * @}
  620.   */
  621.  
  622. /**
  623.   * @}
  624.   */
  625.  
  626. /**
  627.   * @}
  628.   */
  629.  
  630. /* Private macro -------------------------------------------------------------*/
  631. /** @defgroup FSMC_LL_Private_Macros FSMC_LL  Private Macros
  632.   * @{
  633.   */
  634. #if defined(FSMC_BANK1)
  635. /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros
  636.   * @brief macros to handle NOR device enable/disable and read/write operations
  637.   * @{
  638.   */
  639.  
  640. /**
  641.   * @brief  Enable the NORSRAM device access.
  642.   * @param  __INSTANCE__ FSMC_NORSRAM Instance
  643.   * @param  __BANK__ FSMC_NORSRAM Bank
  644.   * @retval None
  645.   */
  646. #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)]\
  647.                                                        |= FSMC_BCRx_MBKEN)
  648.  
  649. /**
  650.   * @brief  Disable the NORSRAM device access.
  651.   * @param  __INSTANCE__ FSMC_NORSRAM Instance
  652.   * @param  __BANK__ FSMC_NORSRAM Bank
  653.   * @retval None
  654.   */
  655. #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
  656.                                                        &= ~FSMC_BCRx_MBKEN)
  657.  
  658. /**
  659.   * @}
  660.   */
  661. #endif /* FSMC_BANK1 */
  662.  
  663. #if defined(FSMC_BANK3)
  664. /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
  665.   *  @brief macros to handle NAND device enable/disable
  666.   *  @{
  667.   */
  668.  
  669. /**
  670.   * @brief  Enable the NAND device access.
  671.   * @param  __INSTANCE__ FSMC_NAND Instance
  672.   * @param  __BANK__     FSMC_NAND Bank
  673.   * @retval None
  674.   */
  675. #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCRx_PBKEN): \
  676.                                                              ((__INSTANCE__)->PCR3 |= FSMC_PCRx_PBKEN))
  677.  
  678. /**
  679.   * @brief  Disable the NAND device access.
  680.   * @param  __INSTANCE__ FSMC_NAND Instance
  681.   * @param  __BANK__     FSMC_NAND Bank
  682.   * @retval None
  683.   */
  684. #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
  685.                                                              CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
  686.  
  687. /**
  688.   * @}
  689.   */
  690. #endif
  691.  
  692. #if defined(FSMC_BANK4)
  693. /** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros
  694.   *  @brief macros to handle PCCARD read/write operations
  695.   *  @{
  696.   */
  697. /**
  698.   * @brief  Enable the PCCARD device access.
  699.   * @param  __INSTANCE__ FSMC_PCCARD Instance
  700.   * @retval None
  701.   */
  702. #define __FSMC_PCCARD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR4 |= FSMC_PCRx_PBKEN)
  703.  
  704. /**
  705.   * @brief  Disable the PCCARD device access.
  706.   * @param  __INSTANCE__ FSMC_PCCARD Instance
  707.   * @retval None
  708.   */
  709. #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCRx_PBKEN)
  710. /**
  711.   * @}
  712.   */
  713.  
  714. #endif
  715. #if defined(FSMC_BANK3)
  716. /** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt
  717.   * @brief macros to handle NAND interrupts
  718.   * @{
  719.   */
  720.  
  721. /**
  722.   * @brief  Enable the NAND device interrupt.
  723.   * @param  __INSTANCE__  FSMC_NAND instance
  724.   * @param  __BANK__     FSMC_NAND Bank
  725.   * @param  __INTERRUPT__ FSMC_NAND interrupt
  726.   *         This parameter can be any combination of the following values:
  727.   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
  728.   *            @arg FSMC_IT_LEVEL: Interrupt level.
  729.   *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
  730.   * @retval None
  731.   */
  732. #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
  733.                                                                                ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
  734.  
  735. /**
  736.   * @brief  Disable the NAND device interrupt.
  737.   * @param  __INSTANCE__  FSMC_NAND Instance
  738.   * @param  __BANK__     FSMC_NAND Bank
  739.   * @param  __INTERRUPT__ FSMC_NAND interrupt
  740.   *         This parameter can be any combination of the following values:
  741.   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
  742.   *            @arg FSMC_IT_LEVEL: Interrupt level.
  743.   *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
  744.   * @retval None
  745.   */
  746. #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
  747.                                                                                 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
  748.  
  749. /**
  750.   * @brief  Get flag status of the NAND device.
  751.   * @param  __INSTANCE__ FSMC_NAND Instance
  752.   * @param  __BANK__     FSMC_NAND Bank
  753.   * @param  __FLAG__     FSMC_NAND flag
  754.   *         This parameter can be any combination of the following values:
  755.   *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
  756.   *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
  757.   *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
  758.   *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.
  759.   * @retval The state of FLAG (SET or RESET).
  760.   */
  761. #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
  762.                                                                          (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
  763.  
  764. /**
  765.   * @brief  Clear flag status of the NAND device.
  766.   * @param  __INSTANCE__ FSMC_NAND Instance
  767.   * @param  __BANK__     FSMC_NAND Bank
  768.   * @param  __FLAG__     FSMC_NAND flag
  769.   *         This parameter can be any combination of the following values:
  770.   *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
  771.   *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
  772.   *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
  773.   *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.
  774.   * @retval None
  775.   */
  776. #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
  777.                                                                            ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
  778.  
  779. /**
  780.   * @}
  781.   */
  782. #endif /* FSMC_BANK3 */
  783.  
  784. #if defined(FSMC_BANK4)
  785. /** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt
  786.   * @brief macros to handle PCCARD interrupts
  787.   * @{
  788.   */
  789.  
  790. /**
  791.   * @brief  Enable the PCCARD device interrupt.
  792.   * @param  __INSTANCE__ FSMC_PCCARD instance
  793.   * @param  __INTERRUPT__ FSMC_PCCARD interrupt
  794.   *         This parameter can be any combination of the following values:
  795.   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
  796.   *            @arg FSMC_IT_LEVEL: Interrupt level.
  797.   *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
  798.   * @retval None
  799.   */
  800. #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
  801.  
  802. /**
  803.   * @brief  Disable the PCCARD device interrupt.
  804.   * @param  __INSTANCE__ FSMC_PCCARD instance
  805.   * @param  __INTERRUPT__ FSMC_PCCARD interrupt
  806.   *         This parameter can be any combination of the following values:
  807.   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
  808.   *            @arg FSMC_IT_LEVEL: Interrupt level.
  809.   *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
  810.   * @retval None
  811.   */
  812. #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
  813.  
  814. /**
  815.   * @brief  Get flag status of the PCCARD device.
  816.   * @param  __INSTANCE__ FSMC_PCCARD instance
  817.   * @param  __FLAG__ FSMC_PCCARD flag
  818.   *         This parameter can be any combination of the following values:
  819.   *            @arg  FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
  820.   *            @arg  FSMC_FLAG_LEVEL: Interrupt level edge flag.
  821.   *            @arg  FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
  822.   *            @arg  FSMC_FLAG_FEMPT: FIFO empty flag.
  823.   * @retval The state of FLAG (SET or RESET).
  824.   */
  825. #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
  826.  
  827. /**
  828.   * @brief  Clear flag status of the PCCARD device.
  829.   * @param  __INSTANCE__ FSMC_PCCARD instance
  830.   * @param  __FLAG__ FSMC_PCCARD flag
  831.   *         This parameter can be any combination of the following values:
  832.   *            @arg  FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
  833.   *            @arg  FSMC_FLAG_LEVEL: Interrupt level edge flag.
  834.   *            @arg  FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
  835.   *            @arg  FSMC_FLAG_FEMPT: FIFO empty flag.
  836.   * @retval None
  837.   */
  838. #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SR4 &= ~(__FLAG__))
  839.  
  840. /**
  841.   * @}
  842.   */
  843. #endif
  844.  
  845. /**
  846.   * @}
  847.   */
  848.  
  849. /**
  850.   * @}
  851.   */
  852.  
  853. /* Private functions ---------------------------------------------------------*/
  854. /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
  855.   *  @{
  856.   */
  857.  
  858. #if defined(FSMC_BANK1)
  859. /** @defgroup FSMC_LL_NORSRAM  NOR SRAM
  860.   *  @{
  861.   */
  862. /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
  863.   *  @{
  864.   */
  865. HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
  866.                                     FSMC_NORSRAM_InitTypeDef *Init);
  867. HAL_StatusTypeDef  FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
  868.                                            FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
  869. HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
  870.                                                     FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
  871.                                                     uint32_t ExtendedMode);
  872. HAL_StatusTypeDef  FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
  873.                                       FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
  874. /**
  875.   * @}
  876.   */
  877.  
  878. /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
  879.   *  @{
  880.   */
  881. HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
  882. HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
  883. /**
  884.   * @}
  885.   */
  886. /**
  887.   * @}
  888.   */
  889. #endif /* FSMC_BANK1 */
  890.  
  891. #if defined(FSMC_BANK3)
  892. /** @defgroup FSMC_LL_NAND NAND
  893.   *  @{
  894.   */
  895. /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
  896.   *  @{
  897.   */
  898. HAL_StatusTypeDef  FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
  899. HAL_StatusTypeDef  FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
  900.                                                     FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
  901. HAL_StatusTypeDef  FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
  902.                                                        FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
  903. HAL_StatusTypeDef  FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
  904. /**
  905.   * @}
  906.   */
  907.  
  908. /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
  909.   *  @{
  910.   */
  911. HAL_StatusTypeDef  FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
  912. HAL_StatusTypeDef  FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
  913. HAL_StatusTypeDef  FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
  914.                                    uint32_t Timeout);
  915. /**
  916.   * @}
  917.   */
  918. /**
  919.   * @}
  920.   */
  921. #endif /* FSMC_BANK3 */
  922.  
  923. #if defined(FSMC_BANK4)
  924. /** @defgroup FSMC_LL_PCCARD PCCARD
  925.   *  @{
  926.   */
  927. /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
  928.   *  @{
  929.   */
  930. HAL_StatusTypeDef  FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
  931. HAL_StatusTypeDef  FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
  932.                                                                FSMC_NAND_PCC_TimingTypeDef *Timing);
  933. HAL_StatusTypeDef  FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
  934.                                                                   FSMC_NAND_PCC_TimingTypeDef *Timing);
  935. HAL_StatusTypeDef  FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
  936.                                                            FSMC_NAND_PCC_TimingTypeDef *Timing);
  937. HAL_StatusTypeDef  FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
  938. /**
  939.   * @}
  940.   */
  941. /**
  942.   * @}
  943.   */
  944. #endif /* FSMC_BANK4 */
  945.  
  946.  
  947. /**
  948.   * @}
  949.   */
  950.  
  951. /**
  952.   * @}
  953.   */
  954.  
  955. /**
  956.   * @}
  957.   */
  958.  
  959. #ifdef __cplusplus
  960. }
  961. #endif
  962.  
  963. #endif /* STM32F1xx_LL_FSMC_H */
  964.  
  965. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  966.