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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_dma.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of DMA LL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10.   *
  11.   * Redistribution and use in source and binary forms, with or without modification,
  12.   * are permitted provided that the following conditions are met:
  13.   *   1. Redistributions of source code must retain the above copyright notice,
  14.   *      this list of conditions and the following disclaimer.
  15.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16.   *      this list of conditions and the following disclaimer in the documentation
  17.   *      and/or other materials provided with the distribution.
  18.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19.   *      may be used to endorse or promote products derived from this software
  20.   *      without specific prior written permission.
  21.   *
  22.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32.   *
  33.   ******************************************************************************
  34.   */
  35.  
  36. /* Define to prevent recursive inclusion -------------------------------------*/
  37. #ifndef __STM32F1xx_LL_DMA_H
  38. #define __STM32F1xx_LL_DMA_H
  39.  
  40. #ifdef __cplusplus
  41. extern "C" {
  42. #endif
  43.  
  44. /* Includes ------------------------------------------------------------------*/
  45. #include "stm32f1xx.h"
  46.  
  47. /** @addtogroup STM32F1xx_LL_Driver
  48.   * @{
  49.   */
  50.  
  51. #if defined (DMA1) || defined (DMA2)
  52.  
  53. /** @defgroup DMA_LL DMA
  54.   * @{
  55.   */
  56.  
  57. /* Private types -------------------------------------------------------------*/
  58. /* Private variables ---------------------------------------------------------*/
  59. /** @defgroup DMA_LL_Private_Variables DMA Private Variables
  60.   * @{
  61.   */
  62. /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
  63. static const uint8_t CHANNEL_OFFSET_TAB[] =
  64. {
  65.   (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
  66.   (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
  67.   (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
  68.   (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
  69.   (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
  70.   (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
  71.   (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
  72. };
  73. /**
  74.   * @}
  75.   */
  76. /* Private constants ---------------------------------------------------------*/
  77. /* Private macros ------------------------------------------------------------*/
  78. #if defined(USE_FULL_LL_DRIVER)
  79. /** @defgroup DMA_LL_Private_Macros DMA Private Macros
  80.   * @{
  81.   */
  82. /**
  83.   * @}
  84.   */
  85. #endif /*USE_FULL_LL_DRIVER*/
  86.  
  87. /* Exported types ------------------------------------------------------------*/
  88. #if defined(USE_FULL_LL_DRIVER)
  89. /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
  90.   * @{
  91.   */
  92. typedef struct
  93. {
  94.   uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
  95.                                         or as Source base address in case of memory to memory transfer direction.
  96.  
  97.                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
  98.  
  99.   uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
  100.                                         or as Destination base address in case of memory to memory transfer direction.
  101.  
  102.                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
  103.  
  104.   uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
  105.                                         from memory to memory or from peripheral to memory.
  106.                                         This parameter can be a value of @ref DMA_LL_EC_DIRECTION
  107.  
  108.                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
  109.  
  110.   uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
  111.                                         This parameter can be a value of @ref DMA_LL_EC_MODE
  112.                                         @note: The circular buffer mode cannot be used if the memory to memory
  113.                                                data transfer direction is configured on the selected Channel
  114.  
  115.                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
  116.  
  117.   uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
  118.                                         is incremented or not.
  119.                                         This parameter can be a value of @ref DMA_LL_EC_PERIPH
  120.  
  121.                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
  122.  
  123.   uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
  124.                                         is incremented or not.
  125.                                         This parameter can be a value of @ref DMA_LL_EC_MEMORY
  126.  
  127.                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
  128.  
  129.   uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
  130.                                         in case of memory to memory transfer direction.
  131.                                         This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
  132.  
  133.                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
  134.  
  135.   uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
  136.                                         in case of memory to memory transfer direction.
  137.                                         This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
  138.  
  139.                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
  140.  
  141.   uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
  142.                                         The data unit is equal to the source buffer configuration set in PeripheralSize
  143.                                         or MemorySize parameters depending in the transfer direction.
  144.                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
  145.  
  146.                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
  147.  
  148.   uint32_t Priority;               /*!< Specifies the channel priority level.
  149.                                         This parameter can be a value of @ref DMA_LL_EC_PRIORITY
  150.  
  151.                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
  152.  
  153. } LL_DMA_InitTypeDef;
  154. /**
  155.   * @}
  156.   */
  157. #endif /*USE_FULL_LL_DRIVER*/
  158.  
  159. /* Exported constants --------------------------------------------------------*/
  160. /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
  161.   * @{
  162.   */
  163. /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
  164.   * @brief    Flags defines which can be used with LL_DMA_WriteReg function
  165.   * @{
  166.   */
  167. #define LL_DMA_IFCR_CGIF1                 DMA_IFCR_CGIF1        /*!< Channel 1 global flag            */
  168. #define LL_DMA_IFCR_CTCIF1                DMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */
  169. #define LL_DMA_IFCR_CHTIF1                DMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */
  170. #define LL_DMA_IFCR_CTEIF1                DMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */
  171. #define LL_DMA_IFCR_CGIF2                 DMA_IFCR_CGIF2        /*!< Channel 2 global flag            */
  172. #define LL_DMA_IFCR_CTCIF2                DMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */
  173. #define LL_DMA_IFCR_CHTIF2                DMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */
  174. #define LL_DMA_IFCR_CTEIF2                DMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */
  175. #define LL_DMA_IFCR_CGIF3                 DMA_IFCR_CGIF3        /*!< Channel 3 global flag            */
  176. #define LL_DMA_IFCR_CTCIF3                DMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */
  177. #define LL_DMA_IFCR_CHTIF3                DMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */
  178. #define LL_DMA_IFCR_CTEIF3                DMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */
  179. #define LL_DMA_IFCR_CGIF4                 DMA_IFCR_CGIF4        /*!< Channel 4 global flag            */
  180. #define LL_DMA_IFCR_CTCIF4                DMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */
  181. #define LL_DMA_IFCR_CHTIF4                DMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */
  182. #define LL_DMA_IFCR_CTEIF4                DMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */
  183. #define LL_DMA_IFCR_CGIF5                 DMA_IFCR_CGIF5        /*!< Channel 5 global flag            */
  184. #define LL_DMA_IFCR_CTCIF5                DMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */
  185. #define LL_DMA_IFCR_CHTIF5                DMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */
  186. #define LL_DMA_IFCR_CTEIF5                DMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */
  187. #define LL_DMA_IFCR_CGIF6                 DMA_IFCR_CGIF6        /*!< Channel 6 global flag            */
  188. #define LL_DMA_IFCR_CTCIF6                DMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */
  189. #define LL_DMA_IFCR_CHTIF6                DMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */
  190. #define LL_DMA_IFCR_CTEIF6                DMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */
  191. #define LL_DMA_IFCR_CGIF7                 DMA_IFCR_CGIF7        /*!< Channel 7 global flag            */
  192. #define LL_DMA_IFCR_CTCIF7                DMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */
  193. #define LL_DMA_IFCR_CHTIF7                DMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */
  194. #define LL_DMA_IFCR_CTEIF7                DMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */
  195. /**
  196.   * @}
  197.   */
  198.  
  199. /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
  200.   * @brief    Flags defines which can be used with LL_DMA_ReadReg function
  201.   * @{
  202.   */
  203. #define LL_DMA_ISR_GIF1                   DMA_ISR_GIF1          /*!< Channel 1 global flag            */
  204. #define LL_DMA_ISR_TCIF1                  DMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */
  205. #define LL_DMA_ISR_HTIF1                  DMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */
  206. #define LL_DMA_ISR_TEIF1                  DMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */
  207. #define LL_DMA_ISR_GIF2                   DMA_ISR_GIF2          /*!< Channel 2 global flag            */
  208. #define LL_DMA_ISR_TCIF2                  DMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */
  209. #define LL_DMA_ISR_HTIF2                  DMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */
  210. #define LL_DMA_ISR_TEIF2                  DMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */
  211. #define LL_DMA_ISR_GIF3                   DMA_ISR_GIF3          /*!< Channel 3 global flag            */
  212. #define LL_DMA_ISR_TCIF3                  DMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */
  213. #define LL_DMA_ISR_HTIF3                  DMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */
  214. #define LL_DMA_ISR_TEIF3                  DMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */
  215. #define LL_DMA_ISR_GIF4                   DMA_ISR_GIF4          /*!< Channel 4 global flag            */
  216. #define LL_DMA_ISR_TCIF4                  DMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */
  217. #define LL_DMA_ISR_HTIF4                  DMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */
  218. #define LL_DMA_ISR_TEIF4                  DMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */
  219. #define LL_DMA_ISR_GIF5                   DMA_ISR_GIF5          /*!< Channel 5 global flag            */
  220. #define LL_DMA_ISR_TCIF5                  DMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */
  221. #define LL_DMA_ISR_HTIF5                  DMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */
  222. #define LL_DMA_ISR_TEIF5                  DMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */
  223. #define LL_DMA_ISR_GIF6                   DMA_ISR_GIF6          /*!< Channel 6 global flag            */
  224. #define LL_DMA_ISR_TCIF6                  DMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */
  225. #define LL_DMA_ISR_HTIF6                  DMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */
  226. #define LL_DMA_ISR_TEIF6                  DMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */
  227. #define LL_DMA_ISR_GIF7                   DMA_ISR_GIF7          /*!< Channel 7 global flag            */
  228. #define LL_DMA_ISR_TCIF7                  DMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */
  229. #define LL_DMA_ISR_HTIF7                  DMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */
  230. #define LL_DMA_ISR_TEIF7                  DMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */
  231. /**
  232.   * @}
  233.   */
  234.  
  235. /** @defgroup DMA_LL_EC_IT IT Defines
  236.   * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMA_WriteReg functions
  237.   * @{
  238.   */
  239. #define LL_DMA_CCR_TCIE                   DMA_CCR_TCIE          /*!< Transfer complete interrupt */
  240. #define LL_DMA_CCR_HTIE                   DMA_CCR_HTIE          /*!< Half Transfer interrupt     */
  241. #define LL_DMA_CCR_TEIE                   DMA_CCR_TEIE          /*!< Transfer error interrupt    */
  242. /**
  243.   * @}
  244.   */
  245.  
  246. /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
  247.   * @{
  248.   */
  249. #define LL_DMA_CHANNEL_1                  0x00000001U /*!< DMA Channel 1 */
  250. #define LL_DMA_CHANNEL_2                  0x00000002U /*!< DMA Channel 2 */
  251. #define LL_DMA_CHANNEL_3                  0x00000003U /*!< DMA Channel 3 */
  252. #define LL_DMA_CHANNEL_4                  0x00000004U /*!< DMA Channel 4 */
  253. #define LL_DMA_CHANNEL_5                  0x00000005U /*!< DMA Channel 5 */
  254. #define LL_DMA_CHANNEL_6                  0x00000006U /*!< DMA Channel 6 */
  255. #define LL_DMA_CHANNEL_7                  0x00000007U /*!< DMA Channel 7 */
  256. #if defined(USE_FULL_LL_DRIVER)
  257. #define LL_DMA_CHANNEL_ALL                0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
  258. #endif /*USE_FULL_LL_DRIVER*/
  259. /**
  260.   * @}
  261.   */
  262.  
  263. /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
  264.   * @{
  265.   */
  266. #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */
  267. #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
  268. #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
  269. /**
  270.   * @}
  271.   */
  272.  
  273. /** @defgroup DMA_LL_EC_MODE Transfer mode
  274.   * @{
  275.   */
  276. #define LL_DMA_MODE_NORMAL                0x00000000U             /*!< Normal Mode                  */
  277. #define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
  278. /**
  279.   * @}
  280.   */
  281.  
  282. /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
  283.   * @{
  284.   */
  285. #define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
  286. #define LL_DMA_PERIPH_NOINCREMENT         0x00000000U             /*!< Peripheral increment mode Disable */
  287. /**
  288.   * @}
  289.   */
  290.  
  291. /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
  292.   * @{
  293.   */
  294. #define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
  295. #define LL_DMA_MEMORY_NOINCREMENT         0x00000000U             /*!< Memory increment mode Disable */
  296. /**
  297.   * @}
  298.   */
  299.  
  300. /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
  301.   * @{
  302.   */
  303. #define LL_DMA_PDATAALIGN_BYTE            0x00000000U             /*!< Peripheral data alignment : Byte     */
  304. #define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
  305. #define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
  306. /**
  307.   * @}
  308.   */
  309.  
  310. /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
  311.   * @{
  312.   */
  313. #define LL_DMA_MDATAALIGN_BYTE            0x00000000U             /*!< Memory data alignment : Byte     */
  314. #define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
  315. #define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
  316. /**
  317.   * @}
  318.   */
  319.  
  320. /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
  321.   * @{
  322.   */
  323. #define LL_DMA_PRIORITY_LOW               0x00000000U             /*!< Priority level : Low       */
  324. #define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
  325. #define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
  326. #define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
  327. /**
  328.   * @}
  329.   */
  330.  
  331. /**
  332.   * @}
  333.   */
  334.  
  335. /* Exported macro ------------------------------------------------------------*/
  336. /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
  337.   * @{
  338.   */
  339.  
  340. /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
  341.   * @{
  342.   */
  343. /**
  344.   * @brief  Write a value in DMA register
  345.   * @param  __INSTANCE__ DMA Instance
  346.   * @param  __REG__ Register to be written
  347.   * @param  __VALUE__ Value to be written in the register
  348.   * @retval None
  349.   */
  350. #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  351.  
  352. /**
  353.   * @brief  Read a value in DMA register
  354.   * @param  __INSTANCE__ DMA Instance
  355.   * @param  __REG__ Register to be read
  356.   * @retval Register value
  357.   */
  358. #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  359. /**
  360.   * @}
  361.   */
  362.  
  363. /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
  364.   * @{
  365.   */
  366.  
  367. /**
  368.   * @brief  Convert DMAx_Channely into DMAx
  369.   * @param  __CHANNEL_INSTANCE__ DMAx_Channely
  370.   * @retval DMAx
  371.   */
  372. #if defined(DMA2)
  373. #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)   \
  374. (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ?  DMA2 : DMA1)
  375. #else
  376. #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)  (DMA1)
  377. #endif
  378.  
  379. /**
  380.   * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y
  381.   * @param  __CHANNEL_INSTANCE__ DMAx_Channely
  382.   * @retval LL_DMA_CHANNEL_y
  383.   */
  384. #if defined (DMA2)
  385. #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
  386. (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
  387.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
  388.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
  389.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
  390.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
  391.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
  392.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
  393.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
  394.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
  395.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
  396.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
  397.  LL_DMA_CHANNEL_7)
  398. #else
  399. #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
  400. (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
  401.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
  402.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
  403.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
  404.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
  405.  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
  406.  LL_DMA_CHANNEL_7)
  407. #endif
  408.  
  409. /**
  410.   * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
  411.   * @param  __DMA_INSTANCE__ DMAx
  412.   * @param  __CHANNEL__ LL_DMA_CHANNEL_y
  413.   * @retval DMAx_Channely
  414.   */
  415. #if defined (DMA2)
  416. #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
  417. ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
  418.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
  419.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
  420.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
  421.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
  422.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
  423.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
  424.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
  425.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
  426.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
  427.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
  428.  DMA1_Channel7)
  429. #else
  430. #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
  431. ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
  432.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
  433.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
  434.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
  435.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
  436.  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
  437.  DMA1_Channel7)
  438. #endif
  439.  
  440. /**
  441.   * @}
  442.   */
  443.  
  444. /**
  445.   * @}
  446.   */
  447.  
  448. /* Exported functions --------------------------------------------------------*/
  449. /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
  450.  * @{
  451.  */
  452.  
  453. /** @defgroup DMA_LL_EF_Configuration Configuration
  454.   * @{
  455.   */
  456. /**
  457.   * @brief  Enable DMA channel.
  458.   * @rmtoll CCR          EN            LL_DMA_EnableChannel
  459.   * @param  DMAx DMAx Instance
  460.   * @param  Channel This parameter can be one of the following values:
  461.   *         @arg @ref LL_DMA_CHANNEL_1
  462.   *         @arg @ref LL_DMA_CHANNEL_2
  463.   *         @arg @ref LL_DMA_CHANNEL_3
  464.   *         @arg @ref LL_DMA_CHANNEL_4
  465.   *         @arg @ref LL_DMA_CHANNEL_5
  466.   *         @arg @ref LL_DMA_CHANNEL_6
  467.   *         @arg @ref LL_DMA_CHANNEL_7
  468.   * @retval None
  469.   */
  470. __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
  471. {
  472.   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
  473. }
  474.  
  475. /**
  476.   * @brief  Disable DMA channel.
  477.   * @rmtoll CCR          EN            LL_DMA_DisableChannel
  478.   * @param  DMAx DMAx Instance
  479.   * @param  Channel This parameter can be one of the following values:
  480.   *         @arg @ref LL_DMA_CHANNEL_1
  481.   *         @arg @ref LL_DMA_CHANNEL_2
  482.   *         @arg @ref LL_DMA_CHANNEL_3
  483.   *         @arg @ref LL_DMA_CHANNEL_4
  484.   *         @arg @ref LL_DMA_CHANNEL_5
  485.   *         @arg @ref LL_DMA_CHANNEL_6
  486.   *         @arg @ref LL_DMA_CHANNEL_7
  487.   * @retval None
  488.   */
  489. __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
  490. {
  491.   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
  492. }
  493.  
  494. /**
  495.   * @brief  Check if DMA channel is enabled or disabled.
  496.   * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel
  497.   * @param  DMAx DMAx Instance
  498.   * @param  Channel This parameter can be one of the following values:
  499.   *         @arg @ref LL_DMA_CHANNEL_1
  500.   *         @arg @ref LL_DMA_CHANNEL_2
  501.   *         @arg @ref LL_DMA_CHANNEL_3
  502.   *         @arg @ref LL_DMA_CHANNEL_4
  503.   *         @arg @ref LL_DMA_CHANNEL_5
  504.   *         @arg @ref LL_DMA_CHANNEL_6
  505.   *         @arg @ref LL_DMA_CHANNEL_7
  506.   * @retval State of bit (1 or 0).
  507.   */
  508. __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
  509. {
  510.   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  511.                    DMA_CCR_EN) == (DMA_CCR_EN));
  512. }
  513.  
  514. /**
  515.   * @brief  Configure all parameters link to DMA transfer.
  516.   * @rmtoll CCR          DIR           LL_DMA_ConfigTransfer\n
  517.   *         CCR          MEM2MEM       LL_DMA_ConfigTransfer\n
  518.   *         CCR          CIRC          LL_DMA_ConfigTransfer\n
  519.   *         CCR          PINC          LL_DMA_ConfigTransfer\n
  520.   *         CCR          MINC          LL_DMA_ConfigTransfer\n
  521.   *         CCR          PSIZE         LL_DMA_ConfigTransfer\n
  522.   *         CCR          MSIZE         LL_DMA_ConfigTransfer\n
  523.   *         CCR          PL            LL_DMA_ConfigTransfer
  524.   * @param  DMAx DMAx Instance
  525.   * @param  Channel This parameter can be one of the following values:
  526.   *         @arg @ref LL_DMA_CHANNEL_1
  527.   *         @arg @ref LL_DMA_CHANNEL_2
  528.   *         @arg @ref LL_DMA_CHANNEL_3
  529.   *         @arg @ref LL_DMA_CHANNEL_4
  530.   *         @arg @ref LL_DMA_CHANNEL_5
  531.   *         @arg @ref LL_DMA_CHANNEL_6
  532.   *         @arg @ref LL_DMA_CHANNEL_7
  533.   * @param  Configuration This parameter must be a combination of all the following values:
  534.   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  535.   *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
  536.   *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
  537.   *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
  538.   *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
  539.   *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
  540.   *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
  541.   * @retval None
  542.   */
  543. __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
  544. {
  545.   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  546.              DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
  547.              Configuration);
  548. }
  549.  
  550. /**
  551.   * @brief  Set Data transfer direction (read from peripheral or from memory).
  552.   * @rmtoll CCR          DIR           LL_DMA_SetDataTransferDirection\n
  553.   *         CCR          MEM2MEM       LL_DMA_SetDataTransferDirection
  554.   * @param  DMAx DMAx Instance
  555.   * @param  Channel This parameter can be one of the following values:
  556.   *         @arg @ref LL_DMA_CHANNEL_1
  557.   *         @arg @ref LL_DMA_CHANNEL_2
  558.   *         @arg @ref LL_DMA_CHANNEL_3
  559.   *         @arg @ref LL_DMA_CHANNEL_4
  560.   *         @arg @ref LL_DMA_CHANNEL_5
  561.   *         @arg @ref LL_DMA_CHANNEL_6
  562.   *         @arg @ref LL_DMA_CHANNEL_7
  563.   * @param  Direction This parameter can be one of the following values:
  564.   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  565.   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  566.   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  567.   * @retval None
  568.   */
  569. __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
  570. {
  571.   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  572.              DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
  573. }
  574.  
  575. /**
  576.   * @brief  Get Data transfer direction (read from peripheral or from memory).
  577.   * @rmtoll CCR          DIR           LL_DMA_GetDataTransferDirection\n
  578.   *         CCR          MEM2MEM       LL_DMA_GetDataTransferDirection
  579.   * @param  DMAx DMAx Instance
  580.   * @param  Channel This parameter can be one of the following values:
  581.   *         @arg @ref LL_DMA_CHANNEL_1
  582.   *         @arg @ref LL_DMA_CHANNEL_2
  583.   *         @arg @ref LL_DMA_CHANNEL_3
  584.   *         @arg @ref LL_DMA_CHANNEL_4
  585.   *         @arg @ref LL_DMA_CHANNEL_5
  586.   *         @arg @ref LL_DMA_CHANNEL_6
  587.   *         @arg @ref LL_DMA_CHANNEL_7
  588.   * @retval Returned value can be one of the following values:
  589.   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  590.   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  591.   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  592.   */
  593. __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
  594. {
  595.   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  596.                    DMA_CCR_DIR | DMA_CCR_MEM2MEM));
  597. }
  598.  
  599. /**
  600.   * @brief  Set DMA mode circular or normal.
  601.   * @note The circular buffer mode cannot be used if the memory-to-memory
  602.   * data transfer is configured on the selected Channel.
  603.   * @rmtoll CCR          CIRC          LL_DMA_SetMode
  604.   * @param  DMAx DMAx Instance
  605.   * @param  Channel This parameter can be one of the following values:
  606.   *         @arg @ref LL_DMA_CHANNEL_1
  607.   *         @arg @ref LL_DMA_CHANNEL_2
  608.   *         @arg @ref LL_DMA_CHANNEL_3
  609.   *         @arg @ref LL_DMA_CHANNEL_4
  610.   *         @arg @ref LL_DMA_CHANNEL_5
  611.   *         @arg @ref LL_DMA_CHANNEL_6
  612.   *         @arg @ref LL_DMA_CHANNEL_7
  613.   * @param  Mode This parameter can be one of the following values:
  614.   *         @arg @ref LL_DMA_MODE_NORMAL
  615.   *         @arg @ref LL_DMA_MODE_CIRCULAR
  616.   * @retval None
  617.   */
  618. __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
  619. {
  620.   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
  621.              Mode);
  622. }
  623.  
  624. /**
  625.   * @brief  Get DMA mode circular or normal.
  626.   * @rmtoll CCR          CIRC          LL_DMA_GetMode
  627.   * @param  DMAx DMAx Instance
  628.   * @param  Channel This parameter can be one of the following values:
  629.   *         @arg @ref LL_DMA_CHANNEL_1
  630.   *         @arg @ref LL_DMA_CHANNEL_2
  631.   *         @arg @ref LL_DMA_CHANNEL_3
  632.   *         @arg @ref LL_DMA_CHANNEL_4
  633.   *         @arg @ref LL_DMA_CHANNEL_5
  634.   *         @arg @ref LL_DMA_CHANNEL_6
  635.   *         @arg @ref LL_DMA_CHANNEL_7
  636.   * @retval Returned value can be one of the following values:
  637.   *         @arg @ref LL_DMA_MODE_NORMAL
  638.   *         @arg @ref LL_DMA_MODE_CIRCULAR
  639.   */
  640. __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
  641. {
  642.   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  643.                    DMA_CCR_CIRC));
  644. }
  645.  
  646. /**
  647.   * @brief  Set Peripheral increment mode.
  648.   * @rmtoll CCR          PINC          LL_DMA_SetPeriphIncMode
  649.   * @param  DMAx DMAx Instance
  650.   * @param  Channel This parameter can be one of the following values:
  651.   *         @arg @ref LL_DMA_CHANNEL_1
  652.   *         @arg @ref LL_DMA_CHANNEL_2
  653.   *         @arg @ref LL_DMA_CHANNEL_3
  654.   *         @arg @ref LL_DMA_CHANNEL_4
  655.   *         @arg @ref LL_DMA_CHANNEL_5
  656.   *         @arg @ref LL_DMA_CHANNEL_6
  657.   *         @arg @ref LL_DMA_CHANNEL_7
  658.   * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:
  659.   *         @arg @ref LL_DMA_PERIPH_INCREMENT
  660.   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
  661.   * @retval None
  662.   */
  663. __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
  664. {
  665.   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
  666.              PeriphOrM2MSrcIncMode);
  667. }
  668.  
  669. /**
  670.   * @brief  Get Peripheral increment mode.
  671.   * @rmtoll CCR          PINC          LL_DMA_GetPeriphIncMode
  672.   * @param  DMAx DMAx Instance
  673.   * @param  Channel This parameter can be one of the following values:
  674.   *         @arg @ref LL_DMA_CHANNEL_1
  675.   *         @arg @ref LL_DMA_CHANNEL_2
  676.   *         @arg @ref LL_DMA_CHANNEL_3
  677.   *         @arg @ref LL_DMA_CHANNEL_4
  678.   *         @arg @ref LL_DMA_CHANNEL_5
  679.   *         @arg @ref LL_DMA_CHANNEL_6
  680.   *         @arg @ref LL_DMA_CHANNEL_7
  681.   * @retval Returned value can be one of the following values:
  682.   *         @arg @ref LL_DMA_PERIPH_INCREMENT
  683.   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
  684.   */
  685. __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
  686. {
  687.   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  688.                    DMA_CCR_PINC));
  689. }
  690.  
  691. /**
  692.   * @brief  Set Memory increment mode.
  693.   * @rmtoll CCR          MINC          LL_DMA_SetMemoryIncMode
  694.   * @param  DMAx DMAx Instance
  695.   * @param  Channel This parameter can be one of the following values:
  696.   *         @arg @ref LL_DMA_CHANNEL_1
  697.   *         @arg @ref LL_DMA_CHANNEL_2
  698.   *         @arg @ref LL_DMA_CHANNEL_3
  699.   *         @arg @ref LL_DMA_CHANNEL_4
  700.   *         @arg @ref LL_DMA_CHANNEL_5
  701.   *         @arg @ref LL_DMA_CHANNEL_6
  702.   *         @arg @ref LL_DMA_CHANNEL_7
  703.   * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:
  704.   *         @arg @ref LL_DMA_MEMORY_INCREMENT
  705.   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
  706.   * @retval None
  707.   */
  708. __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
  709. {
  710.   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
  711.              MemoryOrM2MDstIncMode);
  712. }
  713.  
  714. /**
  715.   * @brief  Get Memory increment mode.
  716.   * @rmtoll CCR          MINC          LL_DMA_GetMemoryIncMode
  717.   * @param  DMAx DMAx Instance
  718.   * @param  Channel This parameter can be one of the following values:
  719.   *         @arg @ref LL_DMA_CHANNEL_1
  720.   *         @arg @ref LL_DMA_CHANNEL_2
  721.   *         @arg @ref LL_DMA_CHANNEL_3
  722.   *         @arg @ref LL_DMA_CHANNEL_4
  723.   *         @arg @ref LL_DMA_CHANNEL_5
  724.   *         @arg @ref LL_DMA_CHANNEL_6
  725.   *         @arg @ref LL_DMA_CHANNEL_7
  726.   * @retval Returned value can be one of the following values:
  727.   *         @arg @ref LL_DMA_MEMORY_INCREMENT
  728.   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
  729.   */
  730. __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
  731. {
  732.   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  733.                    DMA_CCR_MINC));
  734. }
  735.  
  736. /**
  737.   * @brief  Set Peripheral size.
  738.   * @rmtoll CCR          PSIZE         LL_DMA_SetPeriphSize
  739.   * @param  DMAx DMAx Instance
  740.   * @param  Channel This parameter can be one of the following values:
  741.   *         @arg @ref LL_DMA_CHANNEL_1
  742.   *         @arg @ref LL_DMA_CHANNEL_2
  743.   *         @arg @ref LL_DMA_CHANNEL_3
  744.   *         @arg @ref LL_DMA_CHANNEL_4
  745.   *         @arg @ref LL_DMA_CHANNEL_5
  746.   *         @arg @ref LL_DMA_CHANNEL_6
  747.   *         @arg @ref LL_DMA_CHANNEL_7
  748.   * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:
  749.   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
  750.   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
  751.   *         @arg @ref LL_DMA_PDATAALIGN_WORD
  752.   * @retval None
  753.   */
  754. __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
  755. {
  756.   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
  757.              PeriphOrM2MSrcDataSize);
  758. }
  759.  
  760. /**
  761.   * @brief  Get Peripheral size.
  762.   * @rmtoll CCR          PSIZE         LL_DMA_GetPeriphSize
  763.   * @param  DMAx DMAx Instance
  764.   * @param  Channel This parameter can be one of the following values:
  765.   *         @arg @ref LL_DMA_CHANNEL_1
  766.   *         @arg @ref LL_DMA_CHANNEL_2
  767.   *         @arg @ref LL_DMA_CHANNEL_3
  768.   *         @arg @ref LL_DMA_CHANNEL_4
  769.   *         @arg @ref LL_DMA_CHANNEL_5
  770.   *         @arg @ref LL_DMA_CHANNEL_6
  771.   *         @arg @ref LL_DMA_CHANNEL_7
  772.   * @retval Returned value can be one of the following values:
  773.   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
  774.   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
  775.   *         @arg @ref LL_DMA_PDATAALIGN_WORD
  776.   */
  777. __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
  778. {
  779.   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  780.                    DMA_CCR_PSIZE));
  781. }
  782.  
  783. /**
  784.   * @brief  Set Memory size.
  785.   * @rmtoll CCR          MSIZE         LL_DMA_SetMemorySize
  786.   * @param  DMAx DMAx Instance
  787.   * @param  Channel This parameter can be one of the following values:
  788.   *         @arg @ref LL_DMA_CHANNEL_1
  789.   *         @arg @ref LL_DMA_CHANNEL_2
  790.   *         @arg @ref LL_DMA_CHANNEL_3
  791.   *         @arg @ref LL_DMA_CHANNEL_4
  792.   *         @arg @ref LL_DMA_CHANNEL_5
  793.   *         @arg @ref LL_DMA_CHANNEL_6
  794.   *         @arg @ref LL_DMA_CHANNEL_7
  795.   * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:
  796.   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
  797.   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
  798.   *         @arg @ref LL_DMA_MDATAALIGN_WORD
  799.   * @retval None
  800.   */
  801. __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
  802. {
  803.   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
  804.              MemoryOrM2MDstDataSize);
  805. }
  806.  
  807. /**
  808.   * @brief  Get Memory size.
  809.   * @rmtoll CCR          MSIZE         LL_DMA_GetMemorySize
  810.   * @param  DMAx DMAx Instance
  811.   * @param  Channel This parameter can be one of the following values:
  812.   *         @arg @ref LL_DMA_CHANNEL_1
  813.   *         @arg @ref LL_DMA_CHANNEL_2
  814.   *         @arg @ref LL_DMA_CHANNEL_3
  815.   *         @arg @ref LL_DMA_CHANNEL_4
  816.   *         @arg @ref LL_DMA_CHANNEL_5
  817.   *         @arg @ref LL_DMA_CHANNEL_6
  818.   *         @arg @ref LL_DMA_CHANNEL_7
  819.   * @retval Returned value can be one of the following values:
  820.   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
  821.   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
  822.   *         @arg @ref LL_DMA_MDATAALIGN_WORD
  823.   */
  824. __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
  825. {
  826.   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  827.                    DMA_CCR_MSIZE));
  828. }
  829.  
  830. /**
  831.   * @brief  Set Channel priority level.
  832.   * @rmtoll CCR          PL            LL_DMA_SetChannelPriorityLevel
  833.   * @param  DMAx DMAx Instance
  834.   * @param  Channel This parameter can be one of the following values:
  835.   *         @arg @ref LL_DMA_CHANNEL_1
  836.   *         @arg @ref LL_DMA_CHANNEL_2
  837.   *         @arg @ref LL_DMA_CHANNEL_3
  838.   *         @arg @ref LL_DMA_CHANNEL_4
  839.   *         @arg @ref LL_DMA_CHANNEL_5
  840.   *         @arg @ref LL_DMA_CHANNEL_6
  841.   *         @arg @ref LL_DMA_CHANNEL_7
  842.   * @param  Priority This parameter can be one of the following values:
  843.   *         @arg @ref LL_DMA_PRIORITY_LOW
  844.   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
  845.   *         @arg @ref LL_DMA_PRIORITY_HIGH
  846.   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
  847.   * @retval None
  848.   */
  849. __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
  850. {
  851.   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
  852.              Priority);
  853. }
  854.  
  855. /**
  856.   * @brief  Get Channel priority level.
  857.   * @rmtoll CCR          PL            LL_DMA_GetChannelPriorityLevel
  858.   * @param  DMAx DMAx Instance
  859.   * @param  Channel This parameter can be one of the following values:
  860.   *         @arg @ref LL_DMA_CHANNEL_1
  861.   *         @arg @ref LL_DMA_CHANNEL_2
  862.   *         @arg @ref LL_DMA_CHANNEL_3
  863.   *         @arg @ref LL_DMA_CHANNEL_4
  864.   *         @arg @ref LL_DMA_CHANNEL_5
  865.   *         @arg @ref LL_DMA_CHANNEL_6
  866.   *         @arg @ref LL_DMA_CHANNEL_7
  867.   * @retval Returned value can be one of the following values:
  868.   *         @arg @ref LL_DMA_PRIORITY_LOW
  869.   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
  870.   *         @arg @ref LL_DMA_PRIORITY_HIGH
  871.   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
  872.   */
  873. __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
  874. {
  875.   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  876.                    DMA_CCR_PL));
  877. }
  878.  
  879. /**
  880.   * @brief  Set Number of data to transfer.
  881.   * @note   This action has no effect if
  882.   *         channel is enabled.
  883.   * @rmtoll CNDTR        NDT           LL_DMA_SetDataLength
  884.   * @param  DMAx DMAx Instance
  885.   * @param  Channel This parameter can be one of the following values:
  886.   *         @arg @ref LL_DMA_CHANNEL_1
  887.   *         @arg @ref LL_DMA_CHANNEL_2
  888.   *         @arg @ref LL_DMA_CHANNEL_3
  889.   *         @arg @ref LL_DMA_CHANNEL_4
  890.   *         @arg @ref LL_DMA_CHANNEL_5
  891.   *         @arg @ref LL_DMA_CHANNEL_6
  892.   *         @arg @ref LL_DMA_CHANNEL_7
  893.   * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
  894.   * @retval None
  895.   */
  896. __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
  897. {
  898.   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
  899.              DMA_CNDTR_NDT, NbData);
  900. }
  901.  
  902. /**
  903.   * @brief  Get Number of data to transfer.
  904.   * @note   Once the channel is enabled, the return value indicate the
  905.   *         remaining bytes to be transmitted.
  906.   * @rmtoll CNDTR        NDT           LL_DMA_GetDataLength
  907.   * @param  DMAx DMAx Instance
  908.   * @param  Channel This parameter can be one of the following values:
  909.   *         @arg @ref LL_DMA_CHANNEL_1
  910.   *         @arg @ref LL_DMA_CHANNEL_2
  911.   *         @arg @ref LL_DMA_CHANNEL_3
  912.   *         @arg @ref LL_DMA_CHANNEL_4
  913.   *         @arg @ref LL_DMA_CHANNEL_5
  914.   *         @arg @ref LL_DMA_CHANNEL_6
  915.   *         @arg @ref LL_DMA_CHANNEL_7
  916.   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  917.   */
  918. __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
  919. {
  920.   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
  921.                    DMA_CNDTR_NDT));
  922. }
  923.  
  924. /**
  925.   * @brief  Configure the Source and Destination addresses.
  926.   * @note   This API must not be called when the DMA channel is enabled.
  927.   * @note   Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
  928.   * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
  929.   *         CMAR         MA            LL_DMA_ConfigAddresses
  930.   * @param  DMAx DMAx Instance
  931.   * @param  Channel This parameter can be one of the following values:
  932.   *         @arg @ref LL_DMA_CHANNEL_1
  933.   *         @arg @ref LL_DMA_CHANNEL_2
  934.   *         @arg @ref LL_DMA_CHANNEL_3
  935.   *         @arg @ref LL_DMA_CHANNEL_4
  936.   *         @arg @ref LL_DMA_CHANNEL_5
  937.   *         @arg @ref LL_DMA_CHANNEL_6
  938.   *         @arg @ref LL_DMA_CHANNEL_7
  939.   * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  940.   * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  941.   * @param  Direction This parameter can be one of the following values:
  942.   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  943.   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  944.   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  945.   * @retval None
  946.   */
  947. __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
  948.                                             uint32_t DstAddress, uint32_t Direction)
  949. {
  950.   /* Direction Memory to Periph */
  951.   if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
  952.   {
  953.     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
  954.     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
  955.   }
  956.   /* Direction Periph to Memory and Memory to Memory */
  957.   else
  958.   {
  959.     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
  960.     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
  961.   }
  962. }
  963.  
  964. /**
  965.   * @brief  Set the Memory address.
  966.   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
  967.   * @note   This API must not be called when the DMA channel is enabled.
  968.   * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
  969.   * @param  DMAx DMAx Instance
  970.   * @param  Channel This parameter can be one of the following values:
  971.   *         @arg @ref LL_DMA_CHANNEL_1
  972.   *         @arg @ref LL_DMA_CHANNEL_2
  973.   *         @arg @ref LL_DMA_CHANNEL_3
  974.   *         @arg @ref LL_DMA_CHANNEL_4
  975.   *         @arg @ref LL_DMA_CHANNEL_5
  976.   *         @arg @ref LL_DMA_CHANNEL_6
  977.   *         @arg @ref LL_DMA_CHANNEL_7
  978.   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  979.   * @retval None
  980.   */
  981. __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
  982. {
  983.   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
  984. }
  985.  
  986. /**
  987.   * @brief  Set the Peripheral address.
  988.   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
  989.   * @note   This API must not be called when the DMA channel is enabled.
  990.   * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
  991.   * @param  DMAx DMAx Instance
  992.   * @param  Channel This parameter can be one of the following values:
  993.   *         @arg @ref LL_DMA_CHANNEL_1
  994.   *         @arg @ref LL_DMA_CHANNEL_2
  995.   *         @arg @ref LL_DMA_CHANNEL_3
  996.   *         @arg @ref LL_DMA_CHANNEL_4
  997.   *         @arg @ref LL_DMA_CHANNEL_5
  998.   *         @arg @ref LL_DMA_CHANNEL_6
  999.   *         @arg @ref LL_DMA_CHANNEL_7
  1000.   * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  1001.   * @retval None
  1002.   */
  1003. __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
  1004. {
  1005.   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
  1006. }
  1007.  
  1008. /**
  1009.   * @brief  Get Memory address.
  1010.   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
  1011.   * @rmtoll CMAR         MA            LL_DMA_GetMemoryAddress
  1012.   * @param  DMAx DMAx Instance
  1013.   * @param  Channel This parameter can be one of the following values:
  1014.   *         @arg @ref LL_DMA_CHANNEL_1
  1015.   *         @arg @ref LL_DMA_CHANNEL_2
  1016.   *         @arg @ref LL_DMA_CHANNEL_3
  1017.   *         @arg @ref LL_DMA_CHANNEL_4
  1018.   *         @arg @ref LL_DMA_CHANNEL_5
  1019.   *         @arg @ref LL_DMA_CHANNEL_6
  1020.   *         @arg @ref LL_DMA_CHANNEL_7
  1021.   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  1022.   */
  1023. __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
  1024. {
  1025.   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
  1026. }
  1027.  
  1028. /**
  1029.   * @brief  Get Peripheral address.
  1030.   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
  1031.   * @rmtoll CPAR         PA            LL_DMA_GetPeriphAddress
  1032.   * @param  DMAx DMAx Instance
  1033.   * @param  Channel This parameter can be one of the following values:
  1034.   *         @arg @ref LL_DMA_CHANNEL_1
  1035.   *         @arg @ref LL_DMA_CHANNEL_2
  1036.   *         @arg @ref LL_DMA_CHANNEL_3
  1037.   *         @arg @ref LL_DMA_CHANNEL_4
  1038.   *         @arg @ref LL_DMA_CHANNEL_5
  1039.   *         @arg @ref LL_DMA_CHANNEL_6
  1040.   *         @arg @ref LL_DMA_CHANNEL_7
  1041.   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  1042.   */
  1043. __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
  1044. {
  1045.   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
  1046. }
  1047.  
  1048. /**
  1049.   * @brief  Set the Memory to Memory Source address.
  1050.   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
  1051.   * @note   This API must not be called when the DMA channel is enabled.
  1052.   * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
  1053.   * @param  DMAx DMAx Instance
  1054.   * @param  Channel This parameter can be one of the following values:
  1055.   *         @arg @ref LL_DMA_CHANNEL_1
  1056.   *         @arg @ref LL_DMA_CHANNEL_2
  1057.   *         @arg @ref LL_DMA_CHANNEL_3
  1058.   *         @arg @ref LL_DMA_CHANNEL_4
  1059.   *         @arg @ref LL_DMA_CHANNEL_5
  1060.   *         @arg @ref LL_DMA_CHANNEL_6
  1061.   *         @arg @ref LL_DMA_CHANNEL_7
  1062.   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  1063.   * @retval None
  1064.   */
  1065. __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
  1066. {
  1067.   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
  1068. }
  1069.  
  1070. /**
  1071.   * @brief  Set the Memory to Memory Destination address.
  1072.   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
  1073.   * @note   This API must not be called when the DMA channel is enabled.
  1074.   * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
  1075.   * @param  DMAx DMAx Instance
  1076.   * @param  Channel This parameter can be one of the following values:
  1077.   *         @arg @ref LL_DMA_CHANNEL_1
  1078.   *         @arg @ref LL_DMA_CHANNEL_2
  1079.   *         @arg @ref LL_DMA_CHANNEL_3
  1080.   *         @arg @ref LL_DMA_CHANNEL_4
  1081.   *         @arg @ref LL_DMA_CHANNEL_5
  1082.   *         @arg @ref LL_DMA_CHANNEL_6
  1083.   *         @arg @ref LL_DMA_CHANNEL_7
  1084.   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  1085.   * @retval None
  1086.   */
  1087. __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
  1088. {
  1089.   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
  1090. }
  1091.  
  1092. /**
  1093.   * @brief  Get the Memory to Memory Source address.
  1094.   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
  1095.   * @rmtoll CPAR         PA            LL_DMA_GetM2MSrcAddress
  1096.   * @param  DMAx DMAx Instance
  1097.   * @param  Channel This parameter can be one of the following values:
  1098.   *         @arg @ref LL_DMA_CHANNEL_1
  1099.   *         @arg @ref LL_DMA_CHANNEL_2
  1100.   *         @arg @ref LL_DMA_CHANNEL_3
  1101.   *         @arg @ref LL_DMA_CHANNEL_4
  1102.   *         @arg @ref LL_DMA_CHANNEL_5
  1103.   *         @arg @ref LL_DMA_CHANNEL_6
  1104.   *         @arg @ref LL_DMA_CHANNEL_7
  1105.   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  1106.   */
  1107. __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
  1108. {
  1109.   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
  1110. }
  1111.  
  1112. /**
  1113.   * @brief  Get the Memory to Memory Destination address.
  1114.   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
  1115.   * @rmtoll CMAR         MA            LL_DMA_GetM2MDstAddress
  1116.   * @param  DMAx DMAx Instance
  1117.   * @param  Channel This parameter can be one of the following values:
  1118.   *         @arg @ref LL_DMA_CHANNEL_1
  1119.   *         @arg @ref LL_DMA_CHANNEL_2
  1120.   *         @arg @ref LL_DMA_CHANNEL_3
  1121.   *         @arg @ref LL_DMA_CHANNEL_4
  1122.   *         @arg @ref LL_DMA_CHANNEL_5
  1123.   *         @arg @ref LL_DMA_CHANNEL_6
  1124.   *         @arg @ref LL_DMA_CHANNEL_7
  1125.   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
  1126.   */
  1127. __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
  1128. {
  1129.   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
  1130. }
  1131.  
  1132. /**
  1133.   * @}
  1134.   */
  1135.  
  1136. /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
  1137.   * @{
  1138.   */
  1139.  
  1140. /**
  1141.   * @brief  Get Channel 1 global interrupt flag.
  1142.   * @rmtoll ISR          GIF1          LL_DMA_IsActiveFlag_GI1
  1143.   * @param  DMAx DMAx Instance
  1144.   * @retval State of bit (1 or 0).
  1145.   */
  1146. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
  1147. {
  1148.   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
  1149. }
  1150.  
  1151. /**
  1152.   * @brief  Get Channel 2 global interrupt flag.
  1153.   * @rmtoll ISR          GIF2          LL_DMA_IsActiveFlag_GI2
  1154.   * @param  DMAx DMAx Instance
  1155.   * @retval State of bit (1 or 0).
  1156.   */
  1157. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
  1158. {
  1159.   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
  1160. }
  1161.  
  1162. /**
  1163.   * @brief  Get Channel 3 global interrupt flag.
  1164.   * @rmtoll ISR          GIF3          LL_DMA_IsActiveFlag_GI3
  1165.   * @param  DMAx DMAx Instance
  1166.   * @retval State of bit (1 or 0).
  1167.   */
  1168. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
  1169. {
  1170.   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
  1171. }
  1172.  
  1173. /**
  1174.   * @brief  Get Channel 4 global interrupt flag.
  1175.   * @rmtoll ISR          GIF4          LL_DMA_IsActiveFlag_GI4
  1176.   * @param  DMAx DMAx Instance
  1177.   * @retval State of bit (1 or 0).
  1178.   */
  1179. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
  1180. {
  1181.   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
  1182. }
  1183.  
  1184. /**
  1185.   * @brief  Get Channel 5 global interrupt flag.
  1186.   * @rmtoll ISR          GIF5          LL_DMA_IsActiveFlag_GI5
  1187.   * @param  DMAx DMAx Instance
  1188.   * @retval State of bit (1 or 0).
  1189.   */
  1190. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
  1191. {
  1192.   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
  1193. }
  1194.  
  1195. /**
  1196.   * @brief  Get Channel 6 global interrupt flag.
  1197.   * @rmtoll ISR          GIF6          LL_DMA_IsActiveFlag_GI6
  1198.   * @param  DMAx DMAx Instance
  1199.   * @retval State of bit (1 or 0).
  1200.   */
  1201. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
  1202. {
  1203.   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
  1204. }
  1205.  
  1206. /**
  1207.   * @brief  Get Channel 7 global interrupt flag.
  1208.   * @rmtoll ISR          GIF7          LL_DMA_IsActiveFlag_GI7
  1209.   * @param  DMAx DMAx Instance
  1210.   * @retval State of bit (1 or 0).
  1211.   */
  1212. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
  1213. {
  1214.   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
  1215. }
  1216.  
  1217. /**
  1218.   * @brief  Get Channel 1 transfer complete flag.
  1219.   * @rmtoll ISR          TCIF1         LL_DMA_IsActiveFlag_TC1
  1220.   * @param  DMAx DMAx Instance
  1221.   * @retval State of bit (1 or 0).
  1222.   */
  1223. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
  1224. {
  1225.   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
  1226. }
  1227.  
  1228. /**
  1229.   * @brief  Get Channel 2 transfer complete flag.
  1230.   * @rmtoll ISR          TCIF2         LL_DMA_IsActiveFlag_TC2
  1231.   * @param  DMAx DMAx Instance
  1232.   * @retval State of bit (1 or 0).
  1233.   */
  1234. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
  1235. {
  1236.   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
  1237. }
  1238.  
  1239. /**
  1240.   * @brief  Get Channel 3 transfer complete flag.
  1241.   * @rmtoll ISR          TCIF3         LL_DMA_IsActiveFlag_TC3
  1242.   * @param  DMAx DMAx Instance
  1243.   * @retval State of bit (1 or 0).
  1244.   */
  1245. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
  1246. {
  1247.   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
  1248. }
  1249.  
  1250. /**
  1251.   * @brief  Get Channel 4 transfer complete flag.
  1252.   * @rmtoll ISR          TCIF4         LL_DMA_IsActiveFlag_TC4
  1253.   * @param  DMAx DMAx Instance
  1254.   * @retval State of bit (1 or 0).
  1255.   */
  1256. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
  1257. {
  1258.   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
  1259. }
  1260.  
  1261. /**
  1262.   * @brief  Get Channel 5 transfer complete flag.
  1263.   * @rmtoll ISR          TCIF5         LL_DMA_IsActiveFlag_TC5
  1264.   * @param  DMAx DMAx Instance
  1265.   * @retval State of bit (1 or 0).
  1266.   */
  1267. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
  1268. {
  1269.   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
  1270. }
  1271.  
  1272. /**
  1273.   * @brief  Get Channel 6 transfer complete flag.
  1274.   * @rmtoll ISR          TCIF6         LL_DMA_IsActiveFlag_TC6
  1275.   * @param  DMAx DMAx Instance
  1276.   * @retval State of bit (1 or 0).
  1277.   */
  1278. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
  1279. {
  1280.   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
  1281. }
  1282.  
  1283. /**
  1284.   * @brief  Get Channel 7 transfer complete flag.
  1285.   * @rmtoll ISR          TCIF7         LL_DMA_IsActiveFlag_TC7
  1286.   * @param  DMAx DMAx Instance
  1287.   * @retval State of bit (1 or 0).
  1288.   */
  1289. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
  1290. {
  1291.   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
  1292. }
  1293.  
  1294. /**
  1295.   * @brief  Get Channel 1 half transfer flag.
  1296.   * @rmtoll ISR          HTIF1         LL_DMA_IsActiveFlag_HT1
  1297.   * @param  DMAx DMAx Instance
  1298.   * @retval State of bit (1 or 0).
  1299.   */
  1300. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
  1301. {
  1302.   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
  1303. }
  1304.  
  1305. /**
  1306.   * @brief  Get Channel 2 half transfer flag.
  1307.   * @rmtoll ISR          HTIF2         LL_DMA_IsActiveFlag_HT2
  1308.   * @param  DMAx DMAx Instance
  1309.   * @retval State of bit (1 or 0).
  1310.   */
  1311. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
  1312. {
  1313.   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
  1314. }
  1315.  
  1316. /**
  1317.   * @brief  Get Channel 3 half transfer flag.
  1318.   * @rmtoll ISR          HTIF3         LL_DMA_IsActiveFlag_HT3
  1319.   * @param  DMAx DMAx Instance
  1320.   * @retval State of bit (1 or 0).
  1321.   */
  1322. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
  1323. {
  1324.   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
  1325. }
  1326.  
  1327. /**
  1328.   * @brief  Get Channel 4 half transfer flag.
  1329.   * @rmtoll ISR          HTIF4         LL_DMA_IsActiveFlag_HT4
  1330.   * @param  DMAx DMAx Instance
  1331.   * @retval State of bit (1 or 0).
  1332.   */
  1333. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
  1334. {
  1335.   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
  1336. }
  1337.  
  1338. /**
  1339.   * @brief  Get Channel 5 half transfer flag.
  1340.   * @rmtoll ISR          HTIF5         LL_DMA_IsActiveFlag_HT5
  1341.   * @param  DMAx DMAx Instance
  1342.   * @retval State of bit (1 or 0).
  1343.   */
  1344. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
  1345. {
  1346.   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
  1347. }
  1348.  
  1349. /**
  1350.   * @brief  Get Channel 6 half transfer flag.
  1351.   * @rmtoll ISR          HTIF6         LL_DMA_IsActiveFlag_HT6
  1352.   * @param  DMAx DMAx Instance
  1353.   * @retval State of bit (1 or 0).
  1354.   */
  1355. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
  1356. {
  1357.   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
  1358. }
  1359.  
  1360. /**
  1361.   * @brief  Get Channel 7 half transfer flag.
  1362.   * @rmtoll ISR          HTIF7         LL_DMA_IsActiveFlag_HT7
  1363.   * @param  DMAx DMAx Instance
  1364.   * @retval State of bit (1 or 0).
  1365.   */
  1366. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
  1367. {
  1368.   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
  1369. }
  1370.  
  1371. /**
  1372.   * @brief  Get Channel 1 transfer error flag.
  1373.   * @rmtoll ISR          TEIF1         LL_DMA_IsActiveFlag_TE1
  1374.   * @param  DMAx DMAx Instance
  1375.   * @retval State of bit (1 or 0).
  1376.   */
  1377. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
  1378. {
  1379.   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
  1380. }
  1381.  
  1382. /**
  1383.   * @brief  Get Channel 2 transfer error flag.
  1384.   * @rmtoll ISR          TEIF2         LL_DMA_IsActiveFlag_TE2
  1385.   * @param  DMAx DMAx Instance
  1386.   * @retval State of bit (1 or 0).
  1387.   */
  1388. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
  1389. {
  1390.   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
  1391. }
  1392.  
  1393. /**
  1394.   * @brief  Get Channel 3 transfer error flag.
  1395.   * @rmtoll ISR          TEIF3         LL_DMA_IsActiveFlag_TE3
  1396.   * @param  DMAx DMAx Instance
  1397.   * @retval State of bit (1 or 0).
  1398.   */
  1399. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
  1400. {
  1401.   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
  1402. }
  1403.  
  1404. /**
  1405.   * @brief  Get Channel 4 transfer error flag.
  1406.   * @rmtoll ISR          TEIF4         LL_DMA_IsActiveFlag_TE4
  1407.   * @param  DMAx DMAx Instance
  1408.   * @retval State of bit (1 or 0).
  1409.   */
  1410. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
  1411. {
  1412.   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
  1413. }
  1414.  
  1415. /**
  1416.   * @brief  Get Channel 5 transfer error flag.
  1417.   * @rmtoll ISR          TEIF5         LL_DMA_IsActiveFlag_TE5
  1418.   * @param  DMAx DMAx Instance
  1419.   * @retval State of bit (1 or 0).
  1420.   */
  1421. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
  1422. {
  1423.   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
  1424. }
  1425.  
  1426. /**
  1427.   * @brief  Get Channel 6 transfer error flag.
  1428.   * @rmtoll ISR          TEIF6         LL_DMA_IsActiveFlag_TE6
  1429.   * @param  DMAx DMAx Instance
  1430.   * @retval State of bit (1 or 0).
  1431.   */
  1432. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
  1433. {
  1434.   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
  1435. }
  1436.  
  1437. /**
  1438.   * @brief  Get Channel 7 transfer error flag.
  1439.   * @rmtoll ISR          TEIF7         LL_DMA_IsActiveFlag_TE7
  1440.   * @param  DMAx DMAx Instance
  1441.   * @retval State of bit (1 or 0).
  1442.   */
  1443. __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
  1444. {
  1445.   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
  1446. }
  1447.  
  1448. /**
  1449.   * @brief  Clear Channel 1 global interrupt flag.
  1450.   * @rmtoll IFCR         CGIF1         LL_DMA_ClearFlag_GI1
  1451.   * @param  DMAx DMAx Instance
  1452.   * @retval None
  1453.   */
  1454. __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
  1455. {
  1456.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
  1457. }
  1458.  
  1459. /**
  1460.   * @brief  Clear Channel 2 global interrupt flag.
  1461.   * @rmtoll IFCR         CGIF2         LL_DMA_ClearFlag_GI2
  1462.   * @param  DMAx DMAx Instance
  1463.   * @retval None
  1464.   */
  1465. __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
  1466. {
  1467.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
  1468. }
  1469.  
  1470. /**
  1471.   * @brief  Clear Channel 3 global interrupt flag.
  1472.   * @rmtoll IFCR         CGIF3         LL_DMA_ClearFlag_GI3
  1473.   * @param  DMAx DMAx Instance
  1474.   * @retval None
  1475.   */
  1476. __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
  1477. {
  1478.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
  1479. }
  1480.  
  1481. /**
  1482.   * @brief  Clear Channel 4 global interrupt flag.
  1483.   * @rmtoll IFCR         CGIF4         LL_DMA_ClearFlag_GI4
  1484.   * @param  DMAx DMAx Instance
  1485.   * @retval None
  1486.   */
  1487. __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
  1488. {
  1489.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
  1490. }
  1491.  
  1492. /**
  1493.   * @brief  Clear Channel 5 global interrupt flag.
  1494.   * @rmtoll IFCR         CGIF5         LL_DMA_ClearFlag_GI5
  1495.   * @param  DMAx DMAx Instance
  1496.   * @retval None
  1497.   */
  1498. __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
  1499. {
  1500.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
  1501. }
  1502.  
  1503. /**
  1504.   * @brief  Clear Channel 6 global interrupt flag.
  1505.   * @rmtoll IFCR         CGIF6         LL_DMA_ClearFlag_GI6
  1506.   * @param  DMAx DMAx Instance
  1507.   * @retval None
  1508.   */
  1509. __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
  1510. {
  1511.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
  1512. }
  1513.  
  1514. /**
  1515.   * @brief  Clear Channel 7 global interrupt flag.
  1516.   * @rmtoll IFCR         CGIF7         LL_DMA_ClearFlag_GI7
  1517.   * @param  DMAx DMAx Instance
  1518.   * @retval None
  1519.   */
  1520. __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
  1521. {
  1522.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
  1523. }
  1524.  
  1525. /**
  1526.   * @brief  Clear Channel 1  transfer complete flag.
  1527.   * @rmtoll IFCR         CTCIF1        LL_DMA_ClearFlag_TC1
  1528.   * @param  DMAx DMAx Instance
  1529.   * @retval None
  1530.   */
  1531. __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
  1532. {
  1533.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
  1534. }
  1535.  
  1536. /**
  1537.   * @brief  Clear Channel 2  transfer complete flag.
  1538.   * @rmtoll IFCR         CTCIF2        LL_DMA_ClearFlag_TC2
  1539.   * @param  DMAx DMAx Instance
  1540.   * @retval None
  1541.   */
  1542. __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
  1543. {
  1544.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
  1545. }
  1546.  
  1547. /**
  1548.   * @brief  Clear Channel 3  transfer complete flag.
  1549.   * @rmtoll IFCR         CTCIF3        LL_DMA_ClearFlag_TC3
  1550.   * @param  DMAx DMAx Instance
  1551.   * @retval None
  1552.   */
  1553. __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
  1554. {
  1555.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
  1556. }
  1557.  
  1558. /**
  1559.   * @brief  Clear Channel 4  transfer complete flag.
  1560.   * @rmtoll IFCR         CTCIF4        LL_DMA_ClearFlag_TC4
  1561.   * @param  DMAx DMAx Instance
  1562.   * @retval None
  1563.   */
  1564. __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
  1565. {
  1566.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
  1567. }
  1568.  
  1569. /**
  1570.   * @brief  Clear Channel 5  transfer complete flag.
  1571.   * @rmtoll IFCR         CTCIF5        LL_DMA_ClearFlag_TC5
  1572.   * @param  DMAx DMAx Instance
  1573.   * @retval None
  1574.   */
  1575. __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
  1576. {
  1577.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
  1578. }
  1579.  
  1580. /**
  1581.   * @brief  Clear Channel 6  transfer complete flag.
  1582.   * @rmtoll IFCR         CTCIF6        LL_DMA_ClearFlag_TC6
  1583.   * @param  DMAx DMAx Instance
  1584.   * @retval None
  1585.   */
  1586. __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
  1587. {
  1588.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
  1589. }
  1590.  
  1591. /**
  1592.   * @brief  Clear Channel 7  transfer complete flag.
  1593.   * @rmtoll IFCR         CTCIF7        LL_DMA_ClearFlag_TC7
  1594.   * @param  DMAx DMAx Instance
  1595.   * @retval None
  1596.   */
  1597. __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
  1598. {
  1599.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
  1600. }
  1601.  
  1602. /**
  1603.   * @brief  Clear Channel 1  half transfer flag.
  1604.   * @rmtoll IFCR         CHTIF1        LL_DMA_ClearFlag_HT1
  1605.   * @param  DMAx DMAx Instance
  1606.   * @retval None
  1607.   */
  1608. __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
  1609. {
  1610.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
  1611. }
  1612.  
  1613. /**
  1614.   * @brief  Clear Channel 2  half transfer flag.
  1615.   * @rmtoll IFCR         CHTIF2        LL_DMA_ClearFlag_HT2
  1616.   * @param  DMAx DMAx Instance
  1617.   * @retval None
  1618.   */
  1619. __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
  1620. {
  1621.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
  1622. }
  1623.  
  1624. /**
  1625.   * @brief  Clear Channel 3  half transfer flag.
  1626.   * @rmtoll IFCR         CHTIF3        LL_DMA_ClearFlag_HT3
  1627.   * @param  DMAx DMAx Instance
  1628.   * @retval None
  1629.   */
  1630. __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
  1631. {
  1632.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
  1633. }
  1634.  
  1635. /**
  1636.   * @brief  Clear Channel 4  half transfer flag.
  1637.   * @rmtoll IFCR         CHTIF4        LL_DMA_ClearFlag_HT4
  1638.   * @param  DMAx DMAx Instance
  1639.   * @retval None
  1640.   */
  1641. __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
  1642. {
  1643.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
  1644. }
  1645.  
  1646. /**
  1647.   * @brief  Clear Channel 5  half transfer flag.
  1648.   * @rmtoll IFCR         CHTIF5        LL_DMA_ClearFlag_HT5
  1649.   * @param  DMAx DMAx Instance
  1650.   * @retval None
  1651.   */
  1652. __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
  1653. {
  1654.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
  1655. }
  1656.  
  1657. /**
  1658.   * @brief  Clear Channel 6  half transfer flag.
  1659.   * @rmtoll IFCR         CHTIF6        LL_DMA_ClearFlag_HT6
  1660.   * @param  DMAx DMAx Instance
  1661.   * @retval None
  1662.   */
  1663. __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
  1664. {
  1665.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
  1666. }
  1667.  
  1668. /**
  1669.   * @brief  Clear Channel 7  half transfer flag.
  1670.   * @rmtoll IFCR         CHTIF7        LL_DMA_ClearFlag_HT7
  1671.   * @param  DMAx DMAx Instance
  1672.   * @retval None
  1673.   */
  1674. __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
  1675. {
  1676.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
  1677. }
  1678.  
  1679. /**
  1680.   * @brief  Clear Channel 1 transfer error flag.
  1681.   * @rmtoll IFCR         CTEIF1        LL_DMA_ClearFlag_TE1
  1682.   * @param  DMAx DMAx Instance
  1683.   * @retval None
  1684.   */
  1685. __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
  1686. {
  1687.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
  1688. }
  1689.  
  1690. /**
  1691.   * @brief  Clear Channel 2 transfer error flag.
  1692.   * @rmtoll IFCR         CTEIF2        LL_DMA_ClearFlag_TE2
  1693.   * @param  DMAx DMAx Instance
  1694.   * @retval None
  1695.   */
  1696. __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
  1697. {
  1698.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
  1699. }
  1700.  
  1701. /**
  1702.   * @brief  Clear Channel 3 transfer error flag.
  1703.   * @rmtoll IFCR         CTEIF3        LL_DMA_ClearFlag_TE3
  1704.   * @param  DMAx DMAx Instance
  1705.   * @retval None
  1706.   */
  1707. __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
  1708. {
  1709.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
  1710. }
  1711.  
  1712. /**
  1713.   * @brief  Clear Channel 4 transfer error flag.
  1714.   * @rmtoll IFCR         CTEIF4        LL_DMA_ClearFlag_TE4
  1715.   * @param  DMAx DMAx Instance
  1716.   * @retval None
  1717.   */
  1718. __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
  1719. {
  1720.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
  1721. }
  1722.  
  1723. /**
  1724.   * @brief  Clear Channel 5 transfer error flag.
  1725.   * @rmtoll IFCR         CTEIF5        LL_DMA_ClearFlag_TE5
  1726.   * @param  DMAx DMAx Instance
  1727.   * @retval None
  1728.   */
  1729. __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
  1730. {
  1731.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
  1732. }
  1733.  
  1734. /**
  1735.   * @brief  Clear Channel 6 transfer error flag.
  1736.   * @rmtoll IFCR         CTEIF6        LL_DMA_ClearFlag_TE6
  1737.   * @param  DMAx DMAx Instance
  1738.   * @retval None
  1739.   */
  1740. __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
  1741. {
  1742.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
  1743. }
  1744.  
  1745. /**
  1746.   * @brief  Clear Channel 7 transfer error flag.
  1747.   * @rmtoll IFCR         CTEIF7        LL_DMA_ClearFlag_TE7
  1748.   * @param  DMAx DMAx Instance
  1749.   * @retval None
  1750.   */
  1751. __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
  1752. {
  1753.   WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
  1754. }
  1755.  
  1756. /**
  1757.   * @}
  1758.   */
  1759.  
  1760. /** @defgroup DMA_LL_EF_IT_Management IT_Management
  1761.   * @{
  1762.   */
  1763.  
  1764. /**
  1765.   * @brief  Enable Transfer complete interrupt.
  1766.   * @rmtoll CCR          TCIE          LL_DMA_EnableIT_TC
  1767.   * @param  DMAx DMAx Instance
  1768.   * @param  Channel This parameter can be one of the following values:
  1769.   *         @arg @ref LL_DMA_CHANNEL_1
  1770.   *         @arg @ref LL_DMA_CHANNEL_2
  1771.   *         @arg @ref LL_DMA_CHANNEL_3
  1772.   *         @arg @ref LL_DMA_CHANNEL_4
  1773.   *         @arg @ref LL_DMA_CHANNEL_5
  1774.   *         @arg @ref LL_DMA_CHANNEL_6
  1775.   *         @arg @ref LL_DMA_CHANNEL_7
  1776.   * @retval None
  1777.   */
  1778. __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
  1779. {
  1780.   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
  1781. }
  1782.  
  1783. /**
  1784.   * @brief  Enable Half transfer interrupt.
  1785.   * @rmtoll CCR          HTIE          LL_DMA_EnableIT_HT
  1786.   * @param  DMAx DMAx Instance
  1787.   * @param  Channel This parameter can be one of the following values:
  1788.   *         @arg @ref LL_DMA_CHANNEL_1
  1789.   *         @arg @ref LL_DMA_CHANNEL_2
  1790.   *         @arg @ref LL_DMA_CHANNEL_3
  1791.   *         @arg @ref LL_DMA_CHANNEL_4
  1792.   *         @arg @ref LL_DMA_CHANNEL_5
  1793.   *         @arg @ref LL_DMA_CHANNEL_6
  1794.   *         @arg @ref LL_DMA_CHANNEL_7
  1795.   * @retval None
  1796.   */
  1797. __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
  1798. {
  1799.   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
  1800. }
  1801.  
  1802. /**
  1803.   * @brief  Enable Transfer error interrupt.
  1804.   * @rmtoll CCR          TEIE          LL_DMA_EnableIT_TE
  1805.   * @param  DMAx DMAx Instance
  1806.   * @param  Channel This parameter can be one of the following values:
  1807.   *         @arg @ref LL_DMA_CHANNEL_1
  1808.   *         @arg @ref LL_DMA_CHANNEL_2
  1809.   *         @arg @ref LL_DMA_CHANNEL_3
  1810.   *         @arg @ref LL_DMA_CHANNEL_4
  1811.   *         @arg @ref LL_DMA_CHANNEL_5
  1812.   *         @arg @ref LL_DMA_CHANNEL_6
  1813.   *         @arg @ref LL_DMA_CHANNEL_7
  1814.   * @retval None
  1815.   */
  1816. __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
  1817. {
  1818.   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
  1819. }
  1820.  
  1821. /**
  1822.   * @brief  Disable Transfer complete interrupt.
  1823.   * @rmtoll CCR          TCIE          LL_DMA_DisableIT_TC
  1824.   * @param  DMAx DMAx Instance
  1825.   * @param  Channel This parameter can be one of the following values:
  1826.   *         @arg @ref LL_DMA_CHANNEL_1
  1827.   *         @arg @ref LL_DMA_CHANNEL_2
  1828.   *         @arg @ref LL_DMA_CHANNEL_3
  1829.   *         @arg @ref LL_DMA_CHANNEL_4
  1830.   *         @arg @ref LL_DMA_CHANNEL_5
  1831.   *         @arg @ref LL_DMA_CHANNEL_6
  1832.   *         @arg @ref LL_DMA_CHANNEL_7
  1833.   * @retval None
  1834.   */
  1835. __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
  1836. {
  1837.   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
  1838. }
  1839.  
  1840. /**
  1841.   * @brief  Disable Half transfer interrupt.
  1842.   * @rmtoll CCR          HTIE          LL_DMA_DisableIT_HT
  1843.   * @param  DMAx DMAx Instance
  1844.   * @param  Channel This parameter can be one of the following values:
  1845.   *         @arg @ref LL_DMA_CHANNEL_1
  1846.   *         @arg @ref LL_DMA_CHANNEL_2
  1847.   *         @arg @ref LL_DMA_CHANNEL_3
  1848.   *         @arg @ref LL_DMA_CHANNEL_4
  1849.   *         @arg @ref LL_DMA_CHANNEL_5
  1850.   *         @arg @ref LL_DMA_CHANNEL_6
  1851.   *         @arg @ref LL_DMA_CHANNEL_7
  1852.   * @retval None
  1853.   */
  1854. __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
  1855. {
  1856.   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
  1857. }
  1858.  
  1859. /**
  1860.   * @brief  Disable Transfer error interrupt.
  1861.   * @rmtoll CCR          TEIE          LL_DMA_DisableIT_TE
  1862.   * @param  DMAx DMAx Instance
  1863.   * @param  Channel This parameter can be one of the following values:
  1864.   *         @arg @ref LL_DMA_CHANNEL_1
  1865.   *         @arg @ref LL_DMA_CHANNEL_2
  1866.   *         @arg @ref LL_DMA_CHANNEL_3
  1867.   *         @arg @ref LL_DMA_CHANNEL_4
  1868.   *         @arg @ref LL_DMA_CHANNEL_5
  1869.   *         @arg @ref LL_DMA_CHANNEL_6
  1870.   *         @arg @ref LL_DMA_CHANNEL_7
  1871.   * @retval None
  1872.   */
  1873. __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
  1874. {
  1875.   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
  1876. }
  1877.  
  1878. /**
  1879.   * @brief  Check if Transfer complete Interrupt is enabled.
  1880.   * @rmtoll CCR          TCIE          LL_DMA_IsEnabledIT_TC
  1881.   * @param  DMAx DMAx Instance
  1882.   * @param  Channel This parameter can be one of the following values:
  1883.   *         @arg @ref LL_DMA_CHANNEL_1
  1884.   *         @arg @ref LL_DMA_CHANNEL_2
  1885.   *         @arg @ref LL_DMA_CHANNEL_3
  1886.   *         @arg @ref LL_DMA_CHANNEL_4
  1887.   *         @arg @ref LL_DMA_CHANNEL_5
  1888.   *         @arg @ref LL_DMA_CHANNEL_6
  1889.   *         @arg @ref LL_DMA_CHANNEL_7
  1890.   * @retval State of bit (1 or 0).
  1891.   */
  1892. __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
  1893. {
  1894.   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  1895.                    DMA_CCR_TCIE) == (DMA_CCR_TCIE));
  1896. }
  1897.  
  1898. /**
  1899.   * @brief  Check if Half transfer Interrupt is enabled.
  1900.   * @rmtoll CCR          HTIE          LL_DMA_IsEnabledIT_HT
  1901.   * @param  DMAx DMAx Instance
  1902.   * @param  Channel This parameter can be one of the following values:
  1903.   *         @arg @ref LL_DMA_CHANNEL_1
  1904.   *         @arg @ref LL_DMA_CHANNEL_2
  1905.   *         @arg @ref LL_DMA_CHANNEL_3
  1906.   *         @arg @ref LL_DMA_CHANNEL_4
  1907.   *         @arg @ref LL_DMA_CHANNEL_5
  1908.   *         @arg @ref LL_DMA_CHANNEL_6
  1909.   *         @arg @ref LL_DMA_CHANNEL_7
  1910.   * @retval State of bit (1 or 0).
  1911.   */
  1912. __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
  1913. {
  1914.   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  1915.                    DMA_CCR_HTIE) == (DMA_CCR_HTIE));
  1916. }
  1917.  
  1918. /**
  1919.   * @brief  Check if Transfer error Interrupt is enabled.
  1920.   * @rmtoll CCR          TEIE          LL_DMA_IsEnabledIT_TE
  1921.   * @param  DMAx DMAx Instance
  1922.   * @param  Channel This parameter can be one of the following values:
  1923.   *         @arg @ref LL_DMA_CHANNEL_1
  1924.   *         @arg @ref LL_DMA_CHANNEL_2
  1925.   *         @arg @ref LL_DMA_CHANNEL_3
  1926.   *         @arg @ref LL_DMA_CHANNEL_4
  1927.   *         @arg @ref LL_DMA_CHANNEL_5
  1928.   *         @arg @ref LL_DMA_CHANNEL_6
  1929.   *         @arg @ref LL_DMA_CHANNEL_7
  1930.   * @retval State of bit (1 or 0).
  1931.   */
  1932. __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
  1933. {
  1934.   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
  1935.                    DMA_CCR_TEIE) == (DMA_CCR_TEIE));
  1936. }
  1937.  
  1938. /**
  1939.   * @}
  1940.   */
  1941.  
  1942. #if defined(USE_FULL_LL_DRIVER)
  1943. /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
  1944.   * @{
  1945.   */
  1946.  
  1947. uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
  1948. uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
  1949. void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
  1950.  
  1951. /**
  1952.   * @}
  1953.   */
  1954. #endif /* USE_FULL_LL_DRIVER */
  1955.  
  1956. /**
  1957.   * @}
  1958.   */
  1959.  
  1960. /**
  1961.   * @}
  1962.   */
  1963.  
  1964. #endif /* DMA1 || DMA2 */
  1965.  
  1966. /**
  1967.   * @}
  1968.   */
  1969.  
  1970. #ifdef __cplusplus
  1971. }
  1972. #endif
  1973.  
  1974. #endif /* __STM32F1xx_LL_DMA_H */
  1975.  
  1976. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1977.