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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_tim.h
  4.   * @author  MCD Application Team
  5.   * @version V1.0.4
  6.   * @date    29-April-2016
  7.   * @brief   Header file of TIM HAL module.
  8.   ******************************************************************************
  9.   * @attention
  10.   *
  11.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  12.   *
  13.   * Redistribution and use in source and binary forms, with or without modification,
  14.   * are permitted provided that the following conditions are met:
  15.   *   1. Redistributions of source code must retain the above copyright notice,
  16.   *      this list of conditions and the following disclaimer.
  17.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18.   *      this list of conditions and the following disclaimer in the documentation
  19.   *      and/or other materials provided with the distribution.
  20.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21.   *      may be used to endorse or promote products derived from this software
  22.   *      without specific prior written permission.
  23.   *
  24.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34.   *
  35.   ******************************************************************************
  36.   */
  37.  
  38. /* Define to prevent recursive inclusion -------------------------------------*/
  39. #ifndef __STM32F1xx_HAL_TIM_H
  40. #define __STM32F1xx_HAL_TIM_H
  41.  
  42. #ifdef __cplusplus
  43.  extern "C" {
  44. #endif
  45.  
  46. /* Includes ------------------------------------------------------------------*/
  47. #include "stm32f1xx_hal_def.h"
  48.  
  49. /** @addtogroup STM32F1xx_HAL_Driver
  50.   * @{
  51.   */
  52.  
  53. /** @addtogroup TIM
  54.   * @{
  55.   */
  56.  
  57. /* Exported types ------------------------------------------------------------*/
  58. /** @defgroup TIM_Exported_Types TIM Exported Types
  59.   * @{
  60.   */
  61. /**
  62.   * @brief  TIM Time base Configuration Structure definition
  63.   */
  64. typedef struct
  65. {
  66.   uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
  67.                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
  68.  
  69.   uint32_t CounterMode;       /*!< Specifies the counter mode.
  70.                                    This parameter can be a value of @ref TIM_Counter_Mode */
  71.  
  72.   uint32_t Period;            /*!< Specifies the period value to be loaded into the active
  73.                                    Auto-Reload Register at the next update event.
  74.                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
  75.  
  76.   uint32_t ClockDivision;     /*!< Specifies the clock division.
  77.                                    This parameter can be a value of @ref TIM_ClockDivision */
  78.  
  79.   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
  80.                                     reaches zero, an update event is generated and counting restarts
  81.                                     from the RCR value (N).
  82.                                     This means in PWM mode that (N+1) corresponds to:
  83.                                         - the number of PWM periods in edge-aligned mode
  84.                                         - the number of half PWM period in center-aligned mode
  85.                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
  86.                                      @note This parameter is valid only for TIM1 and TIM8. */
  87. } TIM_Base_InitTypeDef;
  88.  
  89. /**
  90.   * @brief  TIM Output Compare Configuration Structure definition
  91.   */
  92. typedef struct
  93. {
  94.   uint32_t OCMode;        /*!< Specifies the TIM mode.
  95.                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
  96.  
  97.   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
  98.                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
  99.  
  100.   uint32_t OCPolarity;    /*!< Specifies the output polarity.
  101.                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
  102.  
  103.   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
  104.                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
  105.                                @note This parameter is valid only for TIM1 and TIM8. */
  106.  
  107.   uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
  108.                                This parameter can be a value of @ref TIM_Output_Fast_State
  109.                                @note This parameter is valid only in PWM1 and PWM2 mode. */
  110.  
  111.  
  112.   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
  113.                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
  114.                                @note This parameter is valid only for TIM1 and TIM8. */
  115.  
  116.   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
  117.                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
  118.                                @note This parameter is valid only for TIM1 and TIM8. */
  119. } TIM_OC_InitTypeDef;
  120.  
  121. /**
  122.   * @brief  TIM One Pulse Mode Configuration Structure definition
  123.   */
  124. typedef struct
  125. {
  126.   uint32_t OCMode;        /*!< Specifies the TIM mode.
  127.                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
  128.  
  129.   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
  130.                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
  131.  
  132.   uint32_t OCPolarity;    /*!< Specifies the output polarity.
  133.                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
  134.  
  135.   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
  136.                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
  137.                                @note This parameter is valid only for TIM1 and TIM8. */
  138.  
  139.   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
  140.                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
  141.                                @note This parameter is valid only for TIM1 and TIM8. */
  142.  
  143.   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
  144.                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
  145.                                @note This parameter is valid only for TIM1 and TIM8. */
  146.  
  147.   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
  148.                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
  149.  
  150.   uint32_t ICSelection;   /*!< Specifies the input.
  151.                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
  152.  
  153.   uint32_t ICFilter;      /*!< Specifies the input capture filter.
  154.                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  155. } TIM_OnePulse_InitTypeDef;
  156.  
  157.  
  158. /**
  159.   * @brief  TIM Input Capture Configuration Structure definition
  160.   */
  161. typedef struct
  162. {
  163.   uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
  164.                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
  165.  
  166.   uint32_t ICSelection;  /*!< Specifies the input.
  167.                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
  168.  
  169.   uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
  170.                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
  171.  
  172.   uint32_t ICFilter;     /*!< Specifies the input capture filter.
  173.                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  174. } TIM_IC_InitTypeDef;
  175.  
  176. /**
  177.   * @brief  TIM Encoder Configuration Structure definition
  178.   */
  179. typedef struct
  180. {
  181.   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
  182.                                This parameter can be a value of @ref TIM_Encoder_Mode */
  183.  
  184.   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
  185.                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
  186.  
  187.   uint32_t IC1Selection;  /*!< Specifies the input.
  188.                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
  189.  
  190.   uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
  191.                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
  192.  
  193.   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
  194.                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  195.  
  196.   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
  197.                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
  198.  
  199.   uint32_t IC2Selection;  /*!< Specifies the input.
  200.                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
  201.  
  202.   uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
  203.                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
  204.  
  205.   uint32_t IC2Filter;     /*!< Specifies the input capture filter.
  206.                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  207. } TIM_Encoder_InitTypeDef;
  208.  
  209.  
  210. /**
  211.   * @brief  TIM Clock Configuration Handle Structure definition
  212.   */
  213. typedef struct
  214. {
  215.   uint32_t ClockSource;     /*!< TIM clock sources
  216.                                  This parameter can be a value of @ref TIM_Clock_Source */
  217.   uint32_t ClockPolarity;   /*!< TIM clock polarity
  218.                                  This parameter can be a value of @ref TIM_Clock_Polarity */
  219.   uint32_t ClockPrescaler;  /*!< TIM clock prescaler
  220.                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
  221.   uint32_t ClockFilter;    /*!< TIM clock filter
  222.                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  223. }TIM_ClockConfigTypeDef;
  224.  
  225. /**
  226.   * @brief  TIM Clear Input Configuration Handle Structure definition
  227.   */
  228. typedef struct
  229. {
  230.   uint32_t ClearInputState;      /*!< TIM clear Input state
  231.                                       This parameter can be ENABLE or DISABLE */
  232.   uint32_t ClearInputSource;     /*!< TIM clear Input sources
  233.                                       This parameter can be a value of @ref TIM_ClearInput_Source */
  234.   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
  235.                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
  236.   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
  237.                                       This parameter can be a value of @ref TIM_ClearInput_Prescaler */
  238.   uint32_t ClearInputFilter;    /*!< TIM Clear Input filter
  239.                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  240. }TIM_ClearInputConfigTypeDef;
  241.  
  242. /**
  243.   * @brief  TIM Slave configuration Structure definition
  244.   */
  245. typedef struct {
  246.   uint32_t  SlaveMode;      /*!< Slave mode selection
  247.                                This parameter can be a value of @ref TIM_Slave_Mode */
  248.   uint32_t  InputTrigger;      /*!< Input Trigger source
  249.                                   This parameter can be a value of @ref TIM_Trigger_Selection */
  250.   uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
  251.                                   This parameter can be a value of @ref TIM_Trigger_Polarity */
  252.   uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
  253.                                   This parameter can be a value of @ref TIM_Trigger_Prescaler */
  254.   uint32_t  TriggerFilter;     /*!< Input trigger filter
  255.                                   This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  256.  
  257. }TIM_SlaveConfigTypeDef;
  258.  
  259. /**
  260.   * @brief  HAL State structures definition
  261.   */
  262. typedef enum
  263. {
  264.   HAL_TIM_STATE_RESET             = 0x00,    /*!< Peripheral not yet initialized or disabled  */
  265.   HAL_TIM_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use    */
  266.   HAL_TIM_STATE_BUSY              = 0x02,    /*!< An internal process is ongoing              */
  267.   HAL_TIM_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                               */
  268.   HAL_TIM_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                */
  269. }HAL_TIM_StateTypeDef;
  270.  
  271. /**
  272.   * @brief  HAL Active channel structures definition
  273.   */
  274. typedef enum
  275. {
  276.   HAL_TIM_ACTIVE_CHANNEL_1        = 0x01,    /*!< The active channel is 1     */
  277.   HAL_TIM_ACTIVE_CHANNEL_2        = 0x02,    /*!< The active channel is 2     */
  278.   HAL_TIM_ACTIVE_CHANNEL_3        = 0x04,    /*!< The active channel is 3     */
  279.   HAL_TIM_ACTIVE_CHANNEL_4        = 0x08,    /*!< The active channel is 4     */
  280.   HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00    /*!< All active channels cleared */
  281. }HAL_TIM_ActiveChannel;
  282.  
  283. /**
  284.   * @brief  TIM Time Base Handle Structure definition
  285.   */
  286. typedef struct
  287. {
  288.   TIM_TypeDef              *Instance;     /*!< Register base address             */
  289.   TIM_Base_InitTypeDef     Init;          /*!< TIM Time Base required parameters */
  290.   HAL_TIM_ActiveChannel    Channel;       /*!< Active channel                    */
  291.   DMA_HandleTypeDef        *hdma[7];      /*!< DMA Handlers array
  292.                                              This array is accessed by a @ref TIM_DMA_Handle_index */
  293.   HAL_LockTypeDef          Lock;          /*!< Locking object                    */
  294.   __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
  295. }TIM_HandleTypeDef;
  296.  
  297. /**
  298.   * @}
  299.   */
  300.  
  301. /* Exported constants --------------------------------------------------------*/
  302. /** @defgroup TIM_Exported_Constants TIM Exported Constants
  303.   * @{
  304.   */
  305.  
  306. /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
  307.   * @{
  308.   */
  309. #define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000)            /*!< Polarity for TIx source */
  310. #define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
  311. #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
  312. /**
  313.   * @}
  314.   */
  315.  
  316. /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
  317.   * @{
  318.   */
  319. #define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
  320. #define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000)                /*!< Polarity for ETR source */
  321. /**
  322.   * @}
  323.   */
  324.  
  325. /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
  326.   * @{
  327.   */
  328. #define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000)                /*!< No prescaler is used */
  329. #define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
  330. #define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
  331. #define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
  332. /**
  333.   * @}
  334.   */
  335.  
  336. /** @defgroup TIM_Counter_Mode TIM Counter Mode
  337.   * @{
  338.   */
  339. #define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000)
  340. #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
  341. #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
  342. #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
  343. #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
  344. /**
  345.   * @}
  346.   */
  347.  
  348. /** @defgroup TIM_ClockDivision TIM ClockDivision
  349.   * @{
  350.   */
  351. #define TIM_CLOCKDIVISION_DIV1                       ((uint32_t)0x0000)
  352. #define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)
  353. #define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)
  354. /**
  355.   * @}
  356.   */
  357.  
  358. /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
  359.   * @{
  360.   */
  361. #define TIM_OCMODE_TIMING                   ((uint32_t)0x0000)
  362. #define TIM_OCMODE_ACTIVE                   (TIM_CCMR1_OC1M_0)
  363. #define TIM_OCMODE_INACTIVE                 (TIM_CCMR1_OC1M_1)
  364. #define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
  365. #define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
  366. #define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M)
  367. #define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
  368. #define TIM_OCMODE_FORCED_INACTIVE          (TIM_CCMR1_OC1M_2)
  369. /**
  370.   * @}
  371.   */
  372.  
  373. /** @defgroup TIM_Output_Compare_State TIM Output Compare State
  374.   * @{
  375.   */
  376. #define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000)
  377. #define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)
  378. /**
  379.   * @}
  380.   */
  381.  
  382. /** @defgroup TIM_Output_Fast_State TIM Output Fast State
  383.   * @{
  384.   */
  385. #define TIM_OCFAST_DISABLE                ((uint32_t)0x0000)
  386. #define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)
  387. /**
  388.   * @}
  389.   */
  390.  
  391. /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
  392.   * @{
  393.   */
  394. #define TIM_OUTPUTNSTATE_DISABLE            ((uint32_t)0x0000)
  395. #define TIM_OUTPUTNSTATE_ENABLE             (TIM_CCER_CC1NE)
  396. /**
  397.   * @}
  398.   */
  399.  
  400. /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
  401.   * @{
  402.   */
  403. #define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000)
  404. #define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
  405. /**
  406.   * @}
  407.   */
  408.  
  409. /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
  410.   * @{
  411.   */
  412. #define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x0000)
  413. #define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
  414. /**
  415.   * @}
  416.   */
  417.  
  418. /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
  419.   * @{
  420.   */
  421. #define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
  422. #define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000)
  423. /**
  424.   * @}
  425.   */
  426.  
  427. /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
  428.   * @{
  429.   */
  430. #define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
  431. #define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x0000)
  432. /**
  433.   * @}
  434.   */
  435.  
  436. /** @defgroup TIM_Channel TIM Channel
  437.   * @{
  438.   */
  439. #define TIM_CHANNEL_1                      ((uint32_t)0x0000)
  440. #define TIM_CHANNEL_2                      ((uint32_t)0x0004)
  441. #define TIM_CHANNEL_3                      ((uint32_t)0x0008)
  442. #define TIM_CHANNEL_4                      ((uint32_t)0x000C)
  443. #define TIM_CHANNEL_ALL                    ((uint32_t)0x0018)
  444. /**
  445.   * @}
  446.   */
  447.  
  448. /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
  449.   * @{
  450.   */
  451. #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
  452. #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
  453. #define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
  454. /**
  455.   * @}
  456.   */
  457.  
  458. /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
  459.   * @{
  460.   */
  461. #define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
  462.                                                                                connected to IC1, IC2, IC3 or IC4, respectively */
  463. #define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
  464.                                                                                connected to IC2, IC1, IC4 or IC3, respectively */
  465. #define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
  466. /**
  467.   * @}
  468.   */
  469.  
  470. /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
  471.   * @{
  472.   */
  473. #define TIM_ICPSC_DIV1                     ((uint32_t)0x0000)                 /*!< Capture performed each time an edge is detected on the capture input */
  474. #define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
  475. #define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
  476. #define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
  477. /**
  478.   * @}
  479.   */
  480.  
  481. /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
  482.   * @{
  483.   */
  484. #define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
  485. #define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000)
  486. /**
  487.   * @}
  488.   */
  489.  
  490. /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
  491.   * @{
  492.   */
  493. #define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
  494. #define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
  495. #define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
  496. /**
  497.   * @}
  498.   */
  499.  
  500. /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
  501.   * @{
  502.   */
  503. #define TIM_IT_UPDATE           (TIM_DIER_UIE)
  504. #define TIM_IT_CC1              (TIM_DIER_CC1IE)
  505. #define TIM_IT_CC2              (TIM_DIER_CC2IE)
  506. #define TIM_IT_CC3              (TIM_DIER_CC3IE)
  507. #define TIM_IT_CC4              (TIM_DIER_CC4IE)
  508. #define TIM_IT_COM              (TIM_DIER_COMIE)
  509. #define TIM_IT_TRIGGER          (TIM_DIER_TIE)
  510. #define TIM_IT_BREAK            (TIM_DIER_BIE)
  511. /**
  512.   * @}
  513.   */
  514.  
  515. /** @defgroup TIM_Commutation_Source  TIM Commutation Source
  516.   * @{
  517.   */
  518. #define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
  519. #define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x0000)
  520.  
  521. /**
  522.   * @}
  523.   */
  524.  
  525. /** @defgroup TIM_DMA_sources TIM DMA Sources
  526.   * @{
  527.   */
  528. #define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
  529. #define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
  530. #define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
  531. #define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
  532. #define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
  533. #define TIM_DMA_COM                        (TIM_DIER_COMDE)
  534. #define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
  535. /**
  536.   * @}
  537.   */
  538.  
  539. /** @defgroup TIM_Event_Source TIM Event Source
  540.   * @{
  541.   */
  542. #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG
  543. #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G
  544. #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G
  545. #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G
  546. #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G
  547. #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG
  548. #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG
  549. #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG
  550. /**
  551.   * @}
  552.   */
  553.  
  554. /** @defgroup TIM_Flag_definition TIM Flag Definition
  555.   * @{
  556.   */
  557. #define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
  558. #define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
  559. #define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
  560. #define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
  561. #define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
  562. #define TIM_FLAG_COM                       (TIM_SR_COMIF)
  563. #define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
  564. #define TIM_FLAG_BREAK                     (TIM_SR_BIF)
  565. #define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
  566. #define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
  567. #define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
  568. #define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
  569. /**
  570.   * @}
  571.   */
  572.  
  573. /** @defgroup TIM_Clock_Source TIM Clock Source
  574.   * @{
  575.   */
  576. #define TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1)
  577. #define TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0)
  578. #define TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000)
  579. #define TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
  580. #define TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
  581. #define TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
  582. #define TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
  583. #define TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
  584. #define TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
  585. #define TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
  586. /**
  587.   * @}
  588.   */
  589.  
  590. /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
  591.   * @{
  592.   */
  593. #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */
  594. #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */
  595. #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */
  596. #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
  597. #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
  598. /**
  599.   * @}
  600.   */
  601.  
  602. /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
  603.   * @{
  604.   */
  605. #define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
  606. #define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
  607. #define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
  608. #define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
  609. /**
  610.   * @}
  611.   */
  612.  
  613. /** @defgroup TIM_ClearInput_Source TIM ClearInput Source
  614.   * @{
  615.   */
  616. #define TIM_CLEARINPUTSOURCE_ETR           ((uint32_t)0x0001)
  617. #define TIM_CLEARINPUTSOURCE_OCREFCLR      ((uint32_t)0x0002)
  618. #define TIM_CLEARINPUTSOURCE_NONE          ((uint32_t)0x0000)
  619. /**
  620.   * @}
  621.   */
  622.  
  623. /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
  624.   * @{
  625.   */
  626. #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */
  627. #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                          /*!< Polarity for ETRx pin */
  628. /**
  629.   * @}
  630.   */
  631.  
  632. /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
  633.   * @{
  634.   */
  635. #define TIM_CLEARINPUTPRESCALER_DIV1                    TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
  636. #define TIM_CLEARINPUTPRESCALER_DIV2                    TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
  637. #define TIM_CLEARINPUTPRESCALER_DIV4                    TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
  638. #define TIM_CLEARINPUTPRESCALER_DIV8                    TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
  639. /**
  640.   * @}
  641.   */
  642.  
  643. /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
  644.   * @{
  645.   */
  646. #define TIM_OSSR_ENABLE         (TIM_BDTR_OSSR)
  647. #define TIM_OSSR_DISABLE              ((uint32_t)0x0000)
  648. /**
  649.   * @}
  650.   */
  651.  
  652. /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
  653.   * @{
  654.   */
  655. #define TIM_OSSI_ENABLE        (TIM_BDTR_OSSI)
  656. #define TIM_OSSI_DISABLE            ((uint32_t)0x0000)
  657. /**
  658.   * @}
  659.   */
  660.  
  661. /** @defgroup TIM_Lock_level TIM Lock level
  662.   * @{
  663.   */
  664. #define TIM_LOCKLEVEL_OFF          ((uint32_t)0x0000)
  665. #define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)
  666. #define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)
  667. #define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)
  668. /**
  669.   * @}
  670.   */
  671.  
  672. /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
  673.   * @{
  674.   */
  675. #define TIM_BREAK_ENABLE          (TIM_BDTR_BKE)
  676. #define TIM_BREAK_DISABLE         ((uint32_t)0x0000)
  677. /**
  678.   * @}
  679.   */
  680.  
  681. /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
  682.   * @{
  683.   */
  684. #define TIM_BREAKPOLARITY_LOW        ((uint32_t)0x0000)
  685. #define TIM_BREAKPOLARITY_HIGH       (TIM_BDTR_BKP)
  686. /**
  687.   * @}
  688.   */
  689. /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
  690.   * @{
  691.   */
  692. #define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)
  693. #define TIM_AUTOMATICOUTPUT_DISABLE          ((uint32_t)0x0000)
  694. /**
  695.   * @}
  696.   */
  697.  
  698. /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
  699.   * @{
  700.   */
  701. #define TIM_TRGO_RESET            ((uint32_t)0x0000)
  702. #define TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
  703. #define TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
  704. #define TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
  705. #define TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)
  706. #define TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
  707. #define TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
  708. #define TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
  709. /**
  710.   * @}
  711.   */
  712.  
  713. /** @defgroup TIM_Slave_Mode TIM Slave Mode
  714.   * @{
  715.   */
  716. #define TIM_SLAVEMODE_DISABLE              ((uint32_t)0x0000)
  717. #define TIM_SLAVEMODE_RESET                ((uint32_t)0x0004)
  718. #define TIM_SLAVEMODE_GATED                ((uint32_t)0x0005)
  719. #define TIM_SLAVEMODE_TRIGGER              ((uint32_t)0x0006)
  720. #define TIM_SLAVEMODE_EXTERNAL1            ((uint32_t)0x0007)
  721. /**
  722.   * @}
  723.   */
  724.  
  725. /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
  726.   * @{
  727.   */
  728. #define TIM_MASTERSLAVEMODE_ENABLE          ((uint32_t)0x0080)
  729. #define TIM_MASTERSLAVEMODE_DISABLE         ((uint32_t)0x0000)
  730. /**
  731.   * @}
  732.   */
  733.  
  734. /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
  735.   * @{
  736.   */
  737. #define TIM_TS_ITR0                        ((uint32_t)0x0000)
  738. #define TIM_TS_ITR1                        ((uint32_t)0x0010)
  739. #define TIM_TS_ITR2                        ((uint32_t)0x0020)
  740. #define TIM_TS_ITR3                        ((uint32_t)0x0030)
  741. #define TIM_TS_TI1F_ED                     ((uint32_t)0x0040)
  742. #define TIM_TS_TI1FP1                      ((uint32_t)0x0050)
  743. #define TIM_TS_TI2FP2                      ((uint32_t)0x0060)
  744. #define TIM_TS_ETRF                        ((uint32_t)0x0070)
  745. #define TIM_TS_NONE                        ((uint32_t)0xFFFF)
  746. /**
  747.   * @}
  748.   */
  749.  
  750. /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
  751.   * @{
  752.   */
  753. #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */
  754. #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */
  755. #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
  756. #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
  757. #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
  758. /**
  759.   * @}
  760.   */
  761.  
  762. /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
  763.   * @{
  764.   */
  765. #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
  766. #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
  767. #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
  768. #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
  769. /**
  770.   * @}
  771.   */
  772.  
  773. /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
  774.   * @{
  775.   */
  776. #define TIM_TI1SELECTION_CH1                ((uint32_t)0x0000)
  777. #define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)
  778. /**
  779.   * @}
  780.   */
  781.  
  782. /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
  783.   * @{
  784.   */
  785. #define TIM_DMABASE_CR1                    (0x00000000)
  786. #define TIM_DMABASE_CR2                    (0x00000001)
  787. #define TIM_DMABASE_SMCR                   (0x00000002)
  788. #define TIM_DMABASE_DIER                   (0x00000003)
  789. #define TIM_DMABASE_SR                     (0x00000004)
  790. #define TIM_DMABASE_EGR                    (0x00000005)
  791. #define TIM_DMABASE_CCMR1                  (0x00000006)
  792. #define TIM_DMABASE_CCMR2                  (0x00000007)
  793. #define TIM_DMABASE_CCER                   (0x00000008)
  794. #define TIM_DMABASE_CNT                    (0x00000009)
  795. #define TIM_DMABASE_PSC                    (0x0000000A)
  796. #define TIM_DMABASE_ARR                    (0x0000000B)
  797. #define TIM_DMABASE_RCR                    (0x0000000C)
  798. #define TIM_DMABASE_CCR1                   (0x0000000D)
  799. #define TIM_DMABASE_CCR2                   (0x0000000E)
  800. #define TIM_DMABASE_CCR3                   (0x0000000F)
  801. #define TIM_DMABASE_CCR4                   (0x00000010)
  802. #define TIM_DMABASE_BDTR                   (0x00000011)
  803. #define TIM_DMABASE_DCR                    (0x00000012)
  804. /**
  805.   * @}
  806.   */
  807.  
  808. /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
  809.   * @{
  810.   */
  811. #define TIM_DMABURSTLENGTH_1TRANSFER           (0x00000000)
  812. #define TIM_DMABURSTLENGTH_2TRANSFERS          (0x00000100)
  813. #define TIM_DMABURSTLENGTH_3TRANSFERS          (0x00000200)
  814. #define TIM_DMABURSTLENGTH_4TRANSFERS          (0x00000300)
  815. #define TIM_DMABURSTLENGTH_5TRANSFERS          (0x00000400)
  816. #define TIM_DMABURSTLENGTH_6TRANSFERS          (0x00000500)
  817. #define TIM_DMABURSTLENGTH_7TRANSFERS          (0x00000600)
  818. #define TIM_DMABURSTLENGTH_8TRANSFERS          (0x00000700)
  819. #define TIM_DMABURSTLENGTH_9TRANSFERS          (0x00000800)
  820. #define TIM_DMABURSTLENGTH_10TRANSFERS         (0x00000900)
  821. #define TIM_DMABURSTLENGTH_11TRANSFERS         (0x00000A00)
  822. #define TIM_DMABURSTLENGTH_12TRANSFERS         (0x00000B00)
  823. #define TIM_DMABURSTLENGTH_13TRANSFERS         (0x00000C00)
  824. #define TIM_DMABURSTLENGTH_14TRANSFERS         (0x00000D00)
  825. #define TIM_DMABURSTLENGTH_15TRANSFERS         (0x00000E00)
  826. #define TIM_DMABURSTLENGTH_16TRANSFERS         (0x00000F00)
  827. #define TIM_DMABURSTLENGTH_17TRANSFERS         (0x00001000)
  828. #define TIM_DMABURSTLENGTH_18TRANSFERS         (0x00001100)
  829. /**
  830.   * @}
  831.   */
  832.  
  833. /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
  834.   * @{
  835.   */
  836. #define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0)       /*!< Index of the DMA handle used for Update DMA requests */
  837. #define TIM_DMA_ID_CC1                   ((uint16_t) 0x1)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
  838. #define TIM_DMA_ID_CC2                   ((uint16_t) 0x2)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
  839. #define TIM_DMA_ID_CC3                   ((uint16_t) 0x3)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
  840. #define TIM_DMA_ID_CC4                   ((uint16_t) 0x4)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
  841. #define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x5)       /*!< Index of the DMA handle used for Commutation DMA requests */
  842. #define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6)       /*!< Index of the DMA handle used for Trigger DMA requests */
  843. /**
  844.   * @}
  845.   */
  846.  
  847. /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
  848.   * @{
  849.   */
  850. #define TIM_CCx_ENABLE                   ((uint32_t)0x0001)
  851. #define TIM_CCx_DISABLE                  ((uint32_t)0x0000)
  852. #define TIM_CCxN_ENABLE                  ((uint32_t)0x0004)
  853. #define TIM_CCxN_DISABLE                 ((uint32_t)0x0000)
  854. /**
  855.   * @}
  856.   */
  857.  
  858. /**
  859.   * @}
  860.   */
  861.  
  862. /* Private Constants -----------------------------------------------------------*/
  863. /** @defgroup TIM_Private_Constants TIM Private Constants
  864.   * @{
  865.   */
  866.  
  867. /* The counter of a timer instance is disabled only if all the CCx and CCxN
  868.    channels have been disabled */
  869. #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
  870. #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
  871.  
  872. /**
  873.   * @}
  874.   */
  875.  
  876. /* Private Macros -----------------------------------------------------------*/
  877. /** @defgroup TIM_Private_Macros TIM Private Macros
  878.  * @{
  879.  */
  880.  
  881. #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP)              || \
  882.                                    ((MODE) == TIM_COUNTERMODE_DOWN)            || \
  883.                                    ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
  884.                                    ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
  885.                                    ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
  886.  
  887. #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
  888.                                        ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
  889.                                        ((DIV) == TIM_CLOCKDIVISION_DIV4))
  890.  
  891. #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
  892.                                ((MODE) == TIM_OCMODE_PWM2))
  893.                              
  894. #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)       || \
  895.                           ((MODE) == TIM_OCMODE_ACTIVE)           || \
  896.                           ((MODE) == TIM_OCMODE_INACTIVE)         || \
  897.                           ((MODE) == TIM_OCMODE_TOGGLE)           || \
  898.                           ((MODE) == TIM_OCMODE_FORCED_ACTIVE)    || \
  899.                           ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
  900.  
  901. #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
  902.                                   ((STATE) == TIM_OCFAST_ENABLE))
  903.  
  904. #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
  905.                                       ((POLARITY) == TIM_OCPOLARITY_LOW))
  906.  
  907. #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
  908.                                        ((POLARITY) == TIM_OCNPOLARITY_LOW))
  909.  
  910. #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
  911.                                     ((STATE) == TIM_OCIDLESTATE_RESET))
  912.  
  913. #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
  914.                                      ((STATE) == TIM_OCNIDLESTATE_RESET))
  915.  
  916. #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
  917.                                   ((CHANNEL) == TIM_CHANNEL_2) || \
  918.                                   ((CHANNEL) == TIM_CHANNEL_3) || \
  919.                                   ((CHANNEL) == TIM_CHANNEL_4) || \
  920.                                   ((CHANNEL) == TIM_CHANNEL_ALL))
  921.                                  
  922. #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
  923.                                       ((CHANNEL) == TIM_CHANNEL_2))                                      
  924.                                      
  925. #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
  926.                                                 ((CHANNEL) == TIM_CHANNEL_2) || \
  927.                                                 ((CHANNEL) == TIM_CHANNEL_3))
  928.  
  929. #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING)   || \
  930.                                       ((POLARITY) == TIM_ICPOLARITY_FALLING)  || \
  931.                                       ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
  932.  
  933. #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI)   || \
  934.                                         ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
  935.                                         ((SELECTION) == TIM_ICSELECTION_TRC))
  936.  
  937. #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
  938.                                         ((PRESCALER) == TIM_ICPSC_DIV2) || \
  939.                                         ((PRESCALER) == TIM_ICPSC_DIV4) || \
  940.                                         ((PRESCALER) == TIM_ICPSC_DIV8))
  941.  
  942. #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
  943.                                ((MODE) == TIM_OPMODE_REPETITIVE))
  944.  
  945. #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
  946.                                    ((MODE) == TIM_ENCODERMODE_TI2) || \
  947.                                    ((MODE) == TIM_ENCODERMODE_TI12))  
  948.  
  949. #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
  950.  
  951. #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
  952.  
  953. #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
  954.                                    ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
  955.                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR0)     || \
  956.                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR1)     || \
  957.                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR2)     || \
  958.                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR3)     || \
  959.                                    ((CLOCK) == TIM_CLOCKSOURCE_TI1ED)    || \
  960.                                    ((CLOCK) == TIM_CLOCKSOURCE_TI1)      || \
  961.                                    ((CLOCK) == TIM_CLOCKSOURCE_TI2)      || \
  962.                                    ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
  963.  
  964. #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED)    || \
  965.                                         ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
  966.                                         ((POLARITY) == TIM_CLOCKPOLARITY_RISING)      || \
  967.                                         ((POLARITY) == TIM_CLOCKPOLARITY_FALLING)     || \
  968.                                         ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
  969.  
  970. #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
  971.                                           ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
  972.                                           ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
  973.                                           ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
  974.  
  975. #define IS_TIM_CLOCKFILTER(ICFILTER)       ((ICFILTER) <= 0xF)
  976.  
  977. #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)      || \
  978.                                           ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
  979.                                           ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
  980.  
  981. #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
  982.                                               ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
  983.  
  984. #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)   (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
  985.                                                   ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
  986.                                                   ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
  987.                                                   ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
  988.  
  989. #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
  990.  
  991. #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
  992.                                   ((STATE) == TIM_OSSR_DISABLE))
  993.  
  994. #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
  995.                                   ((STATE) == TIM_OSSI_DISABLE))
  996.  
  997. #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
  998.                                   ((LEVEL) == TIM_LOCKLEVEL_1)   || \
  999.                                   ((LEVEL) == TIM_LOCKLEVEL_2)   || \
  1000.                                   ((LEVEL) == TIM_LOCKLEVEL_3))
  1001.  
  1002. #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
  1003.                                    ((STATE) == TIM_BREAK_DISABLE))
  1004.  
  1005. #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
  1006.                                          ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
  1007.  
  1008. #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
  1009.                                               ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
  1010.  
  1011. #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET)  || \
  1012.                                     ((SOURCE) == TIM_TRGO_ENABLE) || \
  1013.                                     ((SOURCE) == TIM_TRGO_UPDATE) || \
  1014.                                     ((SOURCE) == TIM_TRGO_OC1)    || \
  1015.                                     ((SOURCE) == TIM_TRGO_OC1REF) || \
  1016.                                     ((SOURCE) == TIM_TRGO_OC2REF) || \
  1017.                                     ((SOURCE) == TIM_TRGO_OC3REF) || \
  1018.                                     ((SOURCE) == TIM_TRGO_OC4REF))
  1019.  
  1020. #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
  1021.                                  ((MODE) == TIM_SLAVEMODE_GATED)   || \
  1022.                                  ((MODE) == TIM_SLAVEMODE_RESET)   || \
  1023.                                  ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
  1024.                                  ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
  1025.  
  1026. #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
  1027.                                  ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
  1028.  
  1029. #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0)    || \
  1030.                                              ((SELECTION) == TIM_TS_ITR1)    || \
  1031.                                              ((SELECTION) == TIM_TS_ITR2)    || \
  1032.                                              ((SELECTION) == TIM_TS_ITR3)    || \
  1033.                                              ((SELECTION) == TIM_TS_TI1F_ED) || \
  1034.                                              ((SELECTION) == TIM_TS_TI1FP1)  || \
  1035.                                              ((SELECTION) == TIM_TS_TI2FP2)  || \
  1036.                                              ((SELECTION) == TIM_TS_ETRF))
  1037.  
  1038. #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
  1039.                                                            ((SELECTION) == TIM_TS_ITR1) || \
  1040.                                                            ((SELECTION) == TIM_TS_ITR2) || \
  1041.                                                            ((SELECTION) == TIM_TS_ITR3) || \
  1042.                                                            ((SELECTION) == TIM_TS_NONE))
  1043.  
  1044. #define IS_TIM_TRIGGERPOLARITY(POLARITY)     (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
  1045.                                               ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
  1046.                                               ((POLARITY) == TIM_TRIGGERPOLARITY_RISING     ) || \
  1047.                                               ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING    ) || \
  1048.                                               ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
  1049.  
  1050. #define IS_TIM_TRIGGERPRESCALER(PRESCALER)  (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
  1051.                                              ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
  1052.                                              ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
  1053.                                              ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
  1054.  
  1055. #define IS_TIM_TRIGGERFILTER(ICFILTER)     ((ICFILTER) <= 0xF)
  1056.  
  1057. #define IS_TIM_TI1SELECTION(TI1SELECTION)   (((TI1SELECTION) == TIM_TI1SELECTION_CH1)            || \
  1058.                                              ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
  1059.  
  1060. #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1)   || \
  1061.                                ((BASE) == TIM_DMABASE_CR2)   || \
  1062.                                ((BASE) == TIM_DMABASE_SMCR)  || \
  1063.                                ((BASE) == TIM_DMABASE_DIER)  || \
  1064.                                ((BASE) == TIM_DMABASE_SR)    || \
  1065.                                ((BASE) == TIM_DMABASE_EGR)   || \
  1066.                                ((BASE) == TIM_DMABASE_CCMR1) || \
  1067.                                ((BASE) == TIM_DMABASE_CCMR2) || \
  1068.                                ((BASE) == TIM_DMABASE_CCER)  || \
  1069.                                ((BASE) == TIM_DMABASE_CNT)   || \
  1070.                                ((BASE) == TIM_DMABASE_PSC)   || \
  1071.                                ((BASE) == TIM_DMABASE_ARR)   || \
  1072.                                ((BASE) == TIM_DMABASE_RCR)   || \
  1073.                                ((BASE) == TIM_DMABASE_CCR1)  || \
  1074.                                ((BASE) == TIM_DMABASE_CCR2)  || \
  1075.                                ((BASE) == TIM_DMABASE_CCR3)  || \
  1076.                                ((BASE) == TIM_DMABASE_CCR4)  || \
  1077.                                ((BASE) == TIM_DMABASE_BDTR)  || \
  1078.                                ((BASE) == TIM_DMABASE_DCR))
  1079.  
  1080. #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
  1081.                                    ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
  1082.                                    ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
  1083.                                    ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
  1084.                                    ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
  1085.                                    ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
  1086.                                    ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
  1087.                                    ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
  1088.                                    ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
  1089.                                    ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
  1090.                                    ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
  1091.                                    ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
  1092.                                    ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
  1093.                                    ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
  1094.                                    ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
  1095.                                    ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
  1096.                                    ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
  1097.                                    ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
  1098.  
  1099. #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
  1100.  
  1101. /** @brief Set TIM IC prescaler
  1102.   * @param  __HANDLE__: TIM handle
  1103.   * @param  __CHANNEL__: specifies TIM Channel
  1104.   * @param  __ICPSC__: specifies the prescaler value.
  1105.   * @retval None
  1106.   */
  1107. #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
  1108. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
  1109.  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
  1110.  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
  1111.  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
  1112.  
  1113. /** @brief Reset TIM IC prescaler
  1114.   * @param  __HANDLE__: TIM handle
  1115.   * @param  __CHANNEL__: specifies TIM Channel
  1116.   * @retval None
  1117.   */
  1118. #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
  1119. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
  1120.  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
  1121.  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
  1122.  ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
  1123.  
  1124.  
  1125. /** @brief Set TIM IC polarity
  1126.   * @param  __HANDLE__: TIM handle
  1127.   * @param  __CHANNEL__: specifies TIM Channel
  1128.   * @param  __POLARITY__: specifies TIM Channel Polarity
  1129.   * @retval None
  1130.   */
  1131. #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
  1132. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
  1133.  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
  1134.  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
  1135.  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
  1136.  
  1137. /** @brief Reset TIM IC polarity
  1138.   * @param  __HANDLE__: TIM handle
  1139.   * @param  __CHANNEL__: specifies TIM Channel
  1140.   * @retval None
  1141.   */
  1142. #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
  1143. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
  1144.  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
  1145.  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
  1146.  ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
  1147.  
  1148. /**
  1149.   * @}
  1150.   */
  1151.  
  1152. /* Private Functions --------------------------------------------------------*/
  1153. /** @addtogroup TIM_Private_Functions
  1154.  * @{
  1155.  */
  1156. void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
  1157. void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
  1158. void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  1159. void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
  1160. void TIM_DMAError(DMA_HandleTypeDef *hdma);
  1161. void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
  1162. void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
  1163. /**
  1164.   * @}
  1165.   */
  1166.  
  1167. /* Exported macros -----------------------------------------------------------*/
  1168. /** @defgroup TIM_Exported_Macros TIM Exported Macros
  1169.   * @{
  1170.   */
  1171.  
  1172. /** @brief  Reset TIM handle state
  1173.   * @param  __HANDLE__: TIM handle.
  1174.   * @retval None
  1175.   */
  1176. #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
  1177.  
  1178. /**
  1179.   * @brief  Enable the TIM peripheral.
  1180.   * @param  __HANDLE__: TIM handle
  1181.   * @retval None
  1182.  */
  1183. #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
  1184.  
  1185. /**
  1186.   * @brief  Enable the TIM main Output.
  1187.   * @param  __HANDLE__: TIM handle
  1188.   * @retval None
  1189.   */
  1190. #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
  1191.  
  1192. /**
  1193.   * @brief  Disable the TIM peripheral.
  1194.   * @param  __HANDLE__: TIM handle
  1195.   * @retval None
  1196.   */
  1197. #define __HAL_TIM_DISABLE(__HANDLE__) \
  1198.                         do { \
  1199.                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
  1200.                             { \
  1201.                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
  1202.                             { \
  1203.                               (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
  1204.                             } \
  1205.                           } \
  1206.                         } while(0)
  1207. /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
  1208.    channels have been disabled */
  1209. /**
  1210.   * @brief  Disable the TIM main Output.
  1211.   * @param  __HANDLE__: TIM handle
  1212.   * @retval None
  1213.   * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
  1214.   */
  1215. #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
  1216.                         do { \
  1217.                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
  1218.                           { \
  1219.                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
  1220.                             { \
  1221.                               (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
  1222.                             } \
  1223.                             } \
  1224.                         } while(0)
  1225.  
  1226. /**
  1227.   * @brief  Enables the specified TIM interrupt.
  1228.   * @param  __HANDLE__: specifies the TIM Handle.
  1229.   * @param  __INTERRUPT__: specifies the TIM interrupt source to enable.
  1230.   *          This parameter can be one of the following values:
  1231.   *            @arg TIM_IT_UPDATE: Update interrupt
  1232.   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
  1233.   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
  1234.   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
  1235.   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
  1236.   *            @arg TIM_IT_COM:   Commutation interrupt
  1237.   *            @arg TIM_IT_TRIGGER: Trigger interrupt
  1238.   *            @arg TIM_IT_BREAK: Break interrupt
  1239.   * @retval None
  1240.   */
  1241. #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
  1242.  
  1243. /**
  1244.   * @brief  Disables the specified TIM interrupt.
  1245.   * @param  __HANDLE__: specifies the TIM Handle.
  1246.   * @param  __INTERRUPT__: specifies the TIM interrupt source to disable.
  1247.   *          This parameter can be one of the following values:
  1248.   *            @arg TIM_IT_UPDATE: Update interrupt
  1249.   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
  1250.   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
  1251.   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
  1252.   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
  1253.   *            @arg TIM_IT_COM:   Commutation interrupt
  1254.   *            @arg TIM_IT_TRIGGER: Trigger interrupt
  1255.   *            @arg TIM_IT_BREAK: Break interrupt
  1256.   * @retval None
  1257.   */
  1258. #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
  1259.  
  1260. /**
  1261.   * @brief  Enables the specified DMA request.
  1262.   * @param  __HANDLE__: specifies the TIM Handle.
  1263.   * @param  __DMA__: specifies the TIM DMA request to enable.
  1264.   *          This parameter can be one of the following values:
  1265.   *            @arg TIM_DMA_UPDATE: Update DMA request
  1266.   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
  1267.   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
  1268.   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
  1269.   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
  1270.   *            @arg TIM_DMA_COM:   Commutation DMA request
  1271.   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
  1272.   * @retval None
  1273.   */
  1274. #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
  1275.  
  1276. /**
  1277.   * @brief  Disables the specified DMA request.
  1278.   * @param  __HANDLE__: specifies the TIM Handle.
  1279.   * @param  __DMA__: specifies the TIM DMA request to disable.
  1280.   *          This parameter can be one of the following values:
  1281.   *            @arg TIM_DMA_UPDATE: Update DMA request
  1282.   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
  1283.   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
  1284.   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
  1285.   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
  1286.   *            @arg TIM_DMA_COM:   Commutation DMA request
  1287.   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
  1288.   * @retval None
  1289.   */
  1290. #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
  1291.  
  1292. /**
  1293.   * @brief  Checks whether the specified TIM interrupt flag is set or not.
  1294.   * @param  __HANDLE__: specifies the TIM Handle.
  1295.   * @param  __FLAG__: specifies the TIM interrupt flag to check.
  1296.   *        This parameter can be one of the following values:
  1297.   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
  1298.   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  1299.   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  1300.   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  1301.   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  1302.   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
  1303.   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
  1304.   *            @arg TIM_FLAG_BREAK: Break interrupt flag  
  1305.   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  1306.   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  1307.   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  1308.   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
  1309.   * @retval The new state of __FLAG__ (TRUE or FALSE).
  1310.   */
  1311. #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
  1312.  
  1313. /**
  1314.   * @brief  Clears the specified TIM interrupt flag.
  1315.   * @param  __HANDLE__: specifies the TIM Handle.
  1316.   * @param  __FLAG__: specifies the TIM interrupt flag to clear.
  1317.   *        This parameter can be one of the following values:
  1318.   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
  1319.   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  1320.   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  1321.   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  1322.   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  1323.   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
  1324.   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
  1325.   *            @arg TIM_FLAG_BREAK: Break interrupt flag  
  1326.   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  1327.   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  1328.   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  1329.   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
  1330.   * @retval The new state of __FLAG__ (TRUE or FALSE).
  1331.   */
  1332. #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
  1333.  
  1334. /**
  1335.   * @brief  Checks whether the specified TIM interrupt has occurred or not.
  1336.   * @param  __HANDLE__: TIM handle
  1337.   * @param  __INTERRUPT__: specifies the TIM interrupt source to check.
  1338.   * @retval The state of TIM_IT (SET or RESET).
  1339.   */
  1340. #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
  1341.  
  1342. /**
  1343.   * @brief Clear the TIM interrupt pending bits
  1344.   * @param  __HANDLE__: TIM handle
  1345.   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
  1346.   * @retval None
  1347.   */
  1348. #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
  1349.  
  1350. /**
  1351.   * @brief  Indicates whether or not the TIM Counter is used as downcounter
  1352.   * @param  __HANDLE__: TIM handle.
  1353.   * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
  1354.   * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
  1355. mode.
  1356.   */
  1357. #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)            (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
  1358.  
  1359. /**
  1360.   * @brief  Sets the TIM active prescaler register value on update event.
  1361.   * @param  __HANDLE__: TIM handle.
  1362.   * @param  __PRESC__: specifies the active prescaler register new value.
  1363.   * @retval None
  1364.   */
  1365. #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
  1366.  
  1367. /**
  1368.   * @brief  Sets the TIM Capture Compare Register value on runtime without
  1369.   *         calling another time ConfigChannel function.
  1370.   * @param  __HANDLE__: TIM handle.
  1371.   * @param  __CHANNEL__ : TIM Channels to be configured.
  1372.   *          This parameter can be one of the following values:
  1373.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1374.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1375.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1376.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1377.   * @param  __COMPARE__: specifies the Capture Compare register new value.
  1378.   * @retval None
  1379.   */
  1380. #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
  1381. (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
  1382.  
  1383. /**
  1384.   * @brief  Gets the TIM Capture Compare Register value on runtime
  1385.   * @param  __HANDLE__: TIM handle.
  1386.   * @param  __CHANNEL__ : TIM Channel associated with the capture compare register
  1387.   *          This parameter can be one of the following values:
  1388.   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
  1389.   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
  1390.   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
  1391.   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
  1392.   * @retval None
  1393.   */
  1394. #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
  1395.   (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
  1396.  
  1397. /**
  1398.   * @brief  Sets the TIM Counter Register value on runtime.
  1399.   * @param  __HANDLE__: TIM handle.
  1400.   * @param  __COUNTER__: specifies the Counter register new value.
  1401.   * @retval None
  1402.   */
  1403. #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
  1404.  
  1405. /**
  1406.   * @brief  Gets the TIM Counter Register value on runtime.
  1407.   * @param  __HANDLE__: TIM handle.
  1408.   * @retval None
  1409.   */
  1410. #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
  1411.    ((__HANDLE__)->Instance->CNT)
  1412.  
  1413. /**
  1414.   * @brief  Sets the TIM Autoreload Register value on runtime without calling
  1415.   *         another time any Init function.
  1416.   * @param  __HANDLE__: TIM handle.
  1417.   * @param  __AUTORELOAD__: specifies the Counter register new value.
  1418.   * @retval None
  1419.   */
  1420. #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
  1421.                         do{                                                    \
  1422.                               (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
  1423.                               (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
  1424.                           } while(0)
  1425.  
  1426. /**
  1427.   * @brief  Gets the TIM Autoreload Register value on runtime
  1428.   * @param  __HANDLE__: TIM handle.
  1429.   * @retval None
  1430.   */
  1431. #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
  1432.    ((__HANDLE__)->Instance->ARR)
  1433.  
  1434. /**
  1435.   * @brief  Sets the TIM Clock Division value on runtime without calling
  1436.   *         another time any Init function.
  1437.   * @param  __HANDLE__: TIM handle.
  1438.   * @param  __CKD__: specifies the clock division value.
  1439.   *          This parameter can be one of the following value:
  1440.   *            @arg TIM_CLOCKDIVISION_DIV1
  1441.   *            @arg TIM_CLOCKDIVISION_DIV2
  1442.   *            @arg TIM_CLOCKDIVISION_DIV4
  1443.   * @retval None
  1444.   */
  1445. #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
  1446.                         do{                                                    \
  1447.                               (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
  1448.                               (__HANDLE__)->Instance->CR1 |= (__CKD__);                   \
  1449.                               (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
  1450.                           } while(0)
  1451.  
  1452. /**
  1453.   * @brief  Gets the TIM Clock Division value on runtime
  1454.   * @param  __HANDLE__: TIM handle.
  1455.   * @retval None
  1456.   */
  1457. #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  \
  1458.    ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
  1459.  
  1460. /**
  1461.   * @brief  Sets the TIM Input Capture prescaler on runtime without calling
  1462.   *         another time HAL_TIM_IC_ConfigChannel() function.
  1463.   * @param  __HANDLE__: TIM handle.
  1464.   * @param  __CHANNEL__ : TIM Channels to be configured.
  1465.   *          This parameter can be one of the following values:
  1466.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1467.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1468.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1469.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1470.   * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
  1471.   *          This parameter can be one of the following values:
  1472.   *            @arg TIM_ICPSC_DIV1: no prescaler
  1473.   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
  1474.   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
  1475.   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
  1476.   * @retval None
  1477.   */
  1478. #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
  1479.                         do{                                                    \
  1480.                               TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
  1481.                               TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
  1482.                           } while(0)
  1483.  
  1484. /**
  1485.   * @brief  Gets the TIM Input Capture prescaler on runtime
  1486.   * @param  __HANDLE__: TIM handle.
  1487.   * @param  __CHANNEL__: TIM Channels to be configured.
  1488.   *          This parameter can be one of the following values:
  1489.   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
  1490.   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
  1491.   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
  1492.   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
  1493.   * @retval None
  1494.   */
  1495. #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
  1496.   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
  1497.    ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
  1498.    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
  1499.    (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
  1500.  
  1501. /**
  1502.   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register
  1503.   * @param  __HANDLE__: TIM handle.
  1504.   * @note  When the USR bit of the TIMx_CR1 register is set, only counter
  1505.   *        overflow/underflow generates an update interrupt or DMA request (if
  1506.   *        enabled)
  1507.   * @retval None
  1508.   */
  1509. #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
  1510.     ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
  1511.  
  1512. /**
  1513.   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register
  1514.   * @param  __HANDLE__: TIM handle.
  1515.   * @note  When the USR bit of the TIMx_CR1 register is reset, any of the
  1516.   *        following events generate an update interrupt or DMA request (if
  1517.   *        enabled):
  1518.   *          (+) Counter overflow/underflow
  1519.   *          (+) Setting the UG bit
  1520.   *          (+) Update generation through the slave mode controller
  1521.   * @retval None
  1522.   */
  1523. #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
  1524.       ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
  1525.  
  1526. /**
  1527.   * @brief  Sets the TIM Capture x input polarity on runtime.
  1528.   * @param  __HANDLE__: TIM handle.
  1529.   * @param  __CHANNEL__: TIM Channels to be configured.
  1530.   *          This parameter can be one of the following values:
  1531.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1532.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1533.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1534.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1535.   * @param  __POLARITY__: Polarity for TIx source  
  1536.   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
  1537.   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
  1538.   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
  1539.   * @note  The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized  for TIM Channel 4.    
  1540.   * @retval None
  1541.   */
  1542. #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
  1543.         do{                                                                     \
  1544.           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
  1545.           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
  1546.         }while(0)
  1547.  
  1548. /**
  1549.   * @}
  1550.   */
  1551.  
  1552. /* Include TIM HAL Extension module */
  1553. #include "stm32f1xx_hal_tim_ex.h"
  1554.  
  1555. /* Exported functions --------------------------------------------------------*/
  1556. /** @addtogroup TIM_Exported_Functions
  1557.   * @{
  1558.   */
  1559.  
  1560. /** @addtogroup TIM_Exported_Functions_Group1
  1561.  * @{
  1562.  */
  1563. /* Time Base functions ********************************************************/
  1564. HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
  1565. HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
  1566. void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
  1567. void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
  1568. /* Blocking mode: Polling */
  1569. HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
  1570. HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
  1571. /* Non-Blocking mode: Interrupt */
  1572. HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
  1573. HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
  1574. /* Non-Blocking mode: DMA */
  1575. HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
  1576. HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
  1577. /**
  1578.   * @}
  1579.   */
  1580.  
  1581. /** @addtogroup TIM_Exported_Functions_Group2
  1582.  * @{
  1583.  */
  1584. /* Timer Output Compare functions **********************************************/
  1585. HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
  1586. HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
  1587. void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
  1588. void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
  1589. /* Blocking mode: Polling */
  1590. HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1591. HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1592. /* Non-Blocking mode: Interrupt */
  1593. HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1594. HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1595. /* Non-Blocking mode: DMA */
  1596. HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
  1597. HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1598.  
  1599. /**
  1600.   * @}
  1601.   */
  1602.  
  1603. /** @addtogroup TIM_Exported_Functions_Group3
  1604.  * @{
  1605.  */
  1606. /* Timer PWM functions *********************************************************/
  1607. HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
  1608. HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
  1609. void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
  1610. void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
  1611. /* Blocking mode: Polling */
  1612. HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1613. HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1614. /* Non-Blocking mode: Interrupt */
  1615. HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1616. HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1617. /* Non-Blocking mode: DMA */
  1618. HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
  1619. HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1620. /**
  1621.   * @}
  1622.   */
  1623.  
  1624. /** @addtogroup TIM_Exported_Functions_Group4
  1625.  * @{
  1626.  */
  1627. /* Timer Input Capture functions ***********************************************/
  1628. HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
  1629. HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
  1630. void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
  1631. void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
  1632. /* Blocking mode: Polling */
  1633. HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1634. HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1635. /* Non-Blocking mode: Interrupt */
  1636. HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1637. HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1638. /* Non-Blocking mode: DMA */
  1639. HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
  1640. HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1641. /**
  1642.   * @}
  1643.   */
  1644.  
  1645. /** @addtogroup TIM_Exported_Functions_Group5
  1646.  * @{
  1647.  */
  1648. /* Timer One Pulse functions ***************************************************/
  1649. HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
  1650. HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
  1651. void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
  1652. void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
  1653. /* Blocking mode: Polling */
  1654. HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1655. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1656. /* Non-Blocking mode: Interrupt */
  1657. HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1658. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1659. /**
  1660.   * @}
  1661.   */
  1662.  
  1663. /** @addtogroup TIM_Exported_Functions_Group6
  1664.  * @{
  1665.  */
  1666. /* Timer Encoder functions *****************************************************/
  1667. HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
  1668. HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
  1669. void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
  1670. void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
  1671.  /* Blocking mode: Polling */
  1672. HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1673. HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1674. /* Non-Blocking mode: Interrupt */
  1675. HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1676. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1677. /* Non-Blocking mode: DMA */
  1678. HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
  1679. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1680.  
  1681. /**
  1682.   * @}
  1683.   */
  1684.  
  1685. /** @addtogroup TIM_Exported_Functions_Group7
  1686.  * @{
  1687.  */
  1688. /* Interrupt Handler functions  **********************************************/
  1689. void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
  1690. /**
  1691.   * @}
  1692.   */
  1693.  
  1694. /** @addtogroup TIM_Exported_Functions_Group8
  1695.  * @{
  1696.  */
  1697. /* Control functions  *********************************************************/
  1698. HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
  1699. HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
  1700. HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
  1701. HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
  1702. HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
  1703. HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
  1704. HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
  1705. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
  1706. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
  1707. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
  1708.                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
  1709. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
  1710. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
  1711.                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
  1712. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
  1713. HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
  1714. uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
  1715.  
  1716. /**
  1717.   * @}
  1718.   */
  1719.  
  1720. /** @addtogroup TIM_Exported_Functions_Group9
  1721.  * @{
  1722.  */
  1723. /* Callback in non blocking modes (Interrupt and DMA) *************************/
  1724. void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
  1725. void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
  1726. void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
  1727. void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
  1728. void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
  1729. void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
  1730. /**
  1731.   * @}
  1732.   */
  1733.  
  1734. /** @addtogroup TIM_Exported_Functions_Group10
  1735.  * @{
  1736.  */
  1737. /* Peripheral State functions  **************************************************/
  1738. HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
  1739. HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
  1740. HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
  1741. HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
  1742. HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
  1743. HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
  1744.  
  1745. /**
  1746.   * @}
  1747.   */
  1748.  
  1749. /**
  1750.   * @}
  1751.   */
  1752.  
  1753. /**
  1754.   * @}
  1755.   */
  1756.  
  1757. /**
  1758.   * @}
  1759.   */
  1760.  
  1761. #ifdef __cplusplus
  1762. }
  1763. #endif
  1764.  
  1765. #endif /* __STM32F1xx_HAL_TIM_H */
  1766.  
  1767. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1768.