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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_rcc.h
  4.   * @author  MCD Application Team
  5.   * @version V1.0.1
  6.   * @date    31-July-2015
  7.   * @brief   Header file of RCC HAL module.
  8.   ******************************************************************************
  9.   * @attention
  10.   *
  11.   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  12.   *
  13.   * Redistribution and use in source and binary forms, with or without modification,
  14.   * are permitted provided that the following conditions are met:
  15.   *   1. Redistributions of source code must retain the above copyright notice,
  16.   *      this list of conditions and the following disclaimer.
  17.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18.   *      this list of conditions and the following disclaimer in the documentation
  19.   *      and/or other materials provided with the distribution.
  20.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21.   *      may be used to endorse or promote products derived from this software
  22.   *      without specific prior written permission.
  23.   *
  24.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34.   *
  35.   ******************************************************************************
  36.   */
  37.  
  38. /* Define to prevent recursive inclusion -------------------------------------*/
  39. #ifndef __STM32F1xx_HAL_RCC_H
  40. #define __STM32F1xx_HAL_RCC_H
  41.  
  42. #ifdef __cplusplus
  43.  extern "C" {
  44. #endif
  45.  
  46. /* Includes ------------------------------------------------------------------*/
  47. #include "stm32f1xx_hal_def.h"
  48.  
  49. /** @addtogroup STM32F1xx_HAL_Driver
  50.   * @{
  51.   */
  52.  
  53. /** @addtogroup RCC
  54.   * @{
  55.   */
  56.  
  57. /** @addtogroup RCC_Private_Constants
  58.   * @{
  59.   */
  60.  
  61. /** @defgroup RCC_Timeout RCC Timeout
  62.   * @{
  63.   */
  64.  
  65. /* Disable Backup domain write protection state change timeout */
  66. #define RCC_DBP_TIMEOUT_VALUE  ((uint32_t)100)       /* 100 ms */
  67. /* LSE state change timeout */
  68. #define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
  69. #define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000)  /* 5 s    */
  70. #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
  71. #define HSI_TIMEOUT_VALUE         ((uint32_t)100)    /* 100 ms */
  72. #define LSI_TIMEOUT_VALUE         ((uint32_t)100)    /* 100 ms */
  73. #define PLL_TIMEOUT_VALUE         ((uint32_t)100)    /* 100 ms */
  74. #define LSI_VALUE                 ((uint32_t)40000)  /* 40kHz */
  75.  
  76. /**
  77.   * @}
  78.   */
  79.  
  80. /** @defgroup RCC_Register_Offset Register offsets
  81.   * @{
  82.   */
  83. #define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
  84. #define RCC_CR_OFFSET             0x00
  85. #define RCC_CFGR_OFFSET           0x04
  86. #define RCC_CIR_OFFSET            0x08
  87. #define RCC_BDCR_OFFSET           0x20
  88. #define RCC_CSR_OFFSET            0x24
  89.  
  90. /**
  91.   * @}
  92.   */
  93.  
  94. /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
  95.   * @brief RCC registers bit address in the alias region
  96.   * @{
  97.   */
  98. #define RCC_CR_OFFSET_BB          (RCC_OFFSET + RCC_CR_OFFSET)
  99. #define RCC_CFGR_OFFSET_BB        (RCC_OFFSET + RCC_CFGR_OFFSET)
  100. #define RCC_CIR_OFFSET_BB         (RCC_OFFSET + RCC_CIR_OFFSET)
  101. #define RCC_BDCR_OFFSET_BB        (RCC_OFFSET + RCC_BDCR_OFFSET)
  102. #define RCC_CSR_OFFSET_BB         (RCC_OFFSET + RCC_CSR_OFFSET)
  103.  
  104. /* --- CR Register ---*/
  105. /* Alias word address of HSION bit */
  106. #define RCC_HSION_BIT_NUMBER      POSITION_VAL(RCC_CR_HSION)
  107. #define RCC_CR_HSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4)))
  108. /* Alias word address of HSEON bit */
  109. #define RCC_HSEON_BIT_NUMBER      POSITION_VAL(RCC_CR_HSEON)
  110. #define RCC_CR_HSEON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4)))
  111. /* Alias word address of CSSON bit */
  112. #define RCC_CSSON_BIT_NUMBER      POSITION_VAL(RCC_CR_CSSON)
  113. #define RCC_CR_CSSON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4)))
  114. /* Alias word address of PLLON bit */
  115. #define RCC_PLLON_BIT_NUMBER      POSITION_VAL(RCC_CR_PLLON)
  116. #define RCC_CR_PLLON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4)))
  117.  
  118. /* --- CSR Register ---*/
  119. /* Alias word address of LSION bit */
  120. #define RCC_LSION_BIT_NUMBER      POSITION_VAL(RCC_CSR_LSION)
  121. #define RCC_CSR_LSION_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4)))
  122.  
  123. /* Alias word address of RMVF bit */
  124. #define RCC_RMVF_BIT_NUMBER       POSITION_VAL(RCC_CSR_RMVF)
  125. #define RCC_CSR_RMVF_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4)))
  126.  
  127. /* --- BDCR Registers ---*/
  128. /* Alias word address of LSEON bit */
  129. #define RCC_LSEON_BIT_NUMBER      POSITION_VAL(RCC_BDCR_LSEON)
  130. #define RCC_BDCR_LSEON_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4)))
  131.  
  132. /* Alias word address of LSEON bit */
  133. #define RCC_LSEBYP_BIT_NUMBER     POSITION_VAL(RCC_BDCR_LSEBYP)
  134. #define RCC_BDCR_LSEBYP_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4)))
  135.  
  136. /* Alias word address of RTCEN bit */
  137. #define RCC_RTCEN_BIT_NUMBER      POSITION_VAL(RCC_BDCR_RTCEN)
  138. #define RCC_BDCR_RTCEN_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4)))
  139.  
  140. /* Alias word address of BDRST bit */
  141. #define RCC_BDRST_BIT_NUMBER          POSITION_VAL(RCC_BDCR_BDRST)
  142. #define RCC_BDCR_BDRST_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_BDRST_BIT_NUMBER * 4)))
  143.  
  144. /**
  145.   * @}
  146.   */
  147.  
  148. /* CR register byte 2 (Bits[23:16]) base address */
  149. #define RCC_CR_BYTE2_ADDRESS          ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
  150.  
  151. /* CIR register byte 1 (Bits[15:8]) base address */
  152. #define RCC_CIR_BYTE1_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
  153.  
  154. /* CIR register byte 2 (Bits[23:16]) base address */
  155. #define RCC_CIR_BYTE2_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
  156.  
  157. /* Defines used for Flags */
  158. #define CR_REG_INDEX                     ((uint8_t)1)
  159. #define BDCR_REG_INDEX                   ((uint8_t)2)
  160. #define CSR_REG_INDEX                    ((uint8_t)3)
  161.  
  162. #define RCC_FLAG_MASK                    ((uint8_t)0x1F)
  163.  
  164. /**
  165.   * @}
  166.   */
  167.  
  168. /** @addtogroup RCC_Private_Macros
  169.   * @{
  170.   */
  171. /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
  172.   * @{
  173.   */
  174. #define __HAL_RCC_SYSCFG_CLK_DISABLE    __HAL_RCC_AFIO_CLK_DISABLE
  175. #define __HAL_RCC_SYSCFG_CLK_ENABLE     __HAL_RCC_AFIO_CLK_ENABLE
  176. #define __HAL_RCC_SYSCFG_FORCE_RESET    __HAL_RCC_AFIO_FORCE_RESET
  177. #define __HAL_RCC_SYSCFG_RELEASE_RESET  __HAL_RCC_AFIO_RELEASE_RESET
  178. /**
  179.   * @}
  180.   */
  181.  
  182. #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
  183.                                       ((__SOURCE__) == RCC_PLLSOURCE_HSE))
  184. #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
  185.                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
  186.                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
  187.                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
  188.                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
  189. #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
  190.                              ((__HSE__) == RCC_HSE_BYPASS))
  191. #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
  192.                              ((__LSE__) == RCC_LSE_BYPASS))
  193. #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
  194. #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
  195. #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
  196. #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
  197.                              ((__PLL__) == RCC_PLL_ON))
  198.  
  199. #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
  200.                                (((CLK) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
  201.                                (((CLK) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1)  || \
  202.                                (((CLK) & RCC_CLOCKTYPE_PCLK2)  == RCC_CLOCKTYPE_PCLK2))
  203. #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
  204.                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
  205.                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
  206. #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
  207.                                                 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
  208.                                                 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
  209. #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
  210.                                ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
  211.                                ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
  212.                                ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
  213.                                ((__HCLK__) == RCC_SYSCLK_DIV512))
  214. #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
  215.                                ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
  216.                                ((__PCLK__) == RCC_HCLK_DIV16))
  217. #define IS_RCC_MCO(__MCO__)  ((__MCO__) == RCC_MCO)
  218. #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
  219. #define IS_RCC_RTCCLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
  220.                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)  || \
  221.                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)  || \
  222.                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
  223.  
  224. /**
  225.   * @}
  226.   */
  227.  
  228. /* Exported types ------------------------------------------------------------*/
  229.  
  230. /** @defgroup RCC_Exported_Types RCC Exported Types
  231.   * @{
  232.   */
  233.  
  234. /**
  235.   * @brief  RCC PLL configuration structure definition  
  236.   */
  237. typedef struct
  238. {
  239.   uint32_t PLLState;      /*!< PLLState: The new state of the PLL.
  240.                               This parameter can be a value of @ref RCC_PLL_Config */
  241.  
  242.   uint32_t PLLSource;     /*!< PLLSource: PLL entry clock source.
  243.                               This parameter must be a value of @ref RCC_PLL_Clock_Source */          
  244.  
  245.   uint32_t PLLMUL;        /*!< PLLMUL: Multiplication factor for PLL VCO input clock
  246.                               This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
  247. } RCC_PLLInitTypeDef;
  248.    
  249. /**
  250.   * @brief  RCC System, AHB and APB busses clock configuration structure definition  
  251.   */
  252. typedef struct
  253. {
  254.   uint32_t ClockType;             /*!< The clock to be configured.
  255.                                        This parameter can be a value of @ref RCC_System_Clock_Type */
  256.  
  257.   uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
  258.                                        This parameter can be a value of @ref RCC_System_Clock_Source */
  259.  
  260.   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
  261.                                        This parameter can be a value of @ref RCC_AHB_Clock_Source */
  262.  
  263.   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
  264.                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
  265.  
  266.   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
  267.                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
  268. } RCC_ClkInitTypeDef;
  269.  
  270. /**
  271.   * @}
  272.   */
  273.  
  274. /* Exported constants --------------------------------------------------------*/
  275. /** @defgroup RCC_Exported_Constants RCC Exported Constants
  276.   * @{
  277.   */
  278.  
  279. /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
  280.   * @{
  281.   */
  282.  
  283. #define RCC_PLLSOURCE_HSI_DIV2      ((uint32_t)0x00000000)     /*!< HSI clock divided by 2 selected as PLL entry clock source */
  284. #define RCC_PLLSOURCE_HSE           RCC_CFGR_PLLSRC            /*!< HSE clock selected as PLL entry clock source */
  285.  
  286. /**
  287.   * @}
  288.   */
  289.  
  290. /** @defgroup RCC_Oscillator_Type Oscillator Type
  291.   * @{
  292.   */
  293. #define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000)
  294. #define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001)
  295. #define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002)
  296. #define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004)
  297. #define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008)
  298. /**
  299.   * @}
  300.   */
  301.  
  302. /** @defgroup RCC_HSE_Config HSE Config
  303.   * @{
  304.   */
  305. #define RCC_HSE_OFF                      ((uint32_t)0x00000000)                     /*!< HSE clock deactivation */
  306. #define RCC_HSE_ON                       RCC_CR_HSEON                               /*!< HSE clock activation */
  307. #define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
  308. /**
  309.   * @}
  310.   */
  311.  
  312. /** @defgroup RCC_LSE_Config LSE Config
  313.   * @{
  314.   */
  315. #define RCC_LSE_OFF                      ((uint32_t)0x00000000)                       /*!< LSE clock deactivation */
  316. #define RCC_LSE_ON                       RCC_BDCR_LSEON                                /*!< LSE clock activation */
  317. #define RCC_LSE_BYPASS                   ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
  318.  
  319. /**
  320.   * @}
  321.   */
  322.  
  323. /** @defgroup RCC_HSI_Config HSI Config
  324.   * @{
  325.   */
  326. #define RCC_HSI_OFF                      ((uint32_t)0x00000000)   /*!< HSI clock deactivation */
  327. #define RCC_HSI_ON                       RCC_CR_HSION             /*!< HSI clock activation */
  328.  
  329. #define RCC_HSICALIBRATION_DEFAULT       ((uint32_t)0x10)         /* Default HSI calibration trimming value */
  330.  
  331. /**
  332.   * @}
  333.   */
  334.  
  335. /** @defgroup RCC_LSI_Config LSI Config
  336.   * @{
  337.   */
  338. #define RCC_LSI_OFF                      ((uint32_t)0x00000000)   /*!< LSI clock deactivation */
  339. #define RCC_LSI_ON                       RCC_CSR_LSION            /*!< LSI clock activation */
  340.  
  341. /**
  342.   * @}
  343.   */
  344.  
  345. /** @defgroup RCC_PLL_Config PLL Config
  346.   * @{
  347.   */
  348. #define RCC_PLL_NONE                      ((uint32_t)0x00000000)  /*!< PLL is not configured */
  349. #define RCC_PLL_OFF                       ((uint32_t)0x00000001)  /*!< PLL deactivation */
  350. #define RCC_PLL_ON                        ((uint32_t)0x00000002)  /*!< PLL activation */
  351.  
  352. /**
  353.   * @}
  354.   */
  355.  
  356. /** @defgroup RCC_System_Clock_Type System Clock Type
  357.   * @{
  358.   */
  359. #define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001) /*!< SYSCLK to configure */
  360. #define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002) /*!< HCLK to configure */
  361. #define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004) /*!< PCLK1 to configure */
  362. #define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008) /*!< PCLK2 to configure */
  363.  
  364. /**
  365.   * @}
  366.   */
  367.  
  368. /** @defgroup RCC_System_Clock_Source System Clock Source
  369.   * @{
  370.   */
  371. #define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
  372. #define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
  373. #define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
  374.  
  375. /**
  376.   * @}
  377.   */
  378.  
  379. /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
  380.   * @{
  381.   */
  382. #define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI            /*!< HSI used as system clock */
  383. #define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE            /*!< HSE used as system clock */
  384. #define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL            /*!< PLL used as system clock */
  385.  
  386. /**
  387.   * @}
  388.   */
  389.  
  390. /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
  391.   * @{
  392.   */
  393. #define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
  394. #define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
  395. #define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
  396. #define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
  397. #define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
  398. #define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
  399. #define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
  400. #define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
  401. #define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
  402.  
  403. /**
  404.   * @}
  405.   */
  406.  
  407. /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
  408.   * @{
  409.   */
  410. #define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
  411. #define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
  412. #define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
  413. #define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
  414. #define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
  415.  
  416. /**
  417.   * @}
  418.   */
  419.  
  420. /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
  421.   * @{
  422.   */
  423. #define RCC_RTCCLKSOURCE_NO_CLK          ((uint32_t)0x00000000)                 /*!< No clock */
  424. #define RCC_RTCCLKSOURCE_LSE             RCC_BDCR_RTCSEL_LSE                    /*!< LSE oscillator clock used as RTC clock */
  425. #define RCC_RTCCLKSOURCE_LSI             RCC_BDCR_RTCSEL_LSI                    /*!< LSI oscillator clock used as RTC clock */
  426. #define RCC_RTCCLKSOURCE_HSE_DIV128      RCC_BDCR_RTCSEL_HSE                    /*!< HSE oscillator clock divided by 128 used as RTC clock */
  427. /**
  428.   * @}
  429.   */
  430.  
  431.  
  432. /** @defgroup RCC_MCO_Index MCO Index
  433.   * @{
  434.   */
  435. #define RCC_MCO1                         ((uint32_t)0x00000000)
  436. #define RCC_MCO                          RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
  437.  
  438. /**
  439.   * @}
  440.   */
  441.  
  442. /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
  443.   * @{
  444.   */
  445. #define RCC_MCODIV_1                    ((uint32_t)0x00000000)
  446.  
  447. /**
  448.   * @}
  449.   */
  450.  
  451. /** @defgroup RCC_Interrupt Interrupts
  452.   * @{
  453.   */
  454. #define RCC_IT_LSIRDY                    ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
  455. #define RCC_IT_LSERDY                    ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
  456. #define RCC_IT_HSIRDY                    ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
  457. #define RCC_IT_HSERDY                    ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
  458. #define RCC_IT_PLLRDY                    ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
  459. #define RCC_IT_CSS                       ((uint8_t)RCC_CIR_CSSF)    /*!< Clock Security System Interrupt flag */
  460. /**
  461.   * @}
  462.   */
  463.  
  464. /** @defgroup RCC_Flag Flags
  465.   *        Elements values convention: XXXYYYYYb
  466.   *           - YYYYY  : Flag position in the register
  467.   *           - XXX  : Register index
  468.   *                 - 001: CR register
  469.   *                 - 010: BDCR register
  470.   *                 - 011: CSR register
  471.   * @{
  472.   */
  473. /* Flags in the CR register */
  474. #define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
  475. #define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
  476. #define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
  477.  
  478. /* Flags in the CSR register */
  479. #define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY)))   /*!< Internal Low Speed oscillator Ready */
  480. #define RCC_FLAG_RMV                     ((uint8_t)((CSR_REG_INDEX << 5) | RCC_RMVF_BIT_NUMBER))     /*!< Remove reset flag */
  481. #define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF)))  /*!< PIN reset flag */
  482. #define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF)))  /*!< POR/PDR reset flag */
  483. #define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF)))  /*!< Software Reset flag */
  484. #define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
  485. #define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
  486. #define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
  487.  
  488. /* Flags in the BDCR register */
  489. #define RCC_FLAG_LSERDY                  ((uint8_t)((BDCR_REG_INDEX << 5) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
  490.  
  491. /**
  492.   * @}
  493.   */
  494.  
  495. /**
  496.   * @}
  497.   */
  498.  
  499. /* Exported macro ------------------------------------------------------------*/
  500.  
  501. /** @defgroup RCC_Exported_Macros RCC Exported Macros
  502.   * @{
  503.   */
  504.  
  505. /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
  506.   * @brief  Enable or disable the AHB1 peripheral clock.
  507.   * @note   After reset, the peripheral clock (used for registers read/write access)
  508.   *         is disabled and the application software has to enable this clock before
  509.   *         using it.  
  510.   * @{
  511.   */
  512. #define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
  513.                                         __IO uint32_t tmpreg; \
  514.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
  515.                                         /* Delay after an RCC peripheral clock enabling */\
  516.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
  517.                                         UNUSED(tmpreg); \
  518.                                       } while(0)
  519.  
  520. #define __HAL_RCC_SRAM_CLK_ENABLE()   do { \
  521.                                         __IO uint32_t tmpreg; \
  522.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
  523.                                         /* Delay after an RCC peripheral clock enabling */\
  524.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
  525.                                         UNUSED(tmpreg); \
  526.                                       } while(0)
  527.  
  528. #define __HAL_RCC_FLITF_CLK_ENABLE()   do { \
  529.                                         __IO uint32_t tmpreg; \
  530.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
  531.                                         /* Delay after an RCC peripheral clock enabling */\
  532.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
  533.                                         UNUSED(tmpreg); \
  534.                                       } while(0)
  535.  
  536. #define __HAL_RCC_CRC_CLK_ENABLE()   do { \
  537.                                         __IO uint32_t tmpreg; \
  538.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
  539.                                         /* Delay after an RCC peripheral clock enabling */\
  540.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
  541.                                         UNUSED(tmpreg); \
  542.                                       } while(0)
  543.  
  544. #define __HAL_RCC_DMA1_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
  545. #define __HAL_RCC_SRAM_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
  546. #define __HAL_RCC_FLITF_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
  547. #define __HAL_RCC_CRC_CLK_DISABLE()       (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
  548.  
  549. /**
  550.   * @}
  551.   */
  552.  
  553. /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
  554.   * @brief  Get the enable or disable status of the AHB peripheral clock.
  555.   * @note   After reset, the peripheral clock (used for registers read/write access)
  556.   *         is disabled and the application software has to enable this clock before
  557.   *         using it.
  558.   * @{
  559.   */
  560.  
  561. #define __HAL_RCC_DMA1_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
  562. #define __HAL_RCC_DMA1_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
  563. #define __HAL_RCC_SRAM_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
  564. #define __HAL_RCC_SRAM_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
  565. #define __HAL_RCC_FLITF_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
  566. #define __HAL_RCC_FLITF_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
  567. #define __HAL_RCC_CRC_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
  568. #define __HAL_RCC_CRC_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
  569.  
  570. /**
  571.   * @}
  572.   */
  573.  
  574. /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
  575.   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
  576.   * @note   After reset, the peripheral clock (used for registers read/write access)
  577.   *         is disabled and the application software has to enable this clock before
  578.   *         using it.
  579.   * @{  
  580.   */
  581. #define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
  582.                                         __IO uint32_t tmpreg; \
  583.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
  584.                                         /* Delay after an RCC peripheral clock enabling */\
  585.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
  586.                                         UNUSED(tmpreg); \
  587.                                       } while(0)
  588.  
  589. #define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
  590.                                         __IO uint32_t tmpreg; \
  591.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
  592.                                         /* Delay after an RCC peripheral clock enabling */\
  593.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
  594.                                         UNUSED(tmpreg); \
  595.                                       } while(0)
  596.  
  597. #define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
  598.                                         __IO uint32_t tmpreg; \
  599.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
  600.                                         /* Delay after an RCC peripheral clock enabling */\
  601.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
  602.                                         UNUSED(tmpreg); \
  603.                                       } while(0)
  604.  
  605. #define __HAL_RCC_USART2_CLK_ENABLE()   do { \
  606.                                         __IO uint32_t tmpreg; \
  607.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
  608.                                         /* Delay after an RCC peripheral clock enabling */\
  609.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
  610.                                         UNUSED(tmpreg); \
  611.                                       } while(0)
  612.  
  613. #define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
  614.                                         __IO uint32_t tmpreg; \
  615.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
  616.                                         /* Delay after an RCC peripheral clock enabling */\
  617.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
  618.                                         UNUSED(tmpreg); \
  619.                                       } while(0)
  620.  
  621. #define __HAL_RCC_BKP_CLK_ENABLE()   do { \
  622.                                         __IO uint32_t tmpreg; \
  623.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
  624.                                         /* Delay after an RCC peripheral clock enabling */\
  625.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
  626.                                         UNUSED(tmpreg); \
  627.                                       } while(0)
  628.  
  629. #define __HAL_RCC_PWR_CLK_ENABLE()   do { \
  630.                                         __IO uint32_t tmpreg; \
  631.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
  632.                                         /* Delay after an RCC peripheral clock enabling */\
  633.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
  634.                                         UNUSED(tmpreg); \
  635.                                       } while(0)
  636.  
  637. #define __HAL_RCC_TIM2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
  638. #define __HAL_RCC_TIM3_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
  639. #define __HAL_RCC_WWDG_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
  640. #define __HAL_RCC_USART2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
  641. #define __HAL_RCC_I2C1_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
  642.  
  643. #define __HAL_RCC_BKP_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
  644. #define __HAL_RCC_PWR_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
  645.  
  646. /**
  647.   * @}
  648.   */
  649.  
  650. /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
  651.   * @brief  Get the enable or disable status of the APB1 peripheral clock.
  652.   * @note   After reset, the peripheral clock (used for registers read/write access)
  653.   *         is disabled and the application software has to enable this clock before
  654.   *         using it.
  655.   * @{
  656.   */
  657.  
  658. #define __HAL_RCC_TIM2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
  659. #define __HAL_RCC_TIM2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
  660. #define __HAL_RCC_TIM3_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
  661. #define __HAL_RCC_TIM3_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
  662. #define __HAL_RCC_WWDG_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
  663. #define __HAL_RCC_WWDG_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
  664. #define __HAL_RCC_USART2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
  665. #define __HAL_RCC_USART2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
  666. #define __HAL_RCC_I2C1_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
  667. #define __HAL_RCC_I2C1_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
  668. #define __HAL_RCC_BKP_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
  669. #define __HAL_RCC_BKP_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
  670. #define __HAL_RCC_PWR_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
  671. #define __HAL_RCC_PWR_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
  672.  
  673. /**
  674.   * @}
  675.   */
  676.  
  677. /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
  678.   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
  679.   * @note   After reset, the peripheral clock (used for registers read/write access)
  680.   *         is disabled and the application software has to enable this clock before
  681.   *         using it.
  682.   * @{  
  683.   */
  684. #define __HAL_RCC_AFIO_CLK_ENABLE()   do { \
  685.                                         __IO uint32_t tmpreg; \
  686.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
  687.                                         /* Delay after an RCC peripheral clock enabling */\
  688.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
  689.                                         UNUSED(tmpreg); \
  690.                                       } while(0)
  691.  
  692. #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
  693.                                         __IO uint32_t tmpreg; \
  694.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
  695.                                         /* Delay after an RCC peripheral clock enabling */\
  696.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
  697.                                         UNUSED(tmpreg); \
  698.                                       } while(0)
  699.  
  700. #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
  701.                                         __IO uint32_t tmpreg; \
  702.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
  703.                                         /* Delay after an RCC peripheral clock enabling */\
  704.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
  705.                                         UNUSED(tmpreg); \
  706.                                       } while(0)
  707.  
  708. #define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
  709.                                         __IO uint32_t tmpreg; \
  710.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
  711.                                         /* Delay after an RCC peripheral clock enabling */\
  712.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
  713.                                         UNUSED(tmpreg); \
  714.                                       } while(0)
  715.  
  716. #define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
  717.                                         __IO uint32_t tmpreg; \
  718.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
  719.                                         /* Delay after an RCC peripheral clock enabling */\
  720.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
  721.                                         UNUSED(tmpreg); \
  722.                                       } while(0)
  723.  
  724. #define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
  725.                                         __IO uint32_t tmpreg; \
  726.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
  727.                                         /* Delay after an RCC peripheral clock enabling */\
  728.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
  729.                                         UNUSED(tmpreg); \
  730.                                       } while(0)
  731.  
  732. #define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
  733.                                         __IO uint32_t tmpreg; \
  734.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
  735.                                         /* Delay after an RCC peripheral clock enabling */\
  736.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
  737.                                         UNUSED(tmpreg); \
  738.                                       } while(0)
  739.  
  740. #define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
  741.                                         __IO uint32_t tmpreg; \
  742.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
  743.                                         /* Delay after an RCC peripheral clock enabling */\
  744.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
  745.                                         UNUSED(tmpreg); \
  746.                                       } while(0)
  747.  
  748. #define __HAL_RCC_USART1_CLK_ENABLE()   do { \
  749.                                         __IO uint32_t tmpreg; \
  750.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
  751.                                         /* Delay after an RCC peripheral clock enabling */\
  752.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
  753.                                         UNUSED(tmpreg); \
  754.                                       } while(0)
  755.  
  756. #define __HAL_RCC_AFIO_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
  757. #define __HAL_RCC_GPIOA_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
  758. #define __HAL_RCC_GPIOB_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
  759. #define __HAL_RCC_GPIOC_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
  760. #define __HAL_RCC_GPIOD_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
  761. #define __HAL_RCC_ADC1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
  762.  
  763. #define __HAL_RCC_TIM1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
  764. #define __HAL_RCC_SPI1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
  765. #define __HAL_RCC_USART1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
  766.  
  767. /**
  768.   * @}
  769.   */
  770.  
  771. /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
  772.   * @brief  Get the enable or disable status of the APB2 peripheral clock.
  773.   * @note   After reset, the peripheral clock (used for registers read/write access)
  774.   *         is disabled and the application software has to enable this clock before
  775.   *         using it.
  776.   * @{
  777.   */
  778.  
  779. #define __HAL_RCC_AFIO_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
  780. #define __HAL_RCC_AFIO_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
  781. #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
  782. #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
  783. #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
  784. #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
  785. #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
  786. #define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
  787. #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
  788. #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
  789. #define __HAL_RCC_ADC1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
  790. #define __HAL_RCC_ADC1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
  791. #define __HAL_RCC_TIM1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
  792. #define __HAL_RCC_TIM1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
  793. #define __HAL_RCC_SPI1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
  794. #define __HAL_RCC_SPI1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
  795. #define __HAL_RCC_USART1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
  796. #define __HAL_RCC_USART1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
  797.  
  798. /**
  799.   * @}
  800.   */
  801.  
  802. /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
  803.   * @brief  Force or release APB1 peripheral reset.
  804.   * @{  
  805.   */
  806. #define __HAL_RCC_APB1_FORCE_RESET()       (RCC->APB2RSTR = 0xFFFFFFFF)  
  807. #define __HAL_RCC_TIM2_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
  808. #define __HAL_RCC_TIM3_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
  809. #define __HAL_RCC_WWDG_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
  810. #define __HAL_RCC_USART2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
  811. #define __HAL_RCC_I2C1_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
  812.  
  813. #define __HAL_RCC_BKP_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
  814. #define __HAL_RCC_PWR_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
  815.  
  816. #define __HAL_RCC_APB1_RELEASE_RESET()      (RCC->APB1RSTR = 0x00)  
  817. #define __HAL_RCC_TIM2_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
  818. #define __HAL_RCC_TIM3_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
  819. #define __HAL_RCC_WWDG_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
  820. #define __HAL_RCC_USART2_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
  821. #define __HAL_RCC_I2C1_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
  822.  
  823. #define __HAL_RCC_BKP_RELEASE_RESET()        (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
  824. #define __HAL_RCC_PWR_RELEASE_RESET()        (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
  825.  
  826. /**
  827.   * @}
  828.   */
  829.  
  830. /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
  831.   * @brief  Force or release APB2 peripheral reset.
  832.   * @{  
  833.   */
  834. #define __HAL_RCC_APB2_FORCE_RESET()       (RCC->APB2RSTR = 0xFFFFFFFF)  
  835. #define __HAL_RCC_AFIO_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
  836. #define __HAL_RCC_GPIOA_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
  837. #define __HAL_RCC_GPIOB_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
  838. #define __HAL_RCC_GPIOC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
  839. #define __HAL_RCC_GPIOD_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
  840. #define __HAL_RCC_ADC1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
  841.  
  842. #define __HAL_RCC_TIM1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
  843. #define __HAL_RCC_SPI1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
  844. #define __HAL_RCC_USART1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
  845.  
  846. #define __HAL_RCC_APB2_RELEASE_RESET()      (RCC->APB2RSTR = 0x00)  
  847. #define __HAL_RCC_AFIO_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
  848. #define __HAL_RCC_GPIOA_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
  849. #define __HAL_RCC_GPIOB_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
  850. #define __HAL_RCC_GPIOC_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
  851. #define __HAL_RCC_GPIOD_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
  852. #define __HAL_RCC_ADC1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
  853.  
  854. #define __HAL_RCC_TIM1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
  855. #define __HAL_RCC_SPI1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
  856. #define __HAL_RCC_USART1_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
  857.  
  858. /**
  859.   * @}
  860.   */
  861.  
  862. /** @defgroup RCC_HSI_Configuration HSI Configuration
  863.   * @{  
  864.   */
  865.  
  866. /** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
  867.   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
  868.   * @note   HSI can not be stopped if it is used as system clock source. In this case,
  869.   *         you have to select another source of the system clock then stop the HSI.  
  870.   * @note   After enabling the HSI, the application software should wait on HSIRDY
  871.   *         flag to be set indicating that HSI clock is stable and can be used as
  872.   *         system clock source.  
  873.   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
  874.   *         clock cycles.  
  875.   */
  876. #define __HAL_RCC_HSI_ENABLE()  (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
  877. #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
  878.  
  879. /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
  880.   * @note   The calibration is used to compensate for the variations in voltage
  881.   *         and temperature that influence the frequency of the internal HSI RC.
  882.   * @param  _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
  883.   *         (default is RCC_HSICALIBRATION_DEFAULT).
  884.   *         This parameter must be a number between 0 and 0x1F.
  885.   */  
  886. #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
  887.           (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
  888.  
  889. /**
  890.   * @}
  891.   */
  892.  
  893. /** @defgroup RCC_LSI_Configuration  LSI Configuration
  894.   * @{  
  895.   */
  896.  
  897. /** @brief Macro to enable the Internal Low Speed oscillator (LSI).
  898.   * @note   After enabling the LSI, the application software should wait on
  899.   *         LSIRDY flag to be set indicating that LSI clock is stable and can
  900.   *         be used to clock the IWDG and/or the RTC.
  901.   */
  902. #define __HAL_RCC_LSI_ENABLE()  (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
  903.  
  904. /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
  905.   * @note   LSI can not be disabled if the IWDG is running.  
  906.   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
  907.   *         clock cycles.
  908.   */
  909. #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
  910.  
  911. /**
  912.   * @}
  913.   */
  914.  
  915. /** @defgroup RCC_HSE_Configuration HSE Configuration
  916.   * @{  
  917.   */
  918.  
  919. /**
  920.   * @brief  Macro to configure the External High Speed oscillator (HSE).
  921.   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
  922.   *         supported by this macro. User should request a transition to HSE Off
  923.   *         first and then HSE On or HSE Bypass.
  924.   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
  925.   *         software should wait on HSERDY flag to be set indicating that HSE clock
  926.   *         is stable and can be used to clock the PLL and/or system clock.
  927.   * @note   HSE state can not be changed if it is used directly or through the
  928.   *         PLL as system clock. In this case, you have to select another source
  929.   *         of the system clock then change the HSE state (ex. disable it).
  930.   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
  931.   * @note   This function reset the CSSON bit, so if the Clock security system(CSS)
  932.   *         was previously enabled you have to enable it again after calling this
  933.   *         function.
  934.   * @param  __STATE__ specifies the new state of the HSE.
  935.   *          This parameter can be one of the following values:
  936.   *            @arg RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
  937.   *                              6 HSE oscillator clock cycles.
  938.   *            @arg RCC_HSE_ON turn ON the HSE oscillator
  939.   *            @arg RCC_HSE_BYPASS HSE oscillator bypassed with external clock
  940.   */
  941. #define __HAL_RCC_HSE_CONFIG(__STATE__)                                     \
  942.                     do{                                                     \
  943.                       if ((__STATE__) == RCC_HSE_ON)                        \
  944.                       {                                                     \
  945.                         SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
  946.                       }                                                     \
  947.                       else if ((__STATE__) == RCC_HSE_OFF)                  \
  948.                       {                                                     \
  949.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
  950.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
  951.                       }                                                     \
  952.                       else if ((__STATE__) == RCC_HSE_BYPASS)               \
  953.                       {                                                     \
  954.                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);                    \
  955.                         SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
  956.                       }                                                     \
  957.                       else                                                  \
  958.                       {                                                     \
  959.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
  960.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
  961.                       }                                                     \
  962.                     }while(0)
  963.  
  964. /**
  965.   * @}
  966.   */
  967.  
  968. /** @defgroup RCC_LSE_Configuration LSE Configuration
  969.   * @{  
  970.   */
  971.  
  972. /**
  973.   * @brief  Macro to configure the External Low Speed oscillator (LSE).
  974.   * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
  975.   * @note   As the LSE is in the Backup domain and write access is denied to
  976.   *         this domain after reset, you have to enable write access using
  977.   *         @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
  978.   *         (to be done once after reset).  
  979.   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
  980.   *         software should wait on LSERDY flag to be set indicating that LSE clock
  981.   *         is stable and can be used to clock the RTC.
  982.   * @param  __STATE__ specifies the new state of the LSE.
  983.   *         This parameter can be one of the following values:
  984.   *            @arg RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
  985.   *                              6 LSE oscillator clock cycles.
  986.   *            @arg RCC_LSE_ON turn ON the LSE oscillator.
  987.   *            @arg RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
  988.   */
  989. #define __HAL_RCC_LSE_CONFIG(__STATE__)                                     \
  990.                     do{                                                     \
  991.                       if ((__STATE__) == RCC_LSE_ON)                        \
  992.                       {                                                     \
  993.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
  994.                       }                                                     \
  995.                       else if ((__STATE__) == RCC_LSE_OFF)                  \
  996.                       {                                                     \
  997.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
  998.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
  999.                       }                                                     \
  1000.                       else if ((__STATE__) == RCC_LSE_BYPASS)               \
  1001.                       {                                                     \
  1002.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                  \
  1003.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
  1004.                       }                                                     \
  1005.                       else                                                  \
  1006.                       {                                                     \
  1007.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
  1008.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
  1009.                       }                                                     \
  1010.                     }while(0)
  1011.  
  1012. /**
  1013.   * @}
  1014.   */
  1015.  
  1016. /** @defgroup RCC_PLL_Configuration PLL Configuration
  1017.   * @{  
  1018.   */
  1019.  
  1020. /** @brief Macro to enable the main PLL.
  1021.   * @note   After enabling the main PLL, the application software should wait on
  1022.   *         PLLRDY flag to be set indicating that PLL clock is stable and can
  1023.   *         be used as system clock source.
  1024.   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
  1025.   */
  1026. #define __HAL_RCC_PLL_ENABLE()          (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
  1027.  
  1028. /** @brief Macro to disable the main PLL.
  1029.   * @note   The main PLL can not be disabled if it is used as system clock source
  1030.   */
  1031. #define __HAL_RCC_PLL_DISABLE()         (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
  1032.  
  1033. /** @brief Macro to configure the main PLL clock source and multiplication factors.
  1034.   * @note   This function must be used only when the main PLL is disabled.
  1035.   *  
  1036.   * @param  __RCC_PLLSOURCE__ specifies the PLL entry clock source.
  1037.   *          This parameter can be one of the following values:
  1038.   *            @arg RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
  1039.   *            @arg RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
  1040.   * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
  1041.   *          This parameter can be one of the following values:
  1042.   *             @arg RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 (*)
  1043.   *             @arg RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 (*)
  1044.   *             @arg RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
  1045.   *             @arg RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
  1046.   *             @arg RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 (**)
  1047.   *             @arg RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
  1048.   *             @arg RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
  1049.   *             @arg RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 (*)
  1050.   *             @arg RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 (*)
  1051.   *             @arg RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 (*)
  1052.   *             @arg RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 (*)
  1053.   *             @arg RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 (*)
  1054.   *             @arg RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 (*)
  1055.   *             @arg RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 (*)
  1056.   * @note (*) These values are not available in STM32F105xx & STM32F107xx devices.
  1057.   * @note (**) This value is available in STM32F105xx & STM32F107xx devices only.
  1058.   *  
  1059.   */
  1060. #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
  1061.           MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
  1062.  
  1063. /** @brief  Get oscillator clock selected as PLL input clock
  1064.   * @retval The clock source used for PLL entry. The returned value can be one
  1065.   *         of the following:
  1066.   *             @arg RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
  1067.   *             @arg RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
  1068.   */
  1069. #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
  1070.  
  1071. /**
  1072.   * @}
  1073.   */
  1074.  
  1075. /** @defgroup RCC_Get_Clock_source Get Clock source
  1076.   * @{  
  1077.   */
  1078.  
  1079. /**
  1080.   * @brief  Macro to configure the system clock source.
  1081.   * @param  __RCC_SYSCLKSOURCE__ specifies the system clock source.
  1082.   *          This parameter can be one of the following values:
  1083.   *              @arg RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
  1084.   *              @arg RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
  1085.   *              @arg RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
  1086.   */
  1087. #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \
  1088.                   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
  1089.  
  1090. /** @brief  Macro to get the clock source used as system clock.
  1091.   * @retval The clock source used as system clock. The returned value can be one
  1092.   *         of the following:
  1093.   *             @arg RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
  1094.   *             @arg RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
  1095.   *             @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
  1096.   */
  1097. #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
  1098.  
  1099. /**
  1100.   * @}
  1101.   */
  1102.  
  1103. /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
  1104.   * @{  
  1105.   */
  1106.  
  1107. #if   defined(RCC_CFGR_MCO_3)
  1108. /** @brief  Macro to configure the MCO clock.
  1109.   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
  1110.   *         This parameter can be one of the following values:
  1111.   *            @arg RCC_MCO1SOURCE_NOCLOCK: No clock
  1112.   *            @arg RCC_MCO1SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO clock
  1113.   *            @arg RCC_MCO1SOURCE_HSI: HSI selected as MCO clock
  1114.   *            @arg RCC_MCO1SOURCE_HSE: HSE selected as MCO clock
  1115.   *            @arg RCC_MCO1SOURCE_PLLCLK: PLL clock divided by 2 selected as MCO clock
  1116.   *            @arg RCC_MCO1SOURCE_PLL2CLK: PLL2 clock selected by 2 selected as MCO clock
  1117.   *            @arg RCC_MCO1SOURCE_PLL3CLK_DIV2: PLL3 clock divided by 2 selected as MCO clock
  1118.   *            @arg RCC_MCO1SOURCE_EXT_HSE: XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
  1119.   *            @arg RCC_MCO1SOURCE_PLL3CLK: PLL3 clock selected (for Ethernet) as MCO clock
  1120.   * @param  __MCODIV__ specifies the MCO clock prescaler.
  1121.   *         This parameter can be one of the following values:
  1122.   *            @arg RCC_MCODIV_1: No division applied on MCO clock source
  1123.   */
  1124. #else
  1125. /** @brief  Macro to configure the MCO clock.
  1126.   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
  1127.   *         This parameter can be one of the following values:
  1128.   *            @arg RCC_MCO1SOURCE_NOCLOCK: No clock
  1129.   *            @arg RCC_MCO1SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO clock
  1130.   *            @arg RCC_MCO1SOURCE_HSI: HSI selected as MCO clock
  1131.   *            @arg RCC_MCO1SOURCE_HSE: HSE selected as MCO clock
  1132.   *            @arg RCC_MCO1SOURCE_PLLCLK: PLL clock divided by 2 selected as MCO clock
  1133.   * @param  __MCODIV__ specifies the MCO clock prescaler.
  1134.   *         This parameter can be one of the following values:
  1135.   *            @arg RCC_MCODIV_1: No division applied on MCO clock source
  1136.   */
  1137. #endif
  1138.  
  1139. #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
  1140.                  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
  1141.  
  1142.  
  1143. /**
  1144.   * @}
  1145.   */
  1146.  
  1147.   /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
  1148.   * @{  
  1149.   */
  1150.  
  1151. /** @brief Macro to configure the RTC clock (RTCCLK).
  1152.   * @note   As the RTC clock configuration bits are in the Backup domain and write
  1153.   *         access is denied to this domain after reset, you have to enable write
  1154.   *         access using the Power Backup Access macro before to configure
  1155.   *         the RTC clock source (to be done once after reset).    
  1156.   * @note   Once the RTC clock is configured it can't be changed unless the  
  1157.   *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
  1158.   *         a Power On Reset (POR).
  1159.   *
  1160.   * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
  1161.   *          This parameter can be one of the following values:
  1162.   *             @arg RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
  1163.   *             @arg RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
  1164.   *             @arg RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
  1165.   *             @arg RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
  1166.   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
  1167.   *         work in STOP and STANDBY modes, and can be used as wakeup source.
  1168.   *         However, when the HSE clock is used as RTC clock source, the RTC
  1169.   *         cannot be used in STOP and STANDBY modes.    
  1170.   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
  1171.   *         RTC clock source).
  1172.   */
  1173. #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
  1174.                                                    
  1175. /** @brief Macro to get the RTC clock source.
  1176.   * @retval The clock source can be one of the following values:
  1177.   *            @arg RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
  1178.   *            @arg RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
  1179.   *            @arg RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
  1180.   *            @arg RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
  1181.   */
  1182. #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
  1183.  
  1184. /** @brief Macro to enable the the RTC clock.
  1185.   * @note   These macros must be used only after the RTC clock source was selected.
  1186.   */
  1187. #define __HAL_RCC_RTC_ENABLE()          (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
  1188.  
  1189. /** @brief Macro to disable the the RTC clock.
  1190.   * @note  These macros must be used only after the RTC clock source was selected.
  1191.   */
  1192. #define __HAL_RCC_RTC_DISABLE()         (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
  1193.  
  1194. /** @brief  Macro to force the Backup domain reset.
  1195.   * @note   This function resets the RTC peripheral (including the backup registers)
  1196.   *         and the RTC clock source selection in RCC_BDCR register.
  1197.   */
  1198. #define __HAL_RCC_BACKUPRESET_FORCE()   (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
  1199.  
  1200. /** @brief  Macros to release the Backup domain reset.
  1201.   */
  1202. #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
  1203.  
  1204. /**
  1205.   * @}
  1206.   */
  1207.  
  1208. /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
  1209.   * @brief macros to manage the specified RCC Flags and interrupts.
  1210.   * @{
  1211.   */
  1212.  
  1213. /** @brief Enable RCC interrupt.
  1214.   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
  1215.   *          This parameter can be any combination of the following values:
  1216.   *            @arg RCC_IT_LSIRDY LSI ready interrupt
  1217.   *            @arg RCC_IT_LSERDY LSE ready interrupt
  1218.   *            @arg RCC_IT_HSIRDY HSI ready interrupt
  1219.   *            @arg RCC_IT_HSERDY HSE ready interrupt
  1220.   *            @arg RCC_IT_PLLRDY main PLL ready interrupt
  1221.   *            @arg RCC_IT_PLL2RDY Main PLL2 ready interrupt.(*)
  1222.   *            @arg RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.(*)
  1223.   * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
  1224.   */
  1225. #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
  1226.  
  1227. /** @brief Disable RCC interrupt.
  1228.   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
  1229.   *          This parameter can be any combination of the following values:
  1230.   *            @arg RCC_IT_LSIRDY LSI ready interrupt
  1231.   *            @arg RCC_IT_LSERDY LSE ready interrupt
  1232.   *            @arg RCC_IT_HSIRDY HSI ready interrupt
  1233.   *            @arg RCC_IT_HSERDY HSE ready interrupt
  1234.   *            @arg RCC_IT_PLLRDY main PLL ready interrupt
  1235.   *            @arg RCC_IT_PLL2RDY Main PLL2 ready interrupt.(*)
  1236.   *            @arg RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.(*)
  1237.   * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
  1238.   */
  1239. #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
  1240.  
  1241. /** @brief Clear the RCC's interrupt pending bits.
  1242.   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
  1243.   *          This parameter can be any combination of the following values:
  1244.   *            @arg RCC_IT_LSIRDY LSI ready interrupt.
  1245.   *            @arg RCC_IT_LSERDY LSE ready interrupt.
  1246.   *            @arg RCC_IT_HSIRDY HSI ready interrupt.
  1247.   *            @arg RCC_IT_HSERDY HSE ready interrupt.
  1248.   *            @arg RCC_IT_PLLRDY Main PLL ready interrupt.
  1249.   *            @arg RCC_IT_PLL2RDY Main PLL2 ready interrupt.(*)
  1250.   *            @arg RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.(*)
  1251.   *            @arg RCC_IT_CSS Clock Security System interrupt
  1252.   * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
  1253.   */
  1254. #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
  1255.  
  1256. /** @brief Check the RCC's interrupt has occurred or not.
  1257.   * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
  1258.   *          This parameter can be one of the following values:
  1259.   *            @arg RCC_IT_LSIRDY LSI ready interrupt.
  1260.   *            @arg RCC_IT_LSERDY LSE ready interrupt.
  1261.   *            @arg RCC_IT_HSIRDY HSI ready interrupt.
  1262.   *            @arg RCC_IT_HSERDY HSE ready interrupt.
  1263.   *            @arg RCC_IT_PLLRDY Main PLL ready interrupt.
  1264.   *            @arg RCC_IT_PLL2RDY Main PLL2 ready interrupt.(*)
  1265.   *            @arg RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.(*)
  1266.   *            @arg RCC_IT_CSS Clock Security System interrupt
  1267.   * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
  1268.   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
  1269.   */
  1270. #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
  1271.  
  1272. /** @brief Set RMVF bit to clear the reset flags.
  1273.   *         The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
  1274.   *         RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
  1275.   */
  1276. #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
  1277.  
  1278. /** @brief  Check RCC flag is set or not.
  1279.   * @param  __FLAG__ specifies the flag to check.
  1280.   *          This parameter can be one of the following values:
  1281.   *            @arg RCC_FLAG_HSIRDY HSI oscillator clock ready.
  1282.   *            @arg RCC_FLAG_HSERDY HSE oscillator clock ready.
  1283.   *            @arg RCC_FLAG_PLLRDY Main PLL clock ready.
  1284.   *            @arg RCC_FLAG_PLL2RDY Main PLL2 clock ready.(*)
  1285.   *            @arg RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.(*)
  1286.   *            @arg RCC_FLAG_LSERDY LSE oscillator clock ready.
  1287.   *            @arg RCC_FLAG_LSIRDY LSI oscillator clock ready.
  1288.   *            @arg RCC_FLAG_PINRST Pin reset.
  1289.   *            @arg RCC_FLAG_PORRST POR/PDR reset.
  1290.   *            @arg RCC_FLAG_SFTRST Software reset.
  1291.   *            @arg RCC_FLAG_IWDGRST Independent Watchdog reset.
  1292.   *            @arg RCC_FLAG_WWDGRST Window Watchdog reset.
  1293.   *            @arg RCC_FLAG_LPWRRST Low Power reset.
  1294.   * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
  1295.   * @retval The new state of __FLAG__ (TRUE or FALSE).
  1296.   */
  1297. #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)?   RCC->CR   : \
  1298.                                       ((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \
  1299.                                                                              RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
  1300.  
  1301. /**
  1302.   * @}
  1303.   */
  1304.  
  1305. /**
  1306.   * @}
  1307.   */
  1308.  
  1309. /* Include RCC HAL Extension module */
  1310. #include "stm32f1xx_hal_rcc_ex.h"
  1311.  
  1312. /* Exported functions --------------------------------------------------------*/
  1313. /** @addtogroup RCC_Exported_Functions
  1314.   * @{
  1315.   */
  1316.  
  1317. /** @addtogroup RCC_Exported_Functions_Group1
  1318.   * @{
  1319.   */
  1320.  
  1321. /* Initialization and de-initialization functions  ******************************/
  1322. void              HAL_RCC_DeInit(void);
  1323. HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
  1324. HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency);
  1325.  
  1326. /**
  1327.   * @}
  1328.   */
  1329.  
  1330. /** @addtogroup RCC_Exported_Functions_Group2
  1331.   * @{
  1332.   */
  1333.  
  1334. /* Peripheral Control functions  ************************************************/
  1335. void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
  1336. void              HAL_RCC_EnableCSS(void);
  1337. void              HAL_RCC_DisableCSS(void);
  1338. uint32_t          HAL_RCC_GetSysClockFreq(void);
  1339. uint32_t          HAL_RCC_GetHCLKFreq(void);
  1340. uint32_t          HAL_RCC_GetPCLK1Freq(void);
  1341. uint32_t          HAL_RCC_GetPCLK2Freq(void);
  1342. void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
  1343. void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);
  1344.  
  1345. /* CSS NMI IRQ handler */
  1346. void              HAL_RCC_NMI_IRQHandler(void);
  1347.  
  1348. /* User Callbacks in non blocking mode (IT mode) */
  1349. void              HAL_RCC_CSSCallback(void);
  1350.  
  1351. /**
  1352.   * @}
  1353.   */
  1354.  
  1355. /**
  1356.   * @}
  1357.   */
  1358.  
  1359. /**
  1360.   * @}
  1361.   */
  1362.  
  1363. /**
  1364.   * @}
  1365.   */
  1366.  
  1367. #ifdef __cplusplus
  1368. }
  1369. #endif
  1370.  
  1371. #endif /* __STM32F1xx_HAL_RCC_H */
  1372.  
  1373. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1374.  
  1375.