Subversion Repositories DashDisplay

Rev

Rev 2 | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_rcc.h
  4.   * @author  MCD Application Team
  5.   * @version V1.0.4
  6.   * @date    29-April-2016
  7.   * @brief   Header file of RCC HAL module.
  8.   ******************************************************************************
  9.   * @attention
  10.   *
  11.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  12.   *
  13.   * Redistribution and use in source and binary forms, with or without modification,
  14.   * are permitted provided that the following conditions are met:
  15.   *   1. Redistributions of source code must retain the above copyright notice,
  16.   *      this list of conditions and the following disclaimer.
  17.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18.   *      this list of conditions and the following disclaimer in the documentation
  19.   *      and/or other materials provided with the distribution.
  20.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21.   *      may be used to endorse or promote products derived from this software
  22.   *      without specific prior written permission.
  23.   *
  24.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34.   *
  35.   ******************************************************************************
  36.   */
  37.  
  38. /* Define to prevent recursive inclusion -------------------------------------*/
  39. #ifndef __STM32F1xx_HAL_RCC_H
  40. #define __STM32F1xx_HAL_RCC_H
  41.  
  42. #ifdef __cplusplus
  43.  extern "C" {
  44. #endif
  45.  
  46. /* Includes ------------------------------------------------------------------*/
  47. #include "stm32f1xx_hal_def.h"
  48.  
  49. /** @addtogroup STM32F1xx_HAL_Driver
  50.   * @{
  51.   */
  52.  
  53. /** @addtogroup RCC
  54.   * @{
  55.   */
  56.  
  57. /** @addtogroup RCC_Private_Constants
  58.   * @{
  59.   */
  60.  
  61. /** @defgroup RCC_Timeout RCC Timeout
  62.   * @{
  63.   */
  64.  
  65. /* Disable Backup domain write protection state change timeout */
  66. #define RCC_DBP_TIMEOUT_VALUE  ((uint32_t)100)       /* 100 ms */
  67. /* LSE state change timeout */
  68. #define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
  69. #define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000)  /* 5 s    */
  70. #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
  71. #define HSI_TIMEOUT_VALUE         ((uint32_t)2)      /* 2 ms (minimum Tick + 1) */
  72. #define LSI_TIMEOUT_VALUE         ((uint32_t)2)      /* 2 ms (minimum Tick + 1) */
  73. #define PLL_TIMEOUT_VALUE         ((uint32_t)2)      /* 2 ms (minimum Tick + 1) */
  74. #define LSI_VALUE                 ((uint32_t)40000)  /* 40kHz */
  75. /**
  76.   * @}
  77.   */
  78.  
  79. /** @defgroup RCC_Register_Offset Register offsets
  80.   * @{
  81.   */
  82. #define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
  83. #define RCC_CR_OFFSET             0x00
  84. #define RCC_CFGR_OFFSET           0x04
  85. #define RCC_CIR_OFFSET            0x08
  86. #define RCC_BDCR_OFFSET           0x20
  87. #define RCC_CSR_OFFSET            0x24
  88.  
  89. /**
  90.   * @}
  91.   */
  92.  
  93. /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
  94.   * @brief RCC registers bit address in the alias region
  95.   * @{
  96.   */
  97. #define RCC_CR_OFFSET_BB          (RCC_OFFSET + RCC_CR_OFFSET)
  98. #define RCC_CFGR_OFFSET_BB        (RCC_OFFSET + RCC_CFGR_OFFSET)
  99. #define RCC_CIR_OFFSET_BB         (RCC_OFFSET + RCC_CIR_OFFSET)
  100. #define RCC_BDCR_OFFSET_BB        (RCC_OFFSET + RCC_BDCR_OFFSET)
  101. #define RCC_CSR_OFFSET_BB         (RCC_OFFSET + RCC_CSR_OFFSET)
  102.  
  103. /* --- CR Register ---*/
  104. /* Alias word address of HSION bit */
  105. #define RCC_HSION_BIT_NUMBER      POSITION_VAL(RCC_CR_HSION)
  106. #define RCC_CR_HSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4)))
  107. /* Alias word address of HSEON bit */
  108. #define RCC_HSEON_BIT_NUMBER      POSITION_VAL(RCC_CR_HSEON)
  109. #define RCC_CR_HSEON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4)))
  110. /* Alias word address of CSSON bit */
  111. #define RCC_CSSON_BIT_NUMBER      POSITION_VAL(RCC_CR_CSSON)
  112. #define RCC_CR_CSSON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4)))
  113. /* Alias word address of PLLON bit */
  114. #define RCC_PLLON_BIT_NUMBER      POSITION_VAL(RCC_CR_PLLON)
  115. #define RCC_CR_PLLON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4)))
  116.  
  117. /* --- CSR Register ---*/
  118. /* Alias word address of LSION bit */
  119. #define RCC_LSION_BIT_NUMBER      POSITION_VAL(RCC_CSR_LSION)
  120. #define RCC_CSR_LSION_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4)))
  121.  
  122. /* Alias word address of RMVF bit */
  123. #define RCC_RMVF_BIT_NUMBER       POSITION_VAL(RCC_CSR_RMVF)
  124. #define RCC_CSR_RMVF_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4)))
  125.  
  126. /* --- BDCR Registers ---*/
  127. /* Alias word address of LSEON bit */
  128. #define RCC_LSEON_BIT_NUMBER      POSITION_VAL(RCC_BDCR_LSEON)
  129. #define RCC_BDCR_LSEON_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4)))
  130.  
  131. /* Alias word address of LSEON bit */
  132. #define RCC_LSEBYP_BIT_NUMBER     POSITION_VAL(RCC_BDCR_LSEBYP)
  133. #define RCC_BDCR_LSEBYP_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4)))
  134.  
  135. /* Alias word address of RTCEN bit */
  136. #define RCC_RTCEN_BIT_NUMBER      POSITION_VAL(RCC_BDCR_RTCEN)
  137. #define RCC_BDCR_RTCEN_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4)))
  138.  
  139. /* Alias word address of BDRST bit */
  140. #define RCC_BDRST_BIT_NUMBER          POSITION_VAL(RCC_BDCR_BDRST)
  141. #define RCC_BDCR_BDRST_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_BDRST_BIT_NUMBER * 4)))
  142.  
  143. /**
  144.   * @}
  145.   */
  146.  
  147. /* CR register byte 2 (Bits[23:16]) base address */
  148. #define RCC_CR_BYTE2_ADDRESS          ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
  149.  
  150. /* CIR register byte 1 (Bits[15:8]) base address */
  151. #define RCC_CIR_BYTE1_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
  152.  
  153. /* CIR register byte 2 (Bits[23:16]) base address */
  154. #define RCC_CIR_BYTE2_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
  155.  
  156. /* Defines used for Flags */
  157. #define CR_REG_INDEX                     ((uint8_t)1)
  158. #define BDCR_REG_INDEX                   ((uint8_t)2)
  159. #define CSR_REG_INDEX                    ((uint8_t)3)
  160.  
  161. #define RCC_FLAG_MASK                    ((uint8_t)0x1F)
  162.  
  163. /**
  164.   * @}
  165.   */
  166.  
  167. /** @addtogroup RCC_Private_Macros
  168.   * @{
  169.   */
  170. /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
  171.   * @{
  172.   */
  173. #define __HAL_RCC_SYSCFG_CLK_DISABLE    __HAL_RCC_AFIO_CLK_DISABLE
  174. #define __HAL_RCC_SYSCFG_CLK_ENABLE     __HAL_RCC_AFIO_CLK_ENABLE
  175. #define __HAL_RCC_SYSCFG_FORCE_RESET    __HAL_RCC_AFIO_FORCE_RESET
  176. #define __HAL_RCC_SYSCFG_RELEASE_RESET  __HAL_RCC_AFIO_RELEASE_RESET
  177. /**
  178.   * @}
  179.   */
  180.  
  181. #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
  182.                                       ((__SOURCE__) == RCC_PLLSOURCE_HSE))
  183. #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
  184.                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
  185.                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
  186.                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
  187.                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
  188. #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
  189.                              ((__HSE__) == RCC_HSE_BYPASS))
  190. #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
  191.                              ((__LSE__) == RCC_LSE_BYPASS))
  192. #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
  193. #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
  194. #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
  195. #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
  196.                              ((__PLL__) == RCC_PLL_ON))
  197.  
  198. #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
  199.                                (((CLK) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
  200.                                (((CLK) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1)  || \
  201.                                (((CLK) & RCC_CLOCKTYPE_PCLK2)  == RCC_CLOCKTYPE_PCLK2))
  202. #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
  203.                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
  204.                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
  205. #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
  206.                                                 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
  207.                                                 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
  208. #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
  209.                                ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
  210.                                ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
  211.                                ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
  212.                                ((__HCLK__) == RCC_SYSCLK_DIV512))
  213. #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
  214.                                ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
  215.                                ((__PCLK__) == RCC_HCLK_DIV16))
  216. #define IS_RCC_MCO(__MCO__)  ((__MCO__) == RCC_MCO)
  217. #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
  218. #define IS_RCC_RTCCLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
  219.                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)  || \
  220.                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)  || \
  221.                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
  222.  
  223. /**
  224.   * @}
  225.   */
  226.  
  227. /* Exported types ------------------------------------------------------------*/
  228.  
  229. /** @defgroup RCC_Exported_Types RCC Exported Types
  230.   * @{
  231.   */
  232.  
  233. /**
  234.   * @brief  RCC PLL configuration structure definition  
  235.   */
  236. typedef struct
  237. {
  238.   uint32_t PLLState;      /*!< PLLState: The new state of the PLL.
  239.                               This parameter can be a value of @ref RCC_PLL_Config */
  240.  
  241.   uint32_t PLLSource;     /*!< PLLSource: PLL entry clock source.
  242.                               This parameter must be a value of @ref RCC_PLL_Clock_Source */          
  243.  
  244.   uint32_t PLLMUL;        /*!< PLLMUL: Multiplication factor for PLL VCO input clock
  245.                               This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
  246. } RCC_PLLInitTypeDef;
  247.    
  248. /**
  249.   * @brief  RCC System, AHB and APB busses clock configuration structure definition  
  250.   */
  251. typedef struct
  252. {
  253.   uint32_t ClockType;             /*!< The clock to be configured.
  254.                                        This parameter can be a value of @ref RCC_System_Clock_Type */
  255.  
  256.   uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
  257.                                        This parameter can be a value of @ref RCC_System_Clock_Source */
  258.  
  259.   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
  260.                                        This parameter can be a value of @ref RCC_AHB_Clock_Source */
  261.  
  262.   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
  263.                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
  264.  
  265.   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
  266.                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
  267. } RCC_ClkInitTypeDef;
  268.  
  269. /**
  270.   * @}
  271.   */
  272.  
  273. /* Exported constants --------------------------------------------------------*/
  274. /** @defgroup RCC_Exported_Constants RCC Exported Constants
  275.   * @{
  276.   */
  277.  
  278. /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
  279.   * @{
  280.   */
  281.  
  282. #define RCC_PLLSOURCE_HSI_DIV2      ((uint32_t)0x00000000)     /*!< HSI clock divided by 2 selected as PLL entry clock source */
  283. #define RCC_PLLSOURCE_HSE           RCC_CFGR_PLLSRC            /*!< HSE clock selected as PLL entry clock source */
  284.  
  285. /**
  286.   * @}
  287.   */
  288.  
  289. /** @defgroup RCC_Oscillator_Type Oscillator Type
  290.   * @{
  291.   */
  292. #define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000)
  293. #define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001)
  294. #define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002)
  295. #define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004)
  296. #define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008)
  297. /**
  298.   * @}
  299.   */
  300.  
  301. /** @defgroup RCC_HSE_Config HSE Config
  302.   * @{
  303.   */
  304. #define RCC_HSE_OFF                      ((uint32_t)0x00000000)                     /*!< HSE clock deactivation */
  305. #define RCC_HSE_ON                       RCC_CR_HSEON                               /*!< HSE clock activation */
  306. #define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
  307. /**
  308.   * @}
  309.   */
  310.  
  311. /** @defgroup RCC_LSE_Config LSE Config
  312.   * @{
  313.   */
  314. #define RCC_LSE_OFF                      ((uint32_t)0x00000000)                       /*!< LSE clock deactivation */
  315. #define RCC_LSE_ON                       RCC_BDCR_LSEON                                /*!< LSE clock activation */
  316. #define RCC_LSE_BYPASS                   ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
  317.  
  318. /**
  319.   * @}
  320.   */
  321.  
  322. /** @defgroup RCC_HSI_Config HSI Config
  323.   * @{
  324.   */
  325. #define RCC_HSI_OFF                      ((uint32_t)0x00000000)           /*!< HSI clock deactivation */
  326. #define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
  327.  
  328. #define RCC_HSICALIBRATION_DEFAULT       ((uint32_t)0x10)         /* Default HSI calibration trimming value */
  329.  
  330. /**
  331.   * @}
  332.   */
  333.  
  334. /** @defgroup RCC_LSI_Config LSI Config
  335.   * @{
  336.   */
  337. #define RCC_LSI_OFF                      ((uint32_t)0x00000000)   /*!< LSI clock deactivation */
  338. #define RCC_LSI_ON                       RCC_CSR_LSION            /*!< LSI clock activation */
  339.  
  340. /**
  341.   * @}
  342.   */
  343.  
  344. /** @defgroup RCC_PLL_Config PLL Config
  345.   * @{
  346.   */
  347. #define RCC_PLL_NONE                      ((uint32_t)0x00000000)  /*!< PLL is not configured */
  348. #define RCC_PLL_OFF                       ((uint32_t)0x00000001)  /*!< PLL deactivation */
  349. #define RCC_PLL_ON                        ((uint32_t)0x00000002)  /*!< PLL activation */
  350.  
  351. /**
  352.   * @}
  353.   */
  354.  
  355. /** @defgroup RCC_System_Clock_Type System Clock Type
  356.   * @{
  357.   */
  358. #define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001) /*!< SYSCLK to configure */
  359. #define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002) /*!< HCLK to configure */
  360. #define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004) /*!< PCLK1 to configure */
  361. #define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008) /*!< PCLK2 to configure */
  362.  
  363. /**
  364.   * @}
  365.   */
  366.  
  367. /** @defgroup RCC_System_Clock_Source System Clock Source
  368.   * @{
  369.   */
  370. #define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
  371. #define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
  372. #define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
  373.  
  374. /**
  375.   * @}
  376.   */
  377.  
  378. /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
  379.   * @{
  380.   */
  381. #define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI            /*!< HSI used as system clock */
  382. #define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE            /*!< HSE used as system clock */
  383. #define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL            /*!< PLL used as system clock */
  384.  
  385. /**
  386.   * @}
  387.   */
  388.  
  389. /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
  390.   * @{
  391.   */
  392. #define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
  393. #define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
  394. #define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
  395. #define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
  396. #define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
  397. #define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
  398. #define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
  399. #define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
  400. #define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
  401.  
  402. /**
  403.   * @}
  404.   */
  405.  
  406. /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
  407.   * @{
  408.   */
  409. #define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
  410. #define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
  411. #define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
  412. #define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
  413. #define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
  414.  
  415. /**
  416.   * @}
  417.   */
  418.  
  419. /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
  420.   * @{
  421.   */
  422. #define RCC_RTCCLKSOURCE_NO_CLK          ((uint32_t)0x00000000)                 /*!< No clock */
  423. #define RCC_RTCCLKSOURCE_LSE             RCC_BDCR_RTCSEL_LSE                  /*!< LSE oscillator clock used as RTC clock */
  424. #define RCC_RTCCLKSOURCE_LSI             RCC_BDCR_RTCSEL_LSI                  /*!< LSI oscillator clock used as RTC clock */
  425. #define RCC_RTCCLKSOURCE_HSE_DIV128      RCC_BDCR_RTCSEL_HSE                    /*!< HSE oscillator clock divided by 128 used as RTC clock */
  426. /**
  427.   * @}
  428.   */
  429.  
  430.  
  431. /** @defgroup RCC_MCO_Index MCO Index
  432.   * @{
  433.   */
  434. #define RCC_MCO1                         ((uint32_t)0x00000000)
  435. #define RCC_MCO                          RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
  436.  
  437. /**
  438.   * @}
  439.   */
  440.  
  441. /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
  442.   * @{
  443.   */
  444. #define RCC_MCODIV_1                    ((uint32_t)0x00000000)
  445.  
  446. /**
  447.   * @}
  448.   */
  449.  
  450. /** @defgroup RCC_Interrupt Interrupts
  451.   * @{
  452.   */
  453. #define RCC_IT_LSIRDY                    ((uint8_t)RCC_CIR_LSIRDYF)   /*!< LSI Ready Interrupt flag */
  454. #define RCC_IT_LSERDY                    ((uint8_t)RCC_CIR_LSERDYF)   /*!< LSE Ready Interrupt flag */
  455. #define RCC_IT_HSIRDY                    ((uint8_t)RCC_CIR_HSIRDYF)   /*!< HSI Ready Interrupt flag */
  456. #define RCC_IT_HSERDY                    ((uint8_t)RCC_CIR_HSERDYF)   /*!< HSE Ready Interrupt flag */
  457. #define RCC_IT_PLLRDY                    ((uint8_t)RCC_CIR_PLLRDYF)   /*!< PLL Ready Interrupt flag */
  458. #define RCC_IT_CSS                       ((uint8_t)RCC_CIR_CSSF)      /*!< Clock Security System Interrupt flag */
  459. /**
  460.   * @}
  461.   */
  462.  
  463. /** @defgroup RCC_Flag Flags
  464.   *        Elements values convention: XXXYYYYYb
  465.   *           - YYYYY  : Flag position in the register
  466.   *           - XXX  : Register index
  467.   *                 - 001: CR register
  468.   *                 - 010: BDCR register
  469.   *                 - 011: CSR register
  470.   * @{
  471.   */
  472. /* Flags in the CR register */
  473. #define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
  474. #define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
  475. #define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
  476.  
  477. /* Flags in the CSR register */
  478. #define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY)))   /*!< Internal Low Speed oscillator Ready */
  479. #define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF)))  /*!< PIN reset flag */
  480. #define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF)))  /*!< POR/PDR reset flag */
  481. #define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF)))  /*!< Software Reset flag */
  482. #define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
  483. #define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
  484. #define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
  485.  
  486. /* Flags in the BDCR register */
  487. #define RCC_FLAG_LSERDY                  ((uint8_t)((BDCR_REG_INDEX << 5) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
  488.  
  489. /**
  490.   * @}
  491.   */
  492.  
  493. /**
  494.   * @}
  495.   */
  496.  
  497. /* Exported macro ------------------------------------------------------------*/
  498.  
  499. /** @defgroup RCC_Exported_Macros RCC Exported Macros
  500.   * @{
  501.   */
  502.  
  503. /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
  504.   * @brief  Enable or disable the AHB1 peripheral clock.
  505.   * @note   After reset, the peripheral clock (used for registers read/write access)
  506.   *         is disabled and the application software has to enable this clock before
  507.   *         using it.  
  508.   * @{
  509.   */
  510. #define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
  511.                                         __IO uint32_t tmpreg; \
  512.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
  513.                                         /* Delay after an RCC peripheral clock enabling */\
  514.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
  515.                                         UNUSED(tmpreg); \
  516.                                       } while(0)
  517.  
  518. #define __HAL_RCC_SRAM_CLK_ENABLE()   do { \
  519.                                         __IO uint32_t tmpreg; \
  520.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
  521.                                         /* Delay after an RCC peripheral clock enabling */\
  522.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
  523.                                         UNUSED(tmpreg); \
  524.                                       } while(0)
  525.  
  526. #define __HAL_RCC_FLITF_CLK_ENABLE()   do { \
  527.                                         __IO uint32_t tmpreg; \
  528.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
  529.                                         /* Delay after an RCC peripheral clock enabling */\
  530.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
  531.                                         UNUSED(tmpreg); \
  532.                                       } while(0)
  533.  
  534. #define __HAL_RCC_CRC_CLK_ENABLE()   do { \
  535.                                         __IO uint32_t tmpreg; \
  536.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
  537.                                         /* Delay after an RCC peripheral clock enabling */\
  538.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
  539.                                         UNUSED(tmpreg); \
  540.                                       } while(0)
  541.  
  542. #define __HAL_RCC_DMA1_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
  543. #define __HAL_RCC_SRAM_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
  544. #define __HAL_RCC_FLITF_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
  545. #define __HAL_RCC_CRC_CLK_DISABLE()       (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
  546.  
  547. /**
  548.   * @}
  549.   */
  550.  
  551. /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
  552.   * @brief  Get the enable or disable status of the AHB peripheral clock.
  553.   * @note   After reset, the peripheral clock (used for registers read/write access)
  554.   *         is disabled and the application software has to enable this clock before
  555.   *         using it.
  556.   * @{
  557.   */
  558.  
  559. #define __HAL_RCC_DMA1_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
  560. #define __HAL_RCC_DMA1_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
  561. #define __HAL_RCC_SRAM_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
  562. #define __HAL_RCC_SRAM_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
  563. #define __HAL_RCC_FLITF_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
  564. #define __HAL_RCC_FLITF_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
  565. #define __HAL_RCC_CRC_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
  566. #define __HAL_RCC_CRC_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
  567.  
  568. /**
  569.   * @}
  570.   */
  571.  
  572. /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
  573.   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
  574.   * @note   After reset, the peripheral clock (used for registers read/write access)
  575.   *         is disabled and the application software has to enable this clock before
  576.   *         using it.
  577.   * @{  
  578.   */
  579. #define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
  580.                                         __IO uint32_t tmpreg; \
  581.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
  582.                                         /* Delay after an RCC peripheral clock enabling */\
  583.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
  584.                                         UNUSED(tmpreg); \
  585.                                       } while(0)
  586.  
  587. #define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
  588.                                         __IO uint32_t tmpreg; \
  589.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
  590.                                         /* Delay after an RCC peripheral clock enabling */\
  591.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
  592.                                         UNUSED(tmpreg); \
  593.                                       } while(0)
  594.  
  595. #define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
  596.                                         __IO uint32_t tmpreg; \
  597.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
  598.                                         /* Delay after an RCC peripheral clock enabling */\
  599.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
  600.                                         UNUSED(tmpreg); \
  601.                                       } while(0)
  602.  
  603. #define __HAL_RCC_USART2_CLK_ENABLE()   do { \
  604.                                         __IO uint32_t tmpreg; \
  605.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
  606.                                         /* Delay after an RCC peripheral clock enabling */\
  607.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
  608.                                         UNUSED(tmpreg); \
  609.                                       } while(0)
  610.  
  611. #define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
  612.                                         __IO uint32_t tmpreg; \
  613.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
  614.                                         /* Delay after an RCC peripheral clock enabling */\
  615.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
  616.                                         UNUSED(tmpreg); \
  617.                                       } while(0)
  618.  
  619. #define __HAL_RCC_BKP_CLK_ENABLE()   do { \
  620.                                         __IO uint32_t tmpreg; \
  621.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
  622.                                         /* Delay after an RCC peripheral clock enabling */\
  623.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
  624.                                         UNUSED(tmpreg); \
  625.                                       } while(0)
  626.  
  627. #define __HAL_RCC_PWR_CLK_ENABLE()   do { \
  628.                                         __IO uint32_t tmpreg; \
  629.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
  630.                                         /* Delay after an RCC peripheral clock enabling */\
  631.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
  632.                                         UNUSED(tmpreg); \
  633.                                       } while(0)
  634.  
  635. #define __HAL_RCC_TIM2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
  636. #define __HAL_RCC_TIM3_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
  637. #define __HAL_RCC_WWDG_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
  638. #define __HAL_RCC_USART2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
  639. #define __HAL_RCC_I2C1_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
  640.  
  641. #define __HAL_RCC_BKP_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
  642. #define __HAL_RCC_PWR_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
  643.  
  644. /**
  645.   * @}
  646.   */
  647.  
  648. /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
  649.   * @brief  Get the enable or disable status of the APB1 peripheral clock.
  650.   * @note   After reset, the peripheral clock (used for registers read/write access)
  651.   *         is disabled and the application software has to enable this clock before
  652.   *         using it.
  653.   * @{
  654.   */
  655.  
  656. #define __HAL_RCC_TIM2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
  657. #define __HAL_RCC_TIM2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
  658. #define __HAL_RCC_TIM3_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
  659. #define __HAL_RCC_TIM3_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
  660. #define __HAL_RCC_WWDG_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
  661. #define __HAL_RCC_WWDG_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
  662. #define __HAL_RCC_USART2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
  663. #define __HAL_RCC_USART2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
  664. #define __HAL_RCC_I2C1_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
  665. #define __HAL_RCC_I2C1_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
  666. #define __HAL_RCC_BKP_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
  667. #define __HAL_RCC_BKP_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
  668. #define __HAL_RCC_PWR_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
  669. #define __HAL_RCC_PWR_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
  670.  
  671. /**
  672.   * @}
  673.   */
  674.  
  675. /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
  676.   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
  677.   * @note   After reset, the peripheral clock (used for registers read/write access)
  678.   *         is disabled and the application software has to enable this clock before
  679.   *         using it.
  680.   * @{  
  681.   */
  682. #define __HAL_RCC_AFIO_CLK_ENABLE()   do { \
  683.                                         __IO uint32_t tmpreg; \
  684.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
  685.                                         /* Delay after an RCC peripheral clock enabling */\
  686.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
  687.                                         UNUSED(tmpreg); \
  688.                                       } while(0)
  689.  
  690. #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
  691.                                         __IO uint32_t tmpreg; \
  692.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
  693.                                         /* Delay after an RCC peripheral clock enabling */\
  694.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
  695.                                         UNUSED(tmpreg); \
  696.                                       } while(0)
  697.  
  698. #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
  699.                                         __IO uint32_t tmpreg; \
  700.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
  701.                                         /* Delay after an RCC peripheral clock enabling */\
  702.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
  703.                                         UNUSED(tmpreg); \
  704.                                       } while(0)
  705.  
  706. #define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
  707.                                         __IO uint32_t tmpreg; \
  708.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
  709.                                         /* Delay after an RCC peripheral clock enabling */\
  710.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
  711.                                         UNUSED(tmpreg); \
  712.                                       } while(0)
  713.  
  714. #define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
  715.                                         __IO uint32_t tmpreg; \
  716.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
  717.                                         /* Delay after an RCC peripheral clock enabling */\
  718.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
  719.                                         UNUSED(tmpreg); \
  720.                                       } while(0)
  721.  
  722. #define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
  723.                                         __IO uint32_t tmpreg; \
  724.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
  725.                                         /* Delay after an RCC peripheral clock enabling */\
  726.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
  727.                                         UNUSED(tmpreg); \
  728.                                       } while(0)
  729.  
  730. #define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
  731.                                         __IO uint32_t tmpreg; \
  732.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
  733.                                         /* Delay after an RCC peripheral clock enabling */\
  734.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
  735.                                         UNUSED(tmpreg); \
  736.                                       } while(0)
  737.  
  738. #define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
  739.                                         __IO uint32_t tmpreg; \
  740.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
  741.                                         /* Delay after an RCC peripheral clock enabling */\
  742.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
  743.                                         UNUSED(tmpreg); \
  744.                                       } while(0)
  745.  
  746. #define __HAL_RCC_USART1_CLK_ENABLE()   do { \
  747.                                         __IO uint32_t tmpreg; \
  748.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
  749.                                         /* Delay after an RCC peripheral clock enabling */\
  750.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
  751.                                         UNUSED(tmpreg); \
  752.                                       } while(0)
  753.  
  754. #define __HAL_RCC_AFIO_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
  755. #define __HAL_RCC_GPIOA_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
  756. #define __HAL_RCC_GPIOB_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
  757. #define __HAL_RCC_GPIOC_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
  758. #define __HAL_RCC_GPIOD_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
  759. #define __HAL_RCC_ADC1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
  760.  
  761. #define __HAL_RCC_TIM1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
  762. #define __HAL_RCC_SPI1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
  763. #define __HAL_RCC_USART1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
  764.  
  765. /**
  766.   * @}
  767.   */
  768.  
  769. /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
  770.   * @brief  Get the enable or disable status of the APB2 peripheral clock.
  771.   * @note   After reset, the peripheral clock (used for registers read/write access)
  772.   *         is disabled and the application software has to enable this clock before
  773.   *         using it.
  774.   * @{
  775.   */
  776.  
  777. #define __HAL_RCC_AFIO_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
  778. #define __HAL_RCC_AFIO_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
  779. #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
  780. #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
  781. #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
  782. #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
  783. #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
  784. #define __HAL_RCC_GPIOC_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
  785. #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
  786. #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
  787. #define __HAL_RCC_ADC1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
  788. #define __HAL_RCC_ADC1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
  789. #define __HAL_RCC_TIM1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
  790. #define __HAL_RCC_TIM1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
  791. #define __HAL_RCC_SPI1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
  792. #define __HAL_RCC_SPI1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
  793. #define __HAL_RCC_USART1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
  794. #define __HAL_RCC_USART1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
  795.  
  796. /**
  797.   * @}
  798.   */
  799.  
  800. /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
  801.   * @brief  Force or release APB1 peripheral reset.
  802.   * @{  
  803.   */
  804. #define __HAL_RCC_APB1_FORCE_RESET()       (RCC->APB2RSTR = 0xFFFFFFFFU)  
  805. #define __HAL_RCC_TIM2_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
  806. #define __HAL_RCC_TIM3_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
  807. #define __HAL_RCC_WWDG_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
  808. #define __HAL_RCC_USART2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
  809. #define __HAL_RCC_I2C1_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
  810.  
  811. #define __HAL_RCC_BKP_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
  812. #define __HAL_RCC_PWR_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
  813.  
  814. #define __HAL_RCC_APB1_RELEASE_RESET()      (RCC->APB1RSTR = 0x00)  
  815. #define __HAL_RCC_TIM2_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
  816. #define __HAL_RCC_TIM3_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
  817. #define __HAL_RCC_WWDG_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
  818. #define __HAL_RCC_USART2_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
  819. #define __HAL_RCC_I2C1_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
  820.  
  821. #define __HAL_RCC_BKP_RELEASE_RESET()        (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
  822. #define __HAL_RCC_PWR_RELEASE_RESET()        (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
  823.  
  824. /**
  825.   * @}
  826.   */
  827.  
  828. /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
  829.   * @brief  Force or release APB2 peripheral reset.
  830.   * @{  
  831.   */
  832. #define __HAL_RCC_APB2_FORCE_RESET()       (RCC->APB2RSTR = 0xFFFFFFFFU)  
  833. #define __HAL_RCC_AFIO_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
  834. #define __HAL_RCC_GPIOA_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
  835. #define __HAL_RCC_GPIOB_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
  836. #define __HAL_RCC_GPIOC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
  837. #define __HAL_RCC_GPIOD_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
  838. #define __HAL_RCC_ADC1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
  839.  
  840. #define __HAL_RCC_TIM1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
  841. #define __HAL_RCC_SPI1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
  842. #define __HAL_RCC_USART1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
  843.  
  844. #define __HAL_RCC_APB2_RELEASE_RESET()      (RCC->APB2RSTR = 0x00)  
  845. #define __HAL_RCC_AFIO_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
  846. #define __HAL_RCC_GPIOA_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
  847. #define __HAL_RCC_GPIOB_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
  848. #define __HAL_RCC_GPIOC_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
  849. #define __HAL_RCC_GPIOD_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
  850. #define __HAL_RCC_ADC1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
  851.  
  852. #define __HAL_RCC_TIM1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
  853. #define __HAL_RCC_SPI1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
  854. #define __HAL_RCC_USART1_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
  855.  
  856. /**
  857.   * @}
  858.   */
  859.  
  860. /** @defgroup RCC_HSI_Configuration HSI Configuration
  861.   * @{  
  862.   */
  863.  
  864. /** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
  865.   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
  866.   * @note   HSI can not be stopped if it is used as system clock source. In this case,
  867.   *         you have to select another source of the system clock then stop the HSI.  
  868.   * @note   After enabling the HSI, the application software should wait on HSIRDY
  869.   *         flag to be set indicating that HSI clock is stable and can be used as
  870.   *         system clock source.  
  871.   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
  872.   *         clock cycles.  
  873.   */
  874. #define __HAL_RCC_HSI_ENABLE()  (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
  875. #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
  876.  
  877. /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
  878.   * @note   The calibration is used to compensate for the variations in voltage
  879.   *         and temperature that influence the frequency of the internal HSI RC.
  880.   * @param  _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
  881.   *         (default is RCC_HSICALIBRATION_DEFAULT).
  882.   *         This parameter must be a number between 0 and 0x1F.
  883.   */  
  884. #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
  885.           (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
  886.  
  887. /**
  888.   * @}
  889.   */
  890.  
  891. /** @defgroup RCC_LSI_Configuration  LSI Configuration
  892.   * @{  
  893.   */
  894.  
  895. /** @brief Macro to enable the Internal Low Speed oscillator (LSI).
  896.   * @note   After enabling the LSI, the application software should wait on
  897.   *         LSIRDY flag to be set indicating that LSI clock is stable and can
  898.   *         be used to clock the IWDG and/or the RTC.
  899.   */
  900. #define __HAL_RCC_LSI_ENABLE()  (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
  901.  
  902. /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
  903.   * @note   LSI can not be disabled if the IWDG is running.  
  904.   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
  905.   *         clock cycles.
  906.   */
  907. #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
  908.  
  909. /**
  910.   * @}
  911.   */
  912.  
  913. /** @defgroup RCC_HSE_Configuration HSE Configuration
  914.   * @{  
  915.   */
  916.  
  917. /**
  918.   * @brief  Macro to configure the External High Speed oscillator (HSE).
  919.   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
  920.   *         supported by this macro. User should request a transition to HSE Off
  921.   *         first and then HSE On or HSE Bypass.
  922.   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
  923.   *         software should wait on HSERDY flag to be set indicating that HSE clock
  924.   *         is stable and can be used to clock the PLL and/or system clock.
  925.   * @note   HSE state can not be changed if it is used directly or through the
  926.   *         PLL as system clock. In this case, you have to select another source
  927.   *         of the system clock then change the HSE state (ex. disable it).
  928.   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
  929.   * @note   This function reset the CSSON bit, so if the clock security system(CSS)
  930.   *         was previously enabled you have to enable it again after calling this
  931.   *         function.
  932.   * @param  __STATE__ specifies the new state of the HSE.
  933.   *          This parameter can be one of the following values:
  934.   *            @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
  935.   *                              6 HSE oscillator clock cycles.
  936.   *            @arg @ref RCC_HSE_ON turn ON the HSE oscillator
  937.   *            @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
  938.   */
  939. #define __HAL_RCC_HSE_CONFIG(__STATE__)                                     \
  940.                     do{                                                     \
  941.                       if ((__STATE__) == RCC_HSE_ON)                        \
  942.                       {                                                     \
  943.                         SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
  944.                       }                                                     \
  945.                       else if ((__STATE__) == RCC_HSE_OFF)                  \
  946.                       {                                                     \
  947.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
  948.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
  949.                       }                                                     \
  950.                       else if ((__STATE__) == RCC_HSE_BYPASS)               \
  951.                       {                                                     \
  952.                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);                    \
  953.                         SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
  954.                       }                                                     \
  955.                       else                                                  \
  956.                       {                                                     \
  957.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
  958.                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
  959.                       }                                                     \
  960.                     }while(0)
  961.  
  962. /**
  963.   * @}
  964.   */
  965.  
  966. /** @defgroup RCC_LSE_Configuration LSE Configuration
  967.   * @{  
  968.   */
  969.  
  970. /**
  971.   * @brief  Macro to configure the External Low Speed oscillator (LSE).
  972.   * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
  973.   * @note   As the LSE is in the Backup domain and write access is denied to
  974.   *         this domain after reset, you have to enable write access using
  975.   *         @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
  976.   *         (to be done once after reset).  
  977.   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
  978.   *         software should wait on LSERDY flag to be set indicating that LSE clock
  979.   *         is stable and can be used to clock the RTC.
  980.   * @param  __STATE__ specifies the new state of the LSE.
  981.   *         This parameter can be one of the following values:
  982.   *            @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
  983.   *                              6 LSE oscillator clock cycles.
  984.   *            @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
  985.   *            @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
  986.   */
  987. #define __HAL_RCC_LSE_CONFIG(__STATE__)                                     \
  988.                     do{                                                     \
  989.                       if ((__STATE__) == RCC_LSE_ON)                        \
  990.                       {                                                     \
  991.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
  992.                       }                                                     \
  993.                       else if ((__STATE__) == RCC_LSE_OFF)                  \
  994.                       {                                                     \
  995.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
  996.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
  997.                       }                                                     \
  998.                       else if ((__STATE__) == RCC_LSE_BYPASS)               \
  999.                       {                                                     \
  1000.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                  \
  1001.                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
  1002.                       }                                                     \
  1003.                       else                                                  \
  1004.                       {                                                     \
  1005.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
  1006.                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
  1007.                       }                                                     \
  1008.                     }while(0)
  1009.  
  1010. /**
  1011.   * @}
  1012.   */
  1013.  
  1014. /** @defgroup RCC_PLL_Configuration PLL Configuration
  1015.   * @{  
  1016.   */
  1017.  
  1018. /** @brief Macro to enable the main PLL.
  1019.   * @note   After enabling the main PLL, the application software should wait on
  1020.   *         PLLRDY flag to be set indicating that PLL clock is stable and can
  1021.   *         be used as system clock source.
  1022.   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
  1023.   */
  1024. #define __HAL_RCC_PLL_ENABLE()          (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
  1025.  
  1026. /** @brief Macro to disable the main PLL.
  1027.   * @note   The main PLL can not be disabled if it is used as system clock source
  1028.   */
  1029. #define __HAL_RCC_PLL_DISABLE()         (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
  1030.  
  1031. /** @brief Macro to configure the main PLL clock source and multiplication factors.
  1032.   * @note   This function must be used only when the main PLL is disabled.
  1033.   *  
  1034.   * @param  __RCC_PLLSOURCE__ specifies the PLL entry clock source.
  1035.   *          This parameter can be one of the following values:
  1036.   *            @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
  1037.   *            @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
  1038.   * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
  1039.   *          This parameter can be one of the following values:
  1040.   *             @arg @ref RCC_PLL_MUL4   PLLVCO = PLL clock entry x 4
  1041.   *             @arg @ref RCC_PLL_MUL6   PLLVCO = PLL clock entry x 6
  1042.   @if STM32F105xC
  1043.   *             @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
  1044.   @elseif STM32F107xC
  1045.   *             @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
  1046.   @else
  1047.   *             @arg @ref RCC_PLL_MUL2   PLLVCO = PLL clock entry x 2
  1048.   *             @arg @ref RCC_PLL_MUL3   PLLVCO = PLL clock entry x 3
  1049.   *             @arg @ref RCC_PLL_MUL10  PLLVCO = PLL clock entry x 10
  1050.   *             @arg @ref RCC_PLL_MUL11  PLLVCO = PLL clock entry x 11
  1051.   *             @arg @ref RCC_PLL_MUL12  PLLVCO = PLL clock entry x 12
  1052.   *             @arg @ref RCC_PLL_MUL13  PLLVCO = PLL clock entry x 13
  1053.   *             @arg @ref RCC_PLL_MUL14  PLLVCO = PLL clock entry x 14
  1054.   *             @arg @ref RCC_PLL_MUL15  PLLVCO = PLL clock entry x 15
  1055.   *             @arg @ref RCC_PLL_MUL16  PLLVCO = PLL clock entry x 16
  1056.   @endif
  1057.   *             @arg @ref RCC_PLL_MUL8   PLLVCO = PLL clock entry x 8
  1058.   *             @arg @ref RCC_PLL_MUL9   PLLVCO = PLL clock entry x 9
  1059.   *  
  1060.   */
  1061. #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
  1062.           MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
  1063.  
  1064. /** @brief  Get oscillator clock selected as PLL input clock
  1065.   * @retval The clock source used for PLL entry. The returned value can be one
  1066.   *         of the following:
  1067.   *             @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
  1068.   *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
  1069.   */
  1070. #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
  1071.  
  1072. /**
  1073.   * @}
  1074.   */
  1075.  
  1076. /** @defgroup RCC_Get_Clock_source Get Clock source
  1077.   * @{  
  1078.   */
  1079.  
  1080. /**
  1081.   * @brief  Macro to configure the system clock source.
  1082.   * @param  __SYSCLKSOURCE__ specifies the system clock source.
  1083.   *          This parameter can be one of the following values:
  1084.   *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
  1085.   *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
  1086.   *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
  1087.   */
  1088. #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
  1089.                   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
  1090.  
  1091. /** @brief  Macro to get the clock source used as system clock.
  1092.   * @retval The clock source used as system clock. The returned value can be one
  1093.   *         of the following:
  1094.   *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
  1095.   *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
  1096.   *             @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
  1097.   */
  1098. #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
  1099.  
  1100. /**
  1101.   * @}
  1102.   */
  1103.  
  1104. /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
  1105.   * @{  
  1106.   */
  1107.  
  1108. #if   defined(RCC_CFGR_MCO_3)
  1109. /** @brief  Macro to configure the MCO clock.
  1110.   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
  1111.   *         This parameter can be one of the following values:
  1112.   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK      No clock selected as MCO clock
  1113.   *            @arg @ref RCC_MCO1SOURCE_SYSCLK       System clock (SYSCLK) selected as MCO clock
  1114.   *            @arg @ref RCC_MCO1SOURCE_HSI          HSI selected as MCO clock
  1115.   *            @arg @ref RCC_MCO1SOURCE_HSE          HSE selected as MCO clock
  1116.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock divided by 2 selected as MCO clock
  1117.   *            @arg @ref RCC_MCO1SOURCE_PLL2CLK      PLL2 clock selected by 2 selected as MCO clock
  1118.   *            @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
  1119.   *            @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1  external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
  1120.   *            @arg @ref RCC_MCO1SOURCE_PLL3CLK      PLL3 clock selected (for Ethernet) as MCO clock
  1121.   * @param  __MCODIV__ specifies the MCO clock prescaler.
  1122.   *         This parameter can be one of the following values:
  1123.   *            @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
  1124.   */
  1125. #else
  1126. /** @brief  Macro to configure the MCO clock.
  1127.   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
  1128.   *         This parameter can be one of the following values:
  1129.   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
  1130.   *            @arg @ref RCC_MCO1SOURCE_SYSCLK  System clock (SYSCLK) selected as MCO clock
  1131.   *            @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
  1132.   *            @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
  1133.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK  PLL clock divided by 2 selected as MCO clock
  1134.   * @param  __MCODIV__ specifies the MCO clock prescaler.
  1135.   *         This parameter can be one of the following values:
  1136.   *            @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
  1137.   */
  1138. #endif
  1139.  
  1140. #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
  1141.                  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
  1142.  
  1143.  
  1144. /**
  1145.   * @}
  1146.   */
  1147.  
  1148.   /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
  1149.   * @{  
  1150.   */
  1151.  
  1152. /** @brief Macro to configure the RTC clock (RTCCLK).
  1153.   * @note   As the RTC clock configuration bits are in the Backup domain and write
  1154.   *         access is denied to this domain after reset, you have to enable write
  1155.   *         access using the Power Backup Access macro before to configure
  1156.   *         the RTC clock source (to be done once after reset).    
  1157.   * @note   Once the RTC clock is configured it can't be changed unless the  
  1158.   *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
  1159.   *         a Power On Reset (POR).
  1160.   *
  1161.   * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
  1162.   *          This parameter can be one of the following values:
  1163.   *             @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
  1164.   *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
  1165.   *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
  1166.   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
  1167.   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
  1168.   *         work in STOP and STANDBY modes, and can be used as wakeup source.
  1169.   *         However, when the HSE clock is used as RTC clock source, the RTC
  1170.   *         cannot be used in STOP and STANDBY modes.    
  1171.   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
  1172.   *         RTC clock source).
  1173.   */
  1174. #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
  1175.                                                    
  1176. /** @brief Macro to get the RTC clock source.
  1177.   * @retval The clock source can be one of the following values:
  1178.   *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
  1179.   *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
  1180.   *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
  1181.   *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
  1182.   */
  1183. #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
  1184.  
  1185. /** @brief Macro to enable the the RTC clock.
  1186.   * @note   These macros must be used only after the RTC clock source was selected.
  1187.   */
  1188. #define __HAL_RCC_RTC_ENABLE()          (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
  1189.  
  1190. /** @brief Macro to disable the the RTC clock.
  1191.   * @note  These macros must be used only after the RTC clock source was selected.
  1192.   */
  1193. #define __HAL_RCC_RTC_DISABLE()         (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
  1194.  
  1195. /** @brief  Macro to force the Backup domain reset.
  1196.   * @note   This function resets the RTC peripheral (including the backup registers)
  1197.   *         and the RTC clock source selection in RCC_BDCR register.
  1198.   */
  1199. #define __HAL_RCC_BACKUPRESET_FORCE()   (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
  1200.  
  1201. /** @brief  Macros to release the Backup domain reset.
  1202.   */
  1203. #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
  1204.  
  1205. /**
  1206.   * @}
  1207.   */
  1208.  
  1209. /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
  1210.   * @brief macros to manage the specified RCC Flags and interrupts.
  1211.   * @{
  1212.   */
  1213.  
  1214. /** @brief Enable RCC interrupt.
  1215.   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
  1216.   *          This parameter can be any combination of the following values:
  1217.   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
  1218.   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
  1219.   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
  1220.   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
  1221.   *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
  1222.   @if STM32F105xx
  1223.   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  1224.   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  1225.   @elsif STM32F107xx
  1226.   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  1227.   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  1228.   @endif
  1229.   */
  1230. #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
  1231.  
  1232. /** @brief Disable RCC interrupt.
  1233.   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
  1234.   *          This parameter can be any combination of the following values:
  1235.   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
  1236.   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
  1237.   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
  1238.   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
  1239.   *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
  1240.   @if STM32F105xx
  1241.   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  1242.   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  1243.   @elsif STM32F107xx
  1244.   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  1245.   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  1246.   @endif
  1247.   */
  1248. #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
  1249.  
  1250. /** @brief Clear the RCC's interrupt pending bits.
  1251.   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
  1252.   *          This parameter can be any combination of the following values:
  1253.   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
  1254.   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
  1255.   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
  1256.   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
  1257.   *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
  1258.   @if STM32F105xx
  1259.   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  1260.   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  1261.   @elsif STM32F107xx
  1262.   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  1263.   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  1264.   @endif
  1265.   *            @arg @ref RCC_IT_CSS Clock Security System interrupt
  1266.   */
  1267. #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
  1268.  
  1269. /** @brief Check the RCC's interrupt has occurred or not.
  1270.   * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
  1271.   *          This parameter can be one of the following values:
  1272.   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
  1273.   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
  1274.   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
  1275.   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
  1276.   *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
  1277.   @if STM32F105xx
  1278.   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  1279.   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  1280.   @elsif STM32F107xx
  1281.   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  1282.   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  1283.   @endif
  1284.   *            @arg @ref RCC_IT_CSS Clock Security System interrupt
  1285.   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
  1286.   */
  1287. #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
  1288.  
  1289. /** @brief Set RMVF bit to clear the reset flags.
  1290.   *         The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
  1291.   *         RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
  1292.   */
  1293. #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
  1294.  
  1295. /** @brief  Check RCC flag is set or not.
  1296.   * @param  __FLAG__ specifies the flag to check.
  1297.   *          This parameter can be one of the following values:
  1298.   *            @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
  1299.   *            @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
  1300.   *            @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
  1301.   @if STM32F105xx
  1302.   *            @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
  1303.   *            @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
  1304.   @elsif STM32F107xx
  1305.   *            @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
  1306.   *            @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
  1307.   @endif
  1308.   *            @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
  1309.   *            @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
  1310.   *            @arg @ref RCC_FLAG_PINRST  Pin reset.
  1311.   *            @arg @ref RCC_FLAG_PORRST  POR/PDR reset.
  1312.   *            @arg @ref RCC_FLAG_SFTRST  Software reset.
  1313.   *            @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
  1314.   *            @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
  1315.   *            @arg @ref RCC_FLAG_LPWRRST Low Power reset.
  1316.   * @retval The new state of __FLAG__ (TRUE or FALSE).
  1317.   */
  1318. #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)?   RCC->CR   : \
  1319.                                       ((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \
  1320.                                                                               RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
  1321.  
  1322. /**
  1323.   * @}
  1324.   */
  1325.  
  1326. /**
  1327.   * @}
  1328.   */
  1329.  
  1330. /* Include RCC HAL Extension module */
  1331. #include "stm32f1xx_hal_rcc_ex.h"
  1332.  
  1333. /* Exported functions --------------------------------------------------------*/
  1334. /** @addtogroup RCC_Exported_Functions
  1335.   * @{
  1336.   */
  1337.  
  1338. /** @addtogroup RCC_Exported_Functions_Group1
  1339.   * @{
  1340.   */
  1341.  
  1342. /* Initialization and de-initialization functions  ******************************/
  1343. void              HAL_RCC_DeInit(void);
  1344. HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
  1345. HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency);
  1346.  
  1347. /**
  1348.   * @}
  1349.   */
  1350.  
  1351. /** @addtogroup RCC_Exported_Functions_Group2
  1352.   * @{
  1353.   */
  1354.  
  1355. /* Peripheral Control functions  ************************************************/
  1356. void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
  1357. void              HAL_RCC_EnableCSS(void);
  1358. void              HAL_RCC_DisableCSS(void);
  1359. uint32_t          HAL_RCC_GetSysClockFreq(void);
  1360. uint32_t          HAL_RCC_GetHCLKFreq(void);
  1361. uint32_t          HAL_RCC_GetPCLK1Freq(void);
  1362. uint32_t          HAL_RCC_GetPCLK2Freq(void);
  1363. void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
  1364. void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);
  1365.  
  1366. /* CSS NMI IRQ handler */
  1367. void              HAL_RCC_NMI_IRQHandler(void);
  1368.  
  1369. /* User Callbacks in non blocking mode (IT mode) */
  1370. void              HAL_RCC_CSSCallback(void);
  1371.  
  1372. /**
  1373.   * @}
  1374.   */
  1375.  
  1376. /**
  1377.   * @}
  1378.   */
  1379.  
  1380. /**
  1381.   * @}
  1382.   */
  1383.  
  1384. /**
  1385.   * @}
  1386.   */
  1387.  
  1388. #ifdef __cplusplus
  1389. }
  1390. #endif
  1391.  
  1392. #endif /* __STM32F1xx_HAL_RCC_H */
  1393.  
  1394. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1395.  
  1396.