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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_nand.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of NAND HAL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  10.   *
  11.   * Redistribution and use in source and binary forms, with or without modification,
  12.   * are permitted provided that the following conditions are met:
  13.   *   1. Redistributions of source code must retain the above copyright notice,
  14.   *      this list of conditions and the following disclaimer.
  15.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16.   *      this list of conditions and the following disclaimer in the documentation
  17.   *      and/or other materials provided with the distribution.
  18.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19.   *      may be used to endorse or promote products derived from this software
  20.   *      without specific prior written permission.
  21.   *
  22.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32.   *
  33.   ******************************************************************************
  34.   */
  35.  
  36. /* Define to prevent recursive inclusion -------------------------------------*/
  37. #ifndef __STM32F1xx_HAL_NAND_H
  38. #define __STM32F1xx_HAL_NAND_H
  39.  
  40. #ifdef __cplusplus
  41.  extern "C" {
  42. #endif
  43.  
  44. /* Includes ------------------------------------------------------------------*/
  45. #include "stm32f1xx_ll_fsmc.h"
  46.  
  47. /** @addtogroup STM32F1xx_HAL_Driver
  48.   * @{
  49.   */
  50.  
  51. #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
  52. /** @addtogroup NAND
  53.   * @{
  54.   */
  55.  
  56.  
  57. /* Exported typedef ----------------------------------------------------------*/
  58. /* Exported types ------------------------------------------------------------*/
  59. /** @defgroup NAND_Exported_Types NAND Exported Types
  60.   * @{
  61.   */
  62.  
  63. /**
  64.   * @brief  HAL NAND State structures definition
  65.   */
  66. typedef enum
  67. {
  68.   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
  69.   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
  70.   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
  71.   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
  72. }HAL_NAND_StateTypeDef;
  73.    
  74. /**
  75.   * @brief  NAND Memory electronic signature Structure definition
  76.   */
  77. typedef struct
  78. {
  79.   /*<! NAND memory electronic signature maker and device IDs */
  80.  
  81.   uint8_t Maker_Id;
  82.  
  83.   uint8_t Device_Id;
  84.  
  85.   uint8_t Third_Id;
  86.  
  87.   uint8_t Fourth_Id;
  88. }NAND_IDTypeDef;
  89.  
  90. /**
  91.   * @brief  NAND Memory address Structure definition
  92.   */
  93. typedef struct
  94. {
  95.   uint16_t Page;   /*!< NAND memory Page address    */
  96.  
  97.   uint16_t Plane;   /*!< NAND memory Plane address  */
  98.  
  99.   uint16_t Block;  /*!< NAND memory Block address   */
  100.  
  101. }NAND_AddressTypeDef;
  102.  
  103. /**
  104.   * @brief  NAND Memory info Structure definition
  105.   */
  106. typedef struct
  107. {
  108.   uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
  109.                                               for 8 bits adressing or words for 16 bits addressing             */
  110.  
  111.   uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
  112.                                               for 8 bits adressing or words for 16 bits addressing             */
  113.  
  114.   uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
  115.  
  116.   uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
  117.      
  118.   uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
  119.  
  120.   uint32_t        PlaneSize;             /*!< NAND memory plane size measured in number of blocks              */
  121.  
  122.   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
  123.                                               parameter is mandatory for some NAND parts after the read
  124.                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
  125.                                               Example: Toshiba THTH58BYG3S0HBAI6.
  126.                                               This parameter could be ENABLE or DISABLE
  127.                                               Please check the Read Mode sequnece in the NAND device datasheet */
  128. }NAND_DeviceConfigTypeDef;
  129.  
  130. /**
  131.   * @brief  NAND handle Structure definition
  132.   */  
  133. typedef struct
  134. {
  135.   FSMC_NAND_TypeDef              *Instance;  /*!< Register base address                                 */
  136.  
  137.   FSMC_NAND_InitTypeDef          Init;       /*!< NAND device control configuration parameters          */
  138.  
  139.   HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
  140.  
  141.   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
  142.  
  143.   NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
  144.  
  145. }NAND_HandleTypeDef;
  146.  
  147. /**
  148.   * @}
  149.   */
  150.  
  151. /* Exported constants --------------------------------------------------------*/
  152. /* Exported macros -----------------------------------------------------------*/
  153. /** @defgroup NAND_Exported_Macros NAND Exported Macros
  154.   * @{
  155.   */
  156.  
  157. /** @brief Reset NAND handle state
  158.   * @param  __HANDLE__: specifies the NAND handle.
  159.   * @retval None
  160.   */
  161. #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
  162.  
  163. /**
  164.   * @}
  165.   */
  166.  
  167. /* Exported functions --------------------------------------------------------*/
  168. /** @addtogroup NAND_Exported_Functions NAND Exported Functions
  169.   * @{
  170.   */
  171.    
  172. /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
  173.   * @{
  174.   */
  175.  
  176. /* Initialization/de-initialization functions  ********************************/
  177. HAL_StatusTypeDef   HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
  178. HAL_StatusTypeDef   HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
  179.  
  180. HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
  181.  
  182. HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
  183.  
  184. void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
  185. void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
  186. void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
  187. void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
  188.  
  189. /**
  190.   * @}
  191.   */
  192.  
  193. /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
  194.   * @{
  195.   */
  196.  
  197. /* IO operation functions  ****************************************************/
  198.  
  199. HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
  200.  
  201. HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
  202. HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
  203. HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
  204. HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
  205.  
  206. HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
  207. HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
  208. HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
  209. HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
  210.  
  211. HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
  212. uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
  213. uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
  214.  
  215. /**
  216.   * @}
  217.   */
  218.  
  219. /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
  220.   * @{
  221.   */
  222.  
  223. /* NAND Control functions  ****************************************************/
  224. HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
  225. HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
  226. HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
  227.  
  228. /**
  229.   * @}
  230.   */
  231.    
  232. /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
  233.   * @{
  234.   */
  235.  
  236. /* NAND State functions *******************************************************/
  237. HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
  238. uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
  239.  
  240. /**
  241.   * @}
  242.   */
  243.    
  244. /**
  245.   * @}
  246.   */
  247. /* Private types -------------------------------------------------------------*/
  248. /* Private variables ---------------------------------------------------------*/
  249. /* Private constants ---------------------------------------------------------*/
  250. /** @addtogroup NAND_Private_Constants
  251.   * @{
  252.   */
  253.  
  254. #define NAND_DEVICE1               FSMC_BANK2
  255. #define NAND_DEVICE2               FSMC_BANK3
  256. #define NAND_WRITE_TIMEOUT         1000U
  257.  
  258. #define CMD_AREA                   (1U<<16U)  /* A16 = CLE high */
  259. #define ADDR_AREA                  (1U<<17U)  /* A17 = ALE high */
  260.  
  261. #define NAND_CMD_AREA_A            ((uint8_t)0x00)
  262. #define NAND_CMD_AREA_B            ((uint8_t)0x01)
  263. #define NAND_CMD_AREA_C            ((uint8_t)0x50)
  264. #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
  265.  
  266. #define NAND_CMD_WRITE0            ((uint8_t)0x80)
  267. #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)  
  268. #define NAND_CMD_ERASE0            ((uint8_t)0x60)
  269. #define NAND_CMD_ERASE1            ((uint8_t)0xD0)  
  270. #define NAND_CMD_READID            ((uint8_t)0x90)  
  271. #define NAND_CMD_STATUS            ((uint8_t)0x70)
  272. #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
  273. #define NAND_CMD_RESET             ((uint8_t)0xFF)
  274.  
  275. /* NAND memory status */
  276. #define NAND_VALID_ADDRESS         0x00000100U
  277. #define NAND_INVALID_ADDRESS       0x00000200U
  278. #define NAND_TIMEOUT_ERROR         0x00000400U
  279. #define NAND_BUSY                  0x00000000U
  280. #define NAND_ERROR                 0x00000001U
  281. #define NAND_READY                 0x00000040U
  282.  
  283. /**
  284.   * @}
  285.   */
  286.  
  287. /* Private macros ------------------------------------------------------------*/
  288. /** @addtogroup NAND_Private_Macros
  289.   * @{
  290.   */
  291.  
  292. /**
  293.   * @brief  NAND memory address computation.
  294.   * @param  __ADDRESS__: NAND memory address.
  295.   * @param  __HANDLE__ : NAND handle.
  296.   * @retval NAND Raw address value
  297.   */
  298. #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
  299.                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
  300.  
  301. /**
  302.   * @brief  NAND memory Column address computation.
  303.   * @param  __HANDLE__: NAND handle.
  304.   * @retval NAND Raw address value
  305.   */
  306. #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
  307.    
  308. /**
  309.   * @brief  NAND memory address cycling.
  310.   * @param  __ADDRESS__: NAND memory address.
  311.   * @retval NAND address cycling value.
  312.   */
  313. #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)               /* 1st addressing cycle */
  314. #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8U)       /* 2nd addressing cycle */
  315. #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16U)      /* 3rd addressing cycle */
  316. #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24U)      /* 4th addressing cycle */
  317.  
  318. /**
  319.   * @brief  NAND memory Columns cycling.
  320.   * @param  __ADDRESS__: NAND memory address.
  321.   * @retval NAND Column address cycling value.
  322.   */
  323. #define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st Column addressing cycle */
  324. #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8U)      /* 2nd Column addressing cycle */
  325.  
  326. /**
  327.   * @}
  328.   */
  329.    
  330. /**
  331.   * @}
  332.   */
  333. #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
  334.  
  335. /**
  336.   * @}
  337.   */
  338.  
  339. #ifdef __cplusplus
  340. }
  341. #endif
  342.  
  343. #endif /* __STM32F1xx_HAL_NAND_H */
  344.  
  345. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  346.