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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_gpio_ex.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of GPIO HAL Extension module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10.   *
  11.   * Redistribution and use in source and binary forms, with or without modification,
  12.   * are permitted provided that the following conditions are met:
  13.   *   1. Redistributions of source code must retain the above copyright notice,
  14.   *      this list of conditions and the following disclaimer.
  15.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16.   *      this list of conditions and the following disclaimer in the documentation
  17.   *      and/or other materials provided with the distribution.
  18.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19.   *      may be used to endorse or promote products derived from this software
  20.   *      without specific prior written permission.
  21.   *
  22.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32.   *
  33.   ******************************************************************************
  34.   */
  35.  
  36. /* Define to prevent recursive inclusion -------------------------------------*/
  37. #ifndef __STM32F1xx_HAL_GPIO_EX_H
  38. #define __STM32F1xx_HAL_GPIO_EX_H
  39.  
  40. #ifdef __cplusplus
  41. extern "C" {
  42. #endif
  43.  
  44. /* Includes ------------------------------------------------------------------*/
  45. #include "stm32f1xx_hal_def.h"
  46.  
  47. /** @addtogroup STM32F1xx_HAL_Driver
  48.   * @{
  49.   */
  50.  
  51. /** @defgroup GPIOEx GPIOEx
  52.   * @{
  53.   */
  54. /* Exported types ------------------------------------------------------------*/
  55. /* Exported constants --------------------------------------------------------*/
  56.  
  57. /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
  58.   * @{
  59.   */
  60.  
  61. /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
  62.   * @brief This section propose definition to use the Cortex EVENTOUT signal.
  63.   * @{
  64.   */
  65.  
  66. /** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
  67.   * @{
  68.   */
  69.  
  70. #define AFIO_EVENTOUT_PIN_0  AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
  71. #define AFIO_EVENTOUT_PIN_1  AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
  72. #define AFIO_EVENTOUT_PIN_2  AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
  73. #define AFIO_EVENTOUT_PIN_3  AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
  74. #define AFIO_EVENTOUT_PIN_4  AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
  75. #define AFIO_EVENTOUT_PIN_5  AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
  76. #define AFIO_EVENTOUT_PIN_6  AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
  77. #define AFIO_EVENTOUT_PIN_7  AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
  78. #define AFIO_EVENTOUT_PIN_8  AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
  79. #define AFIO_EVENTOUT_PIN_9  AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
  80. #define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
  81. #define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
  82. #define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
  83. #define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
  84. #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
  85. #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
  86.  
  87. #define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
  88.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
  89.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
  90.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
  91.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
  92.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
  93.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
  94.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
  95.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
  96.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
  97.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
  98.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
  99.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
  100.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
  101.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
  102.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_15))
  103. /**
  104.   * @}
  105.   */
  106.  
  107. /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
  108.   * @{
  109.   */
  110.  
  111. #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
  112. #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
  113. #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
  114. #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
  115. #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
  116.  
  117. #define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
  118.                                          ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
  119.                                          ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
  120.                                          ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
  121.                                          ((__PORT__) == AFIO_EVENTOUT_PORT_E))
  122. /**
  123.   * @}
  124.   */
  125.  
  126. /**
  127.   * @}
  128.   */
  129.  
  130. /** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
  131.   * @brief This section propose definition to remap the alternate function to some other port/pins.
  132.   * @{
  133.   */
  134.  
  135. /**
  136.   * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
  137.   * @note  ENABLE: Remap     (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
  138.   * @retval None
  139.   */
  140. #define __HAL_AFIO_REMAP_SPI1_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)
  141.  
  142. /**
  143.   * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
  144.   * @note  DISABLE: No remap (NSS/PA4,  SCK/PA5, MISO/PA6, MOSI/PA7)
  145.   * @retval None
  146.   */
  147. #define __HAL_AFIO_REMAP_SPI1_DISABLE()  AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)
  148.  
  149. /**
  150.   * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
  151.   * @note  ENABLE: Remap     (SCL/PB8, SDA/PB9)
  152.   * @retval None
  153.   */
  154. #define __HAL_AFIO_REMAP_I2C1_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)
  155.  
  156. /**
  157.   * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
  158.   * @note  DISABLE: No remap (SCL/PB6, SDA/PB7)
  159.   * @retval None
  160.   */
  161. #define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)
  162.  
  163. /**
  164.   * @brief Enable the remapping of USART1 alternate function TX and RX.
  165.   * @note  ENABLE: Remap     (TX/PB6, RX/PB7)
  166.   * @retval None
  167.   */
  168. #define __HAL_AFIO_REMAP_USART1_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)
  169.  
  170. /**
  171.   * @brief Disable the remapping of USART1 alternate function TX and RX.
  172.   * @note  DISABLE: No remap (TX/PA9, RX/PA10)
  173.   * @retval None
  174.   */
  175. #define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)
  176.  
  177. /**
  178.   * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
  179.   * @note  ENABLE: Remap     (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
  180.   * @retval None
  181.   */
  182. #define __HAL_AFIO_REMAP_USART2_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)
  183.  
  184. /**
  185.   * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
  186.   * @note  DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
  187.   * @retval None
  188.   */
  189. #define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)
  190.  
  191. /**
  192.   * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
  193.   * @note  ENABLE: Full remap     (TX/PD8,  RX/PD9,  CK/PD10, CTS/PD11, RTS/PD12)
  194.   * @retval None
  195.   */
  196. #define __HAL_AFIO_REMAP_USART3_ENABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
  197.  
  198. /**
  199.   * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
  200.   * @note  PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
  201.   * @retval None
  202.   */
  203. #define __HAL_AFIO_REMAP_USART3_PARTIAL()  AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
  204.  
  205. /**
  206.   * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
  207.   * @note  DISABLE: No remap      (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
  208.   * @retval None
  209.   */
  210. #define __HAL_AFIO_REMAP_USART3_DISABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
  211.  
  212. /**
  213.   * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
  214.   * @note  ENABLE: Full remap     (ETR/PE7,  CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8,  CH2N/PE10, CH3N/PE12)
  215.   * @retval None
  216.   */
  217. #define __HAL_AFIO_REMAP_TIM1_ENABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
  218.  
  219. /**
  220.   * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
  221.   * @note  PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PA6,  CH1N/PA7,  CH2N/PB0,  CH3N/PB1)
  222.   * @retval None
  223.   */
  224. #define __HAL_AFIO_REMAP_TIM1_PARTIAL()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
  225.  
  226. /**
  227.   * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
  228.   * @note  DISABLE: No remap      (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
  229.   * @retval None
  230.   */
  231. #define __HAL_AFIO_REMAP_TIM1_DISABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
  232.  
  233. /**
  234.   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
  235.   * @note  ENABLE: Full remap       (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
  236.   * @retval None
  237.   */
  238. #define __HAL_AFIO_REMAP_TIM2_ENABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
  239.  
  240. /**
  241.   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
  242.   * @note  PARTIAL_2: Partial remap (CH1/ETR/PA0,  CH2/PA1, CH3/PB10, CH4/PB11)
  243.   * @retval None
  244.   */
  245. #define __HAL_AFIO_REMAP_TIM2_PARTIAL_2()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
  246.  
  247. /**
  248.   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
  249.   * @note  PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2,  CH4/PA3)
  250.   * @retval None
  251.   */
  252. #define __HAL_AFIO_REMAP_TIM2_PARTIAL_1()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
  253.  
  254. /**
  255.   * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
  256.   * @note  DISABLE: No remap        (CH1/ETR/PA0,  CH2/PA1, CH3/PA2,  CH4/PA3)
  257.   * @retval None
  258.   */
  259. #define __HAL_AFIO_REMAP_TIM2_DISABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
  260.  
  261. /**
  262.   * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
  263.   * @note  ENABLE: Full remap     (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
  264.   * @note  TIM3_ETR on PE0 is not re-mapped.
  265.   * @retval None
  266.   */
  267. #define __HAL_AFIO_REMAP_TIM3_ENABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
  268.  
  269. /**
  270.   * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
  271.   * @note  PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
  272.   * @note  TIM3_ETR on PE0 is not re-mapped.
  273.   * @retval None
  274.   */
  275. #define __HAL_AFIO_REMAP_TIM3_PARTIAL()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
  276.  
  277. /**
  278.   * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
  279.   * @note  DISABLE: No remap      (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
  280.   * @note  TIM3_ETR on PE0 is not re-mapped.
  281.   * @retval None
  282.   */
  283. #define __HAL_AFIO_REMAP_TIM3_DISABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
  284.  
  285. /**
  286.   * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
  287.   * @note  ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
  288.   * @note  TIM4_ETR on PE0 is not re-mapped.
  289.   * @retval None
  290.   */
  291. #define __HAL_AFIO_REMAP_TIM4_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP)
  292.  
  293. /**
  294.   * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
  295.   * @note  DISABLE: No remap  (TIM4_CH1/PB6,  TIM4_CH2/PB7,  TIM4_CH3/PB8,  TIM4_CH4/PB9)
  296.   * @note  TIM4_ETR on PE0 is not re-mapped.
  297.   * @retval None
  298.   */
  299. #define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP)
  300.  
  301. #if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
  302.  
  303. /**
  304.   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
  305.   * @note  CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
  306.   * @retval None
  307.   */
  308. #define __HAL_AFIO_REMAP_CAN1_1()  AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP)
  309.  
  310. /**
  311.   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
  312.   * @note  CASE 2: CAN_RX mapped to PB8,  CAN_TX mapped to PB9 (not available on 36-pin package)
  313.   * @retval None
  314.   */
  315. #define __HAL_AFIO_REMAP_CAN1_2()  AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP)
  316.  
  317. /**
  318.   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
  319.   * @note  CASE 3: CAN_RX mapped to PD0,  CAN_TX mapped to PD1
  320.   * @retval None
  321.   */
  322. #define __HAL_AFIO_REMAP_CAN1_3()  AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP)
  323.  
  324. #endif
  325.  
  326. /**
  327.   * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
  328.   *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
  329.   *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
  330.   *        on 100-pin and 144-pin packages, no need for remapping).
  331.   * @note  ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
  332.   * @retval None
  333.   */
  334. #define __HAL_AFIO_REMAP_PD01_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP)
  335.  
  336. /**
  337.   * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
  338.   *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
  339.   *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
  340.   *        on 100-pin and 144-pin packages, no need for remapping).
  341.   * @note  DISABLE: No remapping of PD0 and PD1
  342.   * @retval None
  343.   */
  344. #define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP)
  345.  
  346. #if defined(AFIO_MAPR_TIM5CH4_IREMAP)
  347. /**
  348.   * @brief Enable the remapping of TIM5CH4.
  349.   * @note  ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
  350.   * @note  This function is available only in high density value line devices.
  351.   * @retval None
  352.   */
  353. #define __HAL_AFIO_REMAP_TIM5CH4_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP)
  354.  
  355. /**
  356.   * @brief Disable the remapping of TIM5CH4.
  357.   * @note  DISABLE: TIM5_CH4 is connected to PA3
  358.   * @note  This function is available only in high density value line devices.
  359.   * @retval None
  360.   */
  361. #define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP)
  362. #endif
  363.  
  364. #if defined(AFIO_MAPR_ETH_REMAP)
  365. /**
  366.   * @brief Enable the remapping of Ethernet MAC connections with the PHY.
  367.   * @note  ENABLE: Remap     (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
  368.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  369.   * @retval None
  370.   */
  371. #define __HAL_AFIO_REMAP_ETH_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP)
  372.  
  373. /**
  374.   * @brief Disable the remapping of Ethernet MAC connections with the PHY.
  375.   * @note  DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5,  RXD2/PB0,  RXD3/PB1)
  376.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  377.   * @retval None
  378.   */
  379. #define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP)
  380. #endif
  381.  
  382. #if defined(AFIO_MAPR_CAN2_REMAP)
  383.  
  384. /**
  385.   * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
  386.   * @note  ENABLE: Remap     (CAN2_RX/PB5,  CAN2_TX/PB6)
  387.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  388.   * @retval None
  389.   */
  390. #define __HAL_AFIO_REMAP_CAN2_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP)
  391.  
  392. /**
  393.   * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
  394.   * @note  DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
  395.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  396.   * @retval None
  397.   */
  398. #define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP)
  399. #endif
  400.  
  401. #if defined(AFIO_MAPR_MII_RMII_SEL)
  402. /**
  403.   * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
  404.   * @note  ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
  405.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  406.   * @retval None
  407.   */
  408. #define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL)
  409.  
  410. /**
  411.   * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
  412.   * @note  ETH_MII: Configure Ethernet MAC for connection with an MII PHY
  413.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  414.   * @retval None
  415.   */
  416. #define __HAL_AFIO_ETH_MII()  AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL)
  417. #endif
  418.  
  419. /**
  420.   * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
  421.   * @note  ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
  422.   * @retval None
  423.   */
  424. #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
  425.  
  426. /**
  427.   * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
  428.   * @note  DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
  429.   * @retval None
  430.   */
  431. #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
  432.  
  433. /**
  434.   * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
  435.   * @note  ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
  436.   * @retval None
  437.   */
  438. #define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
  439.  
  440. /**
  441.   * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
  442.   * @note  DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
  443.   * @retval None
  444.   */
  445. #define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
  446.  
  447. #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
  448.  
  449. /**
  450.   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
  451.   * @note  ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
  452.   * @retval None
  453.   */
  454. #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
  455.  
  456. /**
  457.   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
  458.   * @note  DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
  459.   * @retval None
  460.   */
  461. #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
  462. #endif
  463.  
  464. #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
  465.  
  466. /**
  467.   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
  468.   * @note  ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
  469.   * @retval None
  470.   */
  471. #define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
  472.  
  473. /**
  474.   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
  475.   * @note  DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
  476.   * @retval None
  477.   */
  478. #define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
  479. #endif
  480.  
  481. /**
  482.   * @brief Enable the Serial wire JTAG configuration
  483.   * @note  ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
  484.   * @retval None
  485.   */
  486. #define __HAL_AFIO_REMAP_SWJ_ENABLE()  AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET)
  487.  
  488. /**
  489.   * @brief Enable the Serial wire JTAG configuration
  490.   * @note  NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
  491.   * @retval None
  492.   */
  493. #define __HAL_AFIO_REMAP_SWJ_NONJTRST()  AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST)
  494.  
  495. /**
  496.   * @brief Enable the Serial wire JTAG configuration
  497.   * @note  NOJTAG: JTAG-DP Disabled and SW-DP Enabled
  498.   * @retval None
  499.   */
  500.  
  501. #define __HAL_AFIO_REMAP_SWJ_NOJTAG()  AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
  502.  
  503. /**
  504.   * @brief Disable the Serial wire JTAG configuration
  505.   * @note  DISABLE: JTAG-DP Disabled and SW-DP Disabled
  506.   * @retval None
  507.   */
  508. #define __HAL_AFIO_REMAP_SWJ_DISABLE()  AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE)
  509.  
  510. #if defined(AFIO_MAPR_SPI3_REMAP)
  511.  
  512. /**
  513.   * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
  514.   * @note  ENABLE: Remap     (SPI3_NSS-I2S3_WS/PA4,  SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
  515.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  516.   * @retval None
  517.   */
  518. #define __HAL_AFIO_REMAP_SPI3_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP)
  519.  
  520. /**
  521.   * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
  522.   * @note  DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3,  SPI3_MISO/PB4,  SPI3_MOSI-I2S3_SD/PB5).
  523.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  524.   * @retval None
  525.   */
  526. #define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP)
  527. #endif
  528.  
  529. #if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
  530.  
  531. /**
  532.   * @brief Control of TIM2_ITR1 internal mapping.
  533.   * @note  TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
  534.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  535.   * @retval None
  536.   */
  537. #define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
  538.  
  539. /**
  540.   * @brief Control of TIM2_ITR1 internal mapping.
  541.   * @note  TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
  542.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  543.   * @retval None
  544.   */
  545. #define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
  546. #endif
  547.  
  548. #if defined(AFIO_MAPR_PTP_PPS_REMAP)
  549.  
  550. /**
  551.   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
  552.   * @note  ENABLE: PTP_PPS is output on PB5 pin.
  553.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  554.   * @retval None
  555.   */
  556. #define __HAL_AFIO_ETH_PTP_PPS_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP)
  557.  
  558. /**
  559.   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
  560.   * @note  DISABLE: PTP_PPS not output on PB5 pin.
  561.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  562.   * @retval None
  563.   */
  564. #define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP)
  565. #endif
  566.  
  567. #if defined(AFIO_MAPR2_TIM9_REMAP)
  568.  
  569. /**
  570.   * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
  571.   * @note  ENABLE: Remap     (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
  572.   * @retval None
  573.   */
  574. #define __HAL_AFIO_REMAP_TIM9_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
  575.  
  576. /**
  577.   * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
  578.   * @note  DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
  579.   * @retval None
  580.   */
  581. #define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
  582. #endif
  583.  
  584. #if defined(AFIO_MAPR2_TIM10_REMAP)
  585.  
  586. /**
  587.   * @brief Enable the remapping of TIM10_CH1.
  588.   * @note  ENABLE: Remap     (TIM10_CH1 on PF6).
  589.   * @retval None
  590.   */
  591. #define __HAL_AFIO_REMAP_TIM10_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
  592.  
  593. /**
  594.   * @brief Disable the remapping of TIM10_CH1.
  595.   * @note  DISABLE: No remap (TIM10_CH1 on PB8).
  596.   * @retval None
  597.   */
  598. #define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
  599. #endif
  600.  
  601. #if defined(AFIO_MAPR2_TIM11_REMAP)
  602. /**
  603.   * @brief Enable the remapping of TIM11_CH1.
  604.   * @note  ENABLE: Remap     (TIM11_CH1 on PF7).
  605.   * @retval None
  606.   */
  607. #define __HAL_AFIO_REMAP_TIM11_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
  608.  
  609. /**
  610.   * @brief Disable the remapping of TIM11_CH1.
  611.   * @note  DISABLE: No remap (TIM11_CH1 on PB9).
  612.   * @retval None
  613.   */
  614. #define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
  615. #endif
  616.  
  617. #if defined(AFIO_MAPR2_TIM13_REMAP)
  618.  
  619. /**
  620.   * @brief Enable the remapping of TIM13_CH1.
  621.   * @note  ENABLE: Remap     STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
  622.   * @retval None
  623.   */
  624. #define __HAL_AFIO_REMAP_TIM13_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
  625.  
  626. /**
  627.   * @brief Disable the remapping of TIM13_CH1.
  628.   * @note  DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
  629.   * @retval None
  630.   */
  631. #define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
  632. #endif
  633.  
  634. #if defined(AFIO_MAPR2_TIM14_REMAP)
  635.  
  636. /**
  637.   * @brief Enable the remapping of TIM14_CH1.
  638.   * @note  ENABLE: Remap     STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
  639.   * @retval None
  640.   */
  641. #define __HAL_AFIO_REMAP_TIM14_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
  642.  
  643. /**
  644.   * @brief Disable the remapping of TIM14_CH1.
  645.   * @note  DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
  646.   * @retval None
  647.   */
  648. #define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
  649. #endif
  650.  
  651. #if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
  652.  
  653. /**
  654.   * @brief Controls the use of the optional FSMC_NADV signal.
  655.   * @note  DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
  656.   * @retval None
  657.   */
  658. #define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
  659.  
  660. /**
  661.   * @brief Controls the use of the optional FSMC_NADV signal.
  662.   * @note  CONNECTED: The NADV signal is connected to the output (default).
  663.   * @retval None
  664.   */
  665. #define __HAL_AFIO_FSMCNADV_CONNECTED()    CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
  666. #endif
  667.  
  668. #if defined(AFIO_MAPR2_TIM15_REMAP)
  669.  
  670. /**
  671.   * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
  672.   * @note  ENABLE: Remap     (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
  673.   * @retval None
  674.   */
  675. #define __HAL_AFIO_REMAP_TIM15_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
  676.  
  677. /**
  678.   * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
  679.   * @note  DISABLE: No remap (TIM15_CH1 on PA2  and TIM15_CH2 on PA3).
  680.   * @retval None
  681.   */
  682. #define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
  683. #endif
  684.  
  685. #if defined(AFIO_MAPR2_TIM16_REMAP)
  686.  
  687. /**
  688.   * @brief Enable the remapping of TIM16_CH1.
  689.   * @note  ENABLE: Remap     (TIM16_CH1 on PA6).
  690.   * @retval None
  691.   */
  692. #define __HAL_AFIO_REMAP_TIM16_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
  693.  
  694. /**
  695.   * @brief Disable the remapping of TIM16_CH1.
  696.   * @note  DISABLE: No remap (TIM16_CH1 on PB8).
  697.   * @retval None
  698.   */
  699. #define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
  700. #endif
  701.  
  702. #if defined(AFIO_MAPR2_TIM17_REMAP)
  703.  
  704. /**
  705.   * @brief Enable the remapping of TIM17_CH1.
  706.   * @note  ENABLE: Remap     (TIM17_CH1 on PA7).
  707.   * @retval None
  708.   */
  709. #define __HAL_AFIO_REMAP_TIM17_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
  710.  
  711. /**
  712.   * @brief Disable the remapping of TIM17_CH1.
  713.   * @note  DISABLE: No remap (TIM17_CH1 on PB9).
  714.   * @retval None
  715.   */
  716. #define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
  717. #endif
  718.  
  719. #if defined(AFIO_MAPR2_CEC_REMAP)
  720.  
  721. /**
  722.   * @brief Enable the remapping of CEC.
  723.   * @note  ENABLE: Remap     (CEC on PB10).
  724.   * @retval None
  725.   */
  726. #define __HAL_AFIO_REMAP_CEC_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
  727.  
  728. /**
  729.   * @brief Disable the remapping of CEC.
  730.   * @note  DISABLE: No remap (CEC on PB8).
  731.   * @retval None
  732.   */
  733. #define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
  734. #endif
  735.  
  736. #if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
  737.  
  738. /**
  739.   * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
  740.   * @note  ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
  741.   * @retval None
  742.   */
  743. #define __HAL_AFIO_REMAP_TIM1DMA_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
  744.  
  745. /**
  746.   * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
  747.   * @note  DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
  748.   * @retval None
  749.   */
  750. #define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
  751. #endif
  752.  
  753. #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
  754.  
  755. /**
  756.   * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
  757.   * @note  ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
  758.   * @retval None
  759.   */
  760. #define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
  761.  
  762. /**
  763.   * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
  764.   * @note  DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
  765.   * @retval None
  766.   */
  767. #define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
  768. #endif
  769.  
  770. #if defined(AFIO_MAPR2_TIM12_REMAP)
  771.  
  772. /**
  773.   * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
  774.   * @note  ENABLE: Remap     (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
  775.   * @note  This bit is available only in high density value line devices.
  776.   * @retval None
  777.   */
  778. #define __HAL_AFIO_REMAP_TIM12_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
  779.  
  780. /**
  781.   * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
  782.   * @note  DISABLE: No remap (TIM12_CH1 on PC4  and TIM12_CH2 on PC5).
  783.   * @note  This bit is available only in high density value line devices.
  784.   * @retval None
  785.   */
  786. #define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
  787. #endif
  788.  
  789. #if defined(AFIO_MAPR2_MISC_REMAP)
  790.  
  791. /**
  792.   * @brief Miscellaneous features remapping.
  793.   *        This bit is set and cleared by software. It controls miscellaneous features.
  794.   *        The DMA2 channel 5 interrupt position in the vector table.
  795.   *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
  796.   * @note  ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
  797.   *        selected as DAC Trigger 3, TIM15 triggers TIM1/3.
  798.   * @note  This bit is available only in high density value line devices.
  799.   * @retval None
  800.   */
  801. #define __HAL_AFIO_REMAP_MISC_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
  802.  
  803. /**
  804.   * @brief Miscellaneous features remapping.
  805.   *        This bit is set and cleared by software. It controls miscellaneous features.
  806.   *        The DMA2 channel 5 interrupt position in the vector table.
  807.   *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
  808.   * @note  DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
  809.   *        event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
  810.   * @note  This bit is available only in high density value line devices.
  811.   * @retval None
  812.   */
  813. #define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
  814. #endif
  815.  
  816. /**
  817.   * @}
  818.   */
  819.  
  820. /**
  821.   * @}
  822.   */
  823.  
  824. /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
  825.   * @{
  826.   */
  827. #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
  828. #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
  829.                                    ((__GPIOx__) == (GPIOB))? 1U :\
  830.                                    ((__GPIOx__) == (GPIOC))? 2U :3U)
  831. #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
  832. #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
  833.                                    ((__GPIOx__) == (GPIOB))? 1U :\
  834.                                    ((__GPIOx__) == (GPIOC))? 2U :\
  835.                                    ((__GPIOx__) == (GPIOD))? 3U :4U)
  836. #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
  837. #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
  838.                                    ((__GPIOx__) == (GPIOB))? 1U :\
  839.                                    ((__GPIOx__) == (GPIOC))? 2U :\
  840.                                    ((__GPIOx__) == (GPIOD))? 3U :\
  841.                                    ((__GPIOx__) == (GPIOE))? 4U :\
  842.                                    ((__GPIOx__) == (GPIOF))? 5U :6U)
  843. #endif
  844.  
  845. #define AFIO_REMAP_ENABLE(REMAP_PIN)       do{ uint32_t tmpreg = AFIO->MAPR; \
  846.                                                tmpreg |= AFIO_MAPR_SWJ_CFG;  \
  847.                                                tmpreg |= REMAP_PIN;          \
  848.                                                AFIO->MAPR = tmpreg;          \
  849.                                                }while(0U)
  850.  
  851. #define AFIO_REMAP_DISABLE(REMAP_PIN)      do{ uint32_t tmpreg = AFIO->MAPR;  \
  852.                                                tmpreg |= AFIO_MAPR_SWJ_CFG;   \
  853.                                                tmpreg &= ~REMAP_PIN;          \
  854.                                                AFIO->MAPR = tmpreg;           \
  855.                                                }while(0U)
  856.  
  857. #define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \
  858.                                                           tmpreg &= ~REMAP_PIN_MASK;    \
  859.                                                           tmpreg |= AFIO_MAPR_SWJ_CFG;  \
  860.                                                           tmpreg |= REMAP_PIN;          \
  861.                                                           AFIO->MAPR = tmpreg;          \
  862.                                                           }while(0U)
  863.  
  864. #define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG)  do{ uint32_t tmpreg = AFIO->MAPR;     \
  865.                                                tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \
  866.                                                tmpreg |= DBGAFR_SWJCFG;          \
  867.                                                AFIO->MAPR = tmpreg;              \
  868.                                                }while(0U)
  869.  
  870. /**
  871.   * @}
  872.   */
  873.  
  874. /* Exported macro ------------------------------------------------------------*/
  875. /* Exported functions --------------------------------------------------------*/
  876.  
  877. /** @addtogroup GPIOEx_Exported_Functions
  878.   * @{
  879.   */
  880.  
  881. /** @addtogroup GPIOEx_Exported_Functions_Group1
  882.   * @{
  883.   */
  884. void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
  885. void HAL_GPIOEx_EnableEventout(void);
  886. void HAL_GPIOEx_DisableEventout(void);
  887.  
  888. /**
  889.   * @}
  890.   */
  891.  
  892. /**
  893.   * @}
  894.   */
  895.  
  896. /**
  897.   * @}
  898.   */
  899.  
  900. /**
  901.   * @}
  902.   */
  903.  
  904. #ifdef __cplusplus
  905. }
  906. #endif
  907.  
  908. #endif /* __STM32F1xx_HAL_GPIO_EX_H */
  909.  
  910. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  911.