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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_gpio_ex.h
  4.   * @author  MCD Application Team
  5.   * @version V1.0.4
  6.   * @date    29-April-2016
  7.   * @brief   Header file of GPIO HAL Extension module.
  8.   ******************************************************************************
  9.   * @attention
  10.   *
  11.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  12.   *
  13.   * Redistribution and use in source and binary forms, with or without modification,
  14.   * are permitted provided that the following conditions are met:
  15.   *   1. Redistributions of source code must retain the above copyright notice,
  16.   *      this list of conditions and the following disclaimer.
  17.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18.   *      this list of conditions and the following disclaimer in the documentation
  19.   *      and/or other materials provided with the distribution.
  20.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21.   *      may be used to endorse or promote products derived from this software
  22.   *      without specific prior written permission.
  23.   *
  24.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34.   *
  35.   ******************************************************************************
  36.   */
  37.  
  38. /* Define to prevent recursive inclusion -------------------------------------*/
  39. #ifndef __STM32F1xx_HAL_GPIO_EX_H
  40. #define __STM32F1xx_HAL_GPIO_EX_H
  41.  
  42. #ifdef __cplusplus
  43.  extern "C" {
  44. #endif
  45.  
  46. /* Includes ------------------------------------------------------------------*/
  47. #include "stm32f1xx_hal_def.h"
  48.  
  49. /** @addtogroup STM32F1xx_HAL_Driver
  50.   * @{
  51.   */
  52.  
  53. /** @defgroup GPIOEx GPIOEx
  54.   * @{
  55.   */
  56.  
  57. /* Exported types ------------------------------------------------------------*/
  58.  
  59. /* Exported constants --------------------------------------------------------*/
  60.  
  61. /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
  62.   * @{
  63.   */
  64.  
  65. /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
  66.   * @brief This section propose definition to use the Cortex EVENTOUT signal.
  67.   * @{
  68.   */
  69.  
  70. /** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
  71.   * @{
  72.   */
  73.  
  74. #define AFIO_EVENTOUT_PIN_0  AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
  75. #define AFIO_EVENTOUT_PIN_1  AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
  76. #define AFIO_EVENTOUT_PIN_2  AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
  77. #define AFIO_EVENTOUT_PIN_3  AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
  78. #define AFIO_EVENTOUT_PIN_4  AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
  79. #define AFIO_EVENTOUT_PIN_5  AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
  80. #define AFIO_EVENTOUT_PIN_6  AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
  81. #define AFIO_EVENTOUT_PIN_7  AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
  82. #define AFIO_EVENTOUT_PIN_8  AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
  83. #define AFIO_EVENTOUT_PIN_9  AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
  84. #define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
  85. #define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
  86. #define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
  87. #define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
  88. #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
  89. #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
  90.  
  91. #define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
  92.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
  93.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
  94.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
  95.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
  96.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
  97.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
  98.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
  99.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
  100.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
  101.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
  102.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
  103.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
  104.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
  105.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
  106.                                        ((__PIN__) == AFIO_EVENTOUT_PIN_15))
  107. /**
  108.   * @}
  109.   */
  110.  
  111. /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
  112.   * @{
  113.   */
  114.  
  115. #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
  116. #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
  117. #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
  118. #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
  119. #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
  120.  
  121. #define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
  122.                                          ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
  123.                                          ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
  124.                                          ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
  125.                                          ((__PORT__) == AFIO_EVENTOUT_PORT_E))
  126. /**
  127.   * @}
  128.   */
  129.  
  130. /**
  131.   * @}
  132.   */
  133.  
  134. /** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
  135.   * @brief This section propose definition to remap the alternate function to some other port/pins.
  136.   * @{
  137.   */
  138.  
  139. /**
  140.   * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
  141.   * @note  ENABLE: Remap     (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
  142.   * @retval None
  143.   */
  144. #define __HAL_AFIO_REMAP_SPI1_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
  145.  
  146. /**
  147.   * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
  148.   * @note  DISABLE: No remap (NSS/PA4,  SCK/PA5, MISO/PA6, MOSI/PA7)
  149.   * @retval None
  150.   */
  151. #define __HAL_AFIO_REMAP_SPI1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
  152.  
  153. /**
  154.   * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
  155.   * @note  ENABLE: Remap     (SCL/PB8, SDA/PB9)
  156.   * @retval None
  157.   */
  158. #define __HAL_AFIO_REMAP_I2C1_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
  159.  
  160. /**
  161.   * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
  162.   * @note  DISABLE: No remap (SCL/PB6, SDA/PB7)
  163.   * @retval None
  164.   */
  165. #define __HAL_AFIO_REMAP_I2C1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
  166.  
  167. /**
  168.   * @brief Enable the remapping of USART1 alternate function TX and RX.
  169.   * @note  ENABLE: Remap     (TX/PB6, RX/PB7)
  170.   * @retval None
  171.   */
  172. #define __HAL_AFIO_REMAP_USART1_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
  173.  
  174. /**
  175.   * @brief Disable the remapping of USART1 alternate function TX and RX.
  176.   * @note  DISABLE: No remap (TX/PA9, RX/PA10)
  177.   * @retval None
  178.   */
  179. #define __HAL_AFIO_REMAP_USART1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
  180.  
  181. /**
  182.   * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
  183.   * @note  ENABLE: Remap     (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
  184.   * @retval None
  185.   */
  186. #define __HAL_AFIO_REMAP_USART2_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
  187.  
  188. /**
  189.   * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
  190.   * @note  DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
  191.   * @retval None
  192.   */
  193. #define __HAL_AFIO_REMAP_USART2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
  194.  
  195. /**
  196.   * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
  197.   * @note  ENABLE: Full remap     (TX/PD8,  RX/PD9,  CK/PD10, CTS/PD11, RTS/PD12)
  198.   * @retval None
  199.   */
  200. #define __HAL_AFIO_REMAP_USART3_ENABLE()  MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
  201.  
  202. /**
  203.   * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
  204.   * @note  PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
  205.   * @retval None
  206.   */
  207. #define __HAL_AFIO_REMAP_USART3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_PARTIALREMAP)
  208.  
  209. /**
  210.   * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
  211.   * @note  DISABLE: No remap      (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
  212.   * @retval None
  213.   */
  214. #define __HAL_AFIO_REMAP_USART3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_NOREMAP)
  215.  
  216. /**
  217.   * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
  218.   * @note  ENABLE: Full remap     (ETR/PE7,  CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8,  CH2N/PE10, CH3N/PE12)
  219.   * @retval None
  220.   */
  221. #define __HAL_AFIO_REMAP_TIM1_ENABLE()  MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
  222.  
  223. /**
  224.   * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
  225.   * @note  PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PA6,  CH1N/PA7,  CH2N/PB0,  CH3N/PB1)
  226.   * @retval None
  227.   */
  228. #define __HAL_AFIO_REMAP_TIM1_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP)
  229.  
  230. /**
  231.   * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
  232.   * @note  DISABLE: No remap      (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
  233.   * @retval None
  234.   */
  235. #define __HAL_AFIO_REMAP_TIM1_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_NOREMAP)
  236.  
  237. /**
  238.   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
  239.   * @note  ENABLE: Full remap       (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
  240.   * @retval None
  241.   */
  242. #define __HAL_AFIO_REMAP_TIM2_ENABLE()    MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
  243.  
  244. /**
  245.   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
  246.   * @note  PARTIAL_2: Partial remap (CH1/ETR/PA0,  CH2/PA1, CH3/PB10, CH4/PB11)
  247.   * @retval None
  248.   */
  249. #define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2)
  250.  
  251. /**
  252.   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
  253.   * @note  PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2,  CH4/PA3)
  254.   * @retval None
  255.   */
  256. #define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1)
  257.  
  258. /**
  259.   * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
  260.   * @note  DISABLE: No remap        (CH1/ETR/PA0,  CH2/PA1, CH3/PA2,  CH4/PA3)
  261.   * @retval None
  262.   */
  263. #define __HAL_AFIO_REMAP_TIM2_DISABLE()   MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_NOREMAP)
  264.  
  265. /**
  266.   * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
  267.   * @note  ENABLE: Full remap     (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
  268.   * @note  TIM3_ETR on PE0 is not re-mapped.
  269.   * @retval None
  270.   */
  271. #define __HAL_AFIO_REMAP_TIM3_ENABLE()  MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
  272.  
  273. /**
  274.   * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
  275.   * @note  PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
  276.   * @note  TIM3_ETR on PE0 is not re-mapped.
  277.   * @retval None
  278.   */
  279. #define __HAL_AFIO_REMAP_TIM3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP)
  280.  
  281. /**
  282.   * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
  283.   * @note  DISABLE: No remap      (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
  284.   * @note  TIM3_ETR on PE0 is not re-mapped.
  285.   * @retval None
  286.   */
  287. #define __HAL_AFIO_REMAP_TIM3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_NOREMAP)
  288.  
  289. /**
  290.   * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
  291.   * @note  ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
  292.   * @note  TIM4_ETR on PE0 is not re-mapped.
  293.   * @retval None
  294.   */
  295. #define __HAL_AFIO_REMAP_TIM4_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
  296.  
  297. /**
  298.   * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
  299.   * @note  DISABLE: No remap  (TIM4_CH1/PB6,  TIM4_CH2/PB7,  TIM4_CH3/PB8,  TIM4_CH4/PB9)
  300.   * @note  TIM4_ETR on PE0 is not re-mapped.
  301.   * @retval None
  302.   */
  303. #define __HAL_AFIO_REMAP_TIM4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
  304.  
  305. #if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
  306.  
  307. /**
  308.   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
  309.   * @note  CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
  310.   * @retval None
  311.   */
  312. #define __HAL_AFIO_REMAP_CAN1_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP1)
  313.  
  314. /**
  315.   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
  316.   * @note  CASE 2: CAN_RX mapped to PB8,  CAN_TX mapped to PB9 (not available on 36-pin package)
  317.   * @retval None
  318.   */
  319. #define __HAL_AFIO_REMAP_CAN1_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP2)
  320.  
  321. /**
  322.   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
  323.   * @note  CASE 3: CAN_RX mapped to PD0,  CAN_TX mapped to PD1
  324.   * @retval None
  325.   */
  326. #define __HAL_AFIO_REMAP_CAN1_3() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP3)
  327. #endif
  328.  
  329. /**
  330.   * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
  331.   *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
  332.   *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
  333.   *        on 100-pin and 144-pin packages, no need for remapping).
  334.   * @note  ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
  335.   * @retval None
  336.   */
  337. #define __HAL_AFIO_REMAP_PD01_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
  338.  
  339. /**
  340.   * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
  341.   *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
  342.   *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
  343.   *        on 100-pin and 144-pin packages, no need for remapping).
  344.   * @note  DISABLE: No remapping of PD0 and PD1
  345.   * @retval None
  346.   */
  347. #define __HAL_AFIO_REMAP_PD01_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
  348.  
  349. #if defined(AFIO_MAPR_TIM5CH4_IREMAP)
  350. /**
  351.   * @brief Enable the remapping of TIM5CH4.
  352.   * @note  ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
  353.   * @note  This function is available only in high density value line devices.
  354.   * @retval None
  355.   */
  356. #define __HAL_AFIO_REMAP_TIM5CH4_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
  357.  
  358. /**
  359.   * @brief Disable the remapping of TIM5CH4.
  360.   * @note  DISABLE: TIM5_CH4 is connected to PA3
  361.   * @note  This function is available only in high density value line devices.
  362.   * @retval None
  363.   */
  364. #define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
  365. #endif
  366.  
  367. #if defined(AFIO_MAPR_ETH_REMAP)
  368. /**
  369.   * @brief Enable the remapping of Ethernet MAC connections with the PHY.
  370.   * @note  ENABLE: Remap     (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
  371.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  372.   * @retval None
  373.   */
  374. #define __HAL_AFIO_REMAP_ETH_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
  375.  
  376. /**
  377.   * @brief Disable the remapping of Ethernet MAC connections with the PHY.
  378.   * @note  DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5,  RXD2/PB0,  RXD3/PB1)
  379.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  380.   * @retval None
  381.   */
  382. #define __HAL_AFIO_REMAP_ETH_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
  383. #endif
  384.  
  385. #if defined(AFIO_MAPR_CAN2_REMAP)
  386.  
  387. /**
  388.   * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
  389.   * @note  ENABLE: Remap     (CAN2_RX/PB5,  CAN2_TX/PB6)
  390.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  391.   * @retval None
  392.   */
  393. #define __HAL_AFIO_REMAP_CAN2_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
  394.  
  395. /**
  396.   * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
  397.   * @note  DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
  398.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  399.   * @retval None
  400.   */
  401. #define __HAL_AFIO_REMAP_CAN2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
  402. #endif
  403.  
  404. #if defined(AFIO_MAPR_MII_RMII_SEL)
  405. /**
  406.   * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
  407.   * @note  ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
  408.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  409.   * @retval None
  410.   */
  411. #define __HAL_AFIO_ETH_RMII() SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
  412.  
  413. /**
  414.   * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
  415.   * @note  ETH_MII: Configure Ethernet MAC for connection with an MII PHY
  416.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  417.   * @retval None
  418.   */
  419. #define __HAL_AFIO_ETH_MII()  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
  420. #endif
  421.  
  422. /**
  423.   * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
  424.   * @note  ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
  425.   * @retval None
  426.   */
  427. #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
  428.  
  429. /**
  430.   * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
  431.   * @note  DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
  432.   * @retval None
  433.   */
  434. #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
  435.  
  436. /**
  437.   * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
  438.   * @note  ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
  439.   * @retval None
  440.   */
  441. #define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
  442.  
  443. /**
  444.   * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
  445.   * @note  DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
  446.   * @retval None
  447.   */
  448. #define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
  449.  
  450. #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
  451.  
  452. /**
  453.   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
  454.   * @note  ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
  455.   * @retval None
  456.   */
  457. #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
  458.  
  459. /**
  460.   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
  461.   * @note  DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
  462.   * @retval None
  463.   */
  464. #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
  465. #endif
  466.  
  467. #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
  468.  
  469. /**
  470.   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
  471.   * @note  ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
  472.   * @retval None
  473.   */
  474. #define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
  475.  
  476. /**
  477.   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
  478.   * @note  DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
  479.   * @retval None
  480.   */
  481. #define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
  482. #endif
  483.  
  484. /**
  485.   * @brief Enable the Serial wire JTAG configuration
  486.   * @note  ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
  487.   * @retval None
  488.   */
  489. #define __HAL_AFIO_REMAP_SWJ_ENABLE()   MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET)
  490.  
  491. /**
  492.   * @brief Enable the Serial wire JTAG configuration
  493.   * @note  NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
  494.   * @retval None
  495.   */
  496. #define __HAL_AFIO_REMAP_SWJ_NONJTRST() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST)
  497.  
  498. /**
  499.   * @brief Enable the Serial wire JTAG configuration
  500.   * @note  NOJTAG: JTAG-DP Disabled and SW-DP Enabled
  501.   * @retval None
  502.   */
  503. #define __HAL_AFIO_REMAP_SWJ_NOJTAG()   MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
  504.  
  505. /**
  506.   * @brief Disable the Serial wire JTAG configuration
  507.   * @note  DISABLE: JTAG-DP Disabled and SW-DP Disabled
  508.   * @retval None
  509.   */
  510. #define __HAL_AFIO_REMAP_SWJ_DISABLE()  MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE)
  511.  
  512. #if defined(AFIO_MAPR_SPI3_REMAP)
  513.  
  514. /**
  515.   * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
  516.   * @note  ENABLE: Remap     (SPI3_NSS-I2S3_WS/PA4,  SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
  517.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  518.   * @retval None
  519.   */
  520. #define __HAL_AFIO_REMAP_SPI3_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
  521.  
  522. /**
  523.   * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
  524.   * @note  DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3,  SPI3_MISO/PB4,  SPI3_MOSI-I2S3_SD/PB5).
  525.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  526.   * @retval None
  527.   */
  528. #define __HAL_AFIO_REMAP_SPI3_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
  529. #endif
  530.  
  531. #if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
  532.  
  533. /**
  534.   * @brief Control of TIM2_ITR1 internal mapping.
  535.   * @note  TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
  536.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  537.   * @retval None
  538.   */
  539. #define __HAL_AFIO_TIM2ITR1_TO_USB() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
  540.  
  541. /**
  542.   * @brief Control of TIM2_ITR1 internal mapping.
  543.   * @note  TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
  544.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  545.   * @retval None
  546.   */
  547. #define __HAL_AFIO_TIM2ITR1_TO_ETH() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
  548. #endif
  549.  
  550. #if defined(AFIO_MAPR_PTP_PPS_REMAP)
  551.  
  552. /**
  553.   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
  554.   * @note  ENABLE: PTP_PPS is output on PB5 pin.
  555.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  556.   * @retval None
  557.   */
  558. #define __HAL_AFIO_ETH_PTP_PPS_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
  559.  
  560. /**
  561.   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
  562.   * @note  DISABLE: PTP_PPS not output on PB5 pin.
  563.   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
  564.   * @retval None
  565.   */
  566. #define __HAL_AFIO_ETH_PTP_PPS_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
  567. #endif
  568.  
  569. #if defined(AFIO_MAPR2_TIM9_REMAP)
  570.  
  571. /**
  572.   * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
  573.   * @note  ENABLE: Remap     (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
  574.   * @retval None
  575.   */
  576. #define __HAL_AFIO_REMAP_TIM9_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
  577.  
  578. /**
  579.   * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
  580.   * @note  DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
  581.   * @retval None
  582.   */
  583. #define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
  584. #endif
  585.  
  586. #if defined(AFIO_MAPR2_TIM10_REMAP)
  587.  
  588. /**
  589.   * @brief Enable the remapping of TIM10_CH1.
  590.   * @note  ENABLE: Remap     (TIM10_CH1 on PF6).
  591.   * @retval None
  592.   */
  593. #define __HAL_AFIO_REMAP_TIM10_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
  594.  
  595. /**
  596.   * @brief Disable the remapping of TIM10_CH1.
  597.   * @note  DISABLE: No remap (TIM10_CH1 on PB8).
  598.   * @retval None
  599.   */
  600. #define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
  601. #endif
  602.  
  603. #if defined(AFIO_MAPR2_TIM11_REMAP)
  604. /**
  605.   * @brief Enable the remapping of TIM11_CH1.
  606.   * @note  ENABLE: Remap     (TIM11_CH1 on PF7).
  607.   * @retval None
  608.   */
  609. #define __HAL_AFIO_REMAP_TIM11_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
  610.  
  611. /**
  612.   * @brief Disable the remapping of TIM11_CH1.
  613.   * @note  DISABLE: No remap (TIM11_CH1 on PB9).
  614.   * @retval None
  615.   */
  616. #define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
  617. #endif
  618.  
  619. #if defined(AFIO_MAPR2_TIM13_REMAP)
  620.  
  621. /**
  622.   * @brief Enable the remapping of TIM13_CH1.
  623.   * @note  ENABLE: Remap     STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
  624.   * @retval None
  625.   */
  626. #define __HAL_AFIO_REMAP_TIM13_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
  627.  
  628. /**
  629.   * @brief Disable the remapping of TIM13_CH1.
  630.   * @note  DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
  631.   * @retval None
  632.   */
  633. #define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
  634. #endif
  635.  
  636. #if defined(AFIO_MAPR2_TIM14_REMAP)
  637.  
  638. /**
  639.   * @brief Enable the remapping of TIM14_CH1.
  640.   * @note  ENABLE: Remap     STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
  641.   * @retval None
  642.   */
  643. #define __HAL_AFIO_REMAP_TIM14_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
  644.  
  645. /**
  646.   * @brief Disable the remapping of TIM14_CH1.
  647.   * @note  DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
  648.   * @retval None
  649.   */
  650. #define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
  651. #endif
  652.  
  653. #if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
  654.  
  655. /**
  656.   * @brief Controls the use of the optional FSMC_NADV signal.
  657.   * @note  DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
  658.   * @retval None
  659.   */
  660. #define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
  661.  
  662. /**
  663.   * @brief Controls the use of the optional FSMC_NADV signal.
  664.   * @note  CONNECTED: The NADV signal is connected to the output (default).
  665.   * @retval None
  666.   */
  667. #define __HAL_AFIO_FSMCNADV_CONNECTED()    CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
  668. #endif
  669.  
  670. #if defined(AFIO_MAPR2_TIM15_REMAP)
  671.  
  672. /**
  673.   * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
  674.   * @note  ENABLE: Remap     (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
  675.   * @retval None
  676.   */
  677. #define __HAL_AFIO_REMAP_TIM15_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
  678.  
  679. /**
  680.   * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
  681.   * @note  DISABLE: No remap (TIM15_CH1 on PA2  and TIM15_CH2 on PA3).
  682.   * @retval None
  683.   */
  684. #define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
  685. #endif
  686.  
  687. #if defined(AFIO_MAPR2_TIM16_REMAP)
  688.  
  689. /**
  690.   * @brief Enable the remapping of TIM16_CH1.
  691.   * @note  ENABLE: Remap     (TIM16_CH1 on PA6).
  692.   * @retval None
  693.   */
  694. #define __HAL_AFIO_REMAP_TIM16_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
  695.  
  696. /**
  697.   * @brief Disable the remapping of TIM16_CH1.
  698.   * @note  DISABLE: No remap (TIM16_CH1 on PB8).
  699.   * @retval None
  700.   */
  701. #define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
  702. #endif
  703.  
  704. #if defined(AFIO_MAPR2_TIM17_REMAP)
  705.  
  706. /**
  707.   * @brief Enable the remapping of TIM17_CH1.
  708.   * @note  ENABLE: Remap     (TIM17_CH1 on PA7).
  709.   * @retval None
  710.   */
  711. #define __HAL_AFIO_REMAP_TIM17_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
  712.  
  713. /**
  714.   * @brief Disable the remapping of TIM17_CH1.
  715.   * @note  DISABLE: No remap (TIM17_CH1 on PB9).
  716.   * @retval None
  717.   */
  718. #define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
  719. #endif
  720.  
  721. #if defined(AFIO_MAPR2_CEC_REMAP)
  722.  
  723. /**
  724.   * @brief Enable the remapping of CEC.
  725.   * @note  ENABLE: Remap     (CEC on PB10).
  726.   * @retval None
  727.   */
  728. #define __HAL_AFIO_REMAP_CEC_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
  729.  
  730. /**
  731.   * @brief Disable the remapping of CEC.
  732.   * @note  DISABLE: No remap (CEC on PB8).
  733.   * @retval None
  734.   */
  735. #define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
  736. #endif
  737.  
  738. #if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
  739.  
  740. /**
  741.   * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
  742.   * @note  ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
  743.   * @retval None
  744.   */
  745. #define __HAL_AFIO_REMAP_TIM1DMA_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
  746.  
  747. /**
  748.   * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
  749.   * @note  DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
  750.   * @retval None
  751.   */
  752. #define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
  753. #endif
  754.  
  755. #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
  756.  
  757. /**
  758.   * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
  759.   * @note  ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
  760.   * @retval None
  761.   */
  762. #define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
  763.  
  764. /**
  765.   * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
  766.   * @note  DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
  767.   * @retval None
  768.   */
  769. #define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
  770. #endif
  771.  
  772. #if defined(AFIO_MAPR2_TIM12_REMAP)
  773.  
  774. /**
  775.   * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
  776.   * @note  ENABLE: Remap     (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
  777.   * @note  This bit is available only in high density value line devices.
  778.   * @retval None
  779.   */
  780. #define __HAL_AFIO_REMAP_TIM12_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
  781.  
  782. /**
  783.   * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
  784.   * @note  DISABLE: No remap (TIM12_CH1 on PC4  and TIM12_CH2 on PC5).
  785.   * @note  This bit is available only in high density value line devices.
  786.   * @retval None
  787.   */
  788. #define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
  789. #endif
  790.  
  791. #if defined(AFIO_MAPR2_MISC_REMAP)
  792.  
  793. /**
  794.   * @brief Miscellaneous features remapping.
  795.   *        This bit is set and cleared by software. It controls miscellaneous features.
  796.   *        The DMA2 channel 5 interrupt position in the vector table.
  797.   *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
  798.   * @note  ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
  799.   *        selected as DAC Trigger 3, TIM15 triggers TIM1/3.
  800.   * @note  This bit is available only in high density value line devices.
  801.   * @retval None
  802.   */
  803. #define __HAL_AFIO_REMAP_MISC_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
  804.  
  805. /**
  806.   * @brief Miscellaneous features remapping.
  807.   *        This bit is set and cleared by software. It controls miscellaneous features.
  808.   *        The DMA2 channel 5 interrupt position in the vector table.
  809.   *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
  810.   * @note  DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
  811.   *        event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
  812.   * @note  This bit is available only in high density value line devices.
  813.   * @retval None
  814.   */
  815. #define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
  816. #endif
  817.  
  818. /**
  819.   * @}
  820.   */
  821.  
  822. /**
  823.   * @}
  824.   */
  825.  
  826. /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
  827.   * @{
  828.   */
  829. #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
  830. #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
  831.                                    ((__GPIOx__) == (GPIOB))? 1U :\
  832.                                    ((__GPIOx__) == (GPIOC))? 2U :3U)
  833. #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
  834. #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
  835.                                    ((__GPIOx__) == (GPIOB))? 1U :\
  836.                                    ((__GPIOx__) == (GPIOC))? 2U :\
  837.                                    ((__GPIOx__) == (GPIOD))? 3U :4U)
  838. #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
  839. #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
  840.                                    ((__GPIOx__) == (GPIOB))? 1U :\
  841.                                    ((__GPIOx__) == (GPIOC))? 2U :\
  842.                                    ((__GPIOx__) == (GPIOD))? 3U :\
  843.                                    ((__GPIOx__) == (GPIOE))? 4U :\
  844.                                    ((__GPIOx__) == (GPIOF))? 5U :6U)
  845. #endif
  846.  
  847. /**
  848.   * @}
  849.   */
  850.  
  851. /* Exported macro ------------------------------------------------------------*/
  852. /* Exported functions --------------------------------------------------------*/
  853.  
  854. /** @addtogroup GPIOEx_Exported_Functions
  855.   * @{
  856.   */
  857.  
  858. /** @addtogroup GPIOEx_Exported_Functions_Group1
  859.   * @{
  860.   */
  861. void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
  862. void HAL_GPIOEx_EnableEventout(void);
  863. void HAL_GPIOEx_DisableEventout(void);
  864.  
  865. /**
  866.   * @}
  867.   */
  868.  
  869. /**
  870.   * @}
  871.   */
  872.  
  873. /**
  874.   * @}
  875.   */
  876.  
  877. /**
  878.   * @}
  879.   */
  880.  
  881. #ifdef __cplusplus
  882. }
  883. #endif
  884.  
  885. #endif /* __STM32F1xx_HAL_GPIO_EX_H */
  886.  
  887. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  888.