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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_dma.h
  4.   * @author  MCD Application Team
  5.   * @version V1.0.4
  6.   * @date    29-April-2016
  7.   * @brief   Header file of DMA HAL module.
  8.   ******************************************************************************
  9.   * @attention
  10.   *
  11.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  12.   *
  13.   * Redistribution and use in source and binary forms, with or without modification,
  14.   * are permitted provided that the following conditions are met:
  15.   *   1. Redistributions of source code must retain the above copyright notice,
  16.   *      this list of conditions and the following disclaimer.
  17.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18.   *      this list of conditions and the following disclaimer in the documentation
  19.   *      and/or other materials provided with the distribution.
  20.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21.   *      may be used to endorse or promote products derived from this software
  22.   *      without specific prior written permission.
  23.   *
  24.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34.   *
  35.   ******************************************************************************
  36.   */
  37.  
  38. /* Define to prevent recursive inclusion -------------------------------------*/
  39. #ifndef __STM32F1xx_HAL_DMA_H
  40. #define __STM32F1xx_HAL_DMA_H
  41.  
  42. #ifdef __cplusplus
  43.  extern "C" {
  44. #endif
  45.  
  46. /* Includes ------------------------------------------------------------------*/
  47. #include "stm32f1xx_hal_def.h"
  48.  
  49. /** @addtogroup STM32F1xx_HAL_Driver
  50.   * @{
  51.   */
  52.  
  53. /** @addtogroup DMA
  54.   * @{
  55.   */
  56.  
  57. /* Exported types ------------------------------------------------------------*/
  58.  
  59. /** @defgroup DMA_Exported_Types DMA Exported Types
  60.   * @{
  61.   */
  62.    
  63. /**
  64.   * @brief  DMA Configuration Structure definition
  65.   */
  66. typedef struct
  67. {
  68.   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
  69.                                            from memory to memory or from peripheral to memory.
  70.                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
  71.  
  72.   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
  73.                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
  74.                                
  75.   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
  76.                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
  77.  
  78.   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
  79.                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
  80.  
  81.   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
  82.                                            This parameter can be a value of @ref DMA_Memory_data_size */
  83.                                
  84.   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
  85.                                            This parameter can be a value of @ref DMA_mode
  86.                                            @note The circular buffer mode cannot be used if the memory-to-memory
  87.                                                  data transfer is configured on the selected Channel */
  88.  
  89.   uint32_t Priority;                   /*!< Specifies the software priority for the DMAy Channelx.
  90.                                             This parameter can be a value of @ref DMA_Priority_level */
  91. } DMA_InitTypeDef;
  92.  
  93. /**
  94.   * @brief DMA Configuration enumeration values definition
  95.   */  
  96. typedef enum
  97. {
  98.   DMA_MODE            = 0,      /*!< Control related DMA mode Parameter in DMA_InitTypeDef        */
  99.   DMA_PRIORITY        = 1,      /*!< Control related priority level Parameter in DMA_InitTypeDef  */
  100.  
  101. } DMA_ControlTypeDef;
  102.  
  103. /**
  104.   * @brief  HAL DMA State structures definition  
  105.   */
  106. typedef enum
  107. {
  108.   HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
  109.   HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use   */
  110.   HAL_DMA_STATE_READY_HALF        = 0x11,  /*!< DMA Half process success            */
  111.   HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
  112.   HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
  113.   HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
  114. }HAL_DMA_StateTypeDef;
  115.  
  116. /**
  117.   * @brief  HAL DMA Error Code structure definition
  118.   */
  119. typedef enum
  120. {
  121.   HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
  122.   HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
  123. }HAL_DMA_LevelCompleteTypeDef;
  124.  
  125. /**
  126.   * @brief  DMA handle Structure definition
  127.   */
  128. typedef struct __DMA_HandleTypeDef
  129. {
  130.   DMA_Channel_TypeDef   *Instance;                       /*!< Register base address                  */
  131.  
  132.   DMA_InitTypeDef       Init;                            /*!< DMA communication parameters           */
  133.  
  134.   HAL_LockTypeDef       Lock;                            /*!< DMA locking object                     */  
  135.  
  136.   HAL_DMA_StateTypeDef  State;                           /*!< DMA transfer state                     */
  137.  
  138.   void                  *Parent;                                                      /*!< Parent object state                    */  
  139.  
  140.   void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
  141.  
  142.   void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
  143.  
  144.   void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
  145.  
  146.   __IO uint32_t         ErrorCode;                                                    /*!< DMA Error code                         */
  147. } DMA_HandleTypeDef;    
  148. /**
  149.   * @}
  150.   */
  151.  
  152. /* Exported constants --------------------------------------------------------*/
  153.  
  154. /** @defgroup DMA_Exported_Constants DMA Exported Constants
  155.   * @{
  156.   */
  157.  
  158. /** @defgroup DMA_Error_Code DMA Error Code
  159.   * @{
  160.   */
  161.  #define HAL_DMA_ERROR_NONE      ((uint32_t)0x00)    /*!< No error             */
  162.  #define HAL_DMA_ERROR_TE        ((uint32_t)0x01)    /*!< Transfer error       */
  163.  #define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x20)    /*!< Timeout error        */
  164.  
  165. /**
  166.   * @}
  167.   */
  168.  
  169. /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
  170.   * @{
  171.   */
  172. #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)      /*!< Peripheral to memory direction */
  173. #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)     /*!< Memory to peripheral direction */
  174. #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
  175.  
  176. /**
  177.   * @}
  178.   */
  179.  
  180. /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
  181.   * @{
  182.   */
  183. #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)   /*!< Peripheral increment mode Enable */
  184. #define DMA_PINC_DISABLE       ((uint32_t)0x00000000)     /*!< Peripheral increment mode Disable */
  185. /**
  186.   * @}
  187.   */
  188.  
  189. /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
  190.   * @{
  191.   */
  192. #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)   /*!< Memory increment mode Enable  */
  193. #define DMA_MINC_DISABLE        ((uint32_t)0x00000000)     /*!< Memory increment mode Disable */
  194. /**
  195.   * @}
  196.   */
  197.  
  198. /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
  199.   * @{
  200.   */
  201. #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Peripheral data alignment: Byte     */
  202. #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)   /*!< Peripheral data alignment: HalfWord */
  203. #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)   /*!< Peripheral data alignment: Word     */
  204. /**
  205.   * @}
  206.   */
  207.  
  208. /** @defgroup DMA_Memory_data_size DMA Memory data size
  209.   * @{
  210.   */
  211. #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Memory data alignment: Byte     */
  212. #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)   /*!< Memory data alignment: HalfWord */
  213. #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)   /*!< Memory data alignment: Word     */
  214. /**
  215.   * @}
  216.   */
  217.  
  218. /** @defgroup DMA_mode DMA mode
  219.   * @{
  220.   */
  221. #define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
  222. #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */
  223. /**
  224.   * @}
  225.   */
  226.  
  227. /** @defgroup DMA_Priority_level DMA Priority level
  228.   * @{
  229.   */
  230. #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)     /*!< Priority level : Low       */
  231. #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)   /*!< Priority level : Medium    */
  232. #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)   /*!< Priority level : High      */
  233. #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)     /*!< Priority level : Very_High */
  234. /**
  235.   * @}
  236.   */
  237.  
  238.  
  239. /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
  240.   * @{
  241.   */
  242. #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
  243. #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
  244. #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
  245. /**
  246.   * @}
  247.   */
  248.  
  249. /** @defgroup DMA_flag_definitions DMA flag definitions
  250.   * @{
  251.   */
  252. #define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
  253. #define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
  254. #define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
  255. #define DMA_FLAG_TE1                      ((uint32_t)0x00000008)
  256. #define DMA_FLAG_GL2                      ((uint32_t)0x00000010)
  257. #define DMA_FLAG_TC2                      ((uint32_t)0x00000020)
  258. #define DMA_FLAG_HT2                      ((uint32_t)0x00000040)
  259. #define DMA_FLAG_TE2                      ((uint32_t)0x00000080)
  260. #define DMA_FLAG_GL3                      ((uint32_t)0x00000100)
  261. #define DMA_FLAG_TC3                      ((uint32_t)0x00000200)
  262. #define DMA_FLAG_HT3                      ((uint32_t)0x00000400)
  263. #define DMA_FLAG_TE3                      ((uint32_t)0x00000800)
  264. #define DMA_FLAG_GL4                      ((uint32_t)0x00001000)
  265. #define DMA_FLAG_TC4                      ((uint32_t)0x00002000)
  266. #define DMA_FLAG_HT4                      ((uint32_t)0x00004000)
  267. #define DMA_FLAG_TE4                      ((uint32_t)0x00008000)
  268. #define DMA_FLAG_GL5                      ((uint32_t)0x00010000)
  269. #define DMA_FLAG_TC5                      ((uint32_t)0x00020000)
  270. #define DMA_FLAG_HT5                      ((uint32_t)0x00040000)
  271. #define DMA_FLAG_TE5                      ((uint32_t)0x00080000)
  272. #define DMA_FLAG_GL6                      ((uint32_t)0x00100000)
  273. #define DMA_FLAG_TC6                      ((uint32_t)0x00200000)
  274. #define DMA_FLAG_HT6                      ((uint32_t)0x00400000)
  275. #define DMA_FLAG_TE6                      ((uint32_t)0x00800000)
  276. #define DMA_FLAG_GL7                      ((uint32_t)0x01000000)
  277. #define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
  278. #define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
  279. #define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
  280. /**
  281.   * @}
  282.   */
  283.  
  284. /**
  285.   * @}
  286.   */
  287.  
  288.  
  289. /* Exported macro ------------------------------------------------------------*/
  290. /** @defgroup DMA_Exported_Macros DMA Exported Macros
  291.   * @{
  292.   */
  293.  
  294. /** @brief  Reset DMA handle state
  295.   * @param  __HANDLE__: DMA handle.
  296.   * @retval None
  297.   */
  298. #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
  299.  
  300. /**
  301.   * @brief  Enable the specified DMA Channel.
  302.   * @param  __HANDLE__: DMA handle
  303.   * @retval None.
  304.   */
  305. #define __HAL_DMA_ENABLE(__HANDLE__)        (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
  306.  
  307. /**
  308.   * @brief  Disable the specified DMA Channel.
  309.   * @param  __HANDLE__: DMA handle
  310.   * @retval None.
  311.   */
  312. #define __HAL_DMA_DISABLE(__HANDLE__)       (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
  313.  
  314.  
  315. /* Interrupt & Flag management */
  316.  
  317. /**
  318.   * @brief  Enables the specified DMA Channel interrupts.
  319.   * @param  __HANDLE__: DMA handle
  320.   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
  321.   *          This parameter can be any combination of the following values:
  322.   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
  323.   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
  324.   *            @arg DMA_IT_TE:  Transfer error interrupt mask
  325.   * @retval None
  326.   */
  327. #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
  328.  
  329. /**
  330.   * @brief  Disables the specified DMA Channel interrupts.
  331.   * @param  __HANDLE__: DMA handle
  332.   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
  333.   *          This parameter can be any combination of the following values:
  334.   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
  335.   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
  336.   *            @arg DMA_IT_TE:  Transfer error interrupt mask
  337.   * @retval None
  338.   */
  339. #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
  340.  
  341. /**
  342.   * @brief  Checks whether the specified DMA Channel interrupt is enabled or disabled.
  343.   * @param  __HANDLE__: DMA handle
  344.   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
  345.   *          This parameter can be one of the following values:
  346.   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
  347.   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
  348.   *            @arg DMA_IT_TE:  Transfer error interrupt mask
  349.   * @retval The state of DMA_IT (SET or RESET).
  350.   */
  351. #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
  352.  
  353. /**
  354.   * @brief  Returns the number of remaining data units in the current DMAy Channelx transfer.
  355.   * @param  __HANDLE__: DMA handle
  356.   *  
  357.   * @retval The number of remaining data units in the current DMA Channel transfer.
  358.   */
  359. #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
  360.  
  361. /**
  362.   * @}
  363.   */
  364.  
  365. /* Include DMA HAL Extension module */
  366. #include "stm32f1xx_hal_dma_ex.h"  
  367.  
  368. /* Exported functions --------------------------------------------------------*/
  369. /** @addtogroup DMA_Exported_Functions DMA Exported Functions
  370.   * @{
  371.   */
  372.  
  373. /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
  374.   * @{
  375.   */
  376. /* Initialization and de-initialization functions *****************************/
  377. HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
  378. HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
  379. /**
  380.   * @}
  381.   */
  382.  
  383. /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
  384.   * @{
  385.   */
  386. /* IO operation functions *****************************************************/
  387. HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
  388. HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
  389. HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
  390. HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
  391. void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
  392. /**
  393.   * @}
  394.   */
  395.  
  396. /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
  397.   * @{
  398.   */
  399. /* Peripheral State and Error functions ***************************************/
  400. HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
  401. uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
  402. /**
  403.   * @}
  404.   */
  405.  
  406. /**
  407.   * @}
  408.   */
  409.  
  410. /* Private Constants -------------------------------------------------------------*/
  411. /** @defgroup DMA_Private_Constants DMA Private Constants
  412.   * @brief    DMA private defines and constants
  413.   * @{
  414.   */
  415. /**
  416.   * @}
  417.   */
  418.  
  419. /* Private macros ------------------------------------------------------------*/
  420. /** @defgroup DMA_Private_Macros DMA Private Macros
  421.   * @brief    DMA private macros
  422.   * @{
  423.   */
  424.  
  425. #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
  426.  
  427. #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
  428.                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
  429.                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
  430.  
  431. #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
  432.                                             ((STATE) == DMA_PINC_DISABLE))
  433.  
  434. #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
  435.                                         ((STATE) == DMA_MINC_DISABLE))
  436.  
  437. #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
  438.                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
  439.                                            ((SIZE) == DMA_PDATAALIGN_WORD))
  440.  
  441. #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
  442.                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
  443.                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
  444.  
  445. #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
  446.                            ((MODE) == DMA_CIRCULAR))
  447.  
  448. #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
  449.                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
  450.                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
  451.                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
  452.  
  453. /**
  454.   * @}
  455.   */
  456.  
  457. /* Private functions ---------------------------------------------------------*/
  458. /** @defgroup DMA_Private_Functions DMA Private Functions
  459.   * @brief    DMA private  functions
  460.   * @{
  461.   */
  462. /**
  463.   * @}
  464.   */
  465.  
  466. /**
  467.   * @}
  468.   */
  469.  
  470. /**
  471.   * @}
  472.   */
  473.  
  474. #ifdef __cplusplus
  475. }
  476. #endif
  477.  
  478. #endif /* __STM32F1xx_HAL_DMA_H */
  479.  
  480. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  481.