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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_cortex.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of CORTEX HAL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  10.   *
  11.   * Redistribution and use in source and binary forms, with or without modification,
  12.   * are permitted provided that the following conditions are met:
  13.   *   1. Redistributions of source code must retain the above copyright notice,
  14.   *      this list of conditions and the following disclaimer.
  15.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16.   *      this list of conditions and the following disclaimer in the documentation
  17.   *      and/or other materials provided with the distribution.
  18.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19.   *      may be used to endorse or promote products derived from this software
  20.   *      without specific prior written permission.
  21.   *
  22.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32.   *
  33.   ******************************************************************************
  34.   */
  35.  
  36. /* Define to prevent recursive inclusion -------------------------------------*/
  37. #ifndef __STM32F1xx_HAL_CORTEX_H
  38. #define __STM32F1xx_HAL_CORTEX_H
  39.  
  40. #ifdef __cplusplus
  41.  extern "C" {
  42. #endif
  43.  
  44. /* Includes ------------------------------------------------------------------*/
  45. #include "stm32f1xx_hal_def.h"
  46.  
  47. /** @addtogroup STM32F1xx_HAL_Driver
  48.   * @{
  49.   */
  50.  
  51. /** @addtogroup CORTEX
  52.   * @{
  53.   */
  54. /* Exported types ------------------------------------------------------------*/
  55. /** @defgroup CORTEX_Exported_Types Cortex Exported Types
  56.   * @{
  57.   */
  58.  
  59. #if (__MPU_PRESENT == 1U)
  60. /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
  61.   * @brief  MPU Region initialization structure
  62.   * @{
  63.   */
  64. typedef struct
  65. {
  66.   uint8_t                Enable;                /*!< Specifies the status of the region.
  67.                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
  68.   uint8_t                Number;                /*!< Specifies the number of the region to protect.
  69.                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
  70.   uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
  71.   uint8_t                Size;                  /*!< Specifies the size of the region to protect.
  72.                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
  73.   uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
  74.                                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */        
  75.   uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
  76.                                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                
  77.   uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
  78.                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
  79.   uint8_t                DisableExec;           /*!< Specifies the instruction access status.
  80.                                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
  81.   uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
  82.                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
  83.   uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
  84.                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
  85.   uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
  86.                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
  87. }MPU_Region_InitTypeDef;
  88. /**
  89.   * @}
  90.   */
  91. #endif /* __MPU_PRESENT */
  92.  
  93. /**
  94.   * @}
  95.   */
  96.  
  97. /* Exported constants --------------------------------------------------------*/
  98.  
  99. /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
  100.   * @{
  101.   */
  102.  
  103. /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
  104.   * @{
  105.   */
  106. #define NVIC_PRIORITYGROUP_0         0x00000007U /*!< 0 bits for pre-emption priority
  107.                                                       4 bits for subpriority */
  108. #define NVIC_PRIORITYGROUP_1         0x00000006U /*!< 1 bits for pre-emption priority
  109.                                                       3 bits for subpriority */
  110. #define NVIC_PRIORITYGROUP_2         0x00000005U /*!< 2 bits for pre-emption priority
  111.                                                       2 bits for subpriority */
  112. #define NVIC_PRIORITYGROUP_3         0x00000004U /*!< 3 bits for pre-emption priority
  113.                                                       1 bits for subpriority */
  114. #define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority
  115.                                                       0 bits for subpriority */
  116. /**
  117.   * @}
  118.   */
  119.  
  120. /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
  121.   * @{
  122.   */
  123. #define SYSTICK_CLKSOURCE_HCLK_DIV8    0x00000000U
  124. #define SYSTICK_CLKSOURCE_HCLK         0x00000004U
  125.  
  126. /**
  127.   * @}
  128.   */
  129.  
  130. #if (__MPU_PRESENT == 1)
  131. /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
  132.   * @{
  133.   */
  134. #define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
  135. #define  MPU_HARDFAULT_NMI                MPU_CTRL_HFNMIENA_Msk
  136. #define  MPU_PRIVILEGED_DEFAULT           MPU_CTRL_PRIVDEFENA_Msk
  137. #define  MPU_HFNMI_PRIVDEF               (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
  138.  
  139. /**
  140.   * @}
  141.   */
  142.  
  143. /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
  144.   * @{
  145.   */
  146. #define  MPU_REGION_ENABLE     ((uint8_t)0x01)
  147. #define  MPU_REGION_DISABLE    ((uint8_t)0x00)
  148. /**
  149.   * @}
  150.   */
  151.  
  152. /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
  153.   * @{
  154.   */
  155. #define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
  156. #define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
  157. /**
  158.   * @}
  159.   */
  160.  
  161. /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
  162.   * @{
  163.   */
  164. #define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
  165. #define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
  166. /**
  167.   * @}
  168.   */
  169.  
  170. /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
  171.   * @{
  172.   */
  173. #define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
  174. #define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
  175. /**
  176.   * @}
  177.   */
  178.  
  179. /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
  180.   * @{
  181.   */
  182. #define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
  183. #define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
  184. /**
  185.   * @}
  186.   */
  187.  
  188. /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
  189.   * @{
  190.   */
  191. #define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
  192. #define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
  193. #define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
  194. /**
  195.   * @}
  196.   */
  197.  
  198. /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
  199.   * @{
  200.   */
  201. #define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
  202. #define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
  203. #define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
  204. #define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
  205. #define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
  206. #define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
  207. #define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
  208. #define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
  209. #define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
  210. #define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
  211. #define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
  212. #define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
  213. #define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
  214. #define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
  215. #define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
  216. #define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
  217. #define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
  218. #define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
  219. #define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
  220. #define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
  221. #define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
  222. #define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
  223. #define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
  224. #define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
  225. #define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
  226. #define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
  227. #define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
  228. #define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
  229. /**
  230.   * @}
  231.   */
  232.    
  233. /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
  234.   * @{
  235.   */
  236. #define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
  237. #define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
  238. #define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
  239. #define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
  240. #define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
  241. #define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
  242. /**
  243.   * @}
  244.   */
  245.  
  246. /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
  247.   * @{
  248.   */
  249. #define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
  250. #define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
  251. #define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
  252. #define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
  253. #define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
  254. #define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
  255. #define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
  256. #define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
  257. /**
  258.   * @}
  259.   */
  260. #endif /* __MPU_PRESENT */
  261.  
  262. /**
  263.   * @}
  264.   */
  265.  
  266.  
  267. /* Exported Macros -----------------------------------------------------------*/
  268.  
  269. /* Exported functions --------------------------------------------------------*/
  270. /** @addtogroup CORTEX_Exported_Functions
  271.   * @{
  272.   */
  273.  
  274. /** @addtogroup CORTEX_Exported_Functions_Group1
  275.   * @{
  276.   */
  277. /* Initialization and de-initialization functions *****************************/
  278. void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
  279. void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
  280. void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
  281. void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
  282. void HAL_NVIC_SystemReset(void);
  283. uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
  284. /**
  285.   * @}
  286.   */
  287.  
  288. /** @addtogroup CORTEX_Exported_Functions_Group2
  289.   * @{
  290.   */
  291. /* Peripheral Control functions ***********************************************/
  292. uint32_t HAL_NVIC_GetPriorityGrouping(void);
  293. void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
  294. uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
  295. void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
  296. void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
  297. uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
  298. void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
  299. void HAL_SYSTICK_IRQHandler(void);
  300. void HAL_SYSTICK_Callback(void);
  301.  
  302. #if (__MPU_PRESENT == 1U)
  303. void HAL_MPU_Enable(uint32_t MPU_Control);
  304. void HAL_MPU_Disable(void);
  305. void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
  306. #endif /* __MPU_PRESENT */
  307. /**
  308.   * @}
  309.   */
  310.  
  311. /**
  312.   * @}
  313.   */
  314.  
  315. /* Private types -------------------------------------------------------------*/
  316. /* Private variables ---------------------------------------------------------*/
  317. /* Private constants ---------------------------------------------------------*/
  318. /* Private macros ------------------------------------------------------------*/
  319. /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
  320.   * @{
  321.   */
  322. #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
  323.                                        ((GROUP) == NVIC_PRIORITYGROUP_1) || \
  324.                                        ((GROUP) == NVIC_PRIORITYGROUP_2) || \
  325.                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
  326.                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
  327.  
  328. #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
  329.  
  330. #define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
  331.  
  332. #define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= (IRQn_Type)0x00U)
  333.  
  334. #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
  335.                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
  336.  
  337. #if (__MPU_PRESENT == 1U)
  338. #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
  339.                                      ((STATE) == MPU_REGION_DISABLE))
  340.  
  341. #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
  342.                                           ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
  343.  
  344. #define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
  345.                                           ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
  346.  
  347. #define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
  348.                                           ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
  349.  
  350. #define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
  351.                                           ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
  352.  
  353. #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
  354.                                 ((TYPE) == MPU_TEX_LEVEL1)  || \
  355.                                 ((TYPE) == MPU_TEX_LEVEL2))
  356.  
  357. #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
  358.                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
  359.                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
  360.                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
  361.                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
  362.                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))
  363.  
  364. #define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
  365.                                          ((NUMBER) == MPU_REGION_NUMBER1) || \
  366.                                          ((NUMBER) == MPU_REGION_NUMBER2) || \
  367.                                          ((NUMBER) == MPU_REGION_NUMBER3) || \
  368.                                          ((NUMBER) == MPU_REGION_NUMBER4) || \
  369.                                          ((NUMBER) == MPU_REGION_NUMBER5) || \
  370.                                          ((NUMBER) == MPU_REGION_NUMBER6) || \
  371.                                          ((NUMBER) == MPU_REGION_NUMBER7))
  372.  
  373. #define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
  374.                                      ((SIZE) == MPU_REGION_SIZE_64B)   || \
  375.                                      ((SIZE) == MPU_REGION_SIZE_128B)  || \
  376.                                      ((SIZE) == MPU_REGION_SIZE_256B)  || \
  377.                                      ((SIZE) == MPU_REGION_SIZE_512B)  || \
  378.                                      ((SIZE) == MPU_REGION_SIZE_1KB)   || \
  379.                                      ((SIZE) == MPU_REGION_SIZE_2KB)   || \
  380.                                      ((SIZE) == MPU_REGION_SIZE_4KB)   || \
  381.                                      ((SIZE) == MPU_REGION_SIZE_8KB)   || \
  382.                                      ((SIZE) == MPU_REGION_SIZE_16KB)  || \
  383.                                      ((SIZE) == MPU_REGION_SIZE_32KB)  || \
  384.                                      ((SIZE) == MPU_REGION_SIZE_64KB)  || \
  385.                                      ((SIZE) == MPU_REGION_SIZE_128KB) || \
  386.                                      ((SIZE) == MPU_REGION_SIZE_256KB) || \
  387.                                      ((SIZE) == MPU_REGION_SIZE_512KB) || \
  388.                                      ((SIZE) == MPU_REGION_SIZE_1MB)   || \
  389.                                      ((SIZE) == MPU_REGION_SIZE_2MB)   || \
  390.                                      ((SIZE) == MPU_REGION_SIZE_4MB)   || \
  391.                                      ((SIZE) == MPU_REGION_SIZE_8MB)   || \
  392.                                      ((SIZE) == MPU_REGION_SIZE_16MB)  || \
  393.                                      ((SIZE) == MPU_REGION_SIZE_32MB)  || \
  394.                                      ((SIZE) == MPU_REGION_SIZE_64MB)  || \
  395.                                      ((SIZE) == MPU_REGION_SIZE_128MB) || \
  396.                                      ((SIZE) == MPU_REGION_SIZE_256MB) || \
  397.                                      ((SIZE) == MPU_REGION_SIZE_512MB) || \
  398.                                      ((SIZE) == MPU_REGION_SIZE_1GB)   || \
  399.                                      ((SIZE) == MPU_REGION_SIZE_2GB)   || \
  400.                                      ((SIZE) == MPU_REGION_SIZE_4GB))
  401.  
  402. #define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
  403. #endif /* __MPU_PRESENT */
  404.  
  405. /**                                                                          
  406.   * @}                                                                  
  407.   */
  408.  
  409. /* Private functions ---------------------------------------------------------*/
  410.  
  411. /**
  412.   * @}
  413.   */
  414.  
  415. /**
  416.   * @}
  417.   */
  418.  
  419. #ifdef __cplusplus
  420. }
  421. #endif
  422.  
  423. #endif /* __STM32F1xx_HAL_CORTEX_H */
  424.  
  425.  
  426. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  427.