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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_cec.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of CEC HAL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  10.   *
  11.   * Redistribution and use in source and binary forms, with or without modification,
  12.   * are permitted provided that the following conditions are met:
  13.   *   1. Redistributions of source code must retain the above copyright notice,
  14.   *      this list of conditions and the following disclaimer.
  15.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16.   *      this list of conditions and the following disclaimer in the documentation
  17.   *      and/or other materials provided with the distribution.
  18.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19.   *      may be used to endorse or promote products derived from this software
  20.   *      without specific prior written permission.
  21.   *
  22.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32.   *
  33.   ******************************************************************************  
  34.   */
  35.  
  36. /* Define to prevent recursive inclusion -------------------------------------*/
  37. #ifndef __STM32F1xx_HAL_CEC_H
  38. #define __STM32F1xx_HAL_CEC_H
  39.  
  40. #ifdef __cplusplus
  41.  extern "C" {
  42. #endif
  43.  
  44. #if defined(STM32F100xB) || defined(STM32F100xE)
  45. /* Includes ------------------------------------------------------------------*/
  46. #include "stm32f1xx_hal_def.h"
  47.  
  48. /** @addtogroup STM32F1xx_HAL_Driver
  49.   * @{
  50.   */
  51.  
  52. /** @addtogroup CEC
  53.   * @{
  54.   */
  55.  
  56. /* Exported types ------------------------------------------------------------*/
  57. /** @defgroup CEC_Exported_Types CEC Exported Types
  58.   * @{
  59.   */
  60. /**
  61.   * @brief CEC Init Structure definition  
  62.   */
  63. typedef struct
  64. {
  65.   uint32_t TimingErrorFree; /*!< Configures the CEC Bit Timing Error Mode.
  66.                                  This parameter can be a value of @ref CEC_BitTimingErrorMode */
  67.   uint32_t PeriodErrorFree; /*!< Configures the CEC Bit Period Error Mode.
  68.                                  This parameter can be a value of @ref CEC_BitPeriodErrorMode */
  69.   uint16_t  OwnAddress;     /*!< Own addresses configuration
  70.                                  This parameter can be a value of @ref CEC_OWN_ADDRESS */
  71.   uint8_t  *RxBuffer;       /*!< CEC Rx buffer pointeur */
  72. }CEC_InitTypeDef;
  73.  
  74. /**
  75.   * @brief HAL CEC State structures definition
  76.   * @note  HAL CEC State value is a combination of 2 different substates: gState and RxState.
  77.   *        - gState contains CEC state information related to global Handle management
  78.   *          and also information related to Tx operations.
  79.   *          gState value coding follow below described bitmap :
  80.   *          b7 (not used)
  81.   *             x  : Should be set to 0
  82.   *          b6  Error information
  83.   *             0  : No Error
  84.   *             1  : Error
  85.   *          b5     IP initilisation status
  86.   *             0  : Reset (IP not initialized)
  87.   *             1  : Init done (IP initialized. HAL CEC Init function already called)
  88.   *          b4-b3  (not used)
  89.   *             xx : Should be set to 00
  90.   *          b2     Intrinsic process state
  91.   *             0  : Ready
  92.   *             1  : Busy (IP busy with some configuration or internal operations)
  93.   *          b1     (not used)
  94.   *             x  : Should be set to 0
  95.   *          b0     Tx state
  96.   *             0  : Ready (no Tx operation ongoing)
  97.   *             1  : Busy (Tx operation ongoing)
  98.   *        - RxState contains information related to Rx operations.
  99.   *          RxState value coding follow below described bitmap :
  100.   *          b7-b6  (not used)
  101.   *             xx : Should be set to 00
  102.   *          b5     IP initilisation status
  103.   *             0  : Reset (IP not initialized)
  104.   *             1  : Init done (IP initialized)
  105.   *          b4-b2  (not used)
  106.   *            xxx : Should be set to 000
  107.   *          b1     Rx state
  108.   *             0  : Ready (no Rx operation ongoing)
  109.   *             1  : Busy (Rx operation ongoing)
  110.   *          b0     (not used)
  111.   *             x  : Should be set to 0.  
  112.   */
  113. typedef enum
  114. {
  115.   HAL_CEC_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
  116.                                                    Value is allowed for gState and RxState             */
  117.   HAL_CEC_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
  118.                                                    Value is allowed for gState and RxState             */
  119.   HAL_CEC_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
  120.                                                    Value is allowed for gState only                    */
  121.   HAL_CEC_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
  122.                                                    Value is allowed for RxState only                   */
  123.   HAL_CEC_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
  124.                                                    Value is allowed for gState only                    */
  125.   HAL_CEC_STATE_BUSY_RX_TX        = 0x23U,    /*!< an internal process is ongoing
  126.                                                    Value is allowed for gState only                    */
  127.   HAL_CEC_STATE_ERROR             = 0x60U     /*!< Error Value is allowed for gState only              */
  128. }HAL_CEC_StateTypeDef;
  129.  
  130. /**
  131.   * @brief  CEC handle Structure definition  
  132.   */  
  133. typedef struct
  134. {
  135.   CEC_TypeDef             *Instance;      /*!< CEC registers base address */
  136.  
  137.   CEC_InitTypeDef         Init;           /*!< CEC communication parameters */
  138.  
  139.   uint8_t                 *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer */
  140.  
  141.   uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter */
  142.  
  143.   uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only */
  144.  
  145.   HAL_LockTypeDef         Lock;           /*!< Locking object */
  146.  
  147.   HAL_CEC_StateTypeDef    gState;         /*!< CEC state information related to global Handle management
  148.                                                and also related to Tx operations.
  149.                                                This parameter can be a value of @ref HAL_CEC_StateTypeDef */
  150.  
  151.   HAL_CEC_StateTypeDef    RxState;        /*!< CEC state information related to Rx operations.
  152.                                                This parameter can be a value of @ref HAL_CEC_StateTypeDef */
  153.  
  154.   uint32_t                ErrorCode;      /*!< For errors handling purposes, copy of ISR register
  155.                                                in case error is reported */    
  156. }CEC_HandleTypeDef;
  157. /**
  158.   * @}
  159.   */
  160.  
  161. /* Exported constants --------------------------------------------------------*/
  162. /** @defgroup CEC_Exported_Constants CEC Exported Constants
  163.   * @{
  164.   */
  165.  
  166. /** @defgroup CEC_Error_Code CEC Error Code
  167.   * @{
  168.   */
  169. #define HAL_CEC_ERROR_NONE   0x00000000U    /*!< no error */
  170. #define HAL_CEC_ERROR_BTE    CEC_ESR_BTE    /*!< Bit Timing Error */
  171. #define HAL_CEC_ERROR_BPE    CEC_ESR_BPE    /*!< Bit Period Error */
  172. #define HAL_CEC_ERROR_RBTFE  CEC_ESR_RBTFE  /*!< Rx Block Transfer Finished Error */
  173. #define HAL_CEC_ERROR_SBE    CEC_ESR_SBE    /*!< Start Bit Error */
  174. #define HAL_CEC_ERROR_ACKE   CEC_ESR_ACKE   /*!< Block Acknowledge Error */
  175. #define HAL_CEC_ERROR_LINE   CEC_ESR_LINE   /*!< Line Error */
  176. #define HAL_CEC_ERROR_TBTFE  CEC_ESR_TBTFE  /*!< Tx Block Transfer Finished Error */
  177. /**
  178.   * @}
  179.   */
  180.  
  181. /** @defgroup CEC_BitTimingErrorMode Bit Timing Error Mode
  182.   * @{
  183.   */
  184. #define CEC_BIT_TIMING_ERROR_MODE_STANDARD  0x00000000U      /*!< Bit timing error Standard Mode */
  185. #define CEC_BIT_TIMING_ERROR_MODE_ERRORFREE CEC_CFGR_BTEM    /*!< Bit timing error Free Mode */
  186. /**
  187.   * @}
  188.   */
  189.  
  190. /** @defgroup CEC_BitPeriodErrorMode Bit Period Error Mode
  191.   * @{
  192.   */
  193. #define CEC_BIT_PERIOD_ERROR_MODE_STANDARD 0x00000000U      /*!< Bit period error Standard Mode */
  194. #define CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE CEC_CFGR_BPEM    /*!< Bit period error Flexible Mode */
  195. /**
  196.   * @}
  197.   */
  198.  
  199. /** @defgroup CEC_Initiator_Position   CEC Initiator logical address position in message header    
  200.   * @{
  201.   */
  202. #define CEC_INITIATOR_LSB_POS                  4U
  203. /**
  204.   * @}
  205.   */
  206.  
  207. /** @defgroup CEC_OWN_ADDRESS   CEC Own Address    
  208.   * @{
  209.   */
  210. #define CEC_OWN_ADDRESS_NONE            CEC_OWN_ADDRESS_0    /* Reset value */
  211. #define CEC_OWN_ADDRESS_0              ((uint16_t)0x0000U)   /* Logical Address 0 */
  212. #define CEC_OWN_ADDRESS_1              ((uint16_t)0x0001U)   /* Logical Address 1 */
  213. #define CEC_OWN_ADDRESS_2              ((uint16_t)0x0002U)   /* Logical Address 2 */
  214. #define CEC_OWN_ADDRESS_3              ((uint16_t)0x0003U)   /* Logical Address 3 */
  215. #define CEC_OWN_ADDRESS_4              ((uint16_t)0x0004U)   /* Logical Address 4 */
  216. #define CEC_OWN_ADDRESS_5              ((uint16_t)0x0005U)   /* Logical Address 5 */
  217. #define CEC_OWN_ADDRESS_6              ((uint16_t)0x0006U)   /* Logical Address 6 */
  218. #define CEC_OWN_ADDRESS_7              ((uint16_t)0x0007U)   /* Logical Address 7 */
  219. #define CEC_OWN_ADDRESS_8              ((uint16_t)0x0008U)   /* Logical Address 8 */
  220. #define CEC_OWN_ADDRESS_9              ((uint16_t)0x0009U)   /* Logical Address 9 */
  221. #define CEC_OWN_ADDRESS_10             ((uint16_t)0x000AU)   /* Logical Address 10 */
  222. #define CEC_OWN_ADDRESS_11             ((uint16_t)0x000BU)   /* Logical Address 11 */
  223. #define CEC_OWN_ADDRESS_12             ((uint16_t)0x000CU)   /* Logical Address 12 */
  224. #define CEC_OWN_ADDRESS_13             ((uint16_t)0x000DU)   /* Logical Address 13 */
  225. #define CEC_OWN_ADDRESS_14             ((uint16_t)0x000EU)   /* Logical Address 14 */
  226. #define CEC_OWN_ADDRESS_15             ((uint16_t)0x000FU)   /* Logical Address 15 */
  227. /**
  228.   * @}
  229.   */
  230.  
  231. /** @defgroup CEC_Interrupts_Definitions  Interrupts definition
  232.   * @{
  233.   */
  234. #define CEC_IT_IE CEC_CFGR_IE
  235. /**
  236.   * @}
  237.   */
  238.  
  239. /** @defgroup CEC_Flags_Definitions  Flags definition
  240.   * @{
  241.   */
  242. #define CEC_FLAG_TSOM  CEC_CSR_TSOM
  243. #define CEC_FLAG_TEOM  CEC_CSR_TEOM
  244. #define CEC_FLAG_TERR  CEC_CSR_TERR
  245. #define CEC_FLAG_TBTRF CEC_CSR_TBTRF
  246. #define CEC_FLAG_RSOM  CEC_CSR_RSOM
  247. #define CEC_FLAG_REOM  CEC_CSR_REOM
  248. #define CEC_FLAG_RERR  CEC_CSR_RERR
  249. #define CEC_FLAG_RBTF  CEC_CSR_RBTF
  250. /**
  251.   * @}
  252.   */
  253.  
  254. /**
  255.   * @}
  256.   */  
  257.  
  258. /* Exported macros -----------------------------------------------------------*/
  259. /** @defgroup CEC_Exported_Macros CEC Exported Macros
  260.   * @{
  261.   */
  262.  
  263. /** @brief  Reset CEC handle gstate & RxState
  264.   * @param  __HANDLE__: CEC handle.
  265.   * @retval None
  266.   */
  267. #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
  268.                                                        (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
  269.                                                        (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
  270.                                                      } while(0U)
  271.  
  272. /** @brief  Checks whether or not the specified CEC interrupt flag is set.
  273.   * @param  __HANDLE__: specifies the CEC Handle.
  274.   * @param  __FLAG__: specifies the flag to check.
  275.   *     @arg CEC_FLAG_TERR: Tx Error
  276.   *     @arg CEC_FLAG_TBTRF:Tx Block Transfer Finished
  277.   *     @arg CEC_FLAG_RERR: Rx Error
  278.   *     @arg CEC_FLAG_RBTF: Rx Block Transfer Finished
  279.   * @retval ITStatus
  280.   */
  281. #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) READ_BIT((__HANDLE__)->Instance->CSR,(__FLAG__))
  282.  
  283. /** @brief  Clears the CEC's pending flags.
  284.   * @param  __HANDLE__: specifies the CEC Handle.
  285.   * @param  __FLAG__: specifies the flag to clear.
  286.   *   This parameter can be any combination of the following values:
  287.   *     @arg CEC_CSR_TERR: Tx Error
  288.   *     @arg CEC_FLAG_TBTRF: Tx Block Transfer Finished
  289.   *     @arg CEC_CSR_RERR: Rx Error
  290.   *     @arg CEC_CSR_RBTF: Rx Block Transfer Finished
  291.   * @retval none  
  292.   */
  293. #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)                                                                   \
  294.                           do {                                                                                       \
  295.                             uint32_t tmp = 0x0U;                                                                     \
  296.                             tmp = (__HANDLE__)->Instance->CSR & 0x00000002U;                                         \
  297.                             (__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFCU) | tmp);\
  298.                           } while(0U)
  299.  
  300. /** @brief  Enables the specified CEC interrupt.
  301.   * @param  __HANDLE__: specifies the CEC Handle.
  302.   * @param  __INTERRUPT__: specifies the CEC interrupt to enable.
  303.   *          This parameter can be:
  304.   *            @arg CEC_IT_IE         : Interrupt Enable.
  305.   * @retval none
  306.   */
  307. #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
  308.  
  309. /** @brief  Disables the specified CEC interrupt.
  310.   * @param  __HANDLE__: specifies the CEC Handle.
  311.   * @param  __INTERRUPT__: specifies the CEC interrupt to disable.
  312.   *          This parameter can be:
  313.   *            @arg CEC_IT_IE         : Interrupt Enable
  314.   * @retval none
  315.   */  
  316. #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
  317.  
  318. /** @brief  Checks whether or not the specified CEC interrupt is enabled.
  319.   * @param  __HANDLE__: specifies the CEC Handle.
  320.   * @param  __INTERRUPT__: specifies the CEC interrupt to check.
  321.   *          This parameter can be:
  322.   *            @arg CEC_IT_IE         : Interrupt Enable
  323.   * @retval FlagStatus  
  324.   */
  325. #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
  326.  
  327. /** @brief  Enables the CEC device
  328.   * @param  __HANDLE__: specifies the CEC Handle.              
  329.   * @retval none
  330.   */
  331. #define __HAL_CEC_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
  332.  
  333. /** @brief  Disables the CEC device
  334.   * @param  __HANDLE__: specifies the CEC Handle.              
  335.   * @retval none
  336.   */
  337. #define __HAL_CEC_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
  338.  
  339. /** @brief  Set Transmission Start flag
  340.   * @param  __HANDLE__: specifies the CEC Handle.              
  341.   * @retval none
  342.   */
  343. #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
  344.  
  345. /** @brief  Set Transmission End flag
  346.   * @param  __HANDLE__: specifies the CEC Handle.              
  347.   * @retval none
  348.   */
  349. #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
  350.  
  351. /** @brief  Get Transmission Start flag
  352.   * @param  __HANDLE__: specifies the CEC Handle.              
  353.   * @retval FlagStatus
  354.   */
  355. #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
  356.  
  357. /** @brief  Get Transmission End flag
  358.   * @param  __HANDLE__: specifies the CEC Handle.              
  359.   * @retval FlagStatus
  360.   */
  361. #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
  362.  
  363. /** @brief  Clear OAR register
  364.   * @param  __HANDLE__: specifies the CEC Handle.              
  365.   * @retval none
  366.   */
  367. #define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->OAR, CEC_OAR_OA)
  368.  
  369. /** @brief  Set OAR register
  370.   * @param  __HANDLE__: specifies the CEC Handle.
  371.   * @param  __ADDRESS__: Own Address value.
  372.   * @retval none
  373.   */
  374. #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) MODIFY_REG((__HANDLE__)->Instance->OAR, CEC_OAR_OA, (__ADDRESS__));
  375.  
  376. /**
  377.   * @}
  378.   */                      
  379.  
  380. /* Exported functions --------------------------------------------------------*/
  381. /** @addtogroup CEC_Exported_Functions CEC Exported Functions
  382.   * @{
  383.   */
  384.  
  385. /** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
  386.   *  @brief    Initialization and Configuration functions
  387.   * @{
  388.   */
  389. /* Initialization and de-initialization functions  ****************************/
  390. HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
  391. HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
  392. HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
  393. void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
  394. void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
  395. /**
  396.   * @}
  397.   */
  398.  
  399. /** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions
  400.   *  @brief CEC Transmit/Receive functions
  401.   * @{
  402.   */
  403. /* I/O operation functions  ***************************************************/
  404. HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
  405. uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
  406. void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
  407. void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
  408. void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
  409. void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
  410. void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
  411. /**
  412.   * @}
  413.   */
  414.  
  415. /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
  416.   *  @brief   CEC control functions
  417.   * @{
  418.   */
  419. /* Peripheral State and Error functions ***************************************/
  420. HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
  421. uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
  422. /**
  423.   * @}
  424.   */
  425.  
  426. /**
  427.   * @}
  428.   */
  429.  
  430. /* Private types -------------------------------------------------------------*/
  431. /** @defgroup CEC_Private_Types CEC Private Types
  432.   * @{
  433.   */
  434.  
  435. /**
  436.   * @}
  437.   */
  438.  
  439. /* Private variables ---------------------------------------------------------*/
  440. /** @defgroup CEC_Private_Variables CEC Private Variables
  441.   * @{
  442.   */
  443.  
  444. /**
  445.   * @}
  446.   */
  447.  
  448. /* Private constants ---------------------------------------------------------*/
  449. /** @defgroup CEC_Private_Constants CEC Private Constants
  450.   * @{
  451.   */
  452.  
  453. /**
  454.   * @}
  455.   */
  456.  
  457. /* Private macros ------------------------------------------------------------*/
  458. /** @defgroup CEC_Private_Macros CEC Private Macros
  459.   * @{
  460.   */
  461. #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \
  462.                                             ((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE))
  463.  
  464. #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \
  465.                                             ((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE))
  466.  
  467. /** @brief Check CEC message size.
  468.   *       The message size is the payload size: without counting the header,
  469.   *       it varies from 0 byte (ping operation, one header only, no payload) to
  470.   *       15 bytes (1 opcode and up to 14 operands following the header).
  471.   * @param  __SIZE__: CEC message size.              
  472.   * @retval Test result (TRUE or FALSE).
  473.   */
  474. #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
  475. /** @brief Check CEC device Own Address Register (OAR) setting.
  476.   * @param  __ADDRESS__: CEC own address.              
  477.   * @retval Test result (TRUE or FALSE).
  478.   */
  479. #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
  480.  
  481. /** @brief Check CEC initiator or destination logical address setting.
  482.   *        Initiator and destination addresses are coded over 4 bits.
  483.   * @param  __ADDRESS__: CEC initiator or logical address.              
  484.   * @retval Test result (TRUE or FALSE).
  485.   */
  486. #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
  487.  
  488.  
  489.  
  490. /**
  491.   * @}
  492.   */
  493. /* Private functions ---------------------------------------------------------*/
  494. /** @defgroup CEC_Private_Functions CEC Private Functions
  495.   * @{
  496.   */
  497.  
  498. /**
  499.   * @}
  500.   */
  501.  
  502. /**
  503.   * @}
  504.   */
  505.  
  506. /**
  507.   * @}
  508.   */
  509. #endif /* defined(STM32F100xB) || defined(STM32F100xE) */
  510. #ifdef __cplusplus
  511. }
  512. #endif
  513.  
  514. #endif /* __STM32F1xx_HAL_CEC_H */
  515.  
  516. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  517.