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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_hal_can.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of CAN HAL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  10.   *
  11.   * Redistribution and use in source and binary forms, with or without modification,
  12.   * are permitted provided that the following conditions are met:
  13.   *   1. Redistributions of source code must retain the above copyright notice,
  14.   *      this list of conditions and the following disclaimer.
  15.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16.   *      this list of conditions and the following disclaimer in the documentation
  17.   *      and/or other materials provided with the distribution.
  18.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19.   *      may be used to endorse or promote products derived from this software
  20.   *      without specific prior written permission.
  21.   *
  22.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32.   *
  33.   ******************************************************************************
  34.   */
  35.  
  36. /* Define to prevent recursive inclusion -------------------------------------*/
  37. #ifndef __STM32F1xx_HAL_CAN_H
  38. #define __STM32F1xx_HAL_CAN_H
  39.  
  40. #ifdef __cplusplus
  41.  extern "C" {
  42. #endif
  43.      
  44. #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
  45.     defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
  46.  
  47. /* Includes ------------------------------------------------------------------*/
  48. #include "stm32f1xx_hal_def.h"
  49.  
  50. /** @addtogroup STM32F1xx_HAL_Driver
  51.   * @{
  52.   */
  53.  
  54. /** @addtogroup CAN
  55.   * @{
  56.   */
  57.  
  58. /* Exported types ------------------------------------------------------------*/
  59. /** @defgroup CAN_Exported_Types CAN Exported Types
  60.   * @{
  61.   */
  62.  
  63. /**
  64.   * @brief  HAL State structures definition
  65.   */
  66. typedef enum
  67. {
  68.   HAL_CAN_STATE_RESET             = 0x00U,  /*!< CAN not yet initialized or disabled */
  69.   HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */
  70.   HAL_CAN_STATE_BUSY              = 0x02U,  /*!< CAN process is ongoing              */
  71.   HAL_CAN_STATE_BUSY_TX           = 0x12U,  /*!< CAN process is ongoing              */
  72.   HAL_CAN_STATE_BUSY_RX0          = 0x22U,  /*!< CAN process is ongoing              */
  73.   HAL_CAN_STATE_BUSY_RX1          = 0x32U,  /*!< CAN process is ongoing              */
  74.   HAL_CAN_STATE_BUSY_TX_RX0       = 0x42U,  /*!< CAN process is ongoing              */
  75.   HAL_CAN_STATE_BUSY_TX_RX1       = 0x52U,  /*!< CAN process is ongoing              */
  76.   HAL_CAN_STATE_BUSY_RX0_RX1      = 0x62U,  /*!< CAN process is ongoing              */
  77.   HAL_CAN_STATE_BUSY_TX_RX0_RX1   = 0x72U,  /*!< CAN process is ongoing              */
  78.   HAL_CAN_STATE_TIMEOUT           = 0x03U,  /*!< CAN in Timeout state                */
  79.   HAL_CAN_STATE_ERROR             = 0x04U   /*!< CAN error state                     */
  80.  
  81. }HAL_CAN_StateTypeDef;
  82.  
  83. /**
  84.   * @brief  CAN init structure definition
  85.   */
  86. typedef struct
  87. {
  88.   uint32_t Prescaler;  /*!< Specifies the length of a time quantum.
  89.                             This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
  90.  
  91.   uint32_t Mode;       /*!< Specifies the CAN operating mode.
  92.                             This parameter can be a value of @ref CAN_operating_mode */
  93.  
  94.   uint32_t SJW;        /*!< Specifies the maximum number of time quanta
  95.                             the CAN hardware is allowed to lengthen or
  96.                             shorten a bit to perform resynchronization.
  97.                             This parameter can be a value of @ref CAN_synchronisation_jump_width */
  98.  
  99.   uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.
  100.                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
  101.  
  102.   uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
  103.                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
  104.  
  105.   uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
  106.                             This parameter can be set to ENABLE or DISABLE. */
  107.  
  108.   uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
  109.                             This parameter can be set to ENABLE or DISABLE */
  110.  
  111.   uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.
  112.                             This parameter can be set to ENABLE or DISABLE */
  113.  
  114.   uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
  115.                             This parameter can be set to ENABLE or DISABLE */
  116.  
  117.   uint32_t RFLM;       /*!< Enable or disable the receive FIFO Locked mode.
  118.                             This parameter can be set to ENABLE or DISABLE */
  119.  
  120.   uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
  121.                             This parameter can be set to ENABLE or DISABLE */
  122. }CAN_InitTypeDef;
  123.  
  124. /**
  125.   * @brief  CAN Tx message structure definition  
  126.   */
  127. typedef struct
  128. {
  129.   uint32_t StdId;    /*!< Specifies the standard identifier.
  130.                           This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
  131.  
  132.   uint32_t ExtId;    /*!< Specifies the extended identifier.
  133.                           This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
  134.  
  135.   uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
  136.                           This parameter can be a value of @ref CAN_Identifier_Type */
  137.  
  138.   uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
  139.                           This parameter can be a value of @ref CAN_remote_transmission_request */
  140.  
  141.   uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
  142.                           This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
  143.  
  144.   uint8_t Data[8];   /*!< Contains the data to be transmitted.
  145.                           This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
  146.  
  147. }CanTxMsgTypeDef;
  148.  
  149. /**
  150.   * @brief  CAN Rx message structure definition
  151.   */
  152. typedef struct
  153. {
  154.   uint32_t StdId;       /*!< Specifies the standard identifier.
  155.                              This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
  156.  
  157.   uint32_t ExtId;       /*!< Specifies the extended identifier.
  158.                              This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
  159.  
  160.   uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
  161.                              This parameter can be a value of @ref CAN_Identifier_Type */
  162.  
  163.   uint32_t RTR;         /*!< Specifies the type of frame for the received message.
  164.                              This parameter can be a value of @ref CAN_remote_transmission_request */
  165.  
  166.   uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
  167.                              This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
  168.  
  169.   uint8_t Data[8];      /*!< Contains the data to be received.
  170.                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
  171.  
  172.   uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
  173.                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
  174.  
  175.   uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.
  176.                              This parameter can be CAN_FIFO0 or CAN_FIFO1 */
  177.  
  178. }CanRxMsgTypeDef;
  179.  
  180. /**
  181.   * @brief  CAN handle Structure definition
  182.   */
  183. typedef struct
  184. {
  185.   CAN_TypeDef                 *Instance;  /*!< Register base address          */
  186.  
  187.   CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
  188.  
  189.   CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
  190.  
  191.   CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure for RX FIFO0 msg */
  192.  
  193.   CanRxMsgTypeDef*            pRx1Msg;    /*!< Pointer to reception structure for RX FIFO1 msg */
  194.  
  195.   __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
  196.  
  197.   HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
  198.  
  199.   __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */
  200.  
  201. }CAN_HandleTypeDef;
  202.  
  203. /**
  204.   * @}
  205.   */
  206.  
  207. /* Exported constants --------------------------------------------------------*/
  208. /** @defgroup CAN_Exported_Constants CAN Exported Constants
  209.   * @{
  210.   */
  211.  
  212. /** @defgroup CAN_Error_Code CAN Error Code
  213.   * @{
  214.   */
  215. #define   HAL_CAN_ERROR_NONE      0x00000000U    /*!< No error             */
  216. #define   HAL_CAN_ERROR_EWG       0x00000001U    /*!< EWG error            */
  217. #define   HAL_CAN_ERROR_EPV       0x00000002U    /*!< EPV error            */
  218. #define   HAL_CAN_ERROR_BOF       0x00000004U    /*!< BOF error            */
  219. #define   HAL_CAN_ERROR_STF       0x00000008U    /*!< Stuff error          */
  220. #define   HAL_CAN_ERROR_FOR       0x00000010U    /*!< Form error           */
  221. #define   HAL_CAN_ERROR_ACK       0x00000020U    /*!< Acknowledgment error */
  222. #define   HAL_CAN_ERROR_BR        0x00000040U    /*!< Bit recessive        */
  223. #define   HAL_CAN_ERROR_BD        0x00000080U    /*!< LEC dominant         */
  224. #define   HAL_CAN_ERROR_CRC       0x00000100U    /*!< LEC transfer error   */
  225. #define   HAL_CAN_ERROR_FOV0      0x00000200U    /*!< FIFO0 overrun error  */
  226. #define   HAL_CAN_ERROR_FOV1      0x00000400U    /*!< FIFO1 overrun error  */
  227. #define   HAL_CAN_ERROR_TXFAIL    0x00000800U    /*!< Transmit failure     */
  228. /**
  229.   * @}
  230.   */
  231.  
  232. /** @defgroup CAN_InitStatus CAN initialization Status
  233.   * @{
  234.   */
  235. #define CAN_INITSTATUS_FAILED       0x00000000U  /*!< CAN initialization failed */
  236. #define CAN_INITSTATUS_SUCCESS      0x00000001U  /*!< CAN initialization OK */
  237. /**
  238.   * @}
  239.   */
  240.  
  241. /** @defgroup CAN_operating_mode CAN Operating Mode
  242.   * @{
  243.   */
  244. #define CAN_MODE_NORMAL             0x00000000U                                /*!< Normal mode   */
  245. #define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
  246. #define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
  247. #define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
  248. /**
  249.   * @}
  250.   */
  251.  
  252. /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
  253.   * @{
  254.   */
  255. #define CAN_SJW_1TQ                 0x00000000U                /*!< 1 time quantum */
  256. #define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
  257. #define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
  258. #define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
  259. /**
  260.   * @}
  261.   */
  262.  
  263. /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
  264.   * @{
  265.   */
  266. #define CAN_BS1_1TQ                 0x00000000U                                                  /*!< 1 time quantum  */
  267. #define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
  268. #define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
  269. #define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
  270. #define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
  271. #define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
  272. #define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
  273. #define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
  274. #define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
  275. #define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
  276. #define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
  277. #define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
  278. #define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
  279. #define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
  280. #define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
  281. #define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
  282. /**
  283.   * @}
  284.   */
  285.  
  286. /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
  287.   * @{
  288.   */
  289. #define CAN_BS2_1TQ                 0x00000000U                                  /*!< 1 time quantum */
  290. #define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
  291. #define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
  292. #define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
  293. #define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
  294. #define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
  295. #define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
  296. #define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
  297. /**
  298.   * @}
  299.   */
  300.  
  301. /** @defgroup CAN_filter_mode  CAN Filter Mode
  302.   * @{
  303.   */
  304. #define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00)  /*!< Identifier mask mode */
  305. #define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01)  /*!< Identifier list mode */
  306. /**
  307.   * @}
  308.   */
  309.  
  310. /** @defgroup CAN_filter_scale CAN Filter Scale
  311.   * @{
  312.   */
  313. #define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00)  /*!< Two 16-bit filters */
  314. #define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01)  /*!< One 32-bit filter  */
  315. /**
  316.   * @}
  317.   */
  318.  
  319. /** @defgroup CAN_filter_FIFO CAN Filter FIFO
  320.   * @{
  321.   */
  322. #define CAN_FILTER_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
  323. #define CAN_FILTER_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
  324. /**
  325.   * @}
  326.   */
  327.  
  328. /** @defgroup CAN_Identifier_Type CAN Identifier Type
  329.   * @{
  330.   */
  331. #define CAN_ID_STD                  0x00000000U  /*!< Standard Id */
  332. #define CAN_ID_EXT                  0x00000004U  /*!< Extended Id */
  333. /**
  334.   * @}
  335.   */
  336.  
  337. /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
  338.   * @{
  339.   */
  340. #define CAN_RTR_DATA                0x00000000U  /*!< Data frame */
  341. #define CAN_RTR_REMOTE              0x00000002U  /*!< Remote frame */
  342. /**
  343.   * @}
  344.   */
  345.  
  346. /** @defgroup CAN_transmit_constants CAN Transmit Constants
  347.   * @{
  348.   */
  349. #define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
  350. /**
  351.   * @}
  352.   */
  353.  
  354. /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
  355.   * @{
  356.   */
  357. #define CAN_FIFO0                   ((uint8_t)0x00)  /*!< CAN FIFO 0 used to receive */
  358. #define CAN_FIFO1                   ((uint8_t)0x01)  /*!< CAN FIFO 1 used to receive */
  359. /**
  360.   * @}
  361.   */
  362.  
  363. /** @defgroup CAN_flags CAN Flags
  364.   * @{
  365.   */
  366. /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
  367.    and CAN_ClearFlag() functions. */
  368. /* If the flag is 0x1XXXXXXX, it means that it can only be used with
  369.    CAN_GetFlagStatus() function.  */
  370.  
  371. /* Transmit Flags */
  372. #define CAN_FLAG_RQCP0             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION))  /*!< Request MailBox0 flag         */
  373. #define CAN_FLAG_RQCP1             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION))  /*!< Request MailBox1 flag         */
  374. #define CAN_FLAG_RQCP2             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION))  /*!< Request MailBox2 flag         */
  375. #define CAN_FLAG_TXOK0             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION))  /*!< Transmission OK MailBox0 flag */
  376. #define CAN_FLAG_TXOK1             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION))  /*!< Transmission OK MailBox1 flag */
  377. #define CAN_FLAG_TXOK2             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK2_BIT_POSITION))  /*!< Transmission OK MailBox2 flag */
  378. #define CAN_FLAG_TME0              ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION))   /*!< Transmit mailbox 0 empty flag */
  379. #define CAN_FLAG_TME1              ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION))   /*!< Transmit mailbox 0 empty flag */
  380. #define CAN_FLAG_TME2              ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION))   /*!< Transmit mailbox 0 empty flag */
  381.  
  382. /* Receive Flags */
  383. #define CAN_FLAG_FF0               ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION))  /*!< FIFO 0 Full flag    */
  384. #define CAN_FLAG_FOV0              ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION)) /*!< FIFO 0 Overrun flag */
  385.  
  386. #define CAN_FLAG_FF1               ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION))  /*!< FIFO 1 Full flag    */
  387. #define CAN_FLAG_FOV1              ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION)) /*!< FIFO 1 Overrun flag */
  388.  
  389. /* Operating Mode Flags */
  390. #define CAN_FLAG_WKU               ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION))    /*!< Wake up flag           */
  391. #define CAN_FLAG_SLAK              ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION))   /*!< Sleep acknowledge flag */
  392. #define CAN_FLAG_SLAKI             ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION))  /*!< Sleep acknowledge flag */
  393.  
  394. /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
  395.          In this case the SLAK bit can be polled.*/
  396.  
  397. /* Error Flags */
  398. #define CAN_FLAG_EWG               ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION))    /*!< Error warning flag   */
  399. #define CAN_FLAG_EPV               ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION))    /*!< Error passive flag   */
  400. #define CAN_FLAG_BOF               ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION))    /*!< Bus-Off flag         */
  401.  
  402. /**
  403.   * @}
  404.   */
  405.  
  406. /** @defgroup CAN_Interrupts CAN Interrupts
  407.   * @{
  408.   */
  409. #define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
  410.  
  411. /* Receive Interrupts */
  412. #define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
  413. #define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
  414. #define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
  415. #define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
  416. #define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
  417. #define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
  418.  
  419. /* Operating Mode Interrupts */
  420. #define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
  421. #define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
  422.  
  423. /* Error Interrupts */
  424. #define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
  425. #define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
  426. #define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
  427. #define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
  428. #define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
  429. /**
  430.   * @}
  431.   */
  432.  
  433. /**
  434.   * @}
  435.   */
  436.  
  437. /** @defgroup CAN_Private_Constants CAN Private Constants
  438.   * @{
  439.   */
  440.  
  441. /* CAN intermediate shift values used for CAN flags */
  442. #define TSR_REGISTER_INDEX      0x5U
  443. #define RF0R_REGISTER_INDEX     0x2U
  444. #define RF1R_REGISTER_INDEX     0x4U
  445. #define MSR_REGISTER_INDEX      0x1U
  446. #define ESR_REGISTER_INDEX      0x3U
  447.  
  448. /* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR regsiters) */
  449. /* Transmit Flags */
  450. #define CAN_TSR_RQCP0_BIT_POSITION     0x00000000U
  451. #define CAN_TSR_RQCP1_BIT_POSITION     0x00000008U
  452. #define CAN_TSR_RQCP2_BIT_POSITION     0x00000010U
  453. #define CAN_TSR_TXOK0_BIT_POSITION     0x00000001U
  454. #define CAN_TSR_TXOK1_BIT_POSITION     0x00000009U
  455. #define CAN_TSR_TXOK2_BIT_POSITION     0x00000011U
  456. #define CAN_TSR_TME0_BIT_POSITION      0x0000001AU
  457. #define CAN_TSR_TME1_BIT_POSITION      0x0000001BU
  458. #define CAN_TSR_TME2_BIT_POSITION      0x0000001CU
  459.  
  460. /* Receive Flags */
  461. #define CAN_RF0R_FF0_BIT_POSITION      0x00000003U
  462. #define CAN_RF0R_FOV0_BIT_POSITION     0x00000004U
  463.  
  464. #define CAN_RF1R_FF1_BIT_POSITION      0x00000003U
  465. #define CAN_RF1R_FOV1_BIT_POSITION     0x00000004U
  466.  
  467. /* Operating Mode Flags */
  468. #define CAN_MSR_WKU_BIT_POSITION       0x00000003U
  469. #define CAN_MSR_SLAK_BIT_POSITION      0x00000001U
  470. #define CAN_MSR_SLAKI_BIT_POSITION     0x00000004U
  471.  
  472. /* Error Flags */
  473. #define CAN_ESR_EWG_BIT_POSITION       0x00000000U
  474. #define CAN_ESR_EPV_BIT_POSITION       0x00000001U
  475. #define CAN_ESR_BOF_BIT_POSITION       0x00000002U
  476.  
  477. /* Mask used by macro to get/clear CAN flags*/
  478. #define CAN_FLAG_MASK                  0x000000FFU
  479.  
  480. /* Mailboxes definition */
  481. #define CAN_TXMAILBOX_0   ((uint8_t)0x00)
  482. #define CAN_TXMAILBOX_1   ((uint8_t)0x01)
  483. #define CAN_TXMAILBOX_2   ((uint8_t)0x02)
  484. /**
  485.   * @}
  486.   */
  487.  
  488. /* Exported macros -----------------------------------------------------------*/
  489. /** @defgroup CAN_Exported_Macros CAN Exported Macros
  490.   * @{
  491.   */
  492.  
  493. /** @brief  Reset CAN handle state
  494.   * @param  __HANDLE__: CAN handle.
  495.   * @retval None
  496.   */
  497. #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
  498.  
  499. /**
  500.   * @brief  Enable the specified CAN interrupts
  501.   * @param  __HANDLE__: CAN handle.
  502.   * @param  __INTERRUPT__: CAN Interrupt.
  503.   *         This parameter can be one of the following values:
  504.   *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
  505.   *            @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
  506.   *            @arg CAN_IT_FF0 : FIFO 0 full interrupt
  507.   *            @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
  508.   *            @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
  509.   *            @arg CAN_IT_FF1 : FIFO 1 full interrupt
  510.   *            @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
  511.   *            @arg CAN_IT_WKU : Wake-up interrupt
  512.   *            @arg CAN_IT_SLK : Sleep acknowledge interrupt
  513.   *            @arg CAN_IT_EWG : Error warning interrupt
  514.   *            @arg CAN_IT_EPV : Error passive interrupt
  515.   *            @arg CAN_IT_BOF : Bus-off interrupt
  516.   *            @arg CAN_IT_LEC : Last error code interrupt
  517.   *            @arg CAN_IT_ERR : Error Interrupt
  518.   * @retval None.
  519.   */
  520. #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
  521.  
  522. /**
  523.   * @brief  Disable the specified CAN interrupts
  524.   * @param  __HANDLE__: CAN handle.
  525.   * @param  __INTERRUPT__: CAN Interrupt.
  526.   *         This parameter can be one of the following values:
  527.   *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
  528.   *            @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
  529.   *            @arg CAN_IT_FF0 : FIFO 0 full interrupt
  530.   *            @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
  531.   *            @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
  532.   *            @arg CAN_IT_FF1 : FIFO 1 full interrupt
  533.   *            @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
  534.   *            @arg CAN_IT_WKU : Wake-up interrupt
  535.   *            @arg CAN_IT_SLK : Sleep acknowledge interrupt
  536.   *            @arg CAN_IT_EWG : Error warning interrupt
  537.   *            @arg CAN_IT_EPV : Error passive interrupt
  538.   *            @arg CAN_IT_BOF : Bus-off interrupt
  539.   *            @arg CAN_IT_LEC : Last error code interrupt
  540.   *            @arg CAN_IT_ERR : Error Interrupt
  541.   * @retval None.
  542.   */
  543. #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
  544.  
  545. /**
  546.   * @brief  Return the number of pending received messages.
  547.   * @param  __HANDLE__: CAN handle.
  548.   * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
  549.   * @retval The number of pending message.
  550.   */
  551. #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
  552. ((uint8_t)((__HANDLE__)->Instance->RF0R & 0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
  553.  
  554. /** @brief  Check whether the specified CAN flag is set or not.
  555.   * @param  __HANDLE__: specifies the CAN Handle.
  556.   * @param  __FLAG__: specifies the flag to check.
  557.   *         This parameter can be one of the following values:
  558.   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
  559.   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
  560.   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
  561.   *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
  562.   *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
  563.   *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
  564.   *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
  565.   *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
  566.   *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
  567.   *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
  568.   *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
  569.   *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
  570.   *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
  571.   *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
  572.   *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
  573.   *            @arg CAN_FLAG_WKU: Wake up Flag
  574.   *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
  575.   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
  576.   *            @arg CAN_FLAG_EWG: Error Warning Flag
  577.   *            @arg CAN_FLAG_EPV: Error Passive Flag
  578.   *            @arg CAN_FLAG_BOF: Bus-Off Flag
  579.   * @retval The new state of __FLAG__ (TRUE or FALSE).
  580.   */
  581. #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
  582. ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
  583.  (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
  584.  (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
  585.  (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
  586.  ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
  587.  
  588. /** @brief  Clear the specified CAN pending flag.
  589.   * @param  __HANDLE__: specifies the CAN Handle.
  590.   * @param  __FLAG__: specifies the flag to check.
  591.   *         This parameter can be one of the following values:
  592.   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
  593.   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
  594.   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
  595.   *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
  596.   *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
  597.   *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
  598.   *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
  599.   *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
  600.   *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
  601.   *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
  602.   *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
  603.   *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
  604.   *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
  605.   *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
  606.   *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
  607.   *            @arg CAN_FLAG_WKU: Wake up Flag
  608.   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
  609.   * @retval The new state of __FLAG__ (TRUE or FALSE).
  610.   */
  611. #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
  612. ((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR)  = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
  613.  (((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
  614.  (((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
  615.  (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR)  = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
  616.  
  617. /** @brief  Check if the specified CAN interrupt source is enabled or disabled.
  618.   * @param  __HANDLE__: specifies the CAN Handle.
  619.   * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
  620.   *         This parameter can be one of the following values:
  621.   *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
  622.   *            @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
  623.   *            @arg CAN_IT_FF0 : FIFO 0 full interrupt
  624.   *            @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
  625.   *            @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
  626.   *            @arg CAN_IT_FF1 : FIFO 1 full interrupt
  627.   *            @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
  628.   *            @arg CAN_IT_WKU : Wake-up interrupt
  629.   *            @arg CAN_IT_SLK : Sleep acknowledge interrupt
  630.   *            @arg CAN_IT_EWG : Error warning interrupt
  631.   *            @arg CAN_IT_EPV : Error passive interrupt
  632.   *            @arg CAN_IT_BOF : Bus-off interrupt
  633.   *            @arg CAN_IT_LEC : Last error code interrupt
  634.   *            @arg CAN_IT_ERR : Error Interrupt
  635.   * @retval The new state of __IT__ (TRUE or FALSE).
  636.   */
  637. #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
  638.  
  639. /**
  640.   * @brief  Check the transmission status of a CAN Frame.
  641.   * @param  __HANDLE__: specifies the CAN Handle.
  642.   * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
  643.   * @retval The new status of transmission  (TRUE or FALSE).
  644.   */
  645. #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
  646. (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
  647.  ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
  648.  ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
  649.  
  650. /**
  651.   * @brief  Release the specified receive FIFO.
  652.   * @param  __HANDLE__: CAN handle.
  653.   * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
  654.   * @retval None.
  655.   */
  656. #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
  657. ((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
  658.  
  659. /**
  660.   * @brief  Cancel a transmit request.
  661.   * @param  __HANDLE__: specifies the CAN Handle.
  662.   * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
  663.   * @retval None.
  664.   */
  665. #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
  666. (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
  667.  ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
  668.  ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
  669.  
  670. /**
  671.   * @brief  Enable or disables the DBG Freeze for CAN.
  672.   * @param  __HANDLE__: specifies the CAN Handle.
  673.   * @param  __NEWSTATE__: new state of the CAN peripheral.
  674.   *         This parameter can be: ENABLE (CAN reception/transmission is frozen
  675.   *         during debug. Reception FIFOs can still be accessed/controlled normally)
  676.   *         or DISABLE (CAN is working during debug).
  677.   * @retval None
  678.   */
  679. #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
  680. ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
  681.  
  682. /**
  683.   * @}
  684.   */
  685.  
  686. /* Include CAN HAL Extension module */
  687. #include "stm32f1xx_hal_can_ex_legacy.h"
  688.  
  689. /* Exported functions --------------------------------------------------------*/
  690. /** @addtogroup CAN_Exported_Functions
  691.   * @{
  692.   */
  693.  
  694. /** @addtogroup CAN_Exported_Functions_Group1
  695.   * @brief    Initialization and Configuration functions
  696.   * @{
  697.   */
  698. /* Initialization and de-initialization functions *****************************/
  699. HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
  700. HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
  701. HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
  702. void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
  703. void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
  704. /**
  705.   * @}
  706.   */
  707.  
  708. /** @addtogroup CAN_Exported_Functions_Group2
  709.   * @brief    I/O operation functions
  710.   * @{
  711.   */
  712. /* I/O operation functions *****************************************************/
  713. HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
  714. HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
  715. HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
  716. HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
  717. HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
  718. HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
  719. void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
  720. void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
  721. void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
  722. void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
  723. /**
  724.   * @}
  725.   */
  726.  
  727. /** @addtogroup CAN_Exported_Functions_Group3
  728.   * @brief   CAN Peripheral State functions
  729.   * @{
  730.   */
  731. /* Peripheral State and Error functions ***************************************/
  732. uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
  733. HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
  734. /**
  735.   * @}
  736.   */
  737.  
  738. /**
  739.   * @}
  740.   */
  741.  
  742. /* Private macros --------------------------------------------------------*/
  743. /** @defgroup CAN_Private_Macros   CAN Private Macros
  744.   * @{
  745.   */
  746.  
  747. #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
  748.                            ((MODE) == CAN_MODE_LOOPBACK)|| \
  749.                            ((MODE) == CAN_MODE_SILENT) || \
  750.                            ((MODE) == CAN_MODE_SILENT_LOOPBACK))
  751. #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
  752.                          ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
  753. #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
  754. #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
  755. #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
  756.  
  757. #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
  758.                                   ((MODE) == CAN_FILTERMODE_IDLIST))
  759. #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
  760.                                     ((SCALE) == CAN_FILTERSCALE_32BIT))
  761. #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
  762.                                   ((FIFO) == CAN_FILTER_FIFO1))
  763. #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
  764.  
  765. #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
  766. #define IS_CAN_STDID(STDID)   ((STDID) <= 0x00007FFU)
  767. #define IS_CAN_EXTID(EXTID)   ((EXTID) <= 0x1FFFFFFFU)
  768. #define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
  769.  
  770. #define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
  771.                                 ((IDTYPE) == CAN_ID_EXT))
  772. #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
  773. #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
  774.  
  775. /**
  776.   * @}
  777.   */
  778.  
  779. /**
  780.   * @}
  781.   */
  782.  
  783. /**
  784.   * @}
  785.   */
  786.  
  787. #endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
  788.  
  789. #ifdef __cplusplus
  790. }
  791. #endif
  792.  
  793. #endif /* __STM32F1xx_HAL_CAN_H */
  794.  
  795.  
  796. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  797.