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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f0xx_ll_tim.c
  4.   * @author  MCD Application Team
  5.   * @brief   TIM LL module driver.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10.   * All rights reserved.</center></h2>
  11.   *
  12.   * This software component is licensed by ST under BSD 3-Clause license,
  13.   * the "License"; You may not use this file except in compliance with the
  14.   * License. You may obtain a copy of the License at:
  15.   *                        opensource.org/licenses/BSD-3-Clause
  16.   *
  17.   ******************************************************************************
  18.   */
  19. #if defined(USE_FULL_LL_DRIVER)
  20.  
  21. /* Includes ------------------------------------------------------------------*/
  22. #include "stm32f0xx_ll_tim.h"
  23. #include "stm32f0xx_ll_bus.h"
  24.  
  25. #ifdef  USE_FULL_ASSERT
  26. #include "stm32_assert.h"
  27. #else
  28. #define assert_param(expr) ((void)0U)
  29. #endif /* USE_FULL_ASSERT */
  30.  
  31. /** @addtogroup STM32F0xx_LL_Driver
  32.   * @{
  33.   */
  34.  
  35. #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
  36.  
  37. /** @addtogroup TIM_LL
  38.   * @{
  39.   */
  40.  
  41. /* Private types -------------------------------------------------------------*/
  42. /* Private variables ---------------------------------------------------------*/
  43. /* Private constants ---------------------------------------------------------*/
  44. /* Private macros ------------------------------------------------------------*/
  45. /** @addtogroup TIM_LL_Private_Macros
  46.   * @{
  47.   */
  48. #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
  49.                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
  50.                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
  51.                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
  52.                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
  53.  
  54. #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
  55.                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
  56.                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
  57.  
  58. #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
  59.                                      || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
  60.                                      || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
  61.                                      || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
  62.                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
  63.                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
  64.                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
  65.                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
  66.  
  67. #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
  68.                                       || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
  69.  
  70. #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
  71.                                          || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
  72.  
  73. #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
  74.                                           || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
  75.  
  76. #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
  77.                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
  78.                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
  79.  
  80. #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
  81.                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
  82.                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
  83.                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
  84.  
  85. #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
  86.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
  87.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
  88.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
  89.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
  90.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
  91.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
  92.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
  93.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
  94.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
  95.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
  96.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
  97.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
  98.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
  99.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
  100.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
  101.  
  102. #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
  103.                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
  104.                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
  105.  
  106. #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
  107.                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
  108.                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
  109.  
  110. #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
  111.                                                   || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
  112.  
  113. #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
  114.                                          || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
  115.  
  116. #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
  117.                                          || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
  118.  
  119. #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
  120.                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
  121.                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
  122.                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
  123.  
  124. #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
  125.                                           || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
  126.  
  127. #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
  128.                                              || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
  129.  
  130. #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
  131.                                                      || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
  132. /**
  133.   * @}
  134.   */
  135.  
  136.  
  137. /* Private function prototypes -----------------------------------------------*/
  138. /** @defgroup TIM_LL_Private_Functions TIM Private Functions
  139.   * @{
  140.   */
  141. static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  142. static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  143. static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  144. static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  145. static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  146. static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  147. static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  148. static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  149. /**
  150.   * @}
  151.   */
  152.  
  153. /* Exported functions --------------------------------------------------------*/
  154. /** @addtogroup TIM_LL_Exported_Functions
  155.   * @{
  156.   */
  157.  
  158. /** @addtogroup TIM_LL_EF_Init
  159.   * @{
  160.   */
  161.  
  162. /**
  163.   * @brief  Set TIMx registers to their reset values.
  164.   * @param  TIMx Timer instance
  165.   * @retval An ErrorStatus enumeration value:
  166.   *          - SUCCESS: TIMx registers are de-initialized
  167.   *          - ERROR: invalid TIMx instance
  168.   */
  169. ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
  170. {
  171.   ErrorStatus result = SUCCESS;
  172.  
  173.   /* Check the parameters */
  174.   assert_param(IS_TIM_INSTANCE(TIMx));
  175.  
  176.   if (TIMx == TIM1)
  177.   {
  178.     LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM1);
  179.     LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM1);
  180.   }
  181. #if defined (TIM2)
  182.   else if (TIMx == TIM2)
  183.   {
  184.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
  185.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
  186.   }
  187. #endif
  188. #if defined(TIM3)
  189.   else if (TIMx == TIM3)
  190.   {
  191.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
  192.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
  193.   }
  194. #endif
  195. #if defined(TIM5)
  196.   else if (TIMx == TIM5)
  197.   {
  198.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
  199.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
  200.   }
  201. #endif
  202. #if defined (TIM6)
  203.   else if (TIMx == TIM6)
  204.   {
  205.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
  206.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
  207.   }
  208. #endif
  209. #if defined (TIM7)
  210.   else if (TIMx == TIM7)
  211.   {
  212.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
  213.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
  214.   }
  215. #endif
  216. #if defined(TIM8)
  217.   else if (TIMx == TIM8)
  218.   {
  219.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
  220.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
  221.   }
  222. #endif
  223. #if defined (TIM14)
  224.   else if (TIMx == TIM14)
  225.   {
  226.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
  227.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
  228.   }
  229. #endif
  230. #if defined (TIM15)
  231.   else if (TIMx == TIM15)
  232.   {
  233.     LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM15);
  234.     LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM15);
  235.   }
  236. #endif
  237. #if defined (TIM16)
  238.   else if (TIMx == TIM16)
  239.   {
  240.     LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM16);
  241.     LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM16);
  242.   }
  243. #endif
  244. #if defined(TIM17)
  245.   else if (TIMx == TIM17)
  246.   {
  247.     LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM17);
  248.     LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM17);
  249.   }
  250. #endif
  251.   else
  252.   {
  253.     result = ERROR;
  254.   }
  255.  
  256.   return result;
  257. }
  258.  
  259. /**
  260.   * @brief  Set the fields of the time base unit configuration data structure
  261.   *         to their default values.
  262.   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
  263.   * @retval None
  264.   */
  265. void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
  266. {
  267.   /* Set the default configuration */
  268.   TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
  269.   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
  270.   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
  271.   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
  272.   TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
  273. }
  274.  
  275. /**
  276.   * @brief  Configure the TIMx time base unit.
  277.   * @param  TIMx Timer Instance
  278.   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
  279.   * @retval An ErrorStatus enumeration value:
  280.   *          - SUCCESS: TIMx registers are de-initialized
  281.   *          - ERROR: not applicable
  282.   */
  283. ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
  284. {
  285.   uint32_t tmpcr1;
  286.  
  287.   /* Check the parameters */
  288.   assert_param(IS_TIM_INSTANCE(TIMx));
  289.   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
  290.   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
  291.  
  292.   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
  293.  
  294.   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  295.   {
  296.     /* Select the Counter Mode */
  297.     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
  298.   }
  299.  
  300.   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  301.   {
  302.     /* Set the clock division */
  303.     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
  304.   }
  305.  
  306.   /* Write to TIMx CR1 */
  307.   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
  308.  
  309.   /* Set the Autoreload value */
  310.   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
  311.  
  312.   /* Set the Prescaler value */
  313.   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
  314.  
  315.   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  316.   {
  317.     /* Set the Repetition Counter value */
  318.     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
  319.   }
  320.  
  321.   /* Generate an update event to reload the Prescaler
  322.      and the repetition counter value (if applicable) immediately */
  323.   LL_TIM_GenerateEvent_UPDATE(TIMx);
  324.  
  325.   return SUCCESS;
  326. }
  327.  
  328. /**
  329.   * @brief  Set the fields of the TIMx output channel configuration data
  330.   *         structure to their default values.
  331.   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
  332.   * @retval None
  333.   */
  334. void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
  335. {
  336.   /* Set the default configuration */
  337.   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
  338.   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
  339.   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
  340.   TIM_OC_InitStruct->CompareValue = 0x00000000U;
  341.   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
  342.   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
  343.   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
  344.   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
  345. }
  346.  
  347. /**
  348.   * @brief  Configure the TIMx output channel.
  349.   * @param  TIMx Timer Instance
  350.   * @param  Channel This parameter can be one of the following values:
  351.   *         @arg @ref LL_TIM_CHANNEL_CH1
  352.   *         @arg @ref LL_TIM_CHANNEL_CH2
  353.   *         @arg @ref LL_TIM_CHANNEL_CH3
  354.   *         @arg @ref LL_TIM_CHANNEL_CH4
  355.   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
  356.   * @retval An ErrorStatus enumeration value:
  357.   *          - SUCCESS: TIMx output channel is initialized
  358.   *          - ERROR: TIMx output channel is not initialized
  359.   */
  360. ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
  361. {
  362.   ErrorStatus result = ERROR;
  363.  
  364.   switch (Channel)
  365.   {
  366.     case LL_TIM_CHANNEL_CH1:
  367.       result = OC1Config(TIMx, TIM_OC_InitStruct);
  368.       break;
  369.     case LL_TIM_CHANNEL_CH2:
  370.       result = OC2Config(TIMx, TIM_OC_InitStruct);
  371.       break;
  372.     case LL_TIM_CHANNEL_CH3:
  373.       result = OC3Config(TIMx, TIM_OC_InitStruct);
  374.       break;
  375.     case LL_TIM_CHANNEL_CH4:
  376.       result = OC4Config(TIMx, TIM_OC_InitStruct);
  377.       break;
  378.     default:
  379.       break;
  380.   }
  381.  
  382.   return result;
  383. }
  384.  
  385. /**
  386.   * @brief  Set the fields of the TIMx input channel configuration data
  387.   *         structure to their default values.
  388.   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
  389.   * @retval None
  390.   */
  391. void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  392. {
  393.   /* Set the default configuration */
  394.   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
  395.   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  396.   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
  397.   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
  398. }
  399.  
  400. /**
  401.   * @brief  Configure the TIMx input channel.
  402.   * @param  TIMx Timer Instance
  403.   * @param  Channel This parameter can be one of the following values:
  404.   *         @arg @ref LL_TIM_CHANNEL_CH1
  405.   *         @arg @ref LL_TIM_CHANNEL_CH2
  406.   *         @arg @ref LL_TIM_CHANNEL_CH3
  407.   *         @arg @ref LL_TIM_CHANNEL_CH4
  408.   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
  409.   * @retval An ErrorStatus enumeration value:
  410.   *          - SUCCESS: TIMx output channel is initialized
  411.   *          - ERROR: TIMx output channel is not initialized
  412.   */
  413. ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
  414. {
  415.   ErrorStatus result = ERROR;
  416.  
  417.   switch (Channel)
  418.   {
  419.     case LL_TIM_CHANNEL_CH1:
  420.       result = IC1Config(TIMx, TIM_IC_InitStruct);
  421.       break;
  422.     case LL_TIM_CHANNEL_CH2:
  423.       result = IC2Config(TIMx, TIM_IC_InitStruct);
  424.       break;
  425.     case LL_TIM_CHANNEL_CH3:
  426.       result = IC3Config(TIMx, TIM_IC_InitStruct);
  427.       break;
  428.     case LL_TIM_CHANNEL_CH4:
  429.       result = IC4Config(TIMx, TIM_IC_InitStruct);
  430.       break;
  431.     default:
  432.       break;
  433.   }
  434.  
  435.   return result;
  436. }
  437.  
  438. /**
  439.   * @brief  Fills each TIM_EncoderInitStruct field with its default value
  440.   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
  441.   * @retval None
  442.   */
  443. void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
  444. {
  445.   /* Set the default configuration */
  446.   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
  447.   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
  448.   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  449.   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
  450.   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
  451.   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
  452.   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  453.   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
  454.   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
  455. }
  456.  
  457. /**
  458.   * @brief  Configure the encoder interface of the timer instance.
  459.   * @param  TIMx Timer Instance
  460.   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
  461.   * @retval An ErrorStatus enumeration value:
  462.   *          - SUCCESS: TIMx registers are de-initialized
  463.   *          - ERROR: not applicable
  464.   */
  465. ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
  466. {
  467.   uint32_t tmpccmr1;
  468.   uint32_t tmpccer;
  469.  
  470.   /* Check the parameters */
  471.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
  472.   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
  473.   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
  474.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
  475.   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
  476.   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
  477.   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
  478.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
  479.   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
  480.   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
  481.  
  482.   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
  483.   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
  484.  
  485.   /* Get the TIMx CCMR1 register value */
  486.   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  487.  
  488.   /* Get the TIMx CCER register value */
  489.   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  490.  
  491.   /* Configure TI1 */
  492.   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
  493.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
  494.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
  495.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
  496.  
  497.   /* Configure TI2 */
  498.   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
  499.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
  500.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
  501.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
  502.  
  503.   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
  504.   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
  505.   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
  506.   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
  507.   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
  508.  
  509.   /* Set encoder mode */
  510.   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
  511.  
  512.   /* Write to TIMx CCMR1 */
  513.   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  514.  
  515.   /* Write to TIMx CCER */
  516.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  517.  
  518.   return SUCCESS;
  519. }
  520.  
  521. /**
  522.   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
  523.   *         structure to their default values.
  524.   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
  525.   * @retval None
  526.   */
  527. void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
  528. {
  529.   /* Set the default configuration */
  530.   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
  531.   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
  532.   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
  533.   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
  534. }
  535.  
  536. /**
  537.   * @brief  Configure the Hall sensor interface of the timer instance.
  538.   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
  539.   *       to the TI1 input channel
  540.   * @note TIMx slave mode controller is configured in reset mode.
  541.           Selected internal trigger is TI1F_ED.
  542.   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
  543.   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
  544.   *       between 2 changes on the inputs. It gives information about motor speed.
  545.   * @note Channel 2 is configured in output PWM 2 mode.
  546.   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
  547.   * @note OC2REF is selected as trigger output on TRGO.
  548.   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
  549.   *       when TIMx operates in Hall sensor interface mode.
  550.   * @param  TIMx Timer Instance
  551.   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
  552.   * @retval An ErrorStatus enumeration value:
  553.   *          - SUCCESS: TIMx registers are de-initialized
  554.   *          - ERROR: not applicable
  555.   */
  556. ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
  557. {
  558.   uint32_t tmpcr2;
  559.   uint32_t tmpccmr1;
  560.   uint32_t tmpccer;
  561.   uint32_t tmpsmcr;
  562.  
  563.   /* Check the parameters */
  564.   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
  565.   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
  566.   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
  567.   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
  568.  
  569.   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
  570.   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
  571.  
  572.   /* Get the TIMx CR2 register value */
  573.   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  574.  
  575.   /* Get the TIMx CCMR1 register value */
  576.   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  577.  
  578.   /* Get the TIMx CCER register value */
  579.   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  580.  
  581.   /* Get the TIMx SMCR register value */
  582.   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
  583.  
  584.   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
  585.   tmpcr2 |= TIM_CR2_TI1S;
  586.  
  587.   /* OC2REF signal is used as trigger output (TRGO) */
  588.   tmpcr2 |= LL_TIM_TRGO_OC2REF;
  589.  
  590.   /* Configure the slave mode controller */
  591.   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
  592.   tmpsmcr |= LL_TIM_TS_TI1F_ED;
  593.   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
  594.  
  595.   /* Configure input channel 1 */
  596.   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
  597.   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
  598.   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
  599.   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
  600.  
  601.   /* Configure input channel 2 */
  602.   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
  603.   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
  604.  
  605.   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
  606.   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
  607.   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
  608.   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
  609.  
  610.   /* Write to TIMx CR2 */
  611.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  612.  
  613.   /* Write to TIMx SMCR */
  614.   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
  615.  
  616.   /* Write to TIMx CCMR1 */
  617.   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  618.  
  619.   /* Write to TIMx CCER */
  620.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  621.  
  622.   /* Write to TIMx CCR2 */
  623.   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
  624.  
  625.   return SUCCESS;
  626. }
  627.  
  628. /**
  629.   * @brief  Set the fields of the Break and Dead Time configuration data structure
  630.   *         to their default values.
  631.   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
  632.   * @retval None
  633.   */
  634. void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
  635. {
  636.   /* Set the default configuration */
  637.   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
  638.   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
  639.   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
  640.   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
  641.   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
  642.   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
  643.   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
  644. }
  645.  
  646. /**
  647.   * @brief  Configure the Break and Dead Time feature of the timer instance.
  648.   * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
  649.   *  depending on the LOCK configuration, it can be necessary to configure all of
  650.   *  them during the first write access to the TIMx_BDTR register.
  651.   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
  652.   *       a timer instance provides a break input.
  653.   * @param  TIMx Timer Instance
  654.   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
  655.   * @retval An ErrorStatus enumeration value:
  656.   *          - SUCCESS: Break and Dead Time is initialized
  657.   *          - ERROR: not applicable
  658.   */
  659. ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
  660. {
  661.   uint32_t tmpbdtr = 0;
  662.  
  663.   /* Check the parameters */
  664.   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
  665.   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
  666.   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
  667.   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
  668.   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
  669.   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
  670.   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
  671.  
  672.   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
  673.   the OSSI State, the dead time value and the Automatic Output Enable Bit */
  674.  
  675.   /* Set the BDTR bits */
  676.   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
  677.   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
  678.   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
  679.   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
  680.   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
  681.   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
  682.   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
  683.   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
  684.  
  685.   /* Set TIMx_BDTR */
  686.   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
  687.  
  688.   return SUCCESS;
  689. }
  690. /**
  691.   * @}
  692.   */
  693.  
  694. /**
  695.   * @}
  696.   */
  697.  
  698. /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
  699.   *  @brief   Private functions
  700.   * @{
  701.   */
  702. /**
  703.   * @brief  Configure the TIMx output channel 1.
  704.   * @param  TIMx Timer Instance
  705.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
  706.   * @retval An ErrorStatus enumeration value:
  707.   *          - SUCCESS: TIMx registers are de-initialized
  708.   *          - ERROR: not applicable
  709.   */
  710. static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  711. {
  712.   uint32_t tmpccmr1;
  713.   uint32_t tmpccer;
  714.   uint32_t tmpcr2;
  715.  
  716.   /* Check the parameters */
  717.   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  718.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  719.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  720.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  721.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
  722.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
  723.  
  724.   /* Disable the Channel 1: Reset the CC1E Bit */
  725.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
  726.  
  727.   /* Get the TIMx CCER register value */
  728.   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  729.  
  730.   /* Get the TIMx CR2 register value */
  731.   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  732.  
  733.   /* Get the TIMx CCMR1 register value */
  734.   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  735.  
  736.   /* Reset Capture/Compare selection Bits */
  737.   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
  738.  
  739.   /* Set the Output Compare Mode */
  740.   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
  741.  
  742.   /* Set the Output Compare Polarity */
  743.   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
  744.  
  745.   /* Set the Output State */
  746.   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
  747.  
  748.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  749.   {
  750.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
  751.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
  752.  
  753.     /* Set the complementary output Polarity */
  754.     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
  755.  
  756.     /* Set the complementary output State */
  757.     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
  758.  
  759.     /* Set the Output Idle state */
  760.     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
  761.  
  762.     /* Set the complementary output Idle state */
  763.     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
  764.   }
  765.  
  766.   /* Write to TIMx CR2 */
  767.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  768.  
  769.   /* Write to TIMx CCMR1 */
  770.   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  771.  
  772.   /* Set the Capture Compare Register value */
  773.   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
  774.  
  775.   /* Write to TIMx CCER */
  776.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  777.  
  778.   return SUCCESS;
  779. }
  780.  
  781. /**
  782.   * @brief  Configure the TIMx output channel 2.
  783.   * @param  TIMx Timer Instance
  784.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
  785.   * @retval An ErrorStatus enumeration value:
  786.   *          - SUCCESS: TIMx registers are de-initialized
  787.   *          - ERROR: not applicable
  788.   */
  789. static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  790. {
  791.   uint32_t tmpccmr1;
  792.   uint32_t tmpccer;
  793.   uint32_t tmpcr2;
  794.  
  795.   /* Check the parameters */
  796.   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
  797.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  798.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  799.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  800.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
  801.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
  802.  
  803.   /* Disable the Channel 2: Reset the CC2E Bit */
  804.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
  805.  
  806.   /* Get the TIMx CCER register value */
  807.   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
  808.  
  809.   /* Get the TIMx CR2 register value */
  810.   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  811.  
  812.   /* Get the TIMx CCMR1 register value */
  813.   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  814.  
  815.   /* Reset Capture/Compare selection Bits */
  816.   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
  817.  
  818.   /* Select the Output Compare Mode */
  819.   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
  820.  
  821.   /* Set the Output Compare Polarity */
  822.   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
  823.  
  824.   /* Set the Output State */
  825.   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
  826.  
  827.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  828.   {
  829.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
  830.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
  831.  
  832.     /* Set the complementary output Polarity */
  833.     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
  834.  
  835.     /* Set the complementary output State */
  836.     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
  837.  
  838.     /* Set the Output Idle state */
  839.     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
  840.  
  841.     /* Set the complementary output Idle state */
  842.     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
  843.   }
  844.  
  845.   /* Write to TIMx CR2 */
  846.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  847.  
  848.   /* Write to TIMx CCMR1 */
  849.   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  850.  
  851.   /* Set the Capture Compare Register value */
  852.   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
  853.  
  854.   /* Write to TIMx CCER */
  855.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  856.  
  857.   return SUCCESS;
  858. }
  859.  
  860. /**
  861.   * @brief  Configure the TIMx output channel 3.
  862.   * @param  TIMx Timer Instance
  863.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
  864.   * @retval An ErrorStatus enumeration value:
  865.   *          - SUCCESS: TIMx registers are de-initialized
  866.   *          - ERROR: not applicable
  867.   */
  868. static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  869. {
  870.   uint32_t tmpccmr2;
  871.   uint32_t tmpccer;
  872.   uint32_t tmpcr2;
  873.  
  874.   /* Check the parameters */
  875.   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
  876.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  877.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  878.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  879.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
  880.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
  881.  
  882.   /* Disable the Channel 3: Reset the CC3E Bit */
  883.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
  884.  
  885.   /* Get the TIMx CCER register value */
  886.   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
  887.  
  888.   /* Get the TIMx CR2 register value */
  889.   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  890.  
  891.   /* Get the TIMx CCMR2 register value */
  892.   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
  893.  
  894.   /* Reset Capture/Compare selection Bits */
  895.   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
  896.  
  897.   /* Select the Output Compare Mode */
  898.   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
  899.  
  900.   /* Set the Output Compare Polarity */
  901.   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
  902.  
  903.   /* Set the Output State */
  904.   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
  905.  
  906.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  907.   {
  908.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
  909.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
  910.  
  911.     /* Set the complementary output Polarity */
  912.     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
  913.  
  914.     /* Set the complementary output State */
  915.     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
  916.  
  917.     /* Set the Output Idle state */
  918.     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
  919.  
  920.     /* Set the complementary output Idle state */
  921.     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
  922.   }
  923.  
  924.   /* Write to TIMx CR2 */
  925.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  926.  
  927.   /* Write to TIMx CCMR2 */
  928.   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
  929.  
  930.   /* Set the Capture Compare Register value */
  931.   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
  932.  
  933.   /* Write to TIMx CCER */
  934.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  935.  
  936.   return SUCCESS;
  937. }
  938.  
  939. /**
  940.   * @brief  Configure the TIMx output channel 4.
  941.   * @param  TIMx Timer Instance
  942.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
  943.   * @retval An ErrorStatus enumeration value:
  944.   *          - SUCCESS: TIMx registers are de-initialized
  945.   *          - ERROR: not applicable
  946.   */
  947. static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  948. {
  949.   uint32_t tmpccmr2;
  950.   uint32_t tmpccer;
  951.   uint32_t tmpcr2;
  952.  
  953.   /* Check the parameters */
  954.   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
  955.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  956.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  957.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  958.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
  959.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
  960.  
  961.   /* Disable the Channel 4: Reset the CC4E Bit */
  962.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
  963.  
  964.   /* Get the TIMx CCER register value */
  965.   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  966.  
  967.   /* Get the TIMx CR2 register value */
  968.   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
  969.  
  970.   /* Get the TIMx CCMR2 register value */
  971.   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
  972.  
  973.   /* Reset Capture/Compare selection Bits */
  974.   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
  975.  
  976.   /* Select the Output Compare Mode */
  977.   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
  978.  
  979.   /* Set the Output Compare Polarity */
  980.   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
  981.  
  982.   /* Set the Output State */
  983.   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
  984.  
  985.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  986.   {
  987.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
  988.     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
  989.  
  990.     /* Set the Output Idle state */
  991.     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
  992.   }
  993.  
  994.   /* Write to TIMx CR2 */
  995.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  996.  
  997.   /* Write to TIMx CCMR2 */
  998.   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
  999.  
  1000.   /* Set the Capture Compare Register value */
  1001.   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
  1002.  
  1003.   /* Write to TIMx CCER */
  1004.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  1005.  
  1006.   return SUCCESS;
  1007. }
  1008.  
  1009.  
  1010. /**
  1011.   * @brief  Configure the TIMx input channel 1.
  1012.   * @param  TIMx Timer Instance
  1013.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
  1014.   * @retval An ErrorStatus enumeration value:
  1015.   *          - SUCCESS: TIMx registers are de-initialized
  1016.   *          - ERROR: not applicable
  1017.   */
  1018. static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  1019. {
  1020.   /* Check the parameters */
  1021.   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  1022.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  1023.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  1024.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  1025.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  1026.  
  1027.   /* Disable the Channel 1: Reset the CC1E Bit */
  1028.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
  1029.  
  1030.   /* Select the Input and set the filter and the prescaler value */
  1031.   MODIFY_REG(TIMx->CCMR1,
  1032.              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
  1033.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
  1034.  
  1035.   /* Select the Polarity and set the CC1E Bit */
  1036.   MODIFY_REG(TIMx->CCER,
  1037.              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
  1038.              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
  1039.  
  1040.   return SUCCESS;
  1041. }
  1042.  
  1043. /**
  1044.   * @brief  Configure the TIMx input channel 2.
  1045.   * @param  TIMx Timer Instance
  1046.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
  1047.   * @retval An ErrorStatus enumeration value:
  1048.   *          - SUCCESS: TIMx registers are de-initialized
  1049.   *          - ERROR: not applicable
  1050.   */
  1051. static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  1052. {
  1053.   /* Check the parameters */
  1054.   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
  1055.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  1056.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  1057.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  1058.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  1059.  
  1060.   /* Disable the Channel 2: Reset the CC2E Bit */
  1061.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
  1062.  
  1063.   /* Select the Input and set the filter and the prescaler value */
  1064.   MODIFY_REG(TIMx->CCMR1,
  1065.              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
  1066.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
  1067.  
  1068.   /* Select the Polarity and set the CC2E Bit */
  1069.   MODIFY_REG(TIMx->CCER,
  1070.              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
  1071.              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
  1072.  
  1073.   return SUCCESS;
  1074. }
  1075.  
  1076. /**
  1077.   * @brief  Configure the TIMx input channel 3.
  1078.   * @param  TIMx Timer Instance
  1079.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
  1080.   * @retval An ErrorStatus enumeration value:
  1081.   *          - SUCCESS: TIMx registers are de-initialized
  1082.   *          - ERROR: not applicable
  1083.   */
  1084. static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  1085. {
  1086.   /* Check the parameters */
  1087.   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
  1088.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  1089.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  1090.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  1091.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  1092.  
  1093.   /* Disable the Channel 3: Reset the CC3E Bit */
  1094.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
  1095.  
  1096.   /* Select the Input and set the filter and the prescaler value */
  1097.   MODIFY_REG(TIMx->CCMR2,
  1098.              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
  1099.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
  1100.  
  1101.   /* Select the Polarity and set the CC3E Bit */
  1102.   MODIFY_REG(TIMx->CCER,
  1103.              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
  1104.              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
  1105.  
  1106.   return SUCCESS;
  1107. }
  1108.  
  1109. /**
  1110.   * @brief  Configure the TIMx input channel 4.
  1111.   * @param  TIMx Timer Instance
  1112.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
  1113.   * @retval An ErrorStatus enumeration value:
  1114.   *          - SUCCESS: TIMx registers are de-initialized
  1115.   *          - ERROR: not applicable
  1116.   */
  1117. static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  1118. {
  1119.   /* Check the parameters */
  1120.   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
  1121.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  1122.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  1123.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  1124.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  1125.  
  1126.   /* Disable the Channel 4: Reset the CC4E Bit */
  1127.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
  1128.  
  1129.   /* Select the Input and set the filter and the prescaler value */
  1130.   MODIFY_REG(TIMx->CCMR2,
  1131.              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
  1132.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
  1133.  
  1134.   /* Select the Polarity and set the CC2E Bit */
  1135.   MODIFY_REG(TIMx->CCER,
  1136.              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
  1137.              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
  1138.  
  1139.   return SUCCESS;
  1140. }
  1141.  
  1142.  
  1143. /**
  1144.   * @}
  1145.   */
  1146.  
  1147. /**
  1148.   * @}
  1149.   */
  1150.  
  1151. #endif /* TIM1 || TIM2 || TIM3  || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
  1152.  
  1153. /**
  1154.   * @}
  1155.   */
  1156.  
  1157. #endif /* USE_FULL_LL_DRIVER */
  1158.  
  1159. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1160.