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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f0xx_hal_tim.c
  4.   * @author  MCD Application Team
  5.   * @brief   TIM HAL module driver.
  6.   *          This file provides firmware functions to manage the following
  7.   *          functionalities of the Timer (TIM) peripheral:
  8.   *           + TIM Time Base Initialization
  9.   *           + TIM Time Base Start
  10.   *           + TIM Time Base Start Interruption
  11.   *           + TIM Time Base Start DMA
  12.   *           + TIM Output Compare/PWM Initialization
  13.   *           + TIM Output Compare/PWM Channel Configuration
  14.   *           + TIM Output Compare/PWM  Start
  15.   *           + TIM Output Compare/PWM  Start Interruption
  16.   *           + TIM Output Compare/PWM Start DMA
  17.   *           + TIM Input Capture Initialization
  18.   *           + TIM Input Capture Channel Configuration
  19.   *           + TIM Input Capture Start
  20.   *           + TIM Input Capture Start Interruption
  21.   *           + TIM Input Capture Start DMA
  22.   *           + TIM One Pulse Initialization
  23.   *           + TIM One Pulse Channel Configuration
  24.   *           + TIM One Pulse Start
  25.   *           + TIM Encoder Interface Initialization
  26.   *           + TIM Encoder Interface Start
  27.   *           + TIM Encoder Interface Start Interruption
  28.   *           + TIM Encoder Interface Start DMA
  29.   *           + Commutation Event configuration with Interruption and DMA
  30.   *           + TIM OCRef clear configuration
  31.   *           + TIM External Clock configuration
  32.   @verbatim
  33.   ==============================================================================
  34.                       ##### TIMER Generic features #####
  35.   ==============================================================================
  36.   [..] The Timer features include:
  37.        (#) 16-bit up, down, up/down auto-reload counter.
  38.        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
  39.            counter clock frequency either by any factor between 1 and 65536.
  40.        (#) Up to 4 independent channels for:
  41.            (++) Input Capture
  42.            (++) Output Compare
  43.            (++) PWM generation (Edge and Center-aligned Mode)
  44.            (++) One-pulse mode output
  45.        (#) Synchronization circuit to control the timer with external signals and to interconnect
  46.             several timers together.
  47.        (#) Supports incremental encoder for positioning purposes
  48.  
  49.             ##### How to use this driver #####
  50.   ==============================================================================
  51.     [..]
  52.      (#) Initialize the TIM low level resources by implementing the following functions
  53.          depending on the selected feature:
  54.            (++) Time Base : HAL_TIM_Base_MspInit()
  55.            (++) Input Capture : HAL_TIM_IC_MspInit()
  56.            (++) Output Compare : HAL_TIM_OC_MspInit()
  57.            (++) PWM generation : HAL_TIM_PWM_MspInit()
  58.            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
  59.            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
  60.  
  61.      (#) Initialize the TIM low level resources :
  62.         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
  63.         (##) TIM pins configuration
  64.             (+++) Enable the clock for the TIM GPIOs using the following function:
  65.              __HAL_RCC_GPIOx_CLK_ENABLE();
  66.             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
  67.  
  68.      (#) The external Clock can be configured, if needed (the default clock is the
  69.          internal clock from the APBx), using the following function:
  70.          HAL_TIM_ConfigClockSource, the clock configuration should be done before
  71.          any start function.
  72.  
  73.      (#) Configure the TIM in the desired functioning mode using one of the
  74.        Initialization function of this driver:
  75.        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
  76.        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
  77.             Output Compare signal.
  78.        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
  79.             PWM signal.
  80.        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
  81.             external signal.
  82.        (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
  83.             in One Pulse Mode.
  84.        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
  85.  
  86.      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
  87.            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
  88.            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
  89.            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
  90.            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
  91.            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
  92.            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
  93.  
  94.      (#) The DMA Burst is managed with the two following functions:
  95.          HAL_TIM_DMABurst_WriteStart()
  96.          HAL_TIM_DMABurst_ReadStart()
  97.  
  98.     *** Callback registration ***
  99.   =============================================
  100.  
  101.   [..]
  102.   The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
  103.   allows the user to configure dynamically the driver callbacks.
  104.  
  105.   [..]
  106.   Use Function HAL_TIM_RegisterCallback() to register a callback.
  107.   HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
  108.   the Callback ID and a pointer to the user callback function.
  109.  
  110.   [..]
  111.   Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
  112.   weak function.
  113.   HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
  114.   and the Callback ID.
  115.  
  116.   [..]
  117.   These functions allow to register/unregister following callbacks:
  118.     (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
  119.     (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
  120.     (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
  121.     (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
  122.     (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
  123.     (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
  124.     (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
  125.     (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
  126.     (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
  127.     (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
  128.     (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
  129.     (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
  130.     (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
  131.     (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
  132.     (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
  133.     (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
  134.     (+) TriggerCallback                   : TIM Trigger Callback.
  135.     (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
  136.     (+) IC_CaptureCallback                : TIM Input Capture Callback.
  137.     (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
  138.     (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
  139.     (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
  140.     (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
  141.     (+) ErrorCallback                     : TIM Error Callback.
  142.     (+) CommutationCallback               : TIM Commutation Callback.
  143.     (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
  144.     (+) BreakCallback                     : TIM Break Callback.
  145.  
  146.   [..]
  147. By default, after the Init and when the state is HAL_TIM_STATE_RESET
  148. all interrupt callbacks are set to the corresponding weak functions:
  149.   examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
  150.  
  151.   [..]
  152.   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
  153.   functionalities in the Init / DeInit only when these callbacks are null
  154.   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
  155.     keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
  156.  
  157.   [..]
  158.     Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
  159.     Exception done MspInit / MspDeInit that can be registered / unregistered
  160.     in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
  161.     thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
  162.   In that case first register the MspInit/MspDeInit user callbacks
  163.       using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
  164.  
  165.   [..]
  166.       When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
  167.       not defined, the callback registration feature is not available and all callbacks
  168.       are set to the corresponding weak functions.
  169.  
  170.   @endverbatim
  171.   ******************************************************************************
  172.   * @attention
  173.   *
  174.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  175.   * All rights reserved.</center></h2>
  176.   *
  177.   * This software component is licensed by ST under BSD 3-Clause license,
  178.   * the "License"; You may not use this file except in compliance with the
  179.   * License. You may obtain a copy of the License at:
  180.   *                        opensource.org/licenses/BSD-3-Clause
  181.   *
  182.   ******************************************************************************
  183.   */
  184.  
  185. /* Includes ------------------------------------------------------------------*/
  186. #include "stm32f0xx_hal.h"
  187.  
  188. /** @addtogroup STM32F0xx_HAL_Driver
  189.   * @{
  190.   */
  191.  
  192. /** @defgroup TIM TIM
  193.   * @brief TIM HAL module driver
  194.   * @{
  195.   */
  196.  
  197. #ifdef HAL_TIM_MODULE_ENABLED
  198.  
  199. /* Private typedef -----------------------------------------------------------*/
  200. /* Private define ------------------------------------------------------------*/
  201. /* Private macros ------------------------------------------------------------*/
  202. /* Private variables ---------------------------------------------------------*/
  203. /* Private function prototypes -----------------------------------------------*/
  204. /** @addtogroup TIM_Private_Functions
  205.   * @{
  206.   */
  207. static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  208. static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  209. static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  210. static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
  211. static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  212.                               uint32_t TIM_ICFilter);
  213. static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
  214. static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  215.                               uint32_t TIM_ICFilter);
  216. static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  217.                               uint32_t TIM_ICFilter);
  218. static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
  219. static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
  220. static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
  221. static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
  222. static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
  223. static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
  224. static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
  225.                                                   TIM_SlaveConfigTypeDef *sSlaveConfig);
  226. /**
  227.   * @}
  228.   */
  229. /* Exported functions --------------------------------------------------------*/
  230.  
  231. /** @defgroup TIM_Exported_Functions TIM Exported Functions
  232.   * @{
  233.   */
  234.  
  235. /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
  236.   *  @brief    Time Base functions
  237.   *
  238. @verbatim
  239.   ==============================================================================
  240.               ##### Time Base functions #####
  241.   ==============================================================================
  242.   [..]
  243.     This section provides functions allowing to:
  244.     (+) Initialize and configure the TIM base.
  245.     (+) De-initialize the TIM base.
  246.     (+) Start the Time Base.
  247.     (+) Stop the Time Base.
  248.     (+) Start the Time Base and enable interrupt.
  249.     (+) Stop the Time Base and disable interrupt.
  250.     (+) Start the Time Base and enable DMA transfer.
  251.     (+) Stop the Time Base and disable DMA transfer.
  252.  
  253. @endverbatim
  254.   * @{
  255.   */
  256. /**
  257.   * @brief  Initializes the TIM Time base Unit according to the specified
  258.   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
  259.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  260.   *         requires a timer reset to avoid unexpected direction
  261.   *         due to DIR bit readonly in center aligned mode.
  262.   *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  263.   * @param  htim TIM Base handle
  264.   * @retval HAL status
  265.   */
  266. HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
  267. {
  268.   /* Check the TIM handle allocation */
  269.   if (htim == NULL)
  270.   {
  271.     return HAL_ERROR;
  272.   }
  273.  
  274.   /* Check the parameters */
  275.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  276.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  277.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  278.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  279.  
  280.   if (htim->State == HAL_TIM_STATE_RESET)
  281.   {
  282.     /* Allocate lock resource and initialize it */
  283.     htim->Lock = HAL_UNLOCKED;
  284.  
  285. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  286.     /* Reset interrupt callbacks to legacy weak callbacks */
  287.     TIM_ResetCallback(htim);
  288.  
  289.     if (htim->Base_MspInitCallback == NULL)
  290.     {
  291.       htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
  292.     }
  293.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  294.     htim->Base_MspInitCallback(htim);
  295. #else
  296.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  297.     HAL_TIM_Base_MspInit(htim);
  298. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  299.   }
  300.  
  301.   /* Set the TIM state */
  302.   htim->State = HAL_TIM_STATE_BUSY;
  303.  
  304.   /* Set the Time Base configuration */
  305.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  306.  
  307.   /* Initialize the DMA burst operation state */
  308.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  309.  
  310.   /* Initialize the TIM channels state */
  311.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  312.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  313.  
  314.   /* Initialize the TIM state*/
  315.   htim->State = HAL_TIM_STATE_READY;
  316.  
  317.   return HAL_OK;
  318. }
  319.  
  320. /**
  321.   * @brief  DeInitializes the TIM Base peripheral
  322.   * @param  htim TIM Base handle
  323.   * @retval HAL status
  324.   */
  325. HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
  326. {
  327.   /* Check the parameters */
  328.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  329.  
  330.   htim->State = HAL_TIM_STATE_BUSY;
  331.  
  332.   /* Disable the TIM Peripheral Clock */
  333.   __HAL_TIM_DISABLE(htim);
  334.  
  335. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  336.   if (htim->Base_MspDeInitCallback == NULL)
  337.   {
  338.     htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
  339.   }
  340.   /* DeInit the low level hardware */
  341.   htim->Base_MspDeInitCallback(htim);
  342. #else
  343.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  344.   HAL_TIM_Base_MspDeInit(htim);
  345. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  346.  
  347.   /* Change the DMA burst operation state */
  348.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  349.  
  350.   /* Change the TIM channels state */
  351.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  352.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  353.  
  354.   /* Change TIM state */
  355.   htim->State = HAL_TIM_STATE_RESET;
  356.  
  357.   /* Release Lock */
  358.   __HAL_UNLOCK(htim);
  359.  
  360.   return HAL_OK;
  361. }
  362.  
  363. /**
  364.   * @brief  Initializes the TIM Base MSP.
  365.   * @param  htim TIM Base handle
  366.   * @retval None
  367.   */
  368. __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
  369. {
  370.   /* Prevent unused argument(s) compilation warning */
  371.   UNUSED(htim);
  372.  
  373.   /* NOTE : This function should not be modified, when the callback is needed,
  374.             the HAL_TIM_Base_MspInit could be implemented in the user file
  375.    */
  376. }
  377.  
  378. /**
  379.   * @brief  DeInitializes TIM Base MSP.
  380.   * @param  htim TIM Base handle
  381.   * @retval None
  382.   */
  383. __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
  384. {
  385.   /* Prevent unused argument(s) compilation warning */
  386.   UNUSED(htim);
  387.  
  388.   /* NOTE : This function should not be modified, when the callback is needed,
  389.             the HAL_TIM_Base_MspDeInit could be implemented in the user file
  390.    */
  391. }
  392.  
  393.  
  394. /**
  395.   * @brief  Starts the TIM Base generation.
  396.   * @param  htim TIM Base handle
  397.   * @retval HAL status
  398.   */
  399. HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
  400. {
  401.   uint32_t tmpsmcr;
  402.  
  403.   /* Check the parameters */
  404.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  405.  
  406.   /* Check the TIM state */
  407.   if (htim->State != HAL_TIM_STATE_READY)
  408.   {
  409.     return HAL_ERROR;
  410.   }
  411.  
  412.   /* Set the TIM state */
  413.   htim->State = HAL_TIM_STATE_BUSY;
  414.  
  415.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  416.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  417.   {
  418.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  419.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  420.     {
  421.       __HAL_TIM_ENABLE(htim);
  422.     }
  423.   }
  424.   else
  425.   {
  426.     __HAL_TIM_ENABLE(htim);
  427.   }
  428.  
  429.   /* Return function status */
  430.   return HAL_OK;
  431. }
  432.  
  433. /**
  434.   * @brief  Stops the TIM Base generation.
  435.   * @param  htim TIM Base handle
  436.   * @retval HAL status
  437.   */
  438. HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
  439. {
  440.   /* Check the parameters */
  441.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  442.  
  443.   /* Disable the Peripheral */
  444.   __HAL_TIM_DISABLE(htim);
  445.  
  446.   /* Set the TIM state */
  447.   htim->State = HAL_TIM_STATE_READY;
  448.  
  449.   /* Return function status */
  450.   return HAL_OK;
  451. }
  452.  
  453. /**
  454.   * @brief  Starts the TIM Base generation in interrupt mode.
  455.   * @param  htim TIM Base handle
  456.   * @retval HAL status
  457.   */
  458. HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
  459. {
  460.   uint32_t tmpsmcr;
  461.  
  462.   /* Check the parameters */
  463.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  464.  
  465.   /* Check the TIM state */
  466.   if (htim->State != HAL_TIM_STATE_READY)
  467.   {
  468.     return HAL_ERROR;
  469.   }
  470.  
  471.   /* Set the TIM state */
  472.   htim->State = HAL_TIM_STATE_BUSY;
  473.  
  474.   /* Enable the TIM Update interrupt */
  475.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
  476.  
  477.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  478.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  479.   {
  480.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  481.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  482.     {
  483.       __HAL_TIM_ENABLE(htim);
  484.     }
  485.   }
  486.   else
  487.   {
  488.     __HAL_TIM_ENABLE(htim);
  489.   }
  490.  
  491.   /* Return function status */
  492.   return HAL_OK;
  493. }
  494.  
  495. /**
  496.   * @brief  Stops the TIM Base generation in interrupt mode.
  497.   * @param  htim TIM Base handle
  498.   * @retval HAL status
  499.   */
  500. HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
  501. {
  502.   /* Check the parameters */
  503.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  504.  
  505.   /* Disable the TIM Update interrupt */
  506.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
  507.  
  508.   /* Disable the Peripheral */
  509.   __HAL_TIM_DISABLE(htim);
  510.  
  511.   /* Set the TIM state */
  512.   htim->State = HAL_TIM_STATE_READY;
  513.  
  514.   /* Return function status */
  515.   return HAL_OK;
  516. }
  517.  
  518. /**
  519.   * @brief  Starts the TIM Base generation in DMA mode.
  520.   * @param  htim TIM Base handle
  521.   * @param  pData The source Buffer address.
  522.   * @param  Length The length of data to be transferred from memory to peripheral.
  523.   * @retval HAL status
  524.   */
  525. HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
  526. {
  527.   uint32_t tmpsmcr;
  528.  
  529.   /* Check the parameters */
  530.   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
  531.  
  532.   /* Set the TIM state */
  533.   if (htim->State == HAL_TIM_STATE_BUSY)
  534.   {
  535.     return HAL_BUSY;
  536.   }
  537.   else if (htim->State == HAL_TIM_STATE_READY)
  538.   {
  539.     if ((pData == NULL) && (Length > 0U))
  540.     {
  541.       return HAL_ERROR;
  542.     }
  543.     else
  544.     {
  545.       htim->State = HAL_TIM_STATE_BUSY;
  546.     }
  547.   }
  548.   else
  549.   {
  550.     return HAL_ERROR;
  551.   }
  552.  
  553.   /* Set the DMA Period elapsed callbacks */
  554.   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  555.   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  556.  
  557.   /* Set the DMA error callback */
  558.   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  559.  
  560.   /* Enable the DMA channel */
  561.   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
  562.                        Length) != HAL_OK)
  563.   {
  564.     /* Return error status */
  565.     return HAL_ERROR;
  566.   }
  567.  
  568.   /* Enable the TIM Update DMA request */
  569.   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
  570.  
  571.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  572.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  573.   {
  574.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  575.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  576.     {
  577.       __HAL_TIM_ENABLE(htim);
  578.     }
  579.   }
  580.   else
  581.   {
  582.     __HAL_TIM_ENABLE(htim);
  583.   }
  584.  
  585.   /* Return function status */
  586.   return HAL_OK;
  587. }
  588.  
  589. /**
  590.   * @brief  Stops the TIM Base generation in DMA mode.
  591.   * @param  htim TIM Base handle
  592.   * @retval HAL status
  593.   */
  594. HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
  595. {
  596.   /* Check the parameters */
  597.   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
  598.  
  599.   /* Disable the TIM Update DMA request */
  600.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
  601.  
  602.   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  603.  
  604.   /* Disable the Peripheral */
  605.   __HAL_TIM_DISABLE(htim);
  606.  
  607.   /* Set the TIM state */
  608.   htim->State = HAL_TIM_STATE_READY;
  609.  
  610.   /* Return function status */
  611.   return HAL_OK;
  612. }
  613.  
  614. /**
  615.   * @}
  616.   */
  617.  
  618. /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
  619.   *  @brief    TIM Output Compare functions
  620.   *
  621. @verbatim
  622.   ==============================================================================
  623.                   ##### TIM Output Compare functions #####
  624.   ==============================================================================
  625.   [..]
  626.     This section provides functions allowing to:
  627.     (+) Initialize and configure the TIM Output Compare.
  628.     (+) De-initialize the TIM Output Compare.
  629.     (+) Start the TIM Output Compare.
  630.     (+) Stop the TIM Output Compare.
  631.     (+) Start the TIM Output Compare and enable interrupt.
  632.     (+) Stop the TIM Output Compare and disable interrupt.
  633.     (+) Start the TIM Output Compare and enable DMA transfer.
  634.     (+) Stop the TIM Output Compare and disable DMA transfer.
  635.  
  636. @endverbatim
  637.   * @{
  638.   */
  639. /**
  640.   * @brief  Initializes the TIM Output Compare according to the specified
  641.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  642.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  643.   *         requires a timer reset to avoid unexpected direction
  644.   *         due to DIR bit readonly in center aligned mode.
  645.   *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
  646.   * @param  htim TIM Output Compare handle
  647.   * @retval HAL status
  648.   */
  649. HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
  650. {
  651.   /* Check the TIM handle allocation */
  652.   if (htim == NULL)
  653.   {
  654.     return HAL_ERROR;
  655.   }
  656.  
  657.   /* Check the parameters */
  658.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  659.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  660.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  661.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  662.  
  663.   if (htim->State == HAL_TIM_STATE_RESET)
  664.   {
  665.     /* Allocate lock resource and initialize it */
  666.     htim->Lock = HAL_UNLOCKED;
  667.  
  668. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  669.     /* Reset interrupt callbacks to legacy weak callbacks */
  670.     TIM_ResetCallback(htim);
  671.  
  672.     if (htim->OC_MspInitCallback == NULL)
  673.     {
  674.       htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
  675.     }
  676.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  677.     htim->OC_MspInitCallback(htim);
  678. #else
  679.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  680.     HAL_TIM_OC_MspInit(htim);
  681. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  682.   }
  683.  
  684.   /* Set the TIM state */
  685.   htim->State = HAL_TIM_STATE_BUSY;
  686.  
  687.   /* Init the base time for the Output Compare */
  688.   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
  689.  
  690.   /* Initialize the DMA burst operation state */
  691.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  692.  
  693.   /* Initialize the TIM channels state */
  694.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  695.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  696.  
  697.   /* Initialize the TIM state*/
  698.   htim->State = HAL_TIM_STATE_READY;
  699.  
  700.   return HAL_OK;
  701. }
  702.  
  703. /**
  704.   * @brief  DeInitializes the TIM peripheral
  705.   * @param  htim TIM Output Compare handle
  706.   * @retval HAL status
  707.   */
  708. HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
  709. {
  710.   /* Check the parameters */
  711.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  712.  
  713.   htim->State = HAL_TIM_STATE_BUSY;
  714.  
  715.   /* Disable the TIM Peripheral Clock */
  716.   __HAL_TIM_DISABLE(htim);
  717.  
  718. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  719.   if (htim->OC_MspDeInitCallback == NULL)
  720.   {
  721.     htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
  722.   }
  723.   /* DeInit the low level hardware */
  724.   htim->OC_MspDeInitCallback(htim);
  725. #else
  726.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  727.   HAL_TIM_OC_MspDeInit(htim);
  728. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  729.  
  730.   /* Change the DMA burst operation state */
  731.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  732.  
  733.   /* Change the TIM channels state */
  734.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  735.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  736.  
  737.   /* Change TIM state */
  738.   htim->State = HAL_TIM_STATE_RESET;
  739.  
  740.   /* Release Lock */
  741.   __HAL_UNLOCK(htim);
  742.  
  743.   return HAL_OK;
  744. }
  745.  
  746. /**
  747.   * @brief  Initializes the TIM Output Compare MSP.
  748.   * @param  htim TIM Output Compare handle
  749.   * @retval None
  750.   */
  751. __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
  752. {
  753.   /* Prevent unused argument(s) compilation warning */
  754.   UNUSED(htim);
  755.  
  756.   /* NOTE : This function should not be modified, when the callback is needed,
  757.             the HAL_TIM_OC_MspInit could be implemented in the user file
  758.    */
  759. }
  760.  
  761. /**
  762.   * @brief  DeInitializes TIM Output Compare MSP.
  763.   * @param  htim TIM Output Compare handle
  764.   * @retval None
  765.   */
  766. __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
  767. {
  768.   /* Prevent unused argument(s) compilation warning */
  769.   UNUSED(htim);
  770.  
  771.   /* NOTE : This function should not be modified, when the callback is needed,
  772.             the HAL_TIM_OC_MspDeInit could be implemented in the user file
  773.    */
  774. }
  775.  
  776. /**
  777.   * @brief  Starts the TIM Output Compare signal generation.
  778.   * @param  htim TIM Output Compare handle
  779.   * @param  Channel TIM Channel to be enabled
  780.   *          This parameter can be one of the following values:
  781.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  782.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  783.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  784.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  785.   * @retval HAL status
  786.   */
  787. HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  788. {
  789.   uint32_t tmpsmcr;
  790.  
  791.   /* Check the parameters */
  792.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  793.  
  794.   /* Check the TIM channel state */
  795.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  796.   {
  797.     return HAL_ERROR;
  798.   }
  799.  
  800.   /* Set the TIM channel state */
  801.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  802.  
  803.   /* Enable the Output compare channel */
  804.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  805.  
  806.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  807.   {
  808.     /* Enable the main output */
  809.     __HAL_TIM_MOE_ENABLE(htim);
  810.   }
  811.  
  812.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  813.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  814.   {
  815.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  816.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  817.     {
  818.       __HAL_TIM_ENABLE(htim);
  819.     }
  820.   }
  821.   else
  822.   {
  823.     __HAL_TIM_ENABLE(htim);
  824.   }
  825.  
  826.   /* Return function status */
  827.   return HAL_OK;
  828. }
  829.  
  830. /**
  831.   * @brief  Stops the TIM Output Compare signal generation.
  832.   * @param  htim TIM Output Compare handle
  833.   * @param  Channel TIM Channel to be disabled
  834.   *          This parameter can be one of the following values:
  835.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  836.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  837.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  838.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  839.   * @retval HAL status
  840.   */
  841. HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  842. {
  843.   /* Check the parameters */
  844.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  845.  
  846.   /* Disable the Output compare channel */
  847.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  848.  
  849.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  850.   {
  851.     /* Disable the Main Output */
  852.     __HAL_TIM_MOE_DISABLE(htim);
  853.   }
  854.  
  855.   /* Disable the Peripheral */
  856.   __HAL_TIM_DISABLE(htim);
  857.  
  858.   /* Set the TIM channel state */
  859.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  860.  
  861.   /* Return function status */
  862.   return HAL_OK;
  863. }
  864.  
  865. /**
  866.   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
  867.   * @param  htim TIM Output Compare handle
  868.   * @param  Channel TIM Channel to be enabled
  869.   *          This parameter can be one of the following values:
  870.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  871.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  872.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  873.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  874.   * @retval HAL status
  875.   */
  876. HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  877. {
  878.   HAL_StatusTypeDef status = HAL_OK;
  879.   uint32_t tmpsmcr;
  880.  
  881.   /* Check the parameters */
  882.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  883.  
  884.   /* Check the TIM channel state */
  885.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  886.   {
  887.     return HAL_ERROR;
  888.   }
  889.  
  890.   /* Set the TIM channel state */
  891.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  892.  
  893.   switch (Channel)
  894.   {
  895.     case TIM_CHANNEL_1:
  896.     {
  897.       /* Enable the TIM Capture/Compare 1 interrupt */
  898.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  899.       break;
  900.     }
  901.  
  902.     case TIM_CHANNEL_2:
  903.     {
  904.       /* Enable the TIM Capture/Compare 2 interrupt */
  905.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  906.       break;
  907.     }
  908.  
  909.     case TIM_CHANNEL_3:
  910.     {
  911.       /* Enable the TIM Capture/Compare 3 interrupt */
  912.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  913.       break;
  914.     }
  915.  
  916.     case TIM_CHANNEL_4:
  917.     {
  918.       /* Enable the TIM Capture/Compare 4 interrupt */
  919.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  920.       break;
  921.     }
  922.  
  923.     default:
  924.       status = HAL_ERROR;
  925.       break;
  926.   }
  927.  
  928.   if (status == HAL_OK)
  929.   {
  930.     /* Enable the Output compare channel */
  931.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  932.  
  933.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  934.     {
  935.       /* Enable the main output */
  936.       __HAL_TIM_MOE_ENABLE(htim);
  937.     }
  938.  
  939.     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  940.     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  941.     {
  942.       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  943.       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  944.       {
  945.         __HAL_TIM_ENABLE(htim);
  946.       }
  947.     }
  948.     else
  949.     {
  950.       __HAL_TIM_ENABLE(htim);
  951.     }
  952.   }
  953.  
  954.   /* Return function status */
  955.   return status;
  956. }
  957.  
  958. /**
  959.   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
  960.   * @param  htim TIM Output Compare handle
  961.   * @param  Channel TIM Channel to be disabled
  962.   *          This parameter can be one of the following values:
  963.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  964.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  965.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  966.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  967.   * @retval HAL status
  968.   */
  969. HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  970. {
  971.   HAL_StatusTypeDef status = HAL_OK;
  972.  
  973.   /* Check the parameters */
  974.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  975.  
  976.   switch (Channel)
  977.   {
  978.     case TIM_CHANNEL_1:
  979.     {
  980.       /* Disable the TIM Capture/Compare 1 interrupt */
  981.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  982.       break;
  983.     }
  984.  
  985.     case TIM_CHANNEL_2:
  986.     {
  987.       /* Disable the TIM Capture/Compare 2 interrupt */
  988.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  989.       break;
  990.     }
  991.  
  992.     case TIM_CHANNEL_3:
  993.     {
  994.       /* Disable the TIM Capture/Compare 3 interrupt */
  995.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  996.       break;
  997.     }
  998.  
  999.     case TIM_CHANNEL_4:
  1000.     {
  1001.       /* Disable the TIM Capture/Compare 4 interrupt */
  1002.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  1003.       break;
  1004.     }
  1005.  
  1006.     default:
  1007.       status = HAL_ERROR;
  1008.       break;
  1009.   }
  1010.  
  1011.   if (status == HAL_OK)
  1012.   {
  1013.     /* Disable the Output compare channel */
  1014.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1015.  
  1016.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1017.     {
  1018.       /* Disable the Main Output */
  1019.       __HAL_TIM_MOE_DISABLE(htim);
  1020.     }
  1021.  
  1022.     /* Disable the Peripheral */
  1023.     __HAL_TIM_DISABLE(htim);
  1024.  
  1025.     /* Set the TIM channel state */
  1026.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1027.   }
  1028.  
  1029.   /* Return function status */
  1030.   return status;
  1031. }
  1032.  
  1033. /**
  1034.   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
  1035.   * @param  htim TIM Output Compare handle
  1036.   * @param  Channel TIM Channel to be enabled
  1037.   *          This parameter can be one of the following values:
  1038.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1039.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1040.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1041.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1042.   * @param  pData The source Buffer address.
  1043.   * @param  Length The length of data to be transferred from memory to TIM peripheral
  1044.   * @retval HAL status
  1045.   */
  1046. HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
  1047. {
  1048.   HAL_StatusTypeDef status = HAL_OK;
  1049.   uint32_t tmpsmcr;
  1050.  
  1051.   /* Check the parameters */
  1052.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1053.  
  1054.   /* Set the TIM channel state */
  1055.   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
  1056.   {
  1057.     return HAL_BUSY;
  1058.   }
  1059.   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
  1060.   {
  1061.     if ((pData == NULL) && (Length > 0U))
  1062.     {
  1063.       return HAL_ERROR;
  1064.     }
  1065.     else
  1066.     {
  1067.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1068.     }
  1069.   }
  1070.   else
  1071.   {
  1072.     return HAL_ERROR;
  1073.   }
  1074.  
  1075.   switch (Channel)
  1076.   {
  1077.     case TIM_CHANNEL_1:
  1078.     {
  1079.       /* Set the DMA compare callbacks */
  1080.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1081.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1082.  
  1083.       /* Set the DMA error callback */
  1084.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  1085.  
  1086.       /* Enable the DMA channel */
  1087.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
  1088.                            Length) != HAL_OK)
  1089.       {
  1090.         /* Return error status */
  1091.         return HAL_ERROR;
  1092.       }
  1093.  
  1094.       /* Enable the TIM Capture/Compare 1 DMA request */
  1095.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  1096.       break;
  1097.     }
  1098.  
  1099.     case TIM_CHANNEL_2:
  1100.     {
  1101.       /* Set the DMA compare callbacks */
  1102.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1103.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1104.  
  1105.       /* Set the DMA error callback */
  1106.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  1107.  
  1108.       /* Enable the DMA channel */
  1109.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
  1110.                            Length) != HAL_OK)
  1111.       {
  1112.         /* Return error status */
  1113.         return HAL_ERROR;
  1114.       }
  1115.  
  1116.       /* Enable the TIM Capture/Compare 2 DMA request */
  1117.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  1118.       break;
  1119.     }
  1120.  
  1121.     case TIM_CHANNEL_3:
  1122.     {
  1123.       /* Set the DMA compare callbacks */
  1124.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1125.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1126.  
  1127.       /* Set the DMA error callback */
  1128.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  1129.  
  1130.       /* Enable the DMA channel */
  1131.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
  1132.                            Length) != HAL_OK)
  1133.       {
  1134.         /* Return error status */
  1135.         return HAL_ERROR;
  1136.       }
  1137.       /* Enable the TIM Capture/Compare 3 DMA request */
  1138.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  1139.       break;
  1140.     }
  1141.  
  1142.     case TIM_CHANNEL_4:
  1143.     {
  1144.       /* Set the DMA compare callbacks */
  1145.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1146.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1147.  
  1148.       /* Set the DMA error callback */
  1149.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  1150.  
  1151.       /* Enable the DMA channel */
  1152.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
  1153.                            Length) != HAL_OK)
  1154.       {
  1155.         /* Return error status */
  1156.         return HAL_ERROR;
  1157.       }
  1158.       /* Enable the TIM Capture/Compare 4 DMA request */
  1159.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  1160.       break;
  1161.     }
  1162.  
  1163.     default:
  1164.       status = HAL_ERROR;
  1165.       break;
  1166.   }
  1167.  
  1168.   if (status == HAL_OK)
  1169.   {
  1170.     /* Enable the Output compare channel */
  1171.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1172.  
  1173.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1174.     {
  1175.       /* Enable the main output */
  1176.       __HAL_TIM_MOE_ENABLE(htim);
  1177.     }
  1178.  
  1179.     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1180.     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1181.     {
  1182.       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1183.       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1184.       {
  1185.         __HAL_TIM_ENABLE(htim);
  1186.       }
  1187.     }
  1188.     else
  1189.     {
  1190.       __HAL_TIM_ENABLE(htim);
  1191.     }
  1192.   }
  1193.  
  1194.   /* Return function status */
  1195.   return status;
  1196. }
  1197.  
  1198. /**
  1199.   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
  1200.   * @param  htim TIM Output Compare handle
  1201.   * @param  Channel TIM Channel to be disabled
  1202.   *          This parameter can be one of the following values:
  1203.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1204.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1205.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1206.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1207.   * @retval HAL status
  1208.   */
  1209. HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  1210. {
  1211.   HAL_StatusTypeDef status = HAL_OK;
  1212.  
  1213.   /* Check the parameters */
  1214.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1215.  
  1216.   switch (Channel)
  1217.   {
  1218.     case TIM_CHANNEL_1:
  1219.     {
  1220.       /* Disable the TIM Capture/Compare 1 DMA request */
  1221.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  1222.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  1223.       break;
  1224.     }
  1225.  
  1226.     case TIM_CHANNEL_2:
  1227.     {
  1228.       /* Disable the TIM Capture/Compare 2 DMA request */
  1229.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  1230.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  1231.       break;
  1232.     }
  1233.  
  1234.     case TIM_CHANNEL_3:
  1235.     {
  1236.       /* Disable the TIM Capture/Compare 3 DMA request */
  1237.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  1238.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  1239.       break;
  1240.     }
  1241.  
  1242.     case TIM_CHANNEL_4:
  1243.     {
  1244.       /* Disable the TIM Capture/Compare 4 interrupt */
  1245.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  1246.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  1247.       break;
  1248.     }
  1249.  
  1250.     default:
  1251.       status = HAL_ERROR;
  1252.       break;
  1253.   }
  1254.  
  1255.   if (status == HAL_OK)
  1256.   {
  1257.     /* Disable the Output compare channel */
  1258.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1259.  
  1260.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1261.     {
  1262.       /* Disable the Main Output */
  1263.       __HAL_TIM_MOE_DISABLE(htim);
  1264.     }
  1265.  
  1266.     /* Disable the Peripheral */
  1267.     __HAL_TIM_DISABLE(htim);
  1268.  
  1269.     /* Set the TIM channel state */
  1270.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1271.   }
  1272.  
  1273.   /* Return function status */
  1274.   return status;
  1275. }
  1276.  
  1277. /**
  1278.   * @}
  1279.   */
  1280.  
  1281. /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
  1282.   *  @brief    TIM PWM functions
  1283.   *
  1284. @verbatim
  1285.   ==============================================================================
  1286.                           ##### TIM PWM functions #####
  1287.   ==============================================================================
  1288.   [..]
  1289.     This section provides functions allowing to:
  1290.     (+) Initialize and configure the TIM PWM.
  1291.     (+) De-initialize the TIM PWM.
  1292.     (+) Start the TIM PWM.
  1293.     (+) Stop the TIM PWM.
  1294.     (+) Start the TIM PWM and enable interrupt.
  1295.     (+) Stop the TIM PWM and disable interrupt.
  1296.     (+) Start the TIM PWM and enable DMA transfer.
  1297.     (+) Stop the TIM PWM and disable DMA transfer.
  1298.  
  1299. @endverbatim
  1300.   * @{
  1301.   */
  1302. /**
  1303.   * @brief  Initializes the TIM PWM Time Base according to the specified
  1304.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  1305.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  1306.   *         requires a timer reset to avoid unexpected direction
  1307.   *         due to DIR bit readonly in center aligned mode.
  1308.   *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
  1309.   * @param  htim TIM PWM handle
  1310.   * @retval HAL status
  1311.   */
  1312. HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
  1313. {
  1314.   /* Check the TIM handle allocation */
  1315.   if (htim == NULL)
  1316.   {
  1317.     return HAL_ERROR;
  1318.   }
  1319.  
  1320.   /* Check the parameters */
  1321.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1322.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  1323.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  1324.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  1325.  
  1326.   if (htim->State == HAL_TIM_STATE_RESET)
  1327.   {
  1328.     /* Allocate lock resource and initialize it */
  1329.     htim->Lock = HAL_UNLOCKED;
  1330.  
  1331. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1332.     /* Reset interrupt callbacks to legacy weak callbacks */
  1333.     TIM_ResetCallback(htim);
  1334.  
  1335.     if (htim->PWM_MspInitCallback == NULL)
  1336.     {
  1337.       htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
  1338.     }
  1339.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  1340.     htim->PWM_MspInitCallback(htim);
  1341. #else
  1342.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  1343.     HAL_TIM_PWM_MspInit(htim);
  1344. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1345.   }
  1346.  
  1347.   /* Set the TIM state */
  1348.   htim->State = HAL_TIM_STATE_BUSY;
  1349.  
  1350.   /* Init the base time for the PWM */
  1351.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  1352.  
  1353.   /* Initialize the DMA burst operation state */
  1354.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  1355.  
  1356.   /* Initialize the TIM channels state */
  1357.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  1358.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  1359.  
  1360.   /* Initialize the TIM state*/
  1361.   htim->State = HAL_TIM_STATE_READY;
  1362.  
  1363.   return HAL_OK;
  1364. }
  1365.  
  1366. /**
  1367.   * @brief  DeInitializes the TIM peripheral
  1368.   * @param  htim TIM PWM handle
  1369.   * @retval HAL status
  1370.   */
  1371. HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
  1372. {
  1373.   /* Check the parameters */
  1374.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1375.  
  1376.   htim->State = HAL_TIM_STATE_BUSY;
  1377.  
  1378.   /* Disable the TIM Peripheral Clock */
  1379.   __HAL_TIM_DISABLE(htim);
  1380.  
  1381. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1382.   if (htim->PWM_MspDeInitCallback == NULL)
  1383.   {
  1384.     htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
  1385.   }
  1386.   /* DeInit the low level hardware */
  1387.   htim->PWM_MspDeInitCallback(htim);
  1388. #else
  1389.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  1390.   HAL_TIM_PWM_MspDeInit(htim);
  1391. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1392.  
  1393.   /* Change the DMA burst operation state */
  1394.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  1395.  
  1396.   /* Change the TIM channels state */
  1397.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  1398.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  1399.  
  1400.   /* Change TIM state */
  1401.   htim->State = HAL_TIM_STATE_RESET;
  1402.  
  1403.   /* Release Lock */
  1404.   __HAL_UNLOCK(htim);
  1405.  
  1406.   return HAL_OK;
  1407. }
  1408.  
  1409. /**
  1410.   * @brief  Initializes the TIM PWM MSP.
  1411.   * @param  htim TIM PWM handle
  1412.   * @retval None
  1413.   */
  1414. __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
  1415. {
  1416.   /* Prevent unused argument(s) compilation warning */
  1417.   UNUSED(htim);
  1418.  
  1419.   /* NOTE : This function should not be modified, when the callback is needed,
  1420.             the HAL_TIM_PWM_MspInit could be implemented in the user file
  1421.    */
  1422. }
  1423.  
  1424. /**
  1425.   * @brief  DeInitializes TIM PWM MSP.
  1426.   * @param  htim TIM PWM handle
  1427.   * @retval None
  1428.   */
  1429. __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
  1430. {
  1431.   /* Prevent unused argument(s) compilation warning */
  1432.   UNUSED(htim);
  1433.  
  1434.   /* NOTE : This function should not be modified, when the callback is needed,
  1435.             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
  1436.    */
  1437. }
  1438.  
  1439. /**
  1440.   * @brief  Starts the PWM signal generation.
  1441.   * @param  htim TIM handle
  1442.   * @param  Channel TIM Channels to be enabled
  1443.   *          This parameter can be one of the following values:
  1444.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1445.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1446.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1447.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1448.   * @retval HAL status
  1449.   */
  1450. HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  1451. {
  1452.   uint32_t tmpsmcr;
  1453.  
  1454.   /* Check the parameters */
  1455.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1456.  
  1457.   /* Check the TIM channel state */
  1458.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  1459.   {
  1460.     return HAL_ERROR;
  1461.   }
  1462.  
  1463.   /* Set the TIM channel state */
  1464.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1465.  
  1466.   /* Enable the Capture compare channel */
  1467.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1468.  
  1469.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1470.   {
  1471.     /* Enable the main output */
  1472.     __HAL_TIM_MOE_ENABLE(htim);
  1473.   }
  1474.  
  1475.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1476.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1477.   {
  1478.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1479.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1480.     {
  1481.       __HAL_TIM_ENABLE(htim);
  1482.     }
  1483.   }
  1484.   else
  1485.   {
  1486.     __HAL_TIM_ENABLE(htim);
  1487.   }
  1488.  
  1489.   /* Return function status */
  1490.   return HAL_OK;
  1491. }
  1492.  
  1493. /**
  1494.   * @brief  Stops the PWM signal generation.
  1495.   * @param  htim TIM PWM handle
  1496.   * @param  Channel TIM Channels to be disabled
  1497.   *          This parameter can be one of the following values:
  1498.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1499.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1500.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1501.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1502.   * @retval HAL status
  1503.   */
  1504. HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  1505. {
  1506.   /* Check the parameters */
  1507.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1508.  
  1509.   /* Disable the Capture compare channel */
  1510.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1511.  
  1512.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1513.   {
  1514.     /* Disable the Main Output */
  1515.     __HAL_TIM_MOE_DISABLE(htim);
  1516.   }
  1517.  
  1518.   /* Disable the Peripheral */
  1519.   __HAL_TIM_DISABLE(htim);
  1520.  
  1521.   /* Set the TIM channel state */
  1522.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1523.  
  1524.   /* Return function status */
  1525.   return HAL_OK;
  1526. }
  1527.  
  1528. /**
  1529.   * @brief  Starts the PWM signal generation in interrupt mode.
  1530.   * @param  htim TIM PWM handle
  1531.   * @param  Channel TIM Channel to be enabled
  1532.   *          This parameter can be one of the following values:
  1533.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1534.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1535.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1536.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1537.   * @retval HAL status
  1538.   */
  1539. HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  1540. {
  1541.   HAL_StatusTypeDef status = HAL_OK;
  1542.   uint32_t tmpsmcr;
  1543.  
  1544.   /* Check the parameters */
  1545.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1546.  
  1547.   /* Check the TIM channel state */
  1548.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  1549.   {
  1550.     return HAL_ERROR;
  1551.   }
  1552.  
  1553.   /* Set the TIM channel state */
  1554.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1555.  
  1556.   switch (Channel)
  1557.   {
  1558.     case TIM_CHANNEL_1:
  1559.     {
  1560.       /* Enable the TIM Capture/Compare 1 interrupt */
  1561.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  1562.       break;
  1563.     }
  1564.  
  1565.     case TIM_CHANNEL_2:
  1566.     {
  1567.       /* Enable the TIM Capture/Compare 2 interrupt */
  1568.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  1569.       break;
  1570.     }
  1571.  
  1572.     case TIM_CHANNEL_3:
  1573.     {
  1574.       /* Enable the TIM Capture/Compare 3 interrupt */
  1575.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  1576.       break;
  1577.     }
  1578.  
  1579.     case TIM_CHANNEL_4:
  1580.     {
  1581.       /* Enable the TIM Capture/Compare 4 interrupt */
  1582.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  1583.       break;
  1584.     }
  1585.  
  1586.     default:
  1587.       status = HAL_ERROR;
  1588.       break;
  1589.   }
  1590.  
  1591.   if (status == HAL_OK)
  1592.   {
  1593.     /* Enable the Capture compare channel */
  1594.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1595.  
  1596.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1597.     {
  1598.       /* Enable the main output */
  1599.       __HAL_TIM_MOE_ENABLE(htim);
  1600.     }
  1601.  
  1602.     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1603.     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1604.     {
  1605.       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1606.       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1607.       {
  1608.         __HAL_TIM_ENABLE(htim);
  1609.       }
  1610.     }
  1611.     else
  1612.     {
  1613.       __HAL_TIM_ENABLE(htim);
  1614.     }
  1615.   }
  1616.  
  1617.   /* Return function status */
  1618.   return status;
  1619. }
  1620.  
  1621. /**
  1622.   * @brief  Stops the PWM signal generation in interrupt mode.
  1623.   * @param  htim TIM PWM handle
  1624.   * @param  Channel TIM Channels to be disabled
  1625.   *          This parameter can be one of the following values:
  1626.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1627.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1628.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1629.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1630.   * @retval HAL status
  1631.   */
  1632. HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  1633. {
  1634.   HAL_StatusTypeDef status = HAL_OK;
  1635.  
  1636.   /* Check the parameters */
  1637.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1638.  
  1639.   switch (Channel)
  1640.   {
  1641.     case TIM_CHANNEL_1:
  1642.     {
  1643.       /* Disable the TIM Capture/Compare 1 interrupt */
  1644.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  1645.       break;
  1646.     }
  1647.  
  1648.     case TIM_CHANNEL_2:
  1649.     {
  1650.       /* Disable the TIM Capture/Compare 2 interrupt */
  1651.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  1652.       break;
  1653.     }
  1654.  
  1655.     case TIM_CHANNEL_3:
  1656.     {
  1657.       /* Disable the TIM Capture/Compare 3 interrupt */
  1658.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  1659.       break;
  1660.     }
  1661.  
  1662.     case TIM_CHANNEL_4:
  1663.     {
  1664.       /* Disable the TIM Capture/Compare 4 interrupt */
  1665.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  1666.       break;
  1667.     }
  1668.  
  1669.     default:
  1670.       status = HAL_ERROR;
  1671.       break;
  1672.   }
  1673.  
  1674.   if (status == HAL_OK)
  1675.   {
  1676.     /* Disable the Capture compare channel */
  1677.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1678.  
  1679.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1680.     {
  1681.       /* Disable the Main Output */
  1682.       __HAL_TIM_MOE_DISABLE(htim);
  1683.     }
  1684.  
  1685.     /* Disable the Peripheral */
  1686.     __HAL_TIM_DISABLE(htim);
  1687.  
  1688.     /* Set the TIM channel state */
  1689.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1690.   }
  1691.  
  1692.   /* Return function status */
  1693.   return status;
  1694. }
  1695.  
  1696. /**
  1697.   * @brief  Starts the TIM PWM signal generation in DMA mode.
  1698.   * @param  htim TIM PWM handle
  1699.   * @param  Channel TIM Channels to be enabled
  1700.   *          This parameter can be one of the following values:
  1701.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1702.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1703.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1704.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1705.   * @param  pData The source Buffer address.
  1706.   * @param  Length The length of data to be transferred from memory to TIM peripheral
  1707.   * @retval HAL status
  1708.   */
  1709. HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
  1710. {
  1711.   HAL_StatusTypeDef status = HAL_OK;
  1712.   uint32_t tmpsmcr;
  1713.  
  1714.   /* Check the parameters */
  1715.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1716.  
  1717.   /* Set the TIM channel state */
  1718.   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
  1719.   {
  1720.     return HAL_BUSY;
  1721.   }
  1722.   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
  1723.   {
  1724.     if ((pData == NULL) && (Length > 0U))
  1725.     {
  1726.       return HAL_ERROR;
  1727.     }
  1728.     else
  1729.     {
  1730.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1731.     }
  1732.   }
  1733.   else
  1734.   {
  1735.     return HAL_ERROR;
  1736.   }
  1737.  
  1738.   switch (Channel)
  1739.   {
  1740.     case TIM_CHANNEL_1:
  1741.     {
  1742.       /* Set the DMA compare callbacks */
  1743.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1744.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1745.  
  1746.       /* Set the DMA error callback */
  1747.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  1748.  
  1749.       /* Enable the DMA channel */
  1750.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
  1751.                            Length) != HAL_OK)
  1752.       {
  1753.         /* Return error status */
  1754.         return HAL_ERROR;
  1755.       }
  1756.  
  1757.       /* Enable the TIM Capture/Compare 1 DMA request */
  1758.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  1759.       break;
  1760.     }
  1761.  
  1762.     case TIM_CHANNEL_2:
  1763.     {
  1764.       /* Set the DMA compare callbacks */
  1765.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1766.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1767.  
  1768.       /* Set the DMA error callback */
  1769.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  1770.  
  1771.       /* Enable the DMA channel */
  1772.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
  1773.                            Length) != HAL_OK)
  1774.       {
  1775.         /* Return error status */
  1776.         return HAL_ERROR;
  1777.       }
  1778.       /* Enable the TIM Capture/Compare 2 DMA request */
  1779.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  1780.       break;
  1781.     }
  1782.  
  1783.     case TIM_CHANNEL_3:
  1784.     {
  1785.       /* Set the DMA compare callbacks */
  1786.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1787.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1788.  
  1789.       /* Set the DMA error callback */
  1790.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  1791.  
  1792.       /* Enable the DMA channel */
  1793.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
  1794.                            Length) != HAL_OK)
  1795.       {
  1796.         /* Return error status */
  1797.         return HAL_ERROR;
  1798.       }
  1799.       /* Enable the TIM Output Capture/Compare 3 request */
  1800.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  1801.       break;
  1802.     }
  1803.  
  1804.     case TIM_CHANNEL_4:
  1805.     {
  1806.       /* Set the DMA compare callbacks */
  1807.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1808.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1809.  
  1810.       /* Set the DMA error callback */
  1811.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  1812.  
  1813.       /* Enable the DMA channel */
  1814.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
  1815.                            Length) != HAL_OK)
  1816.       {
  1817.         /* Return error status */
  1818.         return HAL_ERROR;
  1819.       }
  1820.       /* Enable the TIM Capture/Compare 4 DMA request */
  1821.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  1822.       break;
  1823.     }
  1824.  
  1825.     default:
  1826.       status = HAL_ERROR;
  1827.       break;
  1828.   }
  1829.  
  1830.   if (status == HAL_OK)
  1831.   {
  1832.     /* Enable the Capture compare channel */
  1833.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1834.  
  1835.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1836.     {
  1837.       /* Enable the main output */
  1838.       __HAL_TIM_MOE_ENABLE(htim);
  1839.     }
  1840.  
  1841.     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1842.     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1843.     {
  1844.       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1845.       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1846.       {
  1847.         __HAL_TIM_ENABLE(htim);
  1848.       }
  1849.     }
  1850.     else
  1851.     {
  1852.       __HAL_TIM_ENABLE(htim);
  1853.     }
  1854.   }
  1855.  
  1856.   /* Return function status */
  1857.   return status;
  1858. }
  1859.  
  1860. /**
  1861.   * @brief  Stops the TIM PWM signal generation in DMA mode.
  1862.   * @param  htim TIM PWM handle
  1863.   * @param  Channel TIM Channels to be disabled
  1864.   *          This parameter can be one of the following values:
  1865.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1866.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1867.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1868.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1869.   * @retval HAL status
  1870.   */
  1871. HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  1872. {
  1873.   HAL_StatusTypeDef status = HAL_OK;
  1874.  
  1875.   /* Check the parameters */
  1876.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1877.  
  1878.   switch (Channel)
  1879.   {
  1880.     case TIM_CHANNEL_1:
  1881.     {
  1882.       /* Disable the TIM Capture/Compare 1 DMA request */
  1883.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  1884.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  1885.       break;
  1886.     }
  1887.  
  1888.     case TIM_CHANNEL_2:
  1889.     {
  1890.       /* Disable the TIM Capture/Compare 2 DMA request */
  1891.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  1892.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  1893.       break;
  1894.     }
  1895.  
  1896.     case TIM_CHANNEL_3:
  1897.     {
  1898.       /* Disable the TIM Capture/Compare 3 DMA request */
  1899.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  1900.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  1901.       break;
  1902.     }
  1903.  
  1904.     case TIM_CHANNEL_4:
  1905.     {
  1906.       /* Disable the TIM Capture/Compare 4 interrupt */
  1907.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  1908.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  1909.       break;
  1910.     }
  1911.  
  1912.     default:
  1913.       status = HAL_ERROR;
  1914.       break;
  1915.   }
  1916.  
  1917.   if (status == HAL_OK)
  1918.   {
  1919.     /* Disable the Capture compare channel */
  1920.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1921.  
  1922.     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  1923.     {
  1924.       /* Disable the Main Output */
  1925.       __HAL_TIM_MOE_DISABLE(htim);
  1926.     }
  1927.  
  1928.     /* Disable the Peripheral */
  1929.     __HAL_TIM_DISABLE(htim);
  1930.  
  1931.     /* Set the TIM channel state */
  1932.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1933.   }
  1934.  
  1935.   /* Return function status */
  1936.   return status;
  1937. }
  1938.  
  1939. /**
  1940.   * @}
  1941.   */
  1942.  
  1943. /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
  1944.   *  @brief    TIM Input Capture functions
  1945.   *
  1946. @verbatim
  1947.   ==============================================================================
  1948.               ##### TIM Input Capture functions #####
  1949.   ==============================================================================
  1950.  [..]
  1951.    This section provides functions allowing to:
  1952.    (+) Initialize and configure the TIM Input Capture.
  1953.    (+) De-initialize the TIM Input Capture.
  1954.    (+) Start the TIM Input Capture.
  1955.    (+) Stop the TIM Input Capture.
  1956.    (+) Start the TIM Input Capture and enable interrupt.
  1957.    (+) Stop the TIM Input Capture and disable interrupt.
  1958.    (+) Start the TIM Input Capture and enable DMA transfer.
  1959.    (+) Stop the TIM Input Capture and disable DMA transfer.
  1960.  
  1961. @endverbatim
  1962.   * @{
  1963.   */
  1964. /**
  1965.   * @brief  Initializes the TIM Input Capture Time base according to the specified
  1966.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  1967.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  1968.   *         requires a timer reset to avoid unexpected direction
  1969.   *         due to DIR bit readonly in center aligned mode.
  1970.   *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
  1971.   * @param  htim TIM Input Capture handle
  1972.   * @retval HAL status
  1973.   */
  1974. HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
  1975. {
  1976.   /* Check the TIM handle allocation */
  1977.   if (htim == NULL)
  1978.   {
  1979.     return HAL_ERROR;
  1980.   }
  1981.  
  1982.   /* Check the parameters */
  1983.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1984.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  1985.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  1986.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  1987.  
  1988.   if (htim->State == HAL_TIM_STATE_RESET)
  1989.   {
  1990.     /* Allocate lock resource and initialize it */
  1991.     htim->Lock = HAL_UNLOCKED;
  1992.  
  1993. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1994.     /* Reset interrupt callbacks to legacy weak callbacks */
  1995.     TIM_ResetCallback(htim);
  1996.  
  1997.     if (htim->IC_MspInitCallback == NULL)
  1998.     {
  1999.       htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
  2000.     }
  2001.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  2002.     htim->IC_MspInitCallback(htim);
  2003. #else
  2004.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  2005.     HAL_TIM_IC_MspInit(htim);
  2006. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2007.   }
  2008.  
  2009.   /* Set the TIM state */
  2010.   htim->State = HAL_TIM_STATE_BUSY;
  2011.  
  2012.   /* Init the base time for the input capture */
  2013.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  2014.  
  2015.   /* Initialize the DMA burst operation state */
  2016.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  2017.  
  2018.   /* Initialize the TIM channels state */
  2019.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  2020.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  2021.  
  2022.   /* Initialize the TIM state*/
  2023.   htim->State = HAL_TIM_STATE_READY;
  2024.  
  2025.   return HAL_OK;
  2026. }
  2027.  
  2028. /**
  2029.   * @brief  DeInitializes the TIM peripheral
  2030.   * @param  htim TIM Input Capture handle
  2031.   * @retval HAL status
  2032.   */
  2033. HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
  2034. {
  2035.   /* Check the parameters */
  2036.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  2037.  
  2038.   htim->State = HAL_TIM_STATE_BUSY;
  2039.  
  2040.   /* Disable the TIM Peripheral Clock */
  2041.   __HAL_TIM_DISABLE(htim);
  2042.  
  2043. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2044.   if (htim->IC_MspDeInitCallback == NULL)
  2045.   {
  2046.     htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
  2047.   }
  2048.   /* DeInit the low level hardware */
  2049.   htim->IC_MspDeInitCallback(htim);
  2050. #else
  2051.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  2052.   HAL_TIM_IC_MspDeInit(htim);
  2053. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2054.  
  2055.   /* Change the DMA burst operation state */
  2056.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  2057.  
  2058.   /* Change the TIM channels state */
  2059.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  2060.   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  2061.  
  2062.   /* Change TIM state */
  2063.   htim->State = HAL_TIM_STATE_RESET;
  2064.  
  2065.   /* Release Lock */
  2066.   __HAL_UNLOCK(htim);
  2067.  
  2068.   return HAL_OK;
  2069. }
  2070.  
  2071. /**
  2072.   * @brief  Initializes the TIM Input Capture MSP.
  2073.   * @param  htim TIM Input Capture handle
  2074.   * @retval None
  2075.   */
  2076. __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
  2077. {
  2078.   /* Prevent unused argument(s) compilation warning */
  2079.   UNUSED(htim);
  2080.  
  2081.   /* NOTE : This function should not be modified, when the callback is needed,
  2082.             the HAL_TIM_IC_MspInit could be implemented in the user file
  2083.    */
  2084. }
  2085.  
  2086. /**
  2087.   * @brief  DeInitializes TIM Input Capture MSP.
  2088.   * @param  htim TIM handle
  2089.   * @retval None
  2090.   */
  2091. __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
  2092. {
  2093.   /* Prevent unused argument(s) compilation warning */
  2094.   UNUSED(htim);
  2095.  
  2096.   /* NOTE : This function should not be modified, when the callback is needed,
  2097.             the HAL_TIM_IC_MspDeInit could be implemented in the user file
  2098.    */
  2099. }
  2100.  
  2101. /**
  2102.   * @brief  Starts the TIM Input Capture measurement.
  2103.   * @param  htim TIM Input Capture handle
  2104.   * @param  Channel TIM Channels to be enabled
  2105.   *          This parameter can be one of the following values:
  2106.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2107.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2108.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2109.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2110.   * @retval HAL status
  2111.   */
  2112. HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  2113. {
  2114.   uint32_t tmpsmcr;
  2115.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  2116.   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
  2117.  
  2118.   /* Check the parameters */
  2119.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2120.  
  2121.   /* Check the TIM channel state */
  2122.   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
  2123.       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
  2124.   {
  2125.     return HAL_ERROR;
  2126.   }
  2127.  
  2128.   /* Set the TIM channel state */
  2129.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2130.   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2131.  
  2132.   /* Enable the Input Capture channel */
  2133.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  2134.  
  2135.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  2136.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  2137.   {
  2138.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  2139.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  2140.     {
  2141.       __HAL_TIM_ENABLE(htim);
  2142.     }
  2143.   }
  2144.   else
  2145.   {
  2146.     __HAL_TIM_ENABLE(htim);
  2147.   }
  2148.  
  2149.   /* Return function status */
  2150.   return HAL_OK;
  2151. }
  2152.  
  2153. /**
  2154.   * @brief  Stops the TIM Input Capture measurement.
  2155.   * @param  htim TIM Input Capture handle
  2156.   * @param  Channel TIM Channels to be disabled
  2157.   *          This parameter can be one of the following values:
  2158.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2159.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2160.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2161.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2162.   * @retval HAL status
  2163.   */
  2164. HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  2165. {
  2166.   /* Check the parameters */
  2167.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2168.  
  2169.   /* Disable the Input Capture channel */
  2170.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2171.  
  2172.   /* Disable the Peripheral */
  2173.   __HAL_TIM_DISABLE(htim);
  2174.  
  2175.   /* Set the TIM channel state */
  2176.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2177.   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2178.  
  2179.   /* Return function status */
  2180.   return HAL_OK;
  2181. }
  2182.  
  2183. /**
  2184.   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
  2185.   * @param  htim TIM Input Capture handle
  2186.   * @param  Channel TIM Channels to be enabled
  2187.   *          This parameter can be one of the following values:
  2188.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2189.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2190.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2191.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2192.   * @retval HAL status
  2193.   */
  2194. HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  2195. {
  2196.   HAL_StatusTypeDef status = HAL_OK;
  2197.   uint32_t tmpsmcr;
  2198.  
  2199.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  2200.   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
  2201.  
  2202.   /* Check the parameters */
  2203.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2204.  
  2205.   /* Check the TIM channel state */
  2206.   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
  2207.       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
  2208.   {
  2209.     return HAL_ERROR;
  2210.   }
  2211.  
  2212.   /* Set the TIM channel state */
  2213.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2214.   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2215.  
  2216.   switch (Channel)
  2217.   {
  2218.     case TIM_CHANNEL_1:
  2219.     {
  2220.       /* Enable the TIM Capture/Compare 1 interrupt */
  2221.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  2222.       break;
  2223.     }
  2224.  
  2225.     case TIM_CHANNEL_2:
  2226.     {
  2227.       /* Enable the TIM Capture/Compare 2 interrupt */
  2228.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  2229.       break;
  2230.     }
  2231.  
  2232.     case TIM_CHANNEL_3:
  2233.     {
  2234.       /* Enable the TIM Capture/Compare 3 interrupt */
  2235.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  2236.       break;
  2237.     }
  2238.  
  2239.     case TIM_CHANNEL_4:
  2240.     {
  2241.       /* Enable the TIM Capture/Compare 4 interrupt */
  2242.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  2243.       break;
  2244.     }
  2245.  
  2246.     default:
  2247.       status = HAL_ERROR;
  2248.       break;
  2249.   }
  2250.  
  2251.   if (status == HAL_OK)
  2252.   {
  2253.     /* Enable the Input Capture channel */
  2254.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  2255.  
  2256.     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  2257.     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  2258.     {
  2259.       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  2260.       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  2261.       {
  2262.         __HAL_TIM_ENABLE(htim);
  2263.       }
  2264.     }
  2265.     else
  2266.     {
  2267.       __HAL_TIM_ENABLE(htim);
  2268.     }
  2269.   }
  2270.  
  2271.   /* Return function status */
  2272.   return status;
  2273. }
  2274.  
  2275. /**
  2276.   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
  2277.   * @param  htim TIM Input Capture handle
  2278.   * @param  Channel TIM Channels to be disabled
  2279.   *          This parameter can be one of the following values:
  2280.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2281.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2282.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2283.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2284.   * @retval HAL status
  2285.   */
  2286. HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  2287. {
  2288.   HAL_StatusTypeDef status = HAL_OK;
  2289.  
  2290.   /* Check the parameters */
  2291.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2292.  
  2293.   switch (Channel)
  2294.   {
  2295.     case TIM_CHANNEL_1:
  2296.     {
  2297.       /* Disable the TIM Capture/Compare 1 interrupt */
  2298.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  2299.       break;
  2300.     }
  2301.  
  2302.     case TIM_CHANNEL_2:
  2303.     {
  2304.       /* Disable the TIM Capture/Compare 2 interrupt */
  2305.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  2306.       break;
  2307.     }
  2308.  
  2309.     case TIM_CHANNEL_3:
  2310.     {
  2311.       /* Disable the TIM Capture/Compare 3 interrupt */
  2312.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  2313.       break;
  2314.     }
  2315.  
  2316.     case TIM_CHANNEL_4:
  2317.     {
  2318.       /* Disable the TIM Capture/Compare 4 interrupt */
  2319.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  2320.       break;
  2321.     }
  2322.  
  2323.     default:
  2324.       status = HAL_ERROR;
  2325.       break;
  2326.   }
  2327.  
  2328.   if (status == HAL_OK)
  2329.   {
  2330.     /* Disable the Input Capture channel */
  2331.     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2332.  
  2333.     /* Disable the Peripheral */
  2334.     __HAL_TIM_DISABLE(htim);
  2335.  
  2336.     /* Set the TIM channel state */
  2337.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2338.     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2339.   }
  2340.  
  2341.   /* Return function status */
  2342.   return status;
  2343. }
  2344.  
  2345. /**
  2346.   * @brief  Starts the TIM Input Capture measurement in DMA mode.
  2347.   * @param  htim TIM Input Capture handle
  2348.   * @param  Channel TIM Channels to be enabled
  2349.   *          This parameter can be one of the following values:
  2350.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2351.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2352.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2353.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2354.   * @param  pData The destination Buffer address.
  2355.   * @param  Length The length of data to be transferred from TIM peripheral to memory.
  2356.   * @retval HAL status
  2357.   */
  2358. HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
  2359. {
  2360.   HAL_StatusTypeDef status = HAL_OK;
  2361.   uint32_t tmpsmcr;
  2362.  
  2363.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  2364.   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
  2365.  
  2366.   /* Check the parameters */
  2367.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2368.   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
  2369.  
  2370.   /* Set the TIM channel state */
  2371.   if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
  2372.       || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
  2373.   {
  2374.     return HAL_BUSY;
  2375.   }
  2376.   else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
  2377.            && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
  2378.   {
  2379.     if ((pData == NULL) && (Length > 0U))
  2380.     {
  2381.       return HAL_ERROR;
  2382.     }
  2383.     else
  2384.     {
  2385.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2386.       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2387.     }
  2388.   }
  2389.   else
  2390.   {
  2391.     return HAL_ERROR;
  2392.   }
  2393.  
  2394.   /* Enable the Input Capture channel */
  2395.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  2396.  
  2397.   switch (Channel)
  2398.   {
  2399.     case TIM_CHANNEL_1:
  2400.     {
  2401.       /* Set the DMA capture callbacks */
  2402.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  2403.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2404.  
  2405.       /* Set the DMA error callback */
  2406.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  2407.  
  2408.       /* Enable the DMA channel */
  2409.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
  2410.                            Length) != HAL_OK)
  2411.       {
  2412.         /* Return error status */
  2413.         return HAL_ERROR;
  2414.       }
  2415.       /* Enable the TIM Capture/Compare 1 DMA request */
  2416.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  2417.       break;
  2418.     }
  2419.  
  2420.     case TIM_CHANNEL_2:
  2421.     {
  2422.       /* Set the DMA capture callbacks */
  2423.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  2424.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2425.  
  2426.       /* Set the DMA error callback */
  2427.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  2428.  
  2429.       /* Enable the DMA channel */
  2430.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
  2431.                            Length) != HAL_OK)
  2432.       {
  2433.         /* Return error status */
  2434.         return HAL_ERROR;
  2435.       }
  2436.       /* Enable the TIM Capture/Compare 2  DMA request */
  2437.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  2438.       break;
  2439.     }
  2440.  
  2441.     case TIM_CHANNEL_3:
  2442.     {
  2443.       /* Set the DMA capture callbacks */
  2444.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
  2445.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2446.  
  2447.       /* Set the DMA error callback */
  2448.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  2449.  
  2450.       /* Enable the DMA channel */
  2451.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
  2452.                            Length) != HAL_OK)
  2453.       {
  2454.         /* Return error status */
  2455.         return HAL_ERROR;
  2456.       }
  2457.       /* Enable the TIM Capture/Compare 3  DMA request */
  2458.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  2459.       break;
  2460.     }
  2461.  
  2462.     case TIM_CHANNEL_4:
  2463.     {
  2464.       /* Set the DMA capture callbacks */
  2465.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
  2466.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2467.  
  2468.       /* Set the DMA error callback */
  2469.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  2470.  
  2471.       /* Enable the DMA channel */
  2472.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
  2473.                            Length) != HAL_OK)
  2474.       {
  2475.         /* Return error status */
  2476.         return HAL_ERROR;
  2477.       }
  2478.       /* Enable the TIM Capture/Compare 4  DMA request */
  2479.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  2480.       break;
  2481.     }
  2482.  
  2483.     default:
  2484.       status = HAL_ERROR;
  2485.       break;
  2486.   }
  2487.  
  2488.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  2489.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  2490.   {
  2491.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  2492.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  2493.     {
  2494.       __HAL_TIM_ENABLE(htim);
  2495.     }
  2496.   }
  2497.   else
  2498.   {
  2499.     __HAL_TIM_ENABLE(htim);
  2500.   }
  2501.  
  2502.   /* Return function status */
  2503.   return status;
  2504. }
  2505.  
  2506. /**
  2507.   * @brief  Stops the TIM Input Capture measurement in DMA mode.
  2508.   * @param  htim TIM Input Capture handle
  2509.   * @param  Channel TIM Channels to be disabled
  2510.   *          This parameter can be one of the following values:
  2511.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2512.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2513.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2514.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2515.   * @retval HAL status
  2516.   */
  2517. HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  2518. {
  2519.   HAL_StatusTypeDef status = HAL_OK;
  2520.  
  2521.   /* Check the parameters */
  2522.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2523.   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
  2524.  
  2525.   /* Disable the Input Capture channel */
  2526.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2527.  
  2528.   switch (Channel)
  2529.   {
  2530.     case TIM_CHANNEL_1:
  2531.     {
  2532.       /* Disable the TIM Capture/Compare 1 DMA request */
  2533.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  2534.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  2535.       break;
  2536.     }
  2537.  
  2538.     case TIM_CHANNEL_2:
  2539.     {
  2540.       /* Disable the TIM Capture/Compare 2 DMA request */
  2541.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  2542.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  2543.       break;
  2544.     }
  2545.  
  2546.     case TIM_CHANNEL_3:
  2547.     {
  2548.       /* Disable the TIM Capture/Compare 3  DMA request */
  2549.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  2550.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  2551.       break;
  2552.     }
  2553.  
  2554.     case TIM_CHANNEL_4:
  2555.     {
  2556.       /* Disable the TIM Capture/Compare 4  DMA request */
  2557.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  2558.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  2559.       break;
  2560.     }
  2561.  
  2562.     default:
  2563.       status = HAL_ERROR;
  2564.       break;
  2565.   }
  2566.  
  2567.   if (status == HAL_OK)
  2568.   {
  2569.     /* Disable the Peripheral */
  2570.     __HAL_TIM_DISABLE(htim);
  2571.  
  2572.     /* Set the TIM channel state */
  2573.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2574.     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2575.   }
  2576.  
  2577.   /* Return function status */
  2578.   return status;
  2579. }
  2580. /**
  2581.   * @}
  2582.   */
  2583.  
  2584. /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
  2585.   *  @brief    TIM One Pulse functions
  2586.   *
  2587. @verbatim
  2588.   ==============================================================================
  2589.                         ##### TIM One Pulse functions #####
  2590.   ==============================================================================
  2591.   [..]
  2592.     This section provides functions allowing to:
  2593.     (+) Initialize and configure the TIM One Pulse.
  2594.     (+) De-initialize the TIM One Pulse.
  2595.     (+) Start the TIM One Pulse.
  2596.     (+) Stop the TIM One Pulse.
  2597.     (+) Start the TIM One Pulse and enable interrupt.
  2598.     (+) Stop the TIM One Pulse and disable interrupt.
  2599.     (+) Start the TIM One Pulse and enable DMA transfer.
  2600.     (+) Stop the TIM One Pulse and disable DMA transfer.
  2601.  
  2602. @endverbatim
  2603.   * @{
  2604.   */
  2605. /**
  2606.   * @brief  Initializes the TIM One Pulse Time Base according to the specified
  2607.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  2608.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  2609.   *         requires a timer reset to avoid unexpected direction
  2610.   *         due to DIR bit readonly in center aligned mode.
  2611.   *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
  2612.   * @note   When the timer instance is initialized in One Pulse mode, timer
  2613.   *         channels 1 and channel 2 are reserved and cannot be used for other
  2614.   *         purpose.
  2615.   * @param  htim TIM One Pulse handle
  2616.   * @param  OnePulseMode Select the One pulse mode.
  2617.   *         This parameter can be one of the following values:
  2618.   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
  2619.   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
  2620.   * @retval HAL status
  2621.   */
  2622. HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
  2623. {
  2624.   /* Check the TIM handle allocation */
  2625.   if (htim == NULL)
  2626.   {
  2627.     return HAL_ERROR;
  2628.   }
  2629.  
  2630.   /* Check the parameters */
  2631.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  2632.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  2633.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  2634.   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
  2635.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  2636.  
  2637.   if (htim->State == HAL_TIM_STATE_RESET)
  2638.   {
  2639.     /* Allocate lock resource and initialize it */
  2640.     htim->Lock = HAL_UNLOCKED;
  2641.  
  2642. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2643.     /* Reset interrupt callbacks to legacy weak callbacks */
  2644.     TIM_ResetCallback(htim);
  2645.  
  2646.     if (htim->OnePulse_MspInitCallback == NULL)
  2647.     {
  2648.       htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
  2649.     }
  2650.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  2651.     htim->OnePulse_MspInitCallback(htim);
  2652. #else
  2653.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  2654.     HAL_TIM_OnePulse_MspInit(htim);
  2655. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2656.   }
  2657.  
  2658.   /* Set the TIM state */
  2659.   htim->State = HAL_TIM_STATE_BUSY;
  2660.  
  2661.   /* Configure the Time base in the One Pulse Mode */
  2662.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  2663.  
  2664.   /* Reset the OPM Bit */
  2665.   htim->Instance->CR1 &= ~TIM_CR1_OPM;
  2666.  
  2667.   /* Configure the OPM Mode */
  2668.   htim->Instance->CR1 |= OnePulseMode;
  2669.  
  2670.   /* Initialize the DMA burst operation state */
  2671.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  2672.  
  2673.   /* Initialize the TIM channels state */
  2674.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2675.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2676.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2677.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2678.  
  2679.   /* Initialize the TIM state*/
  2680.   htim->State = HAL_TIM_STATE_READY;
  2681.  
  2682.   return HAL_OK;
  2683. }
  2684.  
  2685. /**
  2686.   * @brief  DeInitializes the TIM One Pulse
  2687.   * @param  htim TIM One Pulse handle
  2688.   * @retval HAL status
  2689.   */
  2690. HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
  2691. {
  2692.   /* Check the parameters */
  2693.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  2694.  
  2695.   htim->State = HAL_TIM_STATE_BUSY;
  2696.  
  2697.   /* Disable the TIM Peripheral Clock */
  2698.   __HAL_TIM_DISABLE(htim);
  2699.  
  2700. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2701.   if (htim->OnePulse_MspDeInitCallback == NULL)
  2702.   {
  2703.     htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
  2704.   }
  2705.   /* DeInit the low level hardware */
  2706.   htim->OnePulse_MspDeInitCallback(htim);
  2707. #else
  2708.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  2709.   HAL_TIM_OnePulse_MspDeInit(htim);
  2710. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2711.  
  2712.   /* Change the DMA burst operation state */
  2713.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  2714.  
  2715.   /* Set the TIM channel state */
  2716.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  2717.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  2718.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  2719.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  2720.  
  2721.   /* Change TIM state */
  2722.   htim->State = HAL_TIM_STATE_RESET;
  2723.  
  2724.   /* Release Lock */
  2725.   __HAL_UNLOCK(htim);
  2726.  
  2727.   return HAL_OK;
  2728. }
  2729.  
  2730. /**
  2731.   * @brief  Initializes the TIM One Pulse MSP.
  2732.   * @param  htim TIM One Pulse handle
  2733.   * @retval None
  2734.   */
  2735. __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
  2736. {
  2737.   /* Prevent unused argument(s) compilation warning */
  2738.   UNUSED(htim);
  2739.  
  2740.   /* NOTE : This function should not be modified, when the callback is needed,
  2741.             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
  2742.    */
  2743. }
  2744.  
  2745. /**
  2746.   * @brief  DeInitializes TIM One Pulse MSP.
  2747.   * @param  htim TIM One Pulse handle
  2748.   * @retval None
  2749.   */
  2750. __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
  2751. {
  2752.   /* Prevent unused argument(s) compilation warning */
  2753.   UNUSED(htim);
  2754.  
  2755.   /* NOTE : This function should not be modified, when the callback is needed,
  2756.             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
  2757.    */
  2758. }
  2759.  
  2760. /**
  2761.   * @brief  Starts the TIM One Pulse signal generation.
  2762.   * @note Though OutputChannel parameter is deprecated and ignored by the function
  2763.   *        it has been kept to avoid HAL_TIM API compatibility break.
  2764.   * @note The pulse output channel is determined when calling
  2765.   *       @ref HAL_TIM_OnePulse_ConfigChannel().
  2766.   * @param  htim TIM One Pulse handle
  2767.   * @param  OutputChannel See note above
  2768.   * @retval HAL status
  2769.   */
  2770. HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2771. {
  2772.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  2773.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  2774.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  2775.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  2776.  
  2777.   /* Prevent unused argument(s) compilation warning */
  2778.   UNUSED(OutputChannel);
  2779.  
  2780.   /* Check the TIM channels state */
  2781.   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2782.       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  2783.       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2784.       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  2785.   {
  2786.     return HAL_ERROR;
  2787.   }
  2788.  
  2789.   /* Set the TIM channels state */
  2790.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2791.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2792.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2793.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2794.  
  2795.   /* Enable the Capture compare and the Input Capture channels
  2796.     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2797.     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2798.     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2799.     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
  2800.  
  2801.     No need to enable the counter, it's enabled automatically by hardware
  2802.     (the counter starts in response to a stimulus and generate a pulse */
  2803.  
  2804.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  2805.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  2806.  
  2807.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  2808.   {
  2809.     /* Enable the main output */
  2810.     __HAL_TIM_MOE_ENABLE(htim);
  2811.   }
  2812.  
  2813.   /* Return function status */
  2814.   return HAL_OK;
  2815. }
  2816.  
  2817. /**
  2818.   * @brief  Stops the TIM One Pulse signal generation.
  2819.   * @note Though OutputChannel parameter is deprecated and ignored by the function
  2820.   *        it has been kept to avoid HAL_TIM API compatibility break.
  2821.   * @note The pulse output channel is determined when calling
  2822.   *       @ref HAL_TIM_OnePulse_ConfigChannel().
  2823.   * @param  htim TIM One Pulse handle
  2824.   * @param  OutputChannel See note above
  2825.   * @retval HAL status
  2826.   */
  2827. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2828. {
  2829.   /* Prevent unused argument(s) compilation warning */
  2830.   UNUSED(OutputChannel);
  2831.  
  2832.   /* Disable the Capture compare and the Input Capture channels
  2833.   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2834.   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2835.   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2836.   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
  2837.  
  2838.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  2839.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  2840.  
  2841.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  2842.   {
  2843.     /* Disable the Main Output */
  2844.     __HAL_TIM_MOE_DISABLE(htim);
  2845.   }
  2846.  
  2847.   /* Disable the Peripheral */
  2848.   __HAL_TIM_DISABLE(htim);
  2849.  
  2850.   /* Set the TIM channels state */
  2851.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2852.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2853.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2854.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2855.  
  2856.   /* Return function status */
  2857.   return HAL_OK;
  2858. }
  2859.  
  2860. /**
  2861.   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
  2862.   * @note Though OutputChannel parameter is deprecated and ignored by the function
  2863.   *        it has been kept to avoid HAL_TIM API compatibility break.
  2864.   * @note The pulse output channel is determined when calling
  2865.   *       @ref HAL_TIM_OnePulse_ConfigChannel().
  2866.   * @param  htim TIM One Pulse handle
  2867.   * @param  OutputChannel See note above
  2868.   * @retval HAL status
  2869.   */
  2870. HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2871. {
  2872.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  2873.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  2874.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  2875.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  2876.  
  2877.   /* Prevent unused argument(s) compilation warning */
  2878.   UNUSED(OutputChannel);
  2879.  
  2880.   /* Check the TIM channels state */
  2881.   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2882.       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  2883.       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2884.       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  2885.   {
  2886.     return HAL_ERROR;
  2887.   }
  2888.  
  2889.   /* Set the TIM channels state */
  2890.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2891.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2892.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2893.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2894.  
  2895.   /* Enable the Capture compare and the Input Capture channels
  2896.     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2897.     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2898.     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2899.     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
  2900.  
  2901.     No need to enable the counter, it's enabled automatically by hardware
  2902.     (the counter starts in response to a stimulus and generate a pulse */
  2903.  
  2904.   /* Enable the TIM Capture/Compare 1 interrupt */
  2905.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  2906.  
  2907.   /* Enable the TIM Capture/Compare 2 interrupt */
  2908.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  2909.  
  2910.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  2911.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  2912.  
  2913.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  2914.   {
  2915.     /* Enable the main output */
  2916.     __HAL_TIM_MOE_ENABLE(htim);
  2917.   }
  2918.  
  2919.   /* Return function status */
  2920.   return HAL_OK;
  2921. }
  2922.  
  2923. /**
  2924.   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
  2925.   * @note Though OutputChannel parameter is deprecated and ignored by the function
  2926.   *        it has been kept to avoid HAL_TIM API compatibility break.
  2927.   * @note The pulse output channel is determined when calling
  2928.   *       @ref HAL_TIM_OnePulse_ConfigChannel().
  2929.   * @param  htim TIM One Pulse handle
  2930.   * @param  OutputChannel See note above
  2931.   * @retval HAL status
  2932.   */
  2933. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2934. {
  2935.   /* Prevent unused argument(s) compilation warning */
  2936.   UNUSED(OutputChannel);
  2937.  
  2938.   /* Disable the TIM Capture/Compare 1 interrupt */
  2939.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  2940.  
  2941.   /* Disable the TIM Capture/Compare 2 interrupt */
  2942.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  2943.  
  2944.   /* Disable the Capture compare and the Input Capture channels
  2945.   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2946.   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2947.   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2948.   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
  2949.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  2950.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  2951.  
  2952.   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
  2953.   {
  2954.     /* Disable the Main Output */
  2955.     __HAL_TIM_MOE_DISABLE(htim);
  2956.   }
  2957.  
  2958.   /* Disable the Peripheral */
  2959.   __HAL_TIM_DISABLE(htim);
  2960.  
  2961.   /* Set the TIM channels state */
  2962.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2963.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2964.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2965.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2966.  
  2967.   /* Return function status */
  2968.   return HAL_OK;
  2969. }
  2970.  
  2971. /**
  2972.   * @}
  2973.   */
  2974.  
  2975. /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
  2976.   *  @brief    TIM Encoder functions
  2977.   *
  2978. @verbatim
  2979.   ==============================================================================
  2980.                           ##### TIM Encoder functions #####
  2981.   ==============================================================================
  2982.   [..]
  2983.     This section provides functions allowing to:
  2984.     (+) Initialize and configure the TIM Encoder.
  2985.     (+) De-initialize the TIM Encoder.
  2986.     (+) Start the TIM Encoder.
  2987.     (+) Stop the TIM Encoder.
  2988.     (+) Start the TIM Encoder and enable interrupt.
  2989.     (+) Stop the TIM Encoder and disable interrupt.
  2990.     (+) Start the TIM Encoder and enable DMA transfer.
  2991.     (+) Stop the TIM Encoder and disable DMA transfer.
  2992.  
  2993. @endverbatim
  2994.   * @{
  2995.   */
  2996. /**
  2997.   * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
  2998.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  2999.   *         requires a timer reset to avoid unexpected direction
  3000.   *         due to DIR bit readonly in center aligned mode.
  3001.   *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
  3002.   * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
  3003.   *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
  3004.   *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
  3005.   * @note   When the timer instance is initialized in Encoder mode, timer
  3006.   *         channels 1 and channel 2 are reserved and cannot be used for other
  3007.   *         purpose.
  3008.   * @param  htim TIM Encoder Interface handle
  3009.   * @param  sConfig TIM Encoder Interface configuration structure
  3010.   * @retval HAL status
  3011.   */
  3012. HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
  3013. {
  3014.   uint32_t tmpsmcr;
  3015.   uint32_t tmpccmr1;
  3016.   uint32_t tmpccer;
  3017.  
  3018.   /* Check the TIM handle allocation */
  3019.   if (htim == NULL)
  3020.   {
  3021.     return HAL_ERROR;
  3022.   }
  3023.  
  3024.   /* Check the parameters */
  3025.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3026.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  3027.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  3028.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  3029.   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
  3030.   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
  3031.   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
  3032.   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
  3033.   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
  3034.   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
  3035.   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
  3036.   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
  3037.   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
  3038.  
  3039.   if (htim->State == HAL_TIM_STATE_RESET)
  3040.   {
  3041.     /* Allocate lock resource and initialize it */
  3042.     htim->Lock = HAL_UNLOCKED;
  3043.  
  3044. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3045.     /* Reset interrupt callbacks to legacy weak callbacks */
  3046.     TIM_ResetCallback(htim);
  3047.  
  3048.     if (htim->Encoder_MspInitCallback == NULL)
  3049.     {
  3050.       htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
  3051.     }
  3052.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  3053.     htim->Encoder_MspInitCallback(htim);
  3054. #else
  3055.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  3056.     HAL_TIM_Encoder_MspInit(htim);
  3057. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3058.   }
  3059.  
  3060.   /* Set the TIM state */
  3061.   htim->State = HAL_TIM_STATE_BUSY;
  3062.  
  3063.   /* Reset the SMS and ECE bits */
  3064.   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
  3065.  
  3066.   /* Configure the Time base in the Encoder Mode */
  3067.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  3068.  
  3069.   /* Get the TIMx SMCR register value */
  3070.   tmpsmcr = htim->Instance->SMCR;
  3071.  
  3072.   /* Get the TIMx CCMR1 register value */
  3073.   tmpccmr1 = htim->Instance->CCMR1;
  3074.  
  3075.   /* Get the TIMx CCER register value */
  3076.   tmpccer = htim->Instance->CCER;
  3077.  
  3078.   /* Set the encoder Mode */
  3079.   tmpsmcr |= sConfig->EncoderMode;
  3080.  
  3081.   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
  3082.   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
  3083.   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
  3084.  
  3085.   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
  3086.   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
  3087.   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
  3088.   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
  3089.   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
  3090.  
  3091.   /* Set the TI1 and the TI2 Polarities */
  3092.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
  3093.   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
  3094.   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
  3095.  
  3096.   /* Write to TIMx SMCR */
  3097.   htim->Instance->SMCR = tmpsmcr;
  3098.  
  3099.   /* Write to TIMx CCMR1 */
  3100.   htim->Instance->CCMR1 = tmpccmr1;
  3101.  
  3102.   /* Write to TIMx CCER */
  3103.   htim->Instance->CCER = tmpccer;
  3104.  
  3105.   /* Initialize the DMA burst operation state */
  3106.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  3107.  
  3108.   /* Set the TIM channels state */
  3109.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3110.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3111.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3112.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3113.  
  3114.   /* Initialize the TIM state*/
  3115.   htim->State = HAL_TIM_STATE_READY;
  3116.  
  3117.   return HAL_OK;
  3118. }
  3119.  
  3120.  
  3121. /**
  3122.   * @brief  DeInitializes the TIM Encoder interface
  3123.   * @param  htim TIM Encoder Interface handle
  3124.   * @retval HAL status
  3125.   */
  3126. HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
  3127. {
  3128.   /* Check the parameters */
  3129.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  3130.  
  3131.   htim->State = HAL_TIM_STATE_BUSY;
  3132.  
  3133.   /* Disable the TIM Peripheral Clock */
  3134.   __HAL_TIM_DISABLE(htim);
  3135.  
  3136. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3137.   if (htim->Encoder_MspDeInitCallback == NULL)
  3138.   {
  3139.     htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
  3140.   }
  3141.   /* DeInit the low level hardware */
  3142.   htim->Encoder_MspDeInitCallback(htim);
  3143. #else
  3144.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  3145.   HAL_TIM_Encoder_MspDeInit(htim);
  3146. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3147.  
  3148.   /* Change the DMA burst operation state */
  3149.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  3150.  
  3151.   /* Set the TIM channels state */
  3152.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  3153.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  3154.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  3155.   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  3156.  
  3157.   /* Change TIM state */
  3158.   htim->State = HAL_TIM_STATE_RESET;
  3159.  
  3160.   /* Release Lock */
  3161.   __HAL_UNLOCK(htim);
  3162.  
  3163.   return HAL_OK;
  3164. }
  3165.  
  3166. /**
  3167.   * @brief  Initializes the TIM Encoder Interface MSP.
  3168.   * @param  htim TIM Encoder Interface handle
  3169.   * @retval None
  3170.   */
  3171. __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
  3172. {
  3173.   /* Prevent unused argument(s) compilation warning */
  3174.   UNUSED(htim);
  3175.  
  3176.   /* NOTE : This function should not be modified, when the callback is needed,
  3177.             the HAL_TIM_Encoder_MspInit could be implemented in the user file
  3178.    */
  3179. }
  3180.  
  3181. /**
  3182.   * @brief  DeInitializes TIM Encoder Interface MSP.
  3183.   * @param  htim TIM Encoder Interface handle
  3184.   * @retval None
  3185.   */
  3186. __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
  3187. {
  3188.   /* Prevent unused argument(s) compilation warning */
  3189.   UNUSED(htim);
  3190.  
  3191.   /* NOTE : This function should not be modified, when the callback is needed,
  3192.             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
  3193.    */
  3194. }
  3195.  
  3196. /**
  3197.   * @brief  Starts the TIM Encoder Interface.
  3198.   * @param  htim TIM Encoder Interface handle
  3199.   * @param  Channel TIM Channels to be enabled
  3200.   *          This parameter can be one of the following values:
  3201.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3202.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3203.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3204.   * @retval HAL status
  3205.   */
  3206. HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  3207. {
  3208.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  3209.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  3210.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  3211.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  3212.  
  3213.   /* Check the parameters */
  3214.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3215.  
  3216.   /* Set the TIM channel(s) state */
  3217.   if (Channel == TIM_CHANNEL_1)
  3218.   {
  3219.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3220.         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
  3221.     {
  3222.       return HAL_ERROR;
  3223.     }
  3224.     else
  3225.     {
  3226.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3227.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3228.     }
  3229.   }
  3230.   else if (Channel == TIM_CHANNEL_2)
  3231.   {
  3232.     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3233.         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3234.     {
  3235.       return HAL_ERROR;
  3236.     }
  3237.     else
  3238.     {
  3239.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3240.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3241.     }
  3242.   }
  3243.   else
  3244.   {
  3245.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3246.         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3247.         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3248.         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3249.     {
  3250.       return HAL_ERROR;
  3251.     }
  3252.     else
  3253.     {
  3254.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3255.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3256.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3257.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3258.     }
  3259.   }
  3260.  
  3261.   /* Enable the encoder interface channels */
  3262.   switch (Channel)
  3263.   {
  3264.     case TIM_CHANNEL_1:
  3265.     {
  3266.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3267.       break;
  3268.     }
  3269.  
  3270.     case TIM_CHANNEL_2:
  3271.     {
  3272.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3273.       break;
  3274.     }
  3275.  
  3276.     default :
  3277.     {
  3278.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3279.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3280.       break;
  3281.     }
  3282.   }
  3283.   /* Enable the Peripheral */
  3284.   __HAL_TIM_ENABLE(htim);
  3285.  
  3286.   /* Return function status */
  3287.   return HAL_OK;
  3288. }
  3289.  
  3290. /**
  3291.   * @brief  Stops the TIM Encoder Interface.
  3292.   * @param  htim TIM Encoder Interface handle
  3293.   * @param  Channel TIM Channels to be disabled
  3294.   *          This parameter can be one of the following values:
  3295.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3296.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3297.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3298.   * @retval HAL status
  3299.   */
  3300. HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  3301. {
  3302.   /* Check the parameters */
  3303.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3304.  
  3305.   /* Disable the Input Capture channels 1 and 2
  3306.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3307.   switch (Channel)
  3308.   {
  3309.     case TIM_CHANNEL_1:
  3310.     {
  3311.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3312.       break;
  3313.     }
  3314.  
  3315.     case TIM_CHANNEL_2:
  3316.     {
  3317.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3318.       break;
  3319.     }
  3320.  
  3321.     default :
  3322.     {
  3323.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3324.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3325.       break;
  3326.     }
  3327.   }
  3328.  
  3329.   /* Disable the Peripheral */
  3330.   __HAL_TIM_DISABLE(htim);
  3331.  
  3332.   /* Set the TIM channel(s) state */
  3333.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3334.   {
  3335.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3336.     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3337.   }
  3338.   else
  3339.   {
  3340.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3341.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3342.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3343.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3344.   }
  3345.  
  3346.   /* Return function status */
  3347.   return HAL_OK;
  3348. }
  3349.  
  3350. /**
  3351.   * @brief  Starts the TIM Encoder Interface in interrupt mode.
  3352.   * @param  htim TIM Encoder Interface handle
  3353.   * @param  Channel TIM Channels to be enabled
  3354.   *          This parameter can be one of the following values:
  3355.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3356.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3357.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3358.   * @retval HAL status
  3359.   */
  3360. HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  3361. {
  3362.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  3363.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  3364.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  3365.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  3366.  
  3367.   /* Check the parameters */
  3368.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3369.  
  3370.   /* Set the TIM channel(s) state */
  3371.   if (Channel == TIM_CHANNEL_1)
  3372.   {
  3373.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3374.         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
  3375.     {
  3376.       return HAL_ERROR;
  3377.     }
  3378.     else
  3379.     {
  3380.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3381.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3382.     }
  3383.   }
  3384.   else if (Channel == TIM_CHANNEL_2)
  3385.   {
  3386.     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3387.         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3388.     {
  3389.       return HAL_ERROR;
  3390.     }
  3391.     else
  3392.     {
  3393.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3394.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3395.     }
  3396.   }
  3397.   else
  3398.   {
  3399.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3400.         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3401.         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3402.         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3403.     {
  3404.       return HAL_ERROR;
  3405.     }
  3406.     else
  3407.     {
  3408.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3409.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3410.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3411.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3412.     }
  3413.   }
  3414.  
  3415.   /* Enable the encoder interface channels */
  3416.   /* Enable the capture compare Interrupts 1 and/or 2 */
  3417.   switch (Channel)
  3418.   {
  3419.     case TIM_CHANNEL_1:
  3420.     {
  3421.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3422.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  3423.       break;
  3424.     }
  3425.  
  3426.     case TIM_CHANNEL_2:
  3427.     {
  3428.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3429.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  3430.       break;
  3431.     }
  3432.  
  3433.     default :
  3434.     {
  3435.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3436.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3437.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  3438.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  3439.       break;
  3440.     }
  3441.   }
  3442.  
  3443.   /* Enable the Peripheral */
  3444.   __HAL_TIM_ENABLE(htim);
  3445.  
  3446.   /* Return function status */
  3447.   return HAL_OK;
  3448. }
  3449.  
  3450. /**
  3451.   * @brief  Stops the TIM Encoder Interface in interrupt mode.
  3452.   * @param  htim TIM Encoder Interface handle
  3453.   * @param  Channel TIM Channels to be disabled
  3454.   *          This parameter can be one of the following values:
  3455.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3456.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3457.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3458.   * @retval HAL status
  3459.   */
  3460. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  3461. {
  3462.   /* Check the parameters */
  3463.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3464.  
  3465.   /* Disable the Input Capture channels 1 and 2
  3466.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3467.   if (Channel == TIM_CHANNEL_1)
  3468.   {
  3469.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3470.  
  3471.     /* Disable the capture compare Interrupts 1 */
  3472.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  3473.   }
  3474.   else if (Channel == TIM_CHANNEL_2)
  3475.   {
  3476.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3477.  
  3478.     /* Disable the capture compare Interrupts 2 */
  3479.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  3480.   }
  3481.   else
  3482.   {
  3483.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3484.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3485.  
  3486.     /* Disable the capture compare Interrupts 1 and 2 */
  3487.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  3488.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  3489.   }
  3490.  
  3491.   /* Disable the Peripheral */
  3492.   __HAL_TIM_DISABLE(htim);
  3493.  
  3494.   /* Set the TIM channel(s) state */
  3495.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3496.   {
  3497.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3498.     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3499.   }
  3500.   else
  3501.   {
  3502.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3503.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3504.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3505.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3506.   }
  3507.  
  3508.   /* Return function status */
  3509.   return HAL_OK;
  3510. }
  3511.  
  3512. /**
  3513.   * @brief  Starts the TIM Encoder Interface in DMA mode.
  3514.   * @param  htim TIM Encoder Interface handle
  3515.   * @param  Channel TIM Channels to be enabled
  3516.   *          This parameter can be one of the following values:
  3517.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3518.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3519.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3520.   * @param  pData1 The destination Buffer address for IC1.
  3521.   * @param  pData2 The destination Buffer address for IC2.
  3522.   * @param  Length The length of data to be transferred from TIM peripheral to memory.
  3523.   * @retval HAL status
  3524.   */
  3525. HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
  3526.                                             uint32_t *pData2, uint16_t Length)
  3527. {
  3528.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  3529.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  3530.   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  3531.   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
  3532.  
  3533.   /* Check the parameters */
  3534.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3535.  
  3536.   /* Set the TIM channel(s) state */
  3537.   if (Channel == TIM_CHANNEL_1)
  3538.   {
  3539.     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3540.         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
  3541.     {
  3542.       return HAL_BUSY;
  3543.     }
  3544.     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
  3545.              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
  3546.     {
  3547.       if ((pData1 == NULL) && (Length > 0U))
  3548.       {
  3549.         return HAL_ERROR;
  3550.       }
  3551.       else
  3552.       {
  3553.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3554.         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3555.       }
  3556.     }
  3557.     else
  3558.     {
  3559.       return HAL_ERROR;
  3560.     }
  3561.   }
  3562.   else if (Channel == TIM_CHANNEL_2)
  3563.   {
  3564.     if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3565.         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
  3566.     {
  3567.       return HAL_BUSY;
  3568.     }
  3569.     else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
  3570.              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
  3571.     {
  3572.       if ((pData2 == NULL) && (Length > 0U))
  3573.       {
  3574.         return HAL_ERROR;
  3575.       }
  3576.       else
  3577.       {
  3578.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3579.         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3580.       }
  3581.     }
  3582.     else
  3583.     {
  3584.       return HAL_ERROR;
  3585.     }
  3586.   }
  3587.   else
  3588.   {
  3589.     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3590.         || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3591.         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3592.         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
  3593.     {
  3594.       return HAL_BUSY;
  3595.     }
  3596.     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
  3597.              && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
  3598.              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
  3599.              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
  3600.     {
  3601.       if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
  3602.       {
  3603.         return HAL_ERROR;
  3604.       }
  3605.       else
  3606.       {
  3607.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3608.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3609.         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3610.         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3611.       }
  3612.     }
  3613.     else
  3614.     {
  3615.       return HAL_ERROR;
  3616.     }
  3617.   }
  3618.  
  3619.   switch (Channel)
  3620.   {
  3621.     case TIM_CHANNEL_1:
  3622.     {
  3623.       /* Set the DMA capture callbacks */
  3624.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  3625.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3626.  
  3627.       /* Set the DMA error callback */
  3628.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  3629.  
  3630.       /* Enable the DMA channel */
  3631.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
  3632.                            Length) != HAL_OK)
  3633.       {
  3634.         /* Return error status */
  3635.         return HAL_ERROR;
  3636.       }
  3637.       /* Enable the TIM Input Capture DMA request */
  3638.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  3639.  
  3640.       /* Enable the Capture compare channel */
  3641.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3642.  
  3643.       /* Enable the Peripheral */
  3644.       __HAL_TIM_ENABLE(htim);
  3645.  
  3646.       break;
  3647.     }
  3648.  
  3649.     case TIM_CHANNEL_2:
  3650.     {
  3651.       /* Set the DMA capture callbacks */
  3652.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  3653.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3654.  
  3655.       /* Set the DMA error callback */
  3656.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
  3657.       /* Enable the DMA channel */
  3658.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
  3659.                            Length) != HAL_OK)
  3660.       {
  3661.         /* Return error status */
  3662.         return HAL_ERROR;
  3663.       }
  3664.       /* Enable the TIM Input Capture  DMA request */
  3665.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  3666.  
  3667.       /* Enable the Capture compare channel */
  3668.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3669.  
  3670.       /* Enable the Peripheral */
  3671.       __HAL_TIM_ENABLE(htim);
  3672.  
  3673.       break;
  3674.     }
  3675.  
  3676.     default:
  3677.     {
  3678.       /* Set the DMA capture callbacks */
  3679.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  3680.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3681.  
  3682.       /* Set the DMA error callback */
  3683.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  3684.  
  3685.       /* Enable the DMA channel */
  3686.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
  3687.                            Length) != HAL_OK)
  3688.       {
  3689.         /* Return error status */
  3690.         return HAL_ERROR;
  3691.       }
  3692.  
  3693.       /* Set the DMA capture callbacks */
  3694.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  3695.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3696.  
  3697.       /* Set the DMA error callback */
  3698.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  3699.  
  3700.       /* Enable the DMA channel */
  3701.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
  3702.                            Length) != HAL_OK)
  3703.       {
  3704.         /* Return error status */
  3705.         return HAL_ERROR;
  3706.       }
  3707.  
  3708.       /* Enable the TIM Input Capture  DMA request */
  3709.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  3710.       /* Enable the TIM Input Capture  DMA request */
  3711.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  3712.  
  3713.       /* Enable the Capture compare channel */
  3714.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3715.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3716.  
  3717.       /* Enable the Peripheral */
  3718.       __HAL_TIM_ENABLE(htim);
  3719.  
  3720.       break;
  3721.     }
  3722.   }
  3723.  
  3724.   /* Return function status */
  3725.   return HAL_OK;
  3726. }
  3727.  
  3728. /**
  3729.   * @brief  Stops the TIM Encoder Interface in DMA mode.
  3730.   * @param  htim TIM Encoder Interface handle
  3731.   * @param  Channel TIM Channels to be enabled
  3732.   *          This parameter can be one of the following values:
  3733.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3734.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3735.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3736.   * @retval HAL status
  3737.   */
  3738. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  3739. {
  3740.   /* Check the parameters */
  3741.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3742.  
  3743.   /* Disable the Input Capture channels 1 and 2
  3744.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3745.   if (Channel == TIM_CHANNEL_1)
  3746.   {
  3747.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3748.  
  3749.     /* Disable the capture compare DMA Request 1 */
  3750.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  3751.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  3752.   }
  3753.   else if (Channel == TIM_CHANNEL_2)
  3754.   {
  3755.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3756.  
  3757.     /* Disable the capture compare DMA Request 2 */
  3758.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  3759.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  3760.   }
  3761.   else
  3762.   {
  3763.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3764.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3765.  
  3766.     /* Disable the capture compare DMA Request 1 and 2 */
  3767.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  3768.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  3769.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  3770.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  3771.   }
  3772.  
  3773.   /* Disable the Peripheral */
  3774.   __HAL_TIM_DISABLE(htim);
  3775.  
  3776.   /* Set the TIM channel(s) state */
  3777.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3778.   {
  3779.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3780.     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3781.   }
  3782.   else
  3783.   {
  3784.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3785.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3786.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3787.     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3788.   }
  3789.  
  3790.   /* Return function status */
  3791.   return HAL_OK;
  3792. }
  3793.  
  3794. /**
  3795.   * @}
  3796.   */
  3797. /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
  3798.   *  @brief    TIM IRQ handler management
  3799.   *
  3800. @verbatim
  3801.   ==============================================================================
  3802.                         ##### IRQ handler management #####
  3803.   ==============================================================================
  3804.   [..]
  3805.     This section provides Timer IRQ handler function.
  3806.  
  3807. @endverbatim
  3808.   * @{
  3809.   */
  3810. /**
  3811.   * @brief  This function handles TIM interrupts requests.
  3812.   * @param  htim TIM  handle
  3813.   * @retval None
  3814.   */
  3815. void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
  3816. {
  3817.   /* Capture compare 1 event */
  3818.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
  3819.   {
  3820.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
  3821.     {
  3822.       {
  3823.         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
  3824.         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  3825.  
  3826.         /* Input capture event */
  3827.         if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
  3828.         {
  3829. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3830.           htim->IC_CaptureCallback(htim);
  3831. #else
  3832.           HAL_TIM_IC_CaptureCallback(htim);
  3833. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3834.         }
  3835.         /* Output compare event */
  3836.         else
  3837.         {
  3838. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3839.           htim->OC_DelayElapsedCallback(htim);
  3840.           htim->PWM_PulseFinishedCallback(htim);
  3841. #else
  3842.           HAL_TIM_OC_DelayElapsedCallback(htim);
  3843.           HAL_TIM_PWM_PulseFinishedCallback(htim);
  3844. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3845.         }
  3846.         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3847.       }
  3848.     }
  3849.   }
  3850.   /* Capture compare 2 event */
  3851.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
  3852.   {
  3853.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
  3854.     {
  3855.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
  3856.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  3857.       /* Input capture event */
  3858.       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
  3859.       {
  3860. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3861.         htim->IC_CaptureCallback(htim);
  3862. #else
  3863.         HAL_TIM_IC_CaptureCallback(htim);
  3864. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3865.       }
  3866.       /* Output compare event */
  3867.       else
  3868.       {
  3869. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3870.         htim->OC_DelayElapsedCallback(htim);
  3871.         htim->PWM_PulseFinishedCallback(htim);
  3872. #else
  3873.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3874.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3875. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3876.       }
  3877.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3878.     }
  3879.   }
  3880.   /* Capture compare 3 event */
  3881.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
  3882.   {
  3883.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
  3884.     {
  3885.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
  3886.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  3887.       /* Input capture event */
  3888.       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
  3889.       {
  3890. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3891.         htim->IC_CaptureCallback(htim);
  3892. #else
  3893.         HAL_TIM_IC_CaptureCallback(htim);
  3894. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3895.       }
  3896.       /* Output compare event */
  3897.       else
  3898.       {
  3899. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3900.         htim->OC_DelayElapsedCallback(htim);
  3901.         htim->PWM_PulseFinishedCallback(htim);
  3902. #else
  3903.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3904.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3905. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3906.       }
  3907.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3908.     }
  3909.   }
  3910.   /* Capture compare 4 event */
  3911.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
  3912.   {
  3913.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
  3914.     {
  3915.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
  3916.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  3917.       /* Input capture event */
  3918.       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
  3919.       {
  3920. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3921.         htim->IC_CaptureCallback(htim);
  3922. #else
  3923.         HAL_TIM_IC_CaptureCallback(htim);
  3924. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3925.       }
  3926.       /* Output compare event */
  3927.       else
  3928.       {
  3929. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3930.         htim->OC_DelayElapsedCallback(htim);
  3931.         htim->PWM_PulseFinishedCallback(htim);
  3932. #else
  3933.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3934.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3935. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3936.       }
  3937.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3938.     }
  3939.   }
  3940.   /* TIM Update event */
  3941.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
  3942.   {
  3943.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
  3944.     {
  3945.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
  3946. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3947.       htim->PeriodElapsedCallback(htim);
  3948. #else
  3949.       HAL_TIM_PeriodElapsedCallback(htim);
  3950. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3951.     }
  3952.   }
  3953.   /* TIM Break input event */
  3954.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
  3955.   {
  3956.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
  3957.     {
  3958.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
  3959. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3960.       htim->BreakCallback(htim);
  3961. #else
  3962.       HAL_TIMEx_BreakCallback(htim);
  3963. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3964.     }
  3965.   }
  3966.   /* TIM Trigger detection event */
  3967.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
  3968.   {
  3969.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
  3970.     {
  3971.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
  3972. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3973.       htim->TriggerCallback(htim);
  3974. #else
  3975.       HAL_TIM_TriggerCallback(htim);
  3976. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3977.     }
  3978.   }
  3979.   /* TIM commutation event */
  3980.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
  3981.   {
  3982.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
  3983.     {
  3984.       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
  3985. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3986.       htim->CommutationCallback(htim);
  3987. #else
  3988.       HAL_TIMEx_CommutCallback(htim);
  3989. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3990.     }
  3991.   }
  3992. }
  3993.  
  3994. /**
  3995.   * @}
  3996.   */
  3997.  
  3998. /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
  3999.   *  @brief    TIM Peripheral Control functions
  4000.   *
  4001. @verbatim
  4002.   ==============================================================================
  4003.                    ##### Peripheral Control functions #####
  4004.   ==============================================================================
  4005.  [..]
  4006.    This section provides functions allowing to:
  4007.       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
  4008.       (+) Configure External Clock source.
  4009.       (+) Configure Complementary channels, break features and dead time.
  4010.       (+) Configure Master and the Slave synchronization.
  4011.       (+) Configure the DMA Burst Mode.
  4012.  
  4013. @endverbatim
  4014.   * @{
  4015.   */
  4016.  
  4017. /**
  4018.   * @brief  Initializes the TIM Output Compare Channels according to the specified
  4019.   *         parameters in the TIM_OC_InitTypeDef.
  4020.   * @param  htim TIM Output Compare handle
  4021.   * @param  sConfig TIM Output Compare configuration structure
  4022.   * @param  Channel TIM Channels to configure
  4023.   *          This parameter can be one of the following values:
  4024.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4025.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4026.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  4027.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  4028.   * @retval HAL status
  4029.   */
  4030. HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
  4031.                                            TIM_OC_InitTypeDef *sConfig,
  4032.                                            uint32_t Channel)
  4033. {
  4034.   HAL_StatusTypeDef status = HAL_OK;
  4035.  
  4036.   /* Check the parameters */
  4037.   assert_param(IS_TIM_CHANNELS(Channel));
  4038.   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
  4039.   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
  4040.  
  4041.   /* Process Locked */
  4042.   __HAL_LOCK(htim);
  4043.  
  4044.   switch (Channel)
  4045.   {
  4046.     case TIM_CHANNEL_1:
  4047.     {
  4048.       /* Check the parameters */
  4049.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4050.  
  4051.       /* Configure the TIM Channel 1 in Output Compare */
  4052.       TIM_OC1_SetConfig(htim->Instance, sConfig);
  4053.       break;
  4054.     }
  4055.  
  4056.     case TIM_CHANNEL_2:
  4057.     {
  4058.       /* Check the parameters */
  4059.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4060.  
  4061.       /* Configure the TIM Channel 2 in Output Compare */
  4062.       TIM_OC2_SetConfig(htim->Instance, sConfig);
  4063.       break;
  4064.     }
  4065.  
  4066.     case TIM_CHANNEL_3:
  4067.     {
  4068.       /* Check the parameters */
  4069.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  4070.  
  4071.       /* Configure the TIM Channel 3 in Output Compare */
  4072.       TIM_OC3_SetConfig(htim->Instance, sConfig);
  4073.       break;
  4074.     }
  4075.  
  4076.     case TIM_CHANNEL_4:
  4077.     {
  4078.       /* Check the parameters */
  4079.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  4080.  
  4081.       /* Configure the TIM Channel 4 in Output Compare */
  4082.       TIM_OC4_SetConfig(htim->Instance, sConfig);
  4083.       break;
  4084.     }
  4085.  
  4086.     default:
  4087.       status = HAL_ERROR;
  4088.       break;
  4089.   }
  4090.  
  4091.   __HAL_UNLOCK(htim);
  4092.  
  4093.   return status;
  4094. }
  4095.  
  4096. /**
  4097.   * @brief  Initializes the TIM Input Capture Channels according to the specified
  4098.   *         parameters in the TIM_IC_InitTypeDef.
  4099.   * @param  htim TIM IC handle
  4100.   * @param  sConfig TIM Input Capture configuration structure
  4101.   * @param  Channel TIM Channel to configure
  4102.   *          This parameter can be one of the following values:
  4103.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4104.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4105.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  4106.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  4107.   * @retval HAL status
  4108.   */
  4109. HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
  4110. {
  4111.   HAL_StatusTypeDef status = HAL_OK;
  4112.  
  4113.   /* Check the parameters */
  4114.   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4115.   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
  4116.   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
  4117.   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
  4118.   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
  4119.  
  4120.   /* Process Locked */
  4121.   __HAL_LOCK(htim);
  4122.  
  4123.   if (Channel == TIM_CHANNEL_1)
  4124.   {
  4125.     /* TI1 Configuration */
  4126.     TIM_TI1_SetConfig(htim->Instance,
  4127.                       sConfig->ICPolarity,
  4128.                       sConfig->ICSelection,
  4129.                       sConfig->ICFilter);
  4130.  
  4131.     /* Reset the IC1PSC Bits */
  4132.     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
  4133.  
  4134.     /* Set the IC1PSC value */
  4135.     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
  4136.   }
  4137.   else if (Channel == TIM_CHANNEL_2)
  4138.   {
  4139.     /* TI2 Configuration */
  4140.     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4141.  
  4142.     TIM_TI2_SetConfig(htim->Instance,
  4143.                       sConfig->ICPolarity,
  4144.                       sConfig->ICSelection,
  4145.                       sConfig->ICFilter);
  4146.  
  4147.     /* Reset the IC2PSC Bits */
  4148.     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
  4149.  
  4150.     /* Set the IC2PSC value */
  4151.     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
  4152.   }
  4153.   else if (Channel == TIM_CHANNEL_3)
  4154.   {
  4155.     /* TI3 Configuration */
  4156.     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  4157.  
  4158.     TIM_TI3_SetConfig(htim->Instance,
  4159.                       sConfig->ICPolarity,
  4160.                       sConfig->ICSelection,
  4161.                       sConfig->ICFilter);
  4162.  
  4163.     /* Reset the IC3PSC Bits */
  4164.     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
  4165.  
  4166.     /* Set the IC3PSC value */
  4167.     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
  4168.   }
  4169.   else if (Channel == TIM_CHANNEL_4)
  4170.   {
  4171.     /* TI4 Configuration */
  4172.     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  4173.  
  4174.     TIM_TI4_SetConfig(htim->Instance,
  4175.                       sConfig->ICPolarity,
  4176.                       sConfig->ICSelection,
  4177.                       sConfig->ICFilter);
  4178.  
  4179.     /* Reset the IC4PSC Bits */
  4180.     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
  4181.  
  4182.     /* Set the IC4PSC value */
  4183.     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
  4184.   }
  4185.   else
  4186.   {
  4187.     status = HAL_ERROR;
  4188.   }
  4189.  
  4190.   __HAL_UNLOCK(htim);
  4191.  
  4192.   return status;
  4193. }
  4194.  
  4195. /**
  4196.   * @brief  Initializes the TIM PWM  channels according to the specified
  4197.   *         parameters in the TIM_OC_InitTypeDef.
  4198.   * @param  htim TIM PWM handle
  4199.   * @param  sConfig TIM PWM configuration structure
  4200.   * @param  Channel TIM Channels to be configured
  4201.   *          This parameter can be one of the following values:
  4202.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4203.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4204.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  4205.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  4206.   * @retval HAL status
  4207.   */
  4208. HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
  4209.                                             TIM_OC_InitTypeDef *sConfig,
  4210.                                             uint32_t Channel)
  4211. {
  4212.   HAL_StatusTypeDef status = HAL_OK;
  4213.  
  4214.   /* Check the parameters */
  4215.   assert_param(IS_TIM_CHANNELS(Channel));
  4216.   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
  4217.   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
  4218.   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
  4219.  
  4220.   /* Process Locked */
  4221.   __HAL_LOCK(htim);
  4222.  
  4223.   switch (Channel)
  4224.   {
  4225.     case TIM_CHANNEL_1:
  4226.     {
  4227.       /* Check the parameters */
  4228.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4229.  
  4230.       /* Configure the Channel 1 in PWM mode */
  4231.       TIM_OC1_SetConfig(htim->Instance, sConfig);
  4232.  
  4233.       /* Set the Preload enable bit for channel1 */
  4234.       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
  4235.  
  4236.       /* Configure the Output Fast mode */
  4237.       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
  4238.       htim->Instance->CCMR1 |= sConfig->OCFastMode;
  4239.       break;
  4240.     }
  4241.  
  4242.     case TIM_CHANNEL_2:
  4243.     {
  4244.       /* Check the parameters */
  4245.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4246.  
  4247.       /* Configure the Channel 2 in PWM mode */
  4248.       TIM_OC2_SetConfig(htim->Instance, sConfig);
  4249.  
  4250.       /* Set the Preload enable bit for channel2 */
  4251.       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
  4252.  
  4253.       /* Configure the Output Fast mode */
  4254.       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
  4255.       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
  4256.       break;
  4257.     }
  4258.  
  4259.     case TIM_CHANNEL_3:
  4260.     {
  4261.       /* Check the parameters */
  4262.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  4263.  
  4264.       /* Configure the Channel 3 in PWM mode */
  4265.       TIM_OC3_SetConfig(htim->Instance, sConfig);
  4266.  
  4267.       /* Set the Preload enable bit for channel3 */
  4268.       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
  4269.  
  4270.       /* Configure the Output Fast mode */
  4271.       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
  4272.       htim->Instance->CCMR2 |= sConfig->OCFastMode;
  4273.       break;
  4274.     }
  4275.  
  4276.     case TIM_CHANNEL_4:
  4277.     {
  4278.       /* Check the parameters */
  4279.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  4280.  
  4281.       /* Configure the Channel 4 in PWM mode */
  4282.       TIM_OC4_SetConfig(htim->Instance, sConfig);
  4283.  
  4284.       /* Set the Preload enable bit for channel4 */
  4285.       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
  4286.  
  4287.       /* Configure the Output Fast mode */
  4288.       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
  4289.       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
  4290.       break;
  4291.     }
  4292.  
  4293.     default:
  4294.       status = HAL_ERROR;
  4295.       break;
  4296.   }
  4297.  
  4298.   __HAL_UNLOCK(htim);
  4299.  
  4300.   return status;
  4301. }
  4302.  
  4303. /**
  4304.   * @brief  Initializes the TIM One Pulse Channels according to the specified
  4305.   *         parameters in the TIM_OnePulse_InitTypeDef.
  4306.   * @param  htim TIM One Pulse handle
  4307.   * @param  sConfig TIM One Pulse configuration structure
  4308.   * @param  OutputChannel TIM output channel to configure
  4309.   *          This parameter can be one of the following values:
  4310.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4311.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4312.   * @param  InputChannel TIM input Channel to configure
  4313.   *          This parameter can be one of the following values:
  4314.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4315.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4316.   * @note  To output a waveform with a minimum delay user can enable the fast
  4317.   *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
  4318.   *        output is forced in response to the edge detection on TIx input,
  4319.   *        without taking in account the comparison.
  4320.   * @retval HAL status
  4321.   */
  4322. HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
  4323.                                                  uint32_t OutputChannel,  uint32_t InputChannel)
  4324. {
  4325.   HAL_StatusTypeDef status = HAL_OK;
  4326.   TIM_OC_InitTypeDef temp1;
  4327.  
  4328.   /* Check the parameters */
  4329.   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
  4330.   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
  4331.  
  4332.   if (OutputChannel != InputChannel)
  4333.   {
  4334.     /* Process Locked */
  4335.     __HAL_LOCK(htim);
  4336.  
  4337.     htim->State = HAL_TIM_STATE_BUSY;
  4338.  
  4339.     /* Extract the Output compare configuration from sConfig structure */
  4340.     temp1.OCMode = sConfig->OCMode;
  4341.     temp1.Pulse = sConfig->Pulse;
  4342.     temp1.OCPolarity = sConfig->OCPolarity;
  4343.     temp1.OCNPolarity = sConfig->OCNPolarity;
  4344.     temp1.OCIdleState = sConfig->OCIdleState;
  4345.     temp1.OCNIdleState = sConfig->OCNIdleState;
  4346.  
  4347.     switch (OutputChannel)
  4348.     {
  4349.       case TIM_CHANNEL_1:
  4350.       {
  4351.         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4352.  
  4353.         TIM_OC1_SetConfig(htim->Instance, &temp1);
  4354.         break;
  4355.       }
  4356.  
  4357.       case TIM_CHANNEL_2:
  4358.       {
  4359.         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4360.  
  4361.         TIM_OC2_SetConfig(htim->Instance, &temp1);
  4362.         break;
  4363.       }
  4364.  
  4365.       default:
  4366.         status = HAL_ERROR;
  4367.         break;
  4368.     }
  4369.  
  4370.     if (status == HAL_OK)
  4371.     {
  4372.       switch (InputChannel)
  4373.       {
  4374.         case TIM_CHANNEL_1:
  4375.         {
  4376.           assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4377.  
  4378.           TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
  4379.                             sConfig->ICSelection, sConfig->ICFilter);
  4380.  
  4381.           /* Reset the IC1PSC Bits */
  4382.           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
  4383.  
  4384.           /* Select the Trigger source */
  4385.           htim->Instance->SMCR &= ~TIM_SMCR_TS;
  4386.           htim->Instance->SMCR |= TIM_TS_TI1FP1;
  4387.  
  4388.           /* Select the Slave Mode */
  4389.           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
  4390.           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
  4391.           break;
  4392.         }
  4393.  
  4394.         case TIM_CHANNEL_2:
  4395.         {
  4396.           assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4397.  
  4398.           TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
  4399.                             sConfig->ICSelection, sConfig->ICFilter);
  4400.  
  4401.           /* Reset the IC2PSC Bits */
  4402.           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
  4403.  
  4404.           /* Select the Trigger source */
  4405.           htim->Instance->SMCR &= ~TIM_SMCR_TS;
  4406.           htim->Instance->SMCR |= TIM_TS_TI2FP2;
  4407.  
  4408.           /* Select the Slave Mode */
  4409.           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
  4410.           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
  4411.           break;
  4412.         }
  4413.  
  4414.         default:
  4415.           status = HAL_ERROR;
  4416.           break;
  4417.       }
  4418.     }
  4419.  
  4420.     htim->State = HAL_TIM_STATE_READY;
  4421.  
  4422.     __HAL_UNLOCK(htim);
  4423.  
  4424.     return status;
  4425.   }
  4426.   else
  4427.   {
  4428.     return HAL_ERROR;
  4429.   }
  4430. }
  4431.  
  4432. /**
  4433.   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
  4434.   * @param  htim TIM handle
  4435.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
  4436.   *         This parameter can be one of the following values:
  4437.   *            @arg TIM_DMABASE_CR1
  4438.   *            @arg TIM_DMABASE_CR2
  4439.   *            @arg TIM_DMABASE_SMCR
  4440.   *            @arg TIM_DMABASE_DIER
  4441.   *            @arg TIM_DMABASE_SR
  4442.   *            @arg TIM_DMABASE_EGR
  4443.   *            @arg TIM_DMABASE_CCMR1
  4444.   *            @arg TIM_DMABASE_CCMR2
  4445.   *            @arg TIM_DMABASE_CCER
  4446.   *            @arg TIM_DMABASE_CNT
  4447.   *            @arg TIM_DMABASE_PSC
  4448.   *            @arg TIM_DMABASE_ARR
  4449.   *            @arg TIM_DMABASE_RCR
  4450.   *            @arg TIM_DMABASE_CCR1
  4451.   *            @arg TIM_DMABASE_CCR2
  4452.   *            @arg TIM_DMABASE_CCR3
  4453.   *            @arg TIM_DMABASE_CCR4
  4454.   *            @arg TIM_DMABASE_BDTR
  4455.   * @param  BurstRequestSrc TIM DMA Request sources
  4456.   *         This parameter can be one of the following values:
  4457.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4458.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4459.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4460.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4461.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4462.   *            @arg TIM_DMA_COM: TIM Commutation DMA source
  4463.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4464.   * @param  BurstBuffer The Buffer address.
  4465.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4466.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4467.   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
  4468.   * @retval HAL status
  4469.   */
  4470. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4471.                                               uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)
  4472. {
  4473.   HAL_StatusTypeDef status = HAL_OK;
  4474.  
  4475.   if (status == HAL_OK)
  4476.   {
  4477.     status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
  4478.                                               ((BurstLength) >> 8U) + 1U);
  4479.   }
  4480.  
  4481.  
  4482.   return status;
  4483. }
  4484.  
  4485. /**
  4486.   * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
  4487.   * @param  htim TIM handle
  4488.   * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
  4489.   *         This parameter can be one of the following values:
  4490.   *            @arg TIM_DMABASE_CR1
  4491.   *            @arg TIM_DMABASE_CR2
  4492.   *            @arg TIM_DMABASE_SMCR
  4493.   *            @arg TIM_DMABASE_DIER
  4494.   *            @arg TIM_DMABASE_SR
  4495.   *            @arg TIM_DMABASE_EGR
  4496.   *            @arg TIM_DMABASE_CCMR1
  4497.   *            @arg TIM_DMABASE_CCMR2
  4498.   *            @arg TIM_DMABASE_CCER
  4499.   *            @arg TIM_DMABASE_CNT
  4500.   *            @arg TIM_DMABASE_PSC
  4501.   *            @arg TIM_DMABASE_ARR
  4502.   *            @arg TIM_DMABASE_RCR
  4503.   *            @arg TIM_DMABASE_CCR1
  4504.   *            @arg TIM_DMABASE_CCR2
  4505.   *            @arg TIM_DMABASE_CCR3
  4506.   *            @arg TIM_DMABASE_CCR4
  4507.   *            @arg TIM_DMABASE_BDTR
  4508.   * @param  BurstRequestSrc TIM DMA Request sources
  4509.   *         This parameter can be one of the following values:
  4510.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4511.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4512.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4513.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4514.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4515.   *            @arg TIM_DMA_COM: TIM Commutation DMA source
  4516.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4517.   * @param  BurstBuffer The Buffer address.
  4518.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4519.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4520.   * @param  DataLength Data length. This parameter can be one value
  4521.   *         between 1 and 0xFFFF.
  4522.   * @retval HAL status
  4523.   */
  4524. HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4525.                                                    uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
  4526.                                                    uint32_t  BurstLength,  uint32_t  DataLength)
  4527. {
  4528.   HAL_StatusTypeDef status = HAL_OK;
  4529.  
  4530.   /* Check the parameters */
  4531.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  4532.   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
  4533.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4534.   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
  4535.   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
  4536.  
  4537.   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
  4538.   {
  4539.     return HAL_BUSY;
  4540.   }
  4541.   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
  4542.   {
  4543.     if ((BurstBuffer == NULL) && (BurstLength > 0U))
  4544.     {
  4545.       return HAL_ERROR;
  4546.     }
  4547.     else
  4548.     {
  4549.       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
  4550.     }
  4551.   }
  4552.   else
  4553.   {
  4554.     /* nothing to do */
  4555.   }
  4556.  
  4557.   switch (BurstRequestSrc)
  4558.   {
  4559.     case TIM_DMA_UPDATE:
  4560.     {
  4561.       /* Set the DMA Period elapsed callbacks */
  4562.       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  4563.       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  4564.  
  4565.       /* Set the DMA error callback */
  4566.       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  4567.  
  4568.       /* Enable the DMA channel */
  4569.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
  4570.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4571.       {
  4572.         /* Return error status */
  4573.         return HAL_ERROR;
  4574.       }
  4575.       break;
  4576.     }
  4577.     case TIM_DMA_CC1:
  4578.     {
  4579.       /* Set the DMA compare callbacks */
  4580.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4581.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4582.  
  4583.       /* Set the DMA error callback */
  4584.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  4585.  
  4586.       /* Enable the DMA channel */
  4587.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
  4588.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4589.       {
  4590.         /* Return error status */
  4591.         return HAL_ERROR;
  4592.       }
  4593.       break;
  4594.     }
  4595.     case TIM_DMA_CC2:
  4596.     {
  4597.       /* Set the DMA compare callbacks */
  4598.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4599.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4600.  
  4601.       /* Set the DMA error callback */
  4602.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  4603.  
  4604.       /* Enable the DMA channel */
  4605.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
  4606.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4607.       {
  4608.         /* Return error status */
  4609.         return HAL_ERROR;
  4610.       }
  4611.       break;
  4612.     }
  4613.     case TIM_DMA_CC3:
  4614.     {
  4615.       /* Set the DMA compare callbacks */
  4616.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4617.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4618.  
  4619.       /* Set the DMA error callback */
  4620.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  4621.  
  4622.       /* Enable the DMA channel */
  4623.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
  4624.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4625.       {
  4626.         /* Return error status */
  4627.         return HAL_ERROR;
  4628.       }
  4629.       break;
  4630.     }
  4631.     case TIM_DMA_CC4:
  4632.     {
  4633.       /* Set the DMA compare callbacks */
  4634.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4635.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4636.  
  4637.       /* Set the DMA error callback */
  4638.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  4639.  
  4640.       /* Enable the DMA channel */
  4641.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
  4642.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4643.       {
  4644.         /* Return error status */
  4645.         return HAL_ERROR;
  4646.       }
  4647.       break;
  4648.     }
  4649.     case TIM_DMA_COM:
  4650.     {
  4651.       /* Set the DMA commutation callbacks */
  4652.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
  4653.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
  4654.  
  4655.       /* Set the DMA error callback */
  4656.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
  4657.  
  4658.       /* Enable the DMA channel */
  4659.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
  4660.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4661.       {
  4662.         /* Return error status */
  4663.         return HAL_ERROR;
  4664.       }
  4665.       break;
  4666.     }
  4667.     case TIM_DMA_TRIGGER:
  4668.     {
  4669.       /* Set the DMA trigger callbacks */
  4670.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
  4671.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
  4672.  
  4673.       /* Set the DMA error callback */
  4674.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
  4675.  
  4676.       /* Enable the DMA channel */
  4677.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
  4678.                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4679.       {
  4680.         /* Return error status */
  4681.         return HAL_ERROR;
  4682.       }
  4683.       break;
  4684.     }
  4685.     default:
  4686.       status = HAL_ERROR;
  4687.       break;
  4688.   }
  4689.  
  4690.   if (status == HAL_OK)
  4691.   {
  4692.     /* Configure the DMA Burst Mode */
  4693.     htim->Instance->DCR = (BurstBaseAddress | BurstLength);
  4694.     /* Enable the TIM DMA Request */
  4695.     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
  4696.   }
  4697.  
  4698.   /* Return function status */
  4699.   return status;
  4700. }
  4701.  
  4702. /**
  4703.   * @brief  Stops the TIM DMA Burst mode
  4704.   * @param  htim TIM handle
  4705.   * @param  BurstRequestSrc TIM DMA Request sources to disable
  4706.   * @retval HAL status
  4707.   */
  4708. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
  4709. {
  4710.   HAL_StatusTypeDef status = HAL_OK;
  4711.  
  4712.   /* Check the parameters */
  4713.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4714.  
  4715.   /* Abort the DMA transfer (at least disable the DMA channel) */
  4716.   switch (BurstRequestSrc)
  4717.   {
  4718.     case TIM_DMA_UPDATE:
  4719.     {
  4720.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  4721.       break;
  4722.     }
  4723.     case TIM_DMA_CC1:
  4724.     {
  4725.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  4726.       break;
  4727.     }
  4728.     case TIM_DMA_CC2:
  4729.     {
  4730.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  4731.       break;
  4732.     }
  4733.     case TIM_DMA_CC3:
  4734.     {
  4735.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  4736.       break;
  4737.     }
  4738.     case TIM_DMA_CC4:
  4739.     {
  4740.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  4741.       break;
  4742.     }
  4743.     case TIM_DMA_COM:
  4744.     {
  4745.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
  4746.       break;
  4747.     }
  4748.     case TIM_DMA_TRIGGER:
  4749.     {
  4750.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
  4751.       break;
  4752.     }
  4753.     default:
  4754.       status = HAL_ERROR;
  4755.       break;
  4756.   }
  4757.  
  4758.   if (status == HAL_OK)
  4759.   {
  4760.     /* Disable the TIM Update DMA request */
  4761.     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
  4762.  
  4763.     /* Change the DMA burst operation state */
  4764.     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  4765.   }
  4766.  
  4767.   /* Return function status */
  4768.   return status;
  4769. }
  4770.  
  4771. /**
  4772.   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
  4773.   * @param  htim TIM handle
  4774.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
  4775.   *         This parameter can be one of the following values:
  4776.   *            @arg TIM_DMABASE_CR1
  4777.   *            @arg TIM_DMABASE_CR2
  4778.   *            @arg TIM_DMABASE_SMCR
  4779.   *            @arg TIM_DMABASE_DIER
  4780.   *            @arg TIM_DMABASE_SR
  4781.   *            @arg TIM_DMABASE_EGR
  4782.   *            @arg TIM_DMABASE_CCMR1
  4783.   *            @arg TIM_DMABASE_CCMR2
  4784.   *            @arg TIM_DMABASE_CCER
  4785.   *            @arg TIM_DMABASE_CNT
  4786.   *            @arg TIM_DMABASE_PSC
  4787.   *            @arg TIM_DMABASE_ARR
  4788.   *            @arg TIM_DMABASE_RCR
  4789.   *            @arg TIM_DMABASE_CCR1
  4790.   *            @arg TIM_DMABASE_CCR2
  4791.   *            @arg TIM_DMABASE_CCR3
  4792.   *            @arg TIM_DMABASE_CCR4
  4793.   *            @arg TIM_DMABASE_BDTR
  4794.   * @param  BurstRequestSrc TIM DMA Request sources
  4795.   *         This parameter can be one of the following values:
  4796.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4797.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4798.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4799.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4800.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4801.   *            @arg TIM_DMA_COM: TIM Commutation DMA source
  4802.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4803.   * @param  BurstBuffer The Buffer address.
  4804.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4805.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4806.   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
  4807.   * @retval HAL status
  4808.   */
  4809. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4810.                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
  4811. {
  4812.   HAL_StatusTypeDef status = HAL_OK;
  4813.  
  4814.   if (status == HAL_OK)
  4815.   {
  4816.     status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
  4817.                                              ((BurstLength) >> 8U) + 1U);
  4818.   }
  4819.  
  4820.   return status;
  4821. }
  4822.  
  4823. /**
  4824.   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
  4825.   * @param  htim TIM handle
  4826.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
  4827.   *         This parameter can be one of the following values:
  4828.   *            @arg TIM_DMABASE_CR1
  4829.   *            @arg TIM_DMABASE_CR2
  4830.   *            @arg TIM_DMABASE_SMCR
  4831.   *            @arg TIM_DMABASE_DIER
  4832.   *            @arg TIM_DMABASE_SR
  4833.   *            @arg TIM_DMABASE_EGR
  4834.   *            @arg TIM_DMABASE_CCMR1
  4835.   *            @arg TIM_DMABASE_CCMR2
  4836.   *            @arg TIM_DMABASE_CCER
  4837.   *            @arg TIM_DMABASE_CNT
  4838.   *            @arg TIM_DMABASE_PSC
  4839.   *            @arg TIM_DMABASE_ARR
  4840.   *            @arg TIM_DMABASE_RCR
  4841.   *            @arg TIM_DMABASE_CCR1
  4842.   *            @arg TIM_DMABASE_CCR2
  4843.   *            @arg TIM_DMABASE_CCR3
  4844.   *            @arg TIM_DMABASE_CCR4
  4845.   *            @arg TIM_DMABASE_BDTR
  4846.   * @param  BurstRequestSrc TIM DMA Request sources
  4847.   *         This parameter can be one of the following values:
  4848.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4849.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4850.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4851.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4852.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4853.   *            @arg TIM_DMA_COM: TIM Commutation DMA source
  4854.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4855.   * @param  BurstBuffer The Buffer address.
  4856.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4857.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4858.   * @param  DataLength Data length. This parameter can be one value
  4859.   *         between 1 and 0xFFFF.
  4860.   * @retval HAL status
  4861.   */
  4862. HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4863.                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
  4864.                                                   uint32_t  BurstLength, uint32_t  DataLength)
  4865. {
  4866.   HAL_StatusTypeDef status = HAL_OK;
  4867.  
  4868.   /* Check the parameters */
  4869.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  4870.   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
  4871.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4872.   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
  4873.   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
  4874.  
  4875.   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
  4876.   {
  4877.     return HAL_BUSY;
  4878.   }
  4879.   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
  4880.   {
  4881.     if ((BurstBuffer == NULL) && (BurstLength > 0U))
  4882.     {
  4883.       return HAL_ERROR;
  4884.     }
  4885.     else
  4886.     {
  4887.       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
  4888.     }
  4889.   }
  4890.   else
  4891.   {
  4892.     /* nothing to do */
  4893.   }
  4894.   switch (BurstRequestSrc)
  4895.   {
  4896.     case TIM_DMA_UPDATE:
  4897.     {
  4898.       /* Set the DMA Period elapsed callbacks */
  4899.       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  4900.       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  4901.  
  4902.       /* Set the DMA error callback */
  4903.       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  4904.  
  4905.       /* Enable the DMA channel */
  4906.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4907.                            DataLength) != HAL_OK)
  4908.       {
  4909.         /* Return error status */
  4910.         return HAL_ERROR;
  4911.       }
  4912.       break;
  4913.     }
  4914.     case TIM_DMA_CC1:
  4915.     {
  4916.       /* Set the DMA capture callbacks */
  4917.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  4918.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4919.  
  4920.       /* Set the DMA error callback */
  4921.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  4922.  
  4923.       /* Enable the DMA channel */
  4924.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4925.                            DataLength) != HAL_OK)
  4926.       {
  4927.         /* Return error status */
  4928.         return HAL_ERROR;
  4929.       }
  4930.       break;
  4931.     }
  4932.     case TIM_DMA_CC2:
  4933.     {
  4934.       /* Set the DMA capture callbacks */
  4935.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  4936.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4937.  
  4938.       /* Set the DMA error callback */
  4939.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  4940.  
  4941.       /* Enable the DMA channel */
  4942.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4943.                            DataLength) != HAL_OK)
  4944.       {
  4945.         /* Return error status */
  4946.         return HAL_ERROR;
  4947.       }
  4948.       break;
  4949.     }
  4950.     case TIM_DMA_CC3:
  4951.     {
  4952.       /* Set the DMA capture callbacks */
  4953.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
  4954.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4955.  
  4956.       /* Set the DMA error callback */
  4957.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  4958.  
  4959.       /* Enable the DMA channel */
  4960.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4961.                            DataLength) != HAL_OK)
  4962.       {
  4963.         /* Return error status */
  4964.         return HAL_ERROR;
  4965.       }
  4966.       break;
  4967.     }
  4968.     case TIM_DMA_CC4:
  4969.     {
  4970.       /* Set the DMA capture callbacks */
  4971.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
  4972.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4973.  
  4974.       /* Set the DMA error callback */
  4975.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  4976.  
  4977.       /* Enable the DMA channel */
  4978.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4979.                            DataLength) != HAL_OK)
  4980.       {
  4981.         /* Return error status */
  4982.         return HAL_ERROR;
  4983.       }
  4984.       break;
  4985.     }
  4986.     case TIM_DMA_COM:
  4987.     {
  4988.       /* Set the DMA commutation callbacks */
  4989.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
  4990.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
  4991.  
  4992.       /* Set the DMA error callback */
  4993.       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
  4994.  
  4995.       /* Enable the DMA channel */
  4996.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4997.                            DataLength) != HAL_OK)
  4998.       {
  4999.         /* Return error status */
  5000.         return HAL_ERROR;
  5001.       }
  5002.       break;
  5003.     }
  5004.     case TIM_DMA_TRIGGER:
  5005.     {
  5006.       /* Set the DMA trigger callbacks */
  5007.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
  5008.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
  5009.  
  5010.       /* Set the DMA error callback */
  5011.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
  5012.  
  5013.       /* Enable the DMA channel */
  5014.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  5015.                            DataLength) != HAL_OK)
  5016.       {
  5017.         /* Return error status */
  5018.         return HAL_ERROR;
  5019.       }
  5020.       break;
  5021.     }
  5022.     default:
  5023.       status = HAL_ERROR;
  5024.       break;
  5025.   }
  5026.  
  5027.   if (status == HAL_OK)
  5028.   {
  5029.     /* Configure the DMA Burst Mode */
  5030.     htim->Instance->DCR = (BurstBaseAddress | BurstLength);
  5031.  
  5032.     /* Enable the TIM DMA Request */
  5033.     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
  5034.   }
  5035.  
  5036.   /* Return function status */
  5037.   return status;
  5038. }
  5039.  
  5040. /**
  5041.   * @brief  Stop the DMA burst reading
  5042.   * @param  htim TIM handle
  5043.   * @param  BurstRequestSrc TIM DMA Request sources to disable.
  5044.   * @retval HAL status
  5045.   */
  5046. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
  5047. {
  5048.   HAL_StatusTypeDef status = HAL_OK;
  5049.  
  5050.   /* Check the parameters */
  5051.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  5052.  
  5053.   /* Abort the DMA transfer (at least disable the DMA channel) */
  5054.   switch (BurstRequestSrc)
  5055.   {
  5056.     case TIM_DMA_UPDATE:
  5057.     {
  5058.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  5059.       break;
  5060.     }
  5061.     case TIM_DMA_CC1:
  5062.     {
  5063.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  5064.       break;
  5065.     }
  5066.     case TIM_DMA_CC2:
  5067.     {
  5068.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  5069.       break;
  5070.     }
  5071.     case TIM_DMA_CC3:
  5072.     {
  5073.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  5074.       break;
  5075.     }
  5076.     case TIM_DMA_CC4:
  5077.     {
  5078.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  5079.       break;
  5080.     }
  5081.     case TIM_DMA_COM:
  5082.     {
  5083.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
  5084.       break;
  5085.     }
  5086.     case TIM_DMA_TRIGGER:
  5087.     {
  5088.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
  5089.       break;
  5090.     }
  5091.     default:
  5092.       status = HAL_ERROR;
  5093.       break;
  5094.   }
  5095.  
  5096.   if (status == HAL_OK)
  5097.   {
  5098.     /* Disable the TIM Update DMA request */
  5099.     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
  5100.  
  5101.     /* Change the DMA burst operation state */
  5102.     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  5103.   }
  5104.  
  5105.   /* Return function status */
  5106.   return status;
  5107. }
  5108.  
  5109. /**
  5110.   * @brief  Generate a software event
  5111.   * @param  htim TIM handle
  5112.   * @param  EventSource specifies the event source.
  5113.   *          This parameter can be one of the following values:
  5114.   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
  5115.   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
  5116.   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
  5117.   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
  5118.   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
  5119.   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
  5120.   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
  5121.   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
  5122.   * @note   Basic timers can only generate an update event.
  5123.   * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
  5124.   * @note   TIM_EVENTSOURCE_BREAK are relevant only for timer instances
  5125.   *         supporting a break input.
  5126.   * @retval HAL status
  5127.   */
  5128.  
  5129. HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
  5130. {
  5131.   /* Check the parameters */
  5132.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  5133.   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
  5134.  
  5135.   /* Process Locked */
  5136.   __HAL_LOCK(htim);
  5137.  
  5138.   /* Change the TIM state */
  5139.   htim->State = HAL_TIM_STATE_BUSY;
  5140.  
  5141.   /* Set the event sources */
  5142.   htim->Instance->EGR = EventSource;
  5143.  
  5144.   /* Change the TIM state */
  5145.   htim->State = HAL_TIM_STATE_READY;
  5146.  
  5147.   __HAL_UNLOCK(htim);
  5148.  
  5149.   /* Return function status */
  5150.   return HAL_OK;
  5151. }
  5152.  
  5153. /**
  5154.   * @brief  Configures the OCRef clear feature
  5155.   * @param  htim TIM handle
  5156.   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
  5157.   *         contains the OCREF clear feature and parameters for the TIM peripheral.
  5158.   * @param  Channel specifies the TIM Channel
  5159.   *          This parameter can be one of the following values:
  5160.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  5161.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  5162.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  5163.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  5164.   * @retval HAL status
  5165.   */
  5166. HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
  5167.                                            TIM_ClearInputConfigTypeDef *sClearInputConfig,
  5168.                                            uint32_t Channel)
  5169. {
  5170.   HAL_StatusTypeDef status = HAL_OK;
  5171.  
  5172.   /* Check the parameters */
  5173.   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
  5174.   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
  5175.  
  5176.   /* Process Locked */
  5177.   __HAL_LOCK(htim);
  5178.  
  5179.   htim->State = HAL_TIM_STATE_BUSY;
  5180.  
  5181.   switch (sClearInputConfig->ClearInputSource)
  5182.   {
  5183.     case TIM_CLEARINPUTSOURCE_NONE:
  5184.     {
  5185.       /* Clear the OCREF clear selection bit and the the ETR Bits */
  5186.       CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
  5187.       break;
  5188.     }
  5189.     case TIM_CLEARINPUTSOURCE_OCREFCLR:
  5190.     {
  5191.       /* Clear the OCREF clear selection bit */
  5192.       CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
  5193.     }
  5194.     break;
  5195.  
  5196.     case TIM_CLEARINPUTSOURCE_ETR:
  5197.     {
  5198.       /* Check the parameters */
  5199.       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
  5200.       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
  5201.       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
  5202.  
  5203.       /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
  5204.       if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
  5205.       {
  5206.         htim->State = HAL_TIM_STATE_READY;
  5207.         __HAL_UNLOCK(htim);
  5208.         return HAL_ERROR;
  5209.       }
  5210.  
  5211.       TIM_ETR_SetConfig(htim->Instance,
  5212.                         sClearInputConfig->ClearInputPrescaler,
  5213.                         sClearInputConfig->ClearInputPolarity,
  5214.                         sClearInputConfig->ClearInputFilter);
  5215.  
  5216.       /* Set the OCREF clear selection bit */
  5217.       SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
  5218.       break;
  5219.     }
  5220.  
  5221.     default:
  5222.       status = HAL_ERROR;
  5223.       break;
  5224.   }
  5225.  
  5226.   if (status == HAL_OK)
  5227.   {
  5228.     switch (Channel)
  5229.     {
  5230.       case TIM_CHANNEL_1:
  5231.       {
  5232.         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  5233.         {
  5234.           /* Enable the OCREF clear feature for Channel 1 */
  5235.           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
  5236.         }
  5237.         else
  5238.         {
  5239.           /* Disable the OCREF clear feature for Channel 1 */
  5240.           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
  5241.         }
  5242.         break;
  5243.       }
  5244.       case TIM_CHANNEL_2:
  5245.       {
  5246.         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  5247.         {
  5248.           /* Enable the OCREF clear feature for Channel 2 */
  5249.           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
  5250.         }
  5251.         else
  5252.         {
  5253.           /* Disable the OCREF clear feature for Channel 2 */
  5254.           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
  5255.         }
  5256.         break;
  5257.       }
  5258.       case TIM_CHANNEL_3:
  5259.       {
  5260.         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  5261.         {
  5262.           /* Enable the OCREF clear feature for Channel 3 */
  5263.           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
  5264.         }
  5265.         else
  5266.         {
  5267.           /* Disable the OCREF clear feature for Channel 3 */
  5268.           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
  5269.         }
  5270.         break;
  5271.       }
  5272.       case TIM_CHANNEL_4:
  5273.       {
  5274.         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  5275.         {
  5276.           /* Enable the OCREF clear feature for Channel 4 */
  5277.           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
  5278.         }
  5279.         else
  5280.         {
  5281.           /* Disable the OCREF clear feature for Channel 4 */
  5282.           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
  5283.         }
  5284.         break;
  5285.       }
  5286.       default:
  5287.         break;
  5288.     }
  5289.   }
  5290.  
  5291.   htim->State = HAL_TIM_STATE_READY;
  5292.  
  5293.   __HAL_UNLOCK(htim);
  5294.  
  5295.   return status;
  5296. }
  5297.  
  5298. /**
  5299.   * @brief   Configures the clock source to be used
  5300.   * @param  htim TIM handle
  5301.   * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
  5302.   *         contains the clock source information for the TIM peripheral.
  5303.   * @retval HAL status
  5304.   */
  5305. HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
  5306. {
  5307.   HAL_StatusTypeDef status = HAL_OK;
  5308.   uint32_t tmpsmcr;
  5309.  
  5310.   /* Process Locked */
  5311.   __HAL_LOCK(htim);
  5312.  
  5313.   htim->State = HAL_TIM_STATE_BUSY;
  5314.  
  5315.   /* Check the parameters */
  5316.   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
  5317.  
  5318.   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
  5319.   tmpsmcr = htim->Instance->SMCR;
  5320.   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
  5321.   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  5322.   htim->Instance->SMCR = tmpsmcr;
  5323.  
  5324.   switch (sClockSourceConfig->ClockSource)
  5325.   {
  5326.     case TIM_CLOCKSOURCE_INTERNAL:
  5327.     {
  5328.       assert_param(IS_TIM_INSTANCE(htim->Instance));
  5329.       break;
  5330.     }
  5331.  
  5332.     case TIM_CLOCKSOURCE_ETRMODE1:
  5333.     {
  5334.       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
  5335.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
  5336.  
  5337.       /* Check ETR input conditioning related parameters */
  5338.       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
  5339.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5340.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5341.  
  5342.       /* Configure the ETR Clock source */
  5343.       TIM_ETR_SetConfig(htim->Instance,
  5344.                         sClockSourceConfig->ClockPrescaler,
  5345.                         sClockSourceConfig->ClockPolarity,
  5346.                         sClockSourceConfig->ClockFilter);
  5347.  
  5348.       /* Select the External clock mode1 and the ETRF trigger */
  5349.       tmpsmcr = htim->Instance->SMCR;
  5350.       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
  5351.       /* Write to TIMx SMCR */
  5352.       htim->Instance->SMCR = tmpsmcr;
  5353.       break;
  5354.     }
  5355.  
  5356.     case TIM_CLOCKSOURCE_ETRMODE2:
  5357.     {
  5358.       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
  5359.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
  5360.  
  5361.       /* Check ETR input conditioning related parameters */
  5362.       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
  5363.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5364.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5365.  
  5366.       /* Configure the ETR Clock source */
  5367.       TIM_ETR_SetConfig(htim->Instance,
  5368.                         sClockSourceConfig->ClockPrescaler,
  5369.                         sClockSourceConfig->ClockPolarity,
  5370.                         sClockSourceConfig->ClockFilter);
  5371.       /* Enable the External clock mode2 */
  5372.       htim->Instance->SMCR |= TIM_SMCR_ECE;
  5373.       break;
  5374.     }
  5375.  
  5376.     case TIM_CLOCKSOURCE_TI1:
  5377.     {
  5378.       /* Check whether or not the timer instance supports external clock mode 1 */
  5379.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  5380.  
  5381.       /* Check TI1 input conditioning related parameters */
  5382.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5383.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5384.  
  5385.       TIM_TI1_ConfigInputStage(htim->Instance,
  5386.                                sClockSourceConfig->ClockPolarity,
  5387.                                sClockSourceConfig->ClockFilter);
  5388.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
  5389.       break;
  5390.     }
  5391.  
  5392.     case TIM_CLOCKSOURCE_TI2:
  5393.     {
  5394.       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
  5395.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  5396.  
  5397.       /* Check TI2 input conditioning related parameters */
  5398.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5399.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5400.  
  5401.       TIM_TI2_ConfigInputStage(htim->Instance,
  5402.                                sClockSourceConfig->ClockPolarity,
  5403.                                sClockSourceConfig->ClockFilter);
  5404.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
  5405.       break;
  5406.     }
  5407.  
  5408.     case TIM_CLOCKSOURCE_TI1ED:
  5409.     {
  5410.       /* Check whether or not the timer instance supports external clock mode 1 */
  5411.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  5412.  
  5413.       /* Check TI1 input conditioning related parameters */
  5414.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5415.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5416.  
  5417.       TIM_TI1_ConfigInputStage(htim->Instance,
  5418.                                sClockSourceConfig->ClockPolarity,
  5419.                                sClockSourceConfig->ClockFilter);
  5420.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
  5421.       break;
  5422.     }
  5423.  
  5424.     case TIM_CLOCKSOURCE_ITR0:
  5425.     case TIM_CLOCKSOURCE_ITR1:
  5426.     case TIM_CLOCKSOURCE_ITR2:
  5427.     case TIM_CLOCKSOURCE_ITR3:
  5428.     {
  5429.       /* Check whether or not the timer instance supports internal trigger input */
  5430.       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
  5431.  
  5432.       TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
  5433.       break;
  5434.     }
  5435.  
  5436.     default:
  5437.       status = HAL_ERROR;
  5438.       break;
  5439.   }
  5440.   htim->State = HAL_TIM_STATE_READY;
  5441.  
  5442.   __HAL_UNLOCK(htim);
  5443.  
  5444.   return status;
  5445. }
  5446.  
  5447. /**
  5448.   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
  5449.   *         or a XOR combination between CH1_input, CH2_input & CH3_input
  5450.   * @param  htim TIM handle.
  5451.   * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
  5452.   *         output of a XOR gate.
  5453.   *          This parameter can be one of the following values:
  5454.   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  5455.   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
  5456.   *            pins are connected to the TI1 input (XOR combination)
  5457.   * @retval HAL status
  5458.   */
  5459. HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
  5460. {
  5461.   uint32_t tmpcr2;
  5462.  
  5463.   /* Check the parameters */
  5464.   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
  5465.   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
  5466.  
  5467.   /* Get the TIMx CR2 register value */
  5468.   tmpcr2 = htim->Instance->CR2;
  5469.  
  5470.   /* Reset the TI1 selection */
  5471.   tmpcr2 &= ~TIM_CR2_TI1S;
  5472.  
  5473.   /* Set the TI1 selection */
  5474.   tmpcr2 |= TI1_Selection;
  5475.  
  5476.   /* Write to TIMxCR2 */
  5477.   htim->Instance->CR2 = tmpcr2;
  5478.  
  5479.   return HAL_OK;
  5480. }
  5481.  
  5482. /**
  5483.   * @brief  Configures the TIM in Slave mode
  5484.   * @param  htim TIM handle.
  5485.   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
  5486.   *         contains the selected trigger (internal trigger input, filtered
  5487.   *         timer input or external trigger input) and the Slave mode
  5488.   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
  5489.   * @retval HAL status
  5490.   */
  5491. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
  5492. {
  5493.   /* Check the parameters */
  5494.   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
  5495.   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
  5496.   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
  5497.  
  5498.   __HAL_LOCK(htim);
  5499.  
  5500.   htim->State = HAL_TIM_STATE_BUSY;
  5501.  
  5502.   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
  5503.   {
  5504.     htim->State = HAL_TIM_STATE_READY;
  5505.     __HAL_UNLOCK(htim);
  5506.     return HAL_ERROR;
  5507.   }
  5508.  
  5509.   /* Disable Trigger Interrupt */
  5510.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
  5511.  
  5512.   /* Disable Trigger DMA request */
  5513.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
  5514.  
  5515.   htim->State = HAL_TIM_STATE_READY;
  5516.  
  5517.   __HAL_UNLOCK(htim);
  5518.  
  5519.   return HAL_OK;
  5520. }
  5521.  
  5522. /**
  5523.   * @brief  Configures the TIM in Slave mode in interrupt mode
  5524.   * @param  htim TIM handle.
  5525.   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
  5526.   *         contains the selected trigger (internal trigger input, filtered
  5527.   *         timer input or external trigger input) and the Slave mode
  5528.   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
  5529.   * @retval HAL status
  5530.   */
  5531. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
  5532.                                                 TIM_SlaveConfigTypeDef *sSlaveConfig)
  5533. {
  5534.   /* Check the parameters */
  5535.   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
  5536.   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
  5537.   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
  5538.  
  5539.   __HAL_LOCK(htim);
  5540.  
  5541.   htim->State = HAL_TIM_STATE_BUSY;
  5542.  
  5543.   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
  5544.   {
  5545.     htim->State = HAL_TIM_STATE_READY;
  5546.     __HAL_UNLOCK(htim);
  5547.     return HAL_ERROR;
  5548.   }
  5549.  
  5550.   /* Enable Trigger Interrupt */
  5551.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
  5552.  
  5553.   /* Disable Trigger DMA request */
  5554.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
  5555.  
  5556.   htim->State = HAL_TIM_STATE_READY;
  5557.  
  5558.   __HAL_UNLOCK(htim);
  5559.  
  5560.   return HAL_OK;
  5561. }
  5562.  
  5563. /**
  5564.   * @brief  Read the captured value from Capture Compare unit
  5565.   * @param  htim TIM handle.
  5566.   * @param  Channel TIM Channels to be enabled
  5567.   *          This parameter can be one of the following values:
  5568.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  5569.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  5570.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  5571.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  5572.   * @retval Captured value
  5573.   */
  5574. uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
  5575. {
  5576.   uint32_t tmpreg = 0U;
  5577.  
  5578.   switch (Channel)
  5579.   {
  5580.     case TIM_CHANNEL_1:
  5581.     {
  5582.       /* Check the parameters */
  5583.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  5584.  
  5585.       /* Return the capture 1 value */
  5586.       tmpreg =  htim->Instance->CCR1;
  5587.  
  5588.       break;
  5589.     }
  5590.     case TIM_CHANNEL_2:
  5591.     {
  5592.       /* Check the parameters */
  5593.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  5594.  
  5595.       /* Return the capture 2 value */
  5596.       tmpreg =   htim->Instance->CCR2;
  5597.  
  5598.       break;
  5599.     }
  5600.  
  5601.     case TIM_CHANNEL_3:
  5602.     {
  5603.       /* Check the parameters */
  5604.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  5605.  
  5606.       /* Return the capture 3 value */
  5607.       tmpreg =   htim->Instance->CCR3;
  5608.  
  5609.       break;
  5610.     }
  5611.  
  5612.     case TIM_CHANNEL_4:
  5613.     {
  5614.       /* Check the parameters */
  5615.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  5616.  
  5617.       /* Return the capture 4 value */
  5618.       tmpreg =   htim->Instance->CCR4;
  5619.  
  5620.       break;
  5621.     }
  5622.  
  5623.     default:
  5624.       break;
  5625.   }
  5626.  
  5627.   return tmpreg;
  5628. }
  5629.  
  5630. /**
  5631.   * @}
  5632.   */
  5633.  
  5634. /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
  5635.   *  @brief    TIM Callbacks functions
  5636.   *
  5637. @verbatim
  5638.   ==============================================================================
  5639.                         ##### TIM Callbacks functions #####
  5640.   ==============================================================================
  5641.  [..]
  5642.    This section provides TIM callback functions:
  5643.    (+) TIM Period elapsed callback
  5644.    (+) TIM Output Compare callback
  5645.    (+) TIM Input capture callback
  5646.    (+) TIM Trigger callback
  5647.    (+) TIM Error callback
  5648.  
  5649. @endverbatim
  5650.   * @{
  5651.   */
  5652.  
  5653. /**
  5654.   * @brief  Period elapsed callback in non-blocking mode
  5655.   * @param  htim TIM handle
  5656.   * @retval None
  5657.   */
  5658. __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
  5659. {
  5660.   /* Prevent unused argument(s) compilation warning */
  5661.   UNUSED(htim);
  5662.  
  5663.   /* NOTE : This function should not be modified, when the callback is needed,
  5664.             the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
  5665.    */
  5666. }
  5667.  
  5668. /**
  5669.   * @brief  Period elapsed half complete callback in non-blocking mode
  5670.   * @param  htim TIM handle
  5671.   * @retval None
  5672.   */
  5673. __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
  5674. {
  5675.   /* Prevent unused argument(s) compilation warning */
  5676.   UNUSED(htim);
  5677.  
  5678.   /* NOTE : This function should not be modified, when the callback is needed,
  5679.             the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
  5680.    */
  5681. }
  5682.  
  5683. /**
  5684.   * @brief  Output Compare callback in non-blocking mode
  5685.   * @param  htim TIM OC handle
  5686.   * @retval None
  5687.   */
  5688. __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
  5689. {
  5690.   /* Prevent unused argument(s) compilation warning */
  5691.   UNUSED(htim);
  5692.  
  5693.   /* NOTE : This function should not be modified, when the callback is needed,
  5694.             the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
  5695.    */
  5696. }
  5697.  
  5698. /**
  5699.   * @brief  Input Capture callback in non-blocking mode
  5700.   * @param  htim TIM IC handle
  5701.   * @retval None
  5702.   */
  5703. __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
  5704. {
  5705.   /* Prevent unused argument(s) compilation warning */
  5706.   UNUSED(htim);
  5707.  
  5708.   /* NOTE : This function should not be modified, when the callback is needed,
  5709.             the HAL_TIM_IC_CaptureCallback could be implemented in the user file
  5710.    */
  5711. }
  5712.  
  5713. /**
  5714.   * @brief  Input Capture half complete callback in non-blocking mode
  5715.   * @param  htim TIM IC handle
  5716.   * @retval None
  5717.   */
  5718. __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
  5719. {
  5720.   /* Prevent unused argument(s) compilation warning */
  5721.   UNUSED(htim);
  5722.  
  5723.   /* NOTE : This function should not be modified, when the callback is needed,
  5724.             the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
  5725.    */
  5726. }
  5727.  
  5728. /**
  5729.   * @brief  PWM Pulse finished callback in non-blocking mode
  5730.   * @param  htim TIM handle
  5731.   * @retval None
  5732.   */
  5733. __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
  5734. {
  5735.   /* Prevent unused argument(s) compilation warning */
  5736.   UNUSED(htim);
  5737.  
  5738.   /* NOTE : This function should not be modified, when the callback is needed,
  5739.             the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
  5740.    */
  5741. }
  5742.  
  5743. /**
  5744.   * @brief  PWM Pulse finished half complete callback in non-blocking mode
  5745.   * @param  htim TIM handle
  5746.   * @retval None
  5747.   */
  5748. __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
  5749. {
  5750.   /* Prevent unused argument(s) compilation warning */
  5751.   UNUSED(htim);
  5752.  
  5753.   /* NOTE : This function should not be modified, when the callback is needed,
  5754.             the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
  5755.    */
  5756. }
  5757.  
  5758. /**
  5759.   * @brief  Hall Trigger detection callback in non-blocking mode
  5760.   * @param  htim TIM handle
  5761.   * @retval None
  5762.   */
  5763. __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
  5764. {
  5765.   /* Prevent unused argument(s) compilation warning */
  5766.   UNUSED(htim);
  5767.  
  5768.   /* NOTE : This function should not be modified, when the callback is needed,
  5769.             the HAL_TIM_TriggerCallback could be implemented in the user file
  5770.    */
  5771. }
  5772.  
  5773. /**
  5774.   * @brief  Hall Trigger detection half complete callback in non-blocking mode
  5775.   * @param  htim TIM handle
  5776.   * @retval None
  5777.   */
  5778. __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
  5779. {
  5780.   /* Prevent unused argument(s) compilation warning */
  5781.   UNUSED(htim);
  5782.  
  5783.   /* NOTE : This function should not be modified, when the callback is needed,
  5784.             the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
  5785.    */
  5786. }
  5787.  
  5788. /**
  5789.   * @brief  Timer error callback in non-blocking mode
  5790.   * @param  htim TIM handle
  5791.   * @retval None
  5792.   */
  5793. __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
  5794. {
  5795.   /* Prevent unused argument(s) compilation warning */
  5796.   UNUSED(htim);
  5797.  
  5798.   /* NOTE : This function should not be modified, when the callback is needed,
  5799.             the HAL_TIM_ErrorCallback could be implemented in the user file
  5800.    */
  5801. }
  5802.  
  5803. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  5804. /**
  5805.   * @brief  Register a User TIM callback to be used instead of the weak predefined callback
  5806.   * @param htim tim handle
  5807.   * @param CallbackID ID of the callback to be registered
  5808.   *        This parameter can be one of the following values:
  5809.   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  5810.   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  5811.   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  5812.   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  5813.   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  5814.   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  5815.   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  5816.   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  5817.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  5818.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  5819.   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  5820.   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  5821.   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
  5822.   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
  5823.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  5824.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  5825.   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  5826.   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  5827.   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  5828.   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  5829.   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  5830.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  5831.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  5832.   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
  5833.   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
  5834.   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
  5835.   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
  5836.   *          @param pCallback pointer to the callback function
  5837.   *          @retval status
  5838.   */
  5839. HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
  5840.                                            pTIM_CallbackTypeDef pCallback)
  5841. {
  5842.   HAL_StatusTypeDef status = HAL_OK;
  5843.  
  5844.   if (pCallback == NULL)
  5845.   {
  5846.     return HAL_ERROR;
  5847.   }
  5848.   /* Process locked */
  5849.   __HAL_LOCK(htim);
  5850.  
  5851.   if (htim->State == HAL_TIM_STATE_READY)
  5852.   {
  5853.     switch (CallbackID)
  5854.     {
  5855.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5856.         htim->Base_MspInitCallback                 = pCallback;
  5857.         break;
  5858.  
  5859.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5860.         htim->Base_MspDeInitCallback               = pCallback;
  5861.         break;
  5862.  
  5863.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5864.         htim->IC_MspInitCallback                   = pCallback;
  5865.         break;
  5866.  
  5867.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5868.         htim->IC_MspDeInitCallback                 = pCallback;
  5869.         break;
  5870.  
  5871.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5872.         htim->OC_MspInitCallback                   = pCallback;
  5873.         break;
  5874.  
  5875.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5876.         htim->OC_MspDeInitCallback                 = pCallback;
  5877.         break;
  5878.  
  5879.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5880.         htim->PWM_MspInitCallback                  = pCallback;
  5881.         break;
  5882.  
  5883.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  5884.         htim->PWM_MspDeInitCallback                = pCallback;
  5885.         break;
  5886.  
  5887.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  5888.         htim->OnePulse_MspInitCallback             = pCallback;
  5889.         break;
  5890.  
  5891.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  5892.         htim->OnePulse_MspDeInitCallback           = pCallback;
  5893.         break;
  5894.  
  5895.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  5896.         htim->Encoder_MspInitCallback              = pCallback;
  5897.         break;
  5898.  
  5899.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  5900.         htim->Encoder_MspDeInitCallback            = pCallback;
  5901.         break;
  5902.  
  5903.       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
  5904.         htim->HallSensor_MspInitCallback           = pCallback;
  5905.         break;
  5906.  
  5907.       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
  5908.         htim->HallSensor_MspDeInitCallback         = pCallback;
  5909.         break;
  5910.  
  5911.       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
  5912.         htim->PeriodElapsedCallback                = pCallback;
  5913.         break;
  5914.  
  5915.       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
  5916.         htim->PeriodElapsedHalfCpltCallback        = pCallback;
  5917.         break;
  5918.  
  5919.       case HAL_TIM_TRIGGER_CB_ID :
  5920.         htim->TriggerCallback                      = pCallback;
  5921.         break;
  5922.  
  5923.       case HAL_TIM_TRIGGER_HALF_CB_ID :
  5924.         htim->TriggerHalfCpltCallback              = pCallback;
  5925.         break;
  5926.  
  5927.       case HAL_TIM_IC_CAPTURE_CB_ID :
  5928.         htim->IC_CaptureCallback                   = pCallback;
  5929.         break;
  5930.  
  5931.       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
  5932.         htim->IC_CaptureHalfCpltCallback           = pCallback;
  5933.         break;
  5934.  
  5935.       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
  5936.         htim->OC_DelayElapsedCallback              = pCallback;
  5937.         break;
  5938.  
  5939.       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
  5940.         htim->PWM_PulseFinishedCallback            = pCallback;
  5941.         break;
  5942.  
  5943.       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
  5944.         htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
  5945.         break;
  5946.  
  5947.       case HAL_TIM_ERROR_CB_ID :
  5948.         htim->ErrorCallback                        = pCallback;
  5949.         break;
  5950.  
  5951.       case HAL_TIM_COMMUTATION_CB_ID :
  5952.         htim->CommutationCallback                  = pCallback;
  5953.         break;
  5954.  
  5955.       case HAL_TIM_COMMUTATION_HALF_CB_ID :
  5956.         htim->CommutationHalfCpltCallback          = pCallback;
  5957.         break;
  5958.  
  5959.       case HAL_TIM_BREAK_CB_ID :
  5960.         htim->BreakCallback                        = pCallback;
  5961.         break;
  5962.  
  5963.       default :
  5964.         /* Return error status */
  5965.         status = HAL_ERROR;
  5966.         break;
  5967.     }
  5968.   }
  5969.   else if (htim->State == HAL_TIM_STATE_RESET)
  5970.   {
  5971.     switch (CallbackID)
  5972.     {
  5973.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5974.         htim->Base_MspInitCallback         = pCallback;
  5975.         break;
  5976.  
  5977.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5978.         htim->Base_MspDeInitCallback       = pCallback;
  5979.         break;
  5980.  
  5981.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5982.         htim->IC_MspInitCallback           = pCallback;
  5983.         break;
  5984.  
  5985.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5986.         htim->IC_MspDeInitCallback         = pCallback;
  5987.         break;
  5988.  
  5989.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5990.         htim->OC_MspInitCallback           = pCallback;
  5991.         break;
  5992.  
  5993.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5994.         htim->OC_MspDeInitCallback         = pCallback;
  5995.         break;
  5996.  
  5997.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5998.         htim->PWM_MspInitCallback          = pCallback;
  5999.         break;
  6000.  
  6001.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  6002.         htim->PWM_MspDeInitCallback        = pCallback;
  6003.         break;
  6004.  
  6005.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  6006.         htim->OnePulse_MspInitCallback     = pCallback;
  6007.         break;
  6008.  
  6009.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  6010.         htim->OnePulse_MspDeInitCallback   = pCallback;
  6011.         break;
  6012.  
  6013.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  6014.         htim->Encoder_MspInitCallback      = pCallback;
  6015.         break;
  6016.  
  6017.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  6018.         htim->Encoder_MspDeInitCallback    = pCallback;
  6019.         break;
  6020.  
  6021.       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
  6022.         htim->HallSensor_MspInitCallback   = pCallback;
  6023.         break;
  6024.  
  6025.       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
  6026.         htim->HallSensor_MspDeInitCallback = pCallback;
  6027.         break;
  6028.  
  6029.       default :
  6030.         /* Return error status */
  6031.         status = HAL_ERROR;
  6032.         break;
  6033.     }
  6034.   }
  6035.   else
  6036.   {
  6037.     /* Return error status */
  6038.     status = HAL_ERROR;
  6039.   }
  6040.  
  6041.   /* Release Lock */
  6042.   __HAL_UNLOCK(htim);
  6043.  
  6044.   return status;
  6045. }
  6046.  
  6047. /**
  6048.   * @brief  Unregister a TIM callback
  6049.   *         TIM callback is redirected to the weak predefined callback
  6050.   * @param htim tim handle
  6051.   * @param CallbackID ID of the callback to be unregistered
  6052.   *        This parameter can be one of the following values:
  6053.   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  6054.   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  6055.   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  6056.   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  6057.   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  6058.   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  6059.   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  6060.   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  6061.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  6062.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  6063.   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  6064.   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  6065.   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
  6066.   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
  6067.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  6068.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  6069.   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  6070.   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  6071.   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  6072.   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  6073.   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  6074.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  6075.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  6076.   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
  6077.   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
  6078.   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
  6079.   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
  6080.   *          @retval status
  6081.   */
  6082. HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
  6083. {
  6084.   HAL_StatusTypeDef status = HAL_OK;
  6085.  
  6086.   /* Process locked */
  6087.   __HAL_LOCK(htim);
  6088.  
  6089.   if (htim->State == HAL_TIM_STATE_READY)
  6090.   {
  6091.     switch (CallbackID)
  6092.     {
  6093.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  6094.         /* Legacy weak Base MspInit Callback */
  6095.         htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
  6096.         break;
  6097.  
  6098.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  6099.         /* Legacy weak Base Msp DeInit Callback */
  6100.         htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
  6101.         break;
  6102.  
  6103.       case HAL_TIM_IC_MSPINIT_CB_ID :
  6104.         /* Legacy weak IC Msp Init Callback */
  6105.         htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
  6106.         break;
  6107.  
  6108.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  6109.         /* Legacy weak IC Msp DeInit Callback */
  6110.         htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
  6111.         break;
  6112.  
  6113.       case HAL_TIM_OC_MSPINIT_CB_ID :
  6114.         /* Legacy weak OC Msp Init Callback */
  6115.         htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
  6116.         break;
  6117.  
  6118.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  6119.         /* Legacy weak OC Msp DeInit Callback */
  6120.         htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
  6121.         break;
  6122.  
  6123.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  6124.         /* Legacy weak PWM Msp Init Callback */
  6125.         htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
  6126.         break;
  6127.  
  6128.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  6129.         /* Legacy weak PWM Msp DeInit Callback */
  6130.         htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
  6131.         break;
  6132.  
  6133.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  6134.         /* Legacy weak One Pulse Msp Init Callback */
  6135.         htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
  6136.         break;
  6137.  
  6138.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  6139.         /* Legacy weak One Pulse Msp DeInit Callback */
  6140.         htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
  6141.         break;
  6142.  
  6143.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  6144.         /* Legacy weak Encoder Msp Init Callback */
  6145.         htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
  6146.         break;
  6147.  
  6148.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  6149.         /* Legacy weak Encoder Msp DeInit Callback */
  6150.         htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
  6151.         break;
  6152.  
  6153.       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
  6154.         /* Legacy weak Hall Sensor Msp Init Callback */
  6155.         htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;
  6156.         break;
  6157.  
  6158.       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
  6159.         /* Legacy weak Hall Sensor Msp DeInit Callback */
  6160.         htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;
  6161.         break;
  6162.  
  6163.       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
  6164.         /* Legacy weak Period Elapsed Callback */
  6165.         htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
  6166.         break;
  6167.  
  6168.       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
  6169.         /* Legacy weak Period Elapsed half complete Callback */
  6170.         htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
  6171.         break;
  6172.  
  6173.       case HAL_TIM_TRIGGER_CB_ID :
  6174.         /* Legacy weak Trigger Callback */
  6175.         htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
  6176.         break;
  6177.  
  6178.       case HAL_TIM_TRIGGER_HALF_CB_ID :
  6179.         /* Legacy weak Trigger half complete Callback */
  6180.         htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
  6181.         break;
  6182.  
  6183.       case HAL_TIM_IC_CAPTURE_CB_ID :
  6184.         /* Legacy weak IC Capture Callback */
  6185.         htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
  6186.         break;
  6187.  
  6188.       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
  6189.         /* Legacy weak IC Capture half complete Callback */
  6190.         htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
  6191.         break;
  6192.  
  6193.       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
  6194.         /* Legacy weak OC Delay Elapsed Callback */
  6195.         htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
  6196.         break;
  6197.  
  6198.       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
  6199.         /* Legacy weak PWM Pulse Finished Callback */
  6200.         htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
  6201.         break;
  6202.  
  6203.       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
  6204.         /* Legacy weak PWM Pulse Finished half complete Callback */
  6205.         htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
  6206.         break;
  6207.  
  6208.       case HAL_TIM_ERROR_CB_ID :
  6209.         /* Legacy weak Error Callback */
  6210.         htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
  6211.         break;
  6212.  
  6213.       case HAL_TIM_COMMUTATION_CB_ID :
  6214.         /* Legacy weak Commutation Callback */
  6215.         htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
  6216.         break;
  6217.  
  6218.       case HAL_TIM_COMMUTATION_HALF_CB_ID :
  6219.         /* Legacy weak Commutation half complete Callback */
  6220.         htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
  6221.         break;
  6222.  
  6223.       case HAL_TIM_BREAK_CB_ID :
  6224.         /* Legacy weak Break Callback */
  6225.         htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
  6226.         break;
  6227.  
  6228.       default :
  6229.         /* Return error status */
  6230.         status = HAL_ERROR;
  6231.         break;
  6232.     }
  6233.   }
  6234.   else if (htim->State == HAL_TIM_STATE_RESET)
  6235.   {
  6236.     switch (CallbackID)
  6237.     {
  6238.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  6239.         /* Legacy weak Base MspInit Callback */
  6240.         htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
  6241.         break;
  6242.  
  6243.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  6244.         /* Legacy weak Base Msp DeInit Callback */
  6245.         htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
  6246.         break;
  6247.  
  6248.       case HAL_TIM_IC_MSPINIT_CB_ID :
  6249.         /* Legacy weak IC Msp Init Callback */
  6250.         htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
  6251.         break;
  6252.  
  6253.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  6254.         /* Legacy weak IC Msp DeInit Callback */
  6255.         htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
  6256.         break;
  6257.  
  6258.       case HAL_TIM_OC_MSPINIT_CB_ID :
  6259.         /* Legacy weak OC Msp Init Callback */
  6260.         htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
  6261.         break;
  6262.  
  6263.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  6264.         /* Legacy weak OC Msp DeInit Callback */
  6265.         htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
  6266.         break;
  6267.  
  6268.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  6269.         /* Legacy weak PWM Msp Init Callback */
  6270.         htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
  6271.         break;
  6272.  
  6273.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  6274.         /* Legacy weak PWM Msp DeInit Callback */
  6275.         htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
  6276.         break;
  6277.  
  6278.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  6279.         /* Legacy weak One Pulse Msp Init Callback */
  6280.         htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
  6281.         break;
  6282.  
  6283.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  6284.         /* Legacy weak One Pulse Msp DeInit Callback */
  6285.         htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
  6286.         break;
  6287.  
  6288.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  6289.         /* Legacy weak Encoder Msp Init Callback */
  6290.         htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
  6291.         break;
  6292.  
  6293.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  6294.         /* Legacy weak Encoder Msp DeInit Callback */
  6295.         htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
  6296.         break;
  6297.  
  6298.       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
  6299.         /* Legacy weak Hall Sensor Msp Init Callback */
  6300.         htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;
  6301.         break;
  6302.  
  6303.       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
  6304.         /* Legacy weak Hall Sensor Msp DeInit Callback */
  6305.         htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
  6306.         break;
  6307.  
  6308.       default :
  6309.         /* Return error status */
  6310.         status = HAL_ERROR;
  6311.         break;
  6312.     }
  6313.   }
  6314.   else
  6315.   {
  6316.     /* Return error status */
  6317.     status = HAL_ERROR;
  6318.   }
  6319.  
  6320.   /* Release Lock */
  6321.   __HAL_UNLOCK(htim);
  6322.  
  6323.   return status;
  6324. }
  6325. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6326.  
  6327. /**
  6328.   * @}
  6329.   */
  6330.  
  6331. /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
  6332.   *  @brief   TIM Peripheral State functions
  6333.   *
  6334. @verbatim
  6335.   ==============================================================================
  6336.                         ##### Peripheral State functions #####
  6337.   ==============================================================================
  6338.     [..]
  6339.     This subsection permits to get in run-time the status of the peripheral
  6340.     and the data flow.
  6341.  
  6342. @endverbatim
  6343.   * @{
  6344.   */
  6345.  
  6346. /**
  6347.   * @brief  Return the TIM Base handle state.
  6348.   * @param  htim TIM Base handle
  6349.   * @retval HAL state
  6350.   */
  6351. HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
  6352. {
  6353.   return htim->State;
  6354. }
  6355.  
  6356. /**
  6357.   * @brief  Return the TIM OC handle state.
  6358.   * @param  htim TIM Output Compare handle
  6359.   * @retval HAL state
  6360.   */
  6361. HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
  6362. {
  6363.   return htim->State;
  6364. }
  6365.  
  6366. /**
  6367.   * @brief  Return the TIM PWM handle state.
  6368.   * @param  htim TIM handle
  6369.   * @retval HAL state
  6370.   */
  6371. HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
  6372. {
  6373.   return htim->State;
  6374. }
  6375.  
  6376. /**
  6377.   * @brief  Return the TIM Input Capture handle state.
  6378.   * @param  htim TIM IC handle
  6379.   * @retval HAL state
  6380.   */
  6381. HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
  6382. {
  6383.   return htim->State;
  6384. }
  6385.  
  6386. /**
  6387.   * @brief  Return the TIM One Pulse Mode handle state.
  6388.   * @param  htim TIM OPM handle
  6389.   * @retval HAL state
  6390.   */
  6391. HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
  6392. {
  6393.   return htim->State;
  6394. }
  6395.  
  6396. /**
  6397.   * @brief  Return the TIM Encoder Mode handle state.
  6398.   * @param  htim TIM Encoder Interface handle
  6399.   * @retval HAL state
  6400.   */
  6401. HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
  6402. {
  6403.   return htim->State;
  6404. }
  6405.  
  6406. /**
  6407.   * @brief  Return the TIM Encoder Mode handle state.
  6408.   * @param  htim TIM handle
  6409.   * @retval Active channel
  6410.   */
  6411. HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
  6412. {
  6413.   return htim->Channel;
  6414. }
  6415.  
  6416. /**
  6417.   * @brief  Return actual state of the TIM channel.
  6418.   * @param  htim TIM handle
  6419.   * @param  Channel TIM Channel
  6420.   *          This parameter can be one of the following values:
  6421.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  6422.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  6423.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  6424.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  6425.   *            @arg TIM_CHANNEL_5: TIM Channel 5
  6426.   *            @arg TIM_CHANNEL_6: TIM Channel 6
  6427.   * @retval TIM Channel state
  6428.   */
  6429. HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel)
  6430. {
  6431.   HAL_TIM_ChannelStateTypeDef channel_state;
  6432.  
  6433.   /* Check the parameters */
  6434.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  6435.  
  6436.   channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  6437.  
  6438.   return channel_state;
  6439. }
  6440.  
  6441. /**
  6442.   * @brief  Return actual state of a DMA burst operation.
  6443.   * @param  htim TIM handle
  6444.   * @retval DMA burst state
  6445.   */
  6446. HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
  6447. {
  6448.   /* Check the parameters */
  6449.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  6450.  
  6451.   return htim->DMABurstState;
  6452. }
  6453.  
  6454. /**
  6455.   * @}
  6456.   */
  6457.  
  6458. /**
  6459.   * @}
  6460.   */
  6461.  
  6462. /** @defgroup TIM_Private_Functions TIM Private Functions
  6463.   * @{
  6464.   */
  6465.  
  6466. /**
  6467.   * @brief  TIM DMA error callback
  6468.   * @param  hdma pointer to DMA handle.
  6469.   * @retval None
  6470.   */
  6471. void TIM_DMAError(DMA_HandleTypeDef *hdma)
  6472. {
  6473.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6474.  
  6475.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6476.   {
  6477.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6478.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6479.   }
  6480.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6481.   {
  6482.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6483.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6484.   }
  6485.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6486.   {
  6487.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6488.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6489.   }
  6490.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6491.   {
  6492.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6493.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6494.   }
  6495.   else
  6496.   {
  6497.     htim->State = HAL_TIM_STATE_READY;
  6498.   }
  6499.  
  6500. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6501.   htim->ErrorCallback(htim);
  6502. #else
  6503.   HAL_TIM_ErrorCallback(htim);
  6504. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6505.  
  6506.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6507. }
  6508.  
  6509. /**
  6510.   * @brief  TIM DMA Delay Pulse complete callback.
  6511.   * @param  hdma pointer to DMA handle.
  6512.   * @retval None
  6513.   */
  6514. static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
  6515. {
  6516.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6517.  
  6518.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6519.   {
  6520.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6521.  
  6522.     if (hdma->Init.Mode == DMA_NORMAL)
  6523.     {
  6524.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6525.     }
  6526.   }
  6527.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6528.   {
  6529.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6530.  
  6531.     if (hdma->Init.Mode == DMA_NORMAL)
  6532.     {
  6533.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6534.     }
  6535.   }
  6536.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6537.   {
  6538.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6539.  
  6540.     if (hdma->Init.Mode == DMA_NORMAL)
  6541.     {
  6542.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6543.     }
  6544.   }
  6545.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6546.   {
  6547.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6548.  
  6549.     if (hdma->Init.Mode == DMA_NORMAL)
  6550.     {
  6551.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6552.     }
  6553.   }
  6554.   else
  6555.   {
  6556.     /* nothing to do */
  6557.   }
  6558.  
  6559. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6560.   htim->PWM_PulseFinishedCallback(htim);
  6561. #else
  6562.   HAL_TIM_PWM_PulseFinishedCallback(htim);
  6563. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6564.  
  6565.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6566. }
  6567.  
  6568. /**
  6569.   * @brief  TIM DMA Delay Pulse half complete callback.
  6570.   * @param  hdma pointer to DMA handle.
  6571.   * @retval None
  6572.   */
  6573. void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
  6574. {
  6575.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6576.  
  6577.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6578.   {
  6579.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6580.   }
  6581.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6582.   {
  6583.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6584.   }
  6585.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6586.   {
  6587.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6588.   }
  6589.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6590.   {
  6591.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6592.   }
  6593.   else
  6594.   {
  6595.     /* nothing to do */
  6596.   }
  6597.  
  6598. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6599.   htim->PWM_PulseFinishedHalfCpltCallback(htim);
  6600. #else
  6601.   HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
  6602. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6603.  
  6604.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6605. }
  6606.  
  6607. /**
  6608.   * @brief  TIM DMA Capture complete callback.
  6609.   * @param  hdma pointer to DMA handle.
  6610.   * @retval None
  6611.   */
  6612. void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
  6613. {
  6614.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6615.  
  6616.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6617.   {
  6618.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6619.  
  6620.     if (hdma->Init.Mode == DMA_NORMAL)
  6621.     {
  6622.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6623.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6624.     }
  6625.   }
  6626.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6627.   {
  6628.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6629.  
  6630.     if (hdma->Init.Mode == DMA_NORMAL)
  6631.     {
  6632.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6633.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6634.     }
  6635.   }
  6636.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6637.   {
  6638.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6639.  
  6640.     if (hdma->Init.Mode == DMA_NORMAL)
  6641.     {
  6642.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6643.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6644.     }
  6645.   }
  6646.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6647.   {
  6648.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6649.  
  6650.     if (hdma->Init.Mode == DMA_NORMAL)
  6651.     {
  6652.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6653.       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6654.     }
  6655.   }
  6656.   else
  6657.   {
  6658.     /* nothing to do */
  6659.   }
  6660.  
  6661. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6662.   htim->IC_CaptureCallback(htim);
  6663. #else
  6664.   HAL_TIM_IC_CaptureCallback(htim);
  6665. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6666.  
  6667.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6668. }
  6669.  
  6670. /**
  6671.   * @brief  TIM DMA Capture half complete callback.
  6672.   * @param  hdma pointer to DMA handle.
  6673.   * @retval None
  6674.   */
  6675. void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
  6676. {
  6677.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6678.  
  6679.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6680.   {
  6681.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6682.   }
  6683.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6684.   {
  6685.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6686.   }
  6687.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6688.   {
  6689.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6690.   }
  6691.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6692.   {
  6693.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6694.   }
  6695.   else
  6696.   {
  6697.     /* nothing to do */
  6698.   }
  6699.  
  6700. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6701.   htim->IC_CaptureHalfCpltCallback(htim);
  6702. #else
  6703.   HAL_TIM_IC_CaptureHalfCpltCallback(htim);
  6704. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6705.  
  6706.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6707. }
  6708.  
  6709. /**
  6710.   * @brief  TIM DMA Period Elapse complete callback.
  6711.   * @param  hdma pointer to DMA handle.
  6712.   * @retval None
  6713.   */
  6714. static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
  6715. {
  6716.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6717.  
  6718.   if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
  6719.   {
  6720.     htim->State = HAL_TIM_STATE_READY;
  6721.   }
  6722.  
  6723. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6724.   htim->PeriodElapsedCallback(htim);
  6725. #else
  6726.   HAL_TIM_PeriodElapsedCallback(htim);
  6727. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6728. }
  6729.  
  6730. /**
  6731.   * @brief  TIM DMA Period Elapse half complete callback.
  6732.   * @param  hdma pointer to DMA handle.
  6733.   * @retval None
  6734.   */
  6735. static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
  6736. {
  6737.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6738.  
  6739. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6740.   htim->PeriodElapsedHalfCpltCallback(htim);
  6741. #else
  6742.   HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
  6743. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6744. }
  6745.  
  6746. /**
  6747.   * @brief  TIM DMA Trigger callback.
  6748.   * @param  hdma pointer to DMA handle.
  6749.   * @retval None
  6750.   */
  6751. static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
  6752. {
  6753.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6754.  
  6755.   if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
  6756.   {
  6757.     htim->State = HAL_TIM_STATE_READY;
  6758.   }
  6759.  
  6760. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6761.   htim->TriggerCallback(htim);
  6762. #else
  6763.   HAL_TIM_TriggerCallback(htim);
  6764. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6765. }
  6766.  
  6767. /**
  6768.   * @brief  TIM DMA Trigger half complete callback.
  6769.   * @param  hdma pointer to DMA handle.
  6770.   * @retval None
  6771.   */
  6772. static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
  6773. {
  6774.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6775.  
  6776. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6777.   htim->TriggerHalfCpltCallback(htim);
  6778. #else
  6779.   HAL_TIM_TriggerHalfCpltCallback(htim);
  6780. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6781. }
  6782.  
  6783. /**
  6784.   * @brief  Time Base configuration
  6785.   * @param  TIMx TIM peripheral
  6786.   * @param  Structure TIM Base configuration structure
  6787.   * @retval None
  6788.   */
  6789. void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
  6790. {
  6791.   uint32_t tmpcr1;
  6792.   tmpcr1 = TIMx->CR1;
  6793.  
  6794.   /* Set TIM Time Base Unit parameters ---------------------------------------*/
  6795.   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  6796.   {
  6797.     /* Select the Counter Mode */
  6798.     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
  6799.     tmpcr1 |= Structure->CounterMode;
  6800.   }
  6801.  
  6802.   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  6803.   {
  6804.     /* Set the clock division */
  6805.     tmpcr1 &= ~TIM_CR1_CKD;
  6806.     tmpcr1 |= (uint32_t)Structure->ClockDivision;
  6807.   }
  6808.  
  6809.   /* Set the auto-reload preload */
  6810.   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
  6811.  
  6812.   TIMx->CR1 = tmpcr1;
  6813.  
  6814.   /* Set the Autoreload value */
  6815.   TIMx->ARR = (uint32_t)Structure->Period ;
  6816.  
  6817.   /* Set the Prescaler value */
  6818.   TIMx->PSC = Structure->Prescaler;
  6819.  
  6820.   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  6821.   {
  6822.     /* Set the Repetition Counter value */
  6823.     TIMx->RCR = Structure->RepetitionCounter;
  6824.   }
  6825.  
  6826.   /* Generate an update event to reload the Prescaler
  6827.      and the repetition counter (only for advanced timer) value immediately */
  6828.   TIMx->EGR = TIM_EGR_UG;
  6829. }
  6830.  
  6831. /**
  6832.   * @brief  Timer Output Compare 1 configuration
  6833.   * @param  TIMx to select the TIM peripheral
  6834.   * @param  OC_Config The output configuration structure
  6835.   * @retval None
  6836.   */
  6837. static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6838. {
  6839.   uint32_t tmpccmrx;
  6840.   uint32_t tmpccer;
  6841.   uint32_t tmpcr2;
  6842.  
  6843.   /* Disable the Channel 1: Reset the CC1E Bit */
  6844.   TIMx->CCER &= ~TIM_CCER_CC1E;
  6845.  
  6846.   /* Get the TIMx CCER register value */
  6847.   tmpccer = TIMx->CCER;
  6848.   /* Get the TIMx CR2 register value */
  6849.   tmpcr2 =  TIMx->CR2;
  6850.  
  6851.   /* Get the TIMx CCMR1 register value */
  6852.   tmpccmrx = TIMx->CCMR1;
  6853.  
  6854.   /* Reset the Output Compare Mode Bits */
  6855.   tmpccmrx &= ~TIM_CCMR1_OC1M;
  6856.   tmpccmrx &= ~TIM_CCMR1_CC1S;
  6857.   /* Select the Output Compare Mode */
  6858.   tmpccmrx |= OC_Config->OCMode;
  6859.  
  6860.   /* Reset the Output Polarity level */
  6861.   tmpccer &= ~TIM_CCER_CC1P;
  6862.   /* Set the Output Compare Polarity */
  6863.   tmpccer |= OC_Config->OCPolarity;
  6864.  
  6865.   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
  6866.   {
  6867.     /* Check parameters */
  6868.     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
  6869.  
  6870.     /* Reset the Output N Polarity level */
  6871.     tmpccer &= ~TIM_CCER_CC1NP;
  6872.     /* Set the Output N Polarity */
  6873.     tmpccer |= OC_Config->OCNPolarity;
  6874.     /* Reset the Output N State */
  6875.     tmpccer &= ~TIM_CCER_CC1NE;
  6876.   }
  6877.  
  6878.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  6879.   {
  6880.     /* Check parameters */
  6881.     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
  6882.     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
  6883.  
  6884.     /* Reset the Output Compare and Output Compare N IDLE State */
  6885.     tmpcr2 &= ~TIM_CR2_OIS1;
  6886.     tmpcr2 &= ~TIM_CR2_OIS1N;
  6887.     /* Set the Output Idle state */
  6888.     tmpcr2 |= OC_Config->OCIdleState;
  6889.     /* Set the Output N Idle state */
  6890.     tmpcr2 |= OC_Config->OCNIdleState;
  6891.   }
  6892.  
  6893.   /* Write to TIMx CR2 */
  6894.   TIMx->CR2 = tmpcr2;
  6895.  
  6896.   /* Write to TIMx CCMR1 */
  6897.   TIMx->CCMR1 = tmpccmrx;
  6898.  
  6899.   /* Set the Capture Compare Register value */
  6900.   TIMx->CCR1 = OC_Config->Pulse;
  6901.  
  6902.   /* Write to TIMx CCER */
  6903.   TIMx->CCER = tmpccer;
  6904. }
  6905.  
  6906. /**
  6907.   * @brief  Timer Output Compare 2 configuration
  6908.   * @param  TIMx to select the TIM peripheral
  6909.   * @param  OC_Config The output configuration structure
  6910.   * @retval None
  6911.   */
  6912. void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6913. {
  6914.   uint32_t tmpccmrx;
  6915.   uint32_t tmpccer;
  6916.   uint32_t tmpcr2;
  6917.  
  6918.   /* Disable the Channel 2: Reset the CC2E Bit */
  6919.   TIMx->CCER &= ~TIM_CCER_CC2E;
  6920.  
  6921.   /* Get the TIMx CCER register value */
  6922.   tmpccer = TIMx->CCER;
  6923.   /* Get the TIMx CR2 register value */
  6924.   tmpcr2 =  TIMx->CR2;
  6925.  
  6926.   /* Get the TIMx CCMR1 register value */
  6927.   tmpccmrx = TIMx->CCMR1;
  6928.  
  6929.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  6930.   tmpccmrx &= ~TIM_CCMR1_OC2M;
  6931.   tmpccmrx &= ~TIM_CCMR1_CC2S;
  6932.  
  6933.   /* Select the Output Compare Mode */
  6934.   tmpccmrx |= (OC_Config->OCMode << 8U);
  6935.  
  6936.   /* Reset the Output Polarity level */
  6937.   tmpccer &= ~TIM_CCER_CC2P;
  6938.   /* Set the Output Compare Polarity */
  6939.   tmpccer |= (OC_Config->OCPolarity << 4U);
  6940.  
  6941.   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
  6942.   {
  6943.     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
  6944.  
  6945.     /* Reset the Output N Polarity level */
  6946.     tmpccer &= ~TIM_CCER_CC2NP;
  6947.     /* Set the Output N Polarity */
  6948.     tmpccer |= (OC_Config->OCNPolarity << 4U);
  6949.     /* Reset the Output N State */
  6950.     tmpccer &= ~TIM_CCER_CC2NE;
  6951.  
  6952.   }
  6953.  
  6954.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  6955.   {
  6956.     /* Check parameters */
  6957.     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
  6958.     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
  6959.  
  6960.     /* Reset the Output Compare and Output Compare N IDLE State */
  6961.     tmpcr2 &= ~TIM_CR2_OIS2;
  6962.     tmpcr2 &= ~TIM_CR2_OIS2N;
  6963.     /* Set the Output Idle state */
  6964.     tmpcr2 |= (OC_Config->OCIdleState << 2U);
  6965.     /* Set the Output N Idle state */
  6966.     tmpcr2 |= (OC_Config->OCNIdleState << 2U);
  6967.   }
  6968.  
  6969.   /* Write to TIMx CR2 */
  6970.   TIMx->CR2 = tmpcr2;
  6971.  
  6972.   /* Write to TIMx CCMR1 */
  6973.   TIMx->CCMR1 = tmpccmrx;
  6974.  
  6975.   /* Set the Capture Compare Register value */
  6976.   TIMx->CCR2 = OC_Config->Pulse;
  6977.  
  6978.   /* Write to TIMx CCER */
  6979.   TIMx->CCER = tmpccer;
  6980. }
  6981.  
  6982. /**
  6983.   * @brief  Timer Output Compare 3 configuration
  6984.   * @param  TIMx to select the TIM peripheral
  6985.   * @param  OC_Config The output configuration structure
  6986.   * @retval None
  6987.   */
  6988. static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6989. {
  6990.   uint32_t tmpccmrx;
  6991.   uint32_t tmpccer;
  6992.   uint32_t tmpcr2;
  6993.  
  6994.   /* Disable the Channel 3: Reset the CC2E Bit */
  6995.   TIMx->CCER &= ~TIM_CCER_CC3E;
  6996.  
  6997.   /* Get the TIMx CCER register value */
  6998.   tmpccer = TIMx->CCER;
  6999.   /* Get the TIMx CR2 register value */
  7000.   tmpcr2 =  TIMx->CR2;
  7001.  
  7002.   /* Get the TIMx CCMR2 register value */
  7003.   tmpccmrx = TIMx->CCMR2;
  7004.  
  7005.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  7006.   tmpccmrx &= ~TIM_CCMR2_OC3M;
  7007.   tmpccmrx &= ~TIM_CCMR2_CC3S;
  7008.   /* Select the Output Compare Mode */
  7009.   tmpccmrx |= OC_Config->OCMode;
  7010.  
  7011.   /* Reset the Output Polarity level */
  7012.   tmpccer &= ~TIM_CCER_CC3P;
  7013.   /* Set the Output Compare Polarity */
  7014.   tmpccer |= (OC_Config->OCPolarity << 8U);
  7015.  
  7016.   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
  7017.   {
  7018.     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
  7019.  
  7020.     /* Reset the Output N Polarity level */
  7021.     tmpccer &= ~TIM_CCER_CC3NP;
  7022.     /* Set the Output N Polarity */
  7023.     tmpccer |= (OC_Config->OCNPolarity << 8U);
  7024.     /* Reset the Output N State */
  7025.     tmpccer &= ~TIM_CCER_CC3NE;
  7026.   }
  7027.  
  7028.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  7029.   {
  7030.     /* Check parameters */
  7031.     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
  7032.     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
  7033.  
  7034.     /* Reset the Output Compare and Output Compare N IDLE State */
  7035.     tmpcr2 &= ~TIM_CR2_OIS3;
  7036.     tmpcr2 &= ~TIM_CR2_OIS3N;
  7037.     /* Set the Output Idle state */
  7038.     tmpcr2 |= (OC_Config->OCIdleState << 4U);
  7039.     /* Set the Output N Idle state */
  7040.     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
  7041.   }
  7042.  
  7043.   /* Write to TIMx CR2 */
  7044.   TIMx->CR2 = tmpcr2;
  7045.  
  7046.   /* Write to TIMx CCMR2 */
  7047.   TIMx->CCMR2 = tmpccmrx;
  7048.  
  7049.   /* Set the Capture Compare Register value */
  7050.   TIMx->CCR3 = OC_Config->Pulse;
  7051.  
  7052.   /* Write to TIMx CCER */
  7053.   TIMx->CCER = tmpccer;
  7054. }
  7055.  
  7056. /**
  7057.   * @brief  Timer Output Compare 4 configuration
  7058.   * @param  TIMx to select the TIM peripheral
  7059.   * @param  OC_Config The output configuration structure
  7060.   * @retval None
  7061.   */
  7062. static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  7063. {
  7064.   uint32_t tmpccmrx;
  7065.   uint32_t tmpccer;
  7066.   uint32_t tmpcr2;
  7067.  
  7068.   /* Disable the Channel 4: Reset the CC4E Bit */
  7069.   TIMx->CCER &= ~TIM_CCER_CC4E;
  7070.  
  7071.   /* Get the TIMx CCER register value */
  7072.   tmpccer = TIMx->CCER;
  7073.   /* Get the TIMx CR2 register value */
  7074.   tmpcr2 =  TIMx->CR2;
  7075.  
  7076.   /* Get the TIMx CCMR2 register value */
  7077.   tmpccmrx = TIMx->CCMR2;
  7078.  
  7079.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  7080.   tmpccmrx &= ~TIM_CCMR2_OC4M;
  7081.   tmpccmrx &= ~TIM_CCMR2_CC4S;
  7082.  
  7083.   /* Select the Output Compare Mode */
  7084.   tmpccmrx |= (OC_Config->OCMode << 8U);
  7085.  
  7086.   /* Reset the Output Polarity level */
  7087.   tmpccer &= ~TIM_CCER_CC4P;
  7088.   /* Set the Output Compare Polarity */
  7089.   tmpccer |= (OC_Config->OCPolarity << 12U);
  7090.  
  7091.   if (IS_TIM_BREAK_INSTANCE(TIMx))
  7092.   {
  7093.     /* Check parameters */
  7094.     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
  7095.  
  7096.     /* Reset the Output Compare IDLE State */
  7097.     tmpcr2 &= ~TIM_CR2_OIS4;
  7098.  
  7099.     /* Set the Output Idle state */
  7100.     tmpcr2 |= (OC_Config->OCIdleState << 6U);
  7101.   }
  7102.  
  7103.   /* Write to TIMx CR2 */
  7104.   TIMx->CR2 = tmpcr2;
  7105.  
  7106.   /* Write to TIMx CCMR2 */
  7107.   TIMx->CCMR2 = tmpccmrx;
  7108.  
  7109.   /* Set the Capture Compare Register value */
  7110.   TIMx->CCR4 = OC_Config->Pulse;
  7111.  
  7112.   /* Write to TIMx CCER */
  7113.   TIMx->CCER = tmpccer;
  7114. }
  7115.  
  7116. /**
  7117.   * @brief  Slave Timer configuration function
  7118.   * @param  htim TIM handle
  7119.   * @param  sSlaveConfig Slave timer configuration
  7120.   * @retval None
  7121.   */
  7122. static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
  7123.                                                   TIM_SlaveConfigTypeDef *sSlaveConfig)
  7124. {
  7125.   HAL_StatusTypeDef status = HAL_OK;
  7126.   uint32_t tmpsmcr;
  7127.   uint32_t tmpccmr1;
  7128.   uint32_t tmpccer;
  7129.  
  7130.   /* Get the TIMx SMCR register value */
  7131.   tmpsmcr = htim->Instance->SMCR;
  7132.  
  7133.   /* Reset the Trigger Selection Bits */
  7134.   tmpsmcr &= ~TIM_SMCR_TS;
  7135.   /* Set the Input Trigger source */
  7136.   tmpsmcr |= sSlaveConfig->InputTrigger;
  7137.  
  7138.   /* Reset the slave mode Bits */
  7139.   tmpsmcr &= ~TIM_SMCR_SMS;
  7140.   /* Set the slave mode */
  7141.   tmpsmcr |= sSlaveConfig->SlaveMode;
  7142.  
  7143.   /* Write to TIMx SMCR */
  7144.   htim->Instance->SMCR = tmpsmcr;
  7145.  
  7146.   /* Configure the trigger prescaler, filter, and polarity */
  7147.   switch (sSlaveConfig->InputTrigger)
  7148.   {
  7149.     case TIM_TS_ETRF:
  7150.     {
  7151.       /* Check the parameters */
  7152.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
  7153.       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
  7154.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  7155.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  7156.       /* Configure the ETR Trigger source */
  7157.       TIM_ETR_SetConfig(htim->Instance,
  7158.                         sSlaveConfig->TriggerPrescaler,
  7159.                         sSlaveConfig->TriggerPolarity,
  7160.                         sSlaveConfig->TriggerFilter);
  7161.       break;
  7162.     }
  7163.  
  7164.     case TIM_TS_TI1F_ED:
  7165.     {
  7166.       /* Check the parameters */
  7167.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  7168.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  7169.  
  7170.       if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
  7171.       {
  7172.         return HAL_ERROR;
  7173.       }
  7174.  
  7175.       /* Disable the Channel 1: Reset the CC1E Bit */
  7176.       tmpccer = htim->Instance->CCER;
  7177.       htim->Instance->CCER &= ~TIM_CCER_CC1E;
  7178.       tmpccmr1 = htim->Instance->CCMR1;
  7179.  
  7180.       /* Set the filter */
  7181.       tmpccmr1 &= ~TIM_CCMR1_IC1F;
  7182.       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
  7183.  
  7184.       /* Write to TIMx CCMR1 and CCER registers */
  7185.       htim->Instance->CCMR1 = tmpccmr1;
  7186.       htim->Instance->CCER = tmpccer;
  7187.       break;
  7188.     }
  7189.  
  7190.     case TIM_TS_TI1FP1:
  7191.     {
  7192.       /* Check the parameters */
  7193.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  7194.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  7195.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  7196.  
  7197.       /* Configure TI1 Filter and Polarity */
  7198.       TIM_TI1_ConfigInputStage(htim->Instance,
  7199.                                sSlaveConfig->TriggerPolarity,
  7200.                                sSlaveConfig->TriggerFilter);
  7201.       break;
  7202.     }
  7203.  
  7204.     case TIM_TS_TI2FP2:
  7205.     {
  7206.       /* Check the parameters */
  7207.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  7208.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  7209.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  7210.  
  7211.       /* Configure TI2 Filter and Polarity */
  7212.       TIM_TI2_ConfigInputStage(htim->Instance,
  7213.                                sSlaveConfig->TriggerPolarity,
  7214.                                sSlaveConfig->TriggerFilter);
  7215.       break;
  7216.     }
  7217.  
  7218.     case TIM_TS_ITR0:
  7219.     case TIM_TS_ITR1:
  7220.     case TIM_TS_ITR2:
  7221.     case TIM_TS_ITR3:
  7222.     {
  7223.       /* Check the parameter */
  7224.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  7225.       break;
  7226.     }
  7227.  
  7228.     default:
  7229.       status = HAL_ERROR;
  7230.       break;
  7231.   }
  7232.  
  7233.   return status;
  7234. }
  7235.  
  7236. /**
  7237.   * @brief  Configure the TI1 as Input.
  7238.   * @param  TIMx to select the TIM peripheral.
  7239.   * @param  TIM_ICPolarity The Input Polarity.
  7240.   *          This parameter can be one of the following values:
  7241.   *            @arg TIM_ICPOLARITY_RISING
  7242.   *            @arg TIM_ICPOLARITY_FALLING
  7243.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  7244.   * @param  TIM_ICSelection specifies the input to be used.
  7245.   *          This parameter can be one of the following values:
  7246.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
  7247.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
  7248.   *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
  7249.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7250.   *          This parameter must be a value between 0x00 and 0x0F.
  7251.   * @retval None
  7252.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
  7253.   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
  7254.   *        protected against un-initialized filter and polarity values.
  7255.   */
  7256. void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  7257.                        uint32_t TIM_ICFilter)
  7258. {
  7259.   uint32_t tmpccmr1;
  7260.   uint32_t tmpccer;
  7261.  
  7262.   /* Disable the Channel 1: Reset the CC1E Bit */
  7263.   TIMx->CCER &= ~TIM_CCER_CC1E;
  7264.   tmpccmr1 = TIMx->CCMR1;
  7265.   tmpccer = TIMx->CCER;
  7266.  
  7267.   /* Select the Input */
  7268.   if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
  7269.   {
  7270.     tmpccmr1 &= ~TIM_CCMR1_CC1S;
  7271.     tmpccmr1 |= TIM_ICSelection;
  7272.   }
  7273.   else
  7274.   {
  7275.     tmpccmr1 |= TIM_CCMR1_CC1S_0;
  7276.   }
  7277.  
  7278.   /* Set the filter */
  7279.   tmpccmr1 &= ~TIM_CCMR1_IC1F;
  7280.   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
  7281.  
  7282.   /* Select the Polarity and set the CC1E Bit */
  7283.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  7284.   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
  7285.  
  7286.   /* Write to TIMx CCMR1 and CCER registers */
  7287.   TIMx->CCMR1 = tmpccmr1;
  7288.   TIMx->CCER = tmpccer;
  7289. }
  7290.  
  7291. /**
  7292.   * @brief  Configure the Polarity and Filter for TI1.
  7293.   * @param  TIMx to select the TIM peripheral.
  7294.   * @param  TIM_ICPolarity The Input Polarity.
  7295.   *          This parameter can be one of the following values:
  7296.   *            @arg TIM_ICPOLARITY_RISING
  7297.   *            @arg TIM_ICPOLARITY_FALLING
  7298.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  7299.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7300.   *          This parameter must be a value between 0x00 and 0x0F.
  7301.   * @retval None
  7302.   */
  7303. static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
  7304. {
  7305.   uint32_t tmpccmr1;
  7306.   uint32_t tmpccer;
  7307.  
  7308.   /* Disable the Channel 1: Reset the CC1E Bit */
  7309.   tmpccer = TIMx->CCER;
  7310.   TIMx->CCER &= ~TIM_CCER_CC1E;
  7311.   tmpccmr1 = TIMx->CCMR1;
  7312.  
  7313.   /* Set the filter */
  7314.   tmpccmr1 &= ~TIM_CCMR1_IC1F;
  7315.   tmpccmr1 |= (TIM_ICFilter << 4U);
  7316.  
  7317.   /* Select the Polarity and set the CC1E Bit */
  7318.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  7319.   tmpccer |= TIM_ICPolarity;
  7320.  
  7321.   /* Write to TIMx CCMR1 and CCER registers */
  7322.   TIMx->CCMR1 = tmpccmr1;
  7323.   TIMx->CCER = tmpccer;
  7324. }
  7325.  
  7326. /**
  7327.   * @brief  Configure the TI2 as Input.
  7328.   * @param  TIMx to select the TIM peripheral
  7329.   * @param  TIM_ICPolarity The Input Polarity.
  7330.   *          This parameter can be one of the following values:
  7331.   *            @arg TIM_ICPOLARITY_RISING
  7332.   *            @arg TIM_ICPOLARITY_FALLING
  7333.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  7334.   * @param  TIM_ICSelection specifies the input to be used.
  7335.   *          This parameter can be one of the following values:
  7336.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
  7337.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
  7338.   *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
  7339.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7340.   *          This parameter must be a value between 0x00 and 0x0F.
  7341.   * @retval None
  7342.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
  7343.   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
  7344.   *        protected against un-initialized filter and polarity values.
  7345.   */
  7346. static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  7347.                               uint32_t TIM_ICFilter)
  7348. {
  7349.   uint32_t tmpccmr1;
  7350.   uint32_t tmpccer;
  7351.  
  7352.   /* Disable the Channel 2: Reset the CC2E Bit */
  7353.   TIMx->CCER &= ~TIM_CCER_CC2E;
  7354.   tmpccmr1 = TIMx->CCMR1;
  7355.   tmpccer = TIMx->CCER;
  7356.  
  7357.   /* Select the Input */
  7358.   tmpccmr1 &= ~TIM_CCMR1_CC2S;
  7359.   tmpccmr1 |= (TIM_ICSelection << 8U);
  7360.  
  7361.   /* Set the filter */
  7362.   tmpccmr1 &= ~TIM_CCMR1_IC2F;
  7363.   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
  7364.  
  7365.   /* Select the Polarity and set the CC2E Bit */
  7366.   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  7367.   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
  7368.  
  7369.   /* Write to TIMx CCMR1 and CCER registers */
  7370.   TIMx->CCMR1 = tmpccmr1 ;
  7371.   TIMx->CCER = tmpccer;
  7372. }
  7373.  
  7374. /**
  7375.   * @brief  Configure the Polarity and Filter for TI2.
  7376.   * @param  TIMx to select the TIM peripheral.
  7377.   * @param  TIM_ICPolarity The Input Polarity.
  7378.   *          This parameter can be one of the following values:
  7379.   *            @arg TIM_ICPOLARITY_RISING
  7380.   *            @arg TIM_ICPOLARITY_FALLING
  7381.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  7382.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7383.   *          This parameter must be a value between 0x00 and 0x0F.
  7384.   * @retval None
  7385.   */
  7386. static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
  7387. {
  7388.   uint32_t tmpccmr1;
  7389.   uint32_t tmpccer;
  7390.  
  7391.   /* Disable the Channel 2: Reset the CC2E Bit */
  7392.   TIMx->CCER &= ~TIM_CCER_CC2E;
  7393.   tmpccmr1 = TIMx->CCMR1;
  7394.   tmpccer = TIMx->CCER;
  7395.  
  7396.   /* Set the filter */
  7397.   tmpccmr1 &= ~TIM_CCMR1_IC2F;
  7398.   tmpccmr1 |= (TIM_ICFilter << 12U);
  7399.  
  7400.   /* Select the Polarity and set the CC2E Bit */
  7401.   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  7402.   tmpccer |= (TIM_ICPolarity << 4U);
  7403.  
  7404.   /* Write to TIMx CCMR1 and CCER registers */
  7405.   TIMx->CCMR1 = tmpccmr1 ;
  7406.   TIMx->CCER = tmpccer;
  7407. }
  7408.  
  7409. /**
  7410.   * @brief  Configure the TI3 as Input.
  7411.   * @param  TIMx to select the TIM peripheral
  7412.   * @param  TIM_ICPolarity The Input Polarity.
  7413.   *          This parameter can be one of the following values:
  7414.   *            @arg TIM_ICPOLARITY_RISING
  7415.   *            @arg TIM_ICPOLARITY_FALLING
  7416.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  7417.   * @param  TIM_ICSelection specifies the input to be used.
  7418.   *          This parameter can be one of the following values:
  7419.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
  7420.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
  7421.   *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
  7422.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7423.   *          This parameter must be a value between 0x00 and 0x0F.
  7424.   * @retval None
  7425.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
  7426.   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
  7427.   *        protected against un-initialized filter and polarity values.
  7428.   */
  7429. static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  7430.                               uint32_t TIM_ICFilter)
  7431. {
  7432.   uint32_t tmpccmr2;
  7433.   uint32_t tmpccer;
  7434.  
  7435.   /* Disable the Channel 3: Reset the CC3E Bit */
  7436.   TIMx->CCER &= ~TIM_CCER_CC3E;
  7437.   tmpccmr2 = TIMx->CCMR2;
  7438.   tmpccer = TIMx->CCER;
  7439.  
  7440.   /* Select the Input */
  7441.   tmpccmr2 &= ~TIM_CCMR2_CC3S;
  7442.   tmpccmr2 |= TIM_ICSelection;
  7443.  
  7444.   /* Set the filter */
  7445.   tmpccmr2 &= ~TIM_CCMR2_IC3F;
  7446.   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
  7447.  
  7448.   /* Select the Polarity and set the CC3E Bit */
  7449.   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
  7450.   tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
  7451.  
  7452.   /* Write to TIMx CCMR2 and CCER registers */
  7453.   TIMx->CCMR2 = tmpccmr2;
  7454.   TIMx->CCER = tmpccer;
  7455. }
  7456.  
  7457. /**
  7458.   * @brief  Configure the TI4 as Input.
  7459.   * @param  TIMx to select the TIM peripheral
  7460.   * @param  TIM_ICPolarity The Input Polarity.
  7461.   *          This parameter can be one of the following values:
  7462.   *            @arg TIM_ICPOLARITY_RISING
  7463.   *            @arg TIM_ICPOLARITY_FALLING
  7464.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  7465.   * @param  TIM_ICSelection specifies the input to be used.
  7466.   *          This parameter can be one of the following values:
  7467.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
  7468.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
  7469.   *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
  7470.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  7471.   *          This parameter must be a value between 0x00 and 0x0F.
  7472.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
  7473.   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
  7474.   *        protected against un-initialized filter and polarity values.
  7475.   * @retval None
  7476.   */
  7477. static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  7478.                               uint32_t TIM_ICFilter)
  7479. {
  7480.   uint32_t tmpccmr2;
  7481.   uint32_t tmpccer;
  7482.  
  7483.   /* Disable the Channel 4: Reset the CC4E Bit */
  7484.   TIMx->CCER &= ~TIM_CCER_CC4E;
  7485.   tmpccmr2 = TIMx->CCMR2;
  7486.   tmpccer = TIMx->CCER;
  7487.  
  7488.   /* Select the Input */
  7489.   tmpccmr2 &= ~TIM_CCMR2_CC4S;
  7490.   tmpccmr2 |= (TIM_ICSelection << 8U);
  7491.  
  7492.   /* Set the filter */
  7493.   tmpccmr2 &= ~TIM_CCMR2_IC4F;
  7494.   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
  7495.  
  7496.   /* Select the Polarity and set the CC4E Bit */
  7497.   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
  7498.   tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
  7499.  
  7500.   /* Write to TIMx CCMR2 and CCER registers */
  7501.   TIMx->CCMR2 = tmpccmr2;
  7502.   TIMx->CCER = tmpccer ;
  7503. }
  7504.  
  7505. /**
  7506.   * @brief  Selects the Input Trigger source
  7507.   * @param  TIMx to select the TIM peripheral
  7508.   * @param  InputTriggerSource The Input Trigger source.
  7509.   *          This parameter can be one of the following values:
  7510.   *            @arg TIM_TS_ITR0: Internal Trigger 0
  7511.   *            @arg TIM_TS_ITR1: Internal Trigger 1
  7512.   *            @arg TIM_TS_ITR2: Internal Trigger 2
  7513.   *            @arg TIM_TS_ITR3: Internal Trigger 3
  7514.   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
  7515.   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
  7516.   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
  7517.   *            @arg TIM_TS_ETRF: External Trigger input
  7518.   * @retval None
  7519.   */
  7520. static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
  7521. {
  7522.   uint32_t tmpsmcr;
  7523.  
  7524.   /* Get the TIMx SMCR register value */
  7525.   tmpsmcr = TIMx->SMCR;
  7526.   /* Reset the TS Bits */
  7527.   tmpsmcr &= ~TIM_SMCR_TS;
  7528.   /* Set the Input Trigger source and the slave mode*/
  7529.   tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
  7530.   /* Write to TIMx SMCR */
  7531.   TIMx->SMCR = tmpsmcr;
  7532. }
  7533. /**
  7534.   * @brief  Configures the TIMx External Trigger (ETR).
  7535.   * @param  TIMx to select the TIM peripheral
  7536.   * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
  7537.   *          This parameter can be one of the following values:
  7538.   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
  7539.   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
  7540.   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
  7541.   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
  7542.   * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
  7543.   *          This parameter can be one of the following values:
  7544.   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
  7545.   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
  7546.   * @param  ExtTRGFilter External Trigger Filter.
  7547.   *          This parameter must be a value between 0x00 and 0x0F
  7548.   * @retval None
  7549.   */
  7550. void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
  7551.                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
  7552. {
  7553.   uint32_t tmpsmcr;
  7554.  
  7555.   tmpsmcr = TIMx->SMCR;
  7556.  
  7557.   /* Reset the ETR Bits */
  7558.   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  7559.  
  7560.   /* Set the Prescaler, the Filter value and the Polarity */
  7561.   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
  7562.  
  7563.   /* Write to TIMx SMCR */
  7564.   TIMx->SMCR = tmpsmcr;
  7565. }
  7566.  
  7567. /**
  7568.   * @brief  Enables or disables the TIM Capture Compare Channel x.
  7569.   * @param  TIMx to select the TIM peripheral
  7570.   * @param  Channel specifies the TIM Channel
  7571.   *          This parameter can be one of the following values:
  7572.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  7573.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  7574.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  7575.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  7576.   * @param  ChannelState specifies the TIM Channel CCxE bit new state.
  7577.   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
  7578.   * @retval None
  7579.   */
  7580. void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
  7581. {
  7582.   uint32_t tmp;
  7583.  
  7584.   /* Check the parameters */
  7585.   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  7586.   assert_param(IS_TIM_CHANNELS(Channel));
  7587.  
  7588.   tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
  7589.  
  7590.   /* Reset the CCxE Bit */
  7591.   TIMx->CCER &= ~tmp;
  7592.  
  7593.   /* Set or reset the CCxE Bit */
  7594.   TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
  7595. }
  7596.  
  7597. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  7598. /**
  7599.   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
  7600.   * @param  htim pointer to a TIM_HandleTypeDef structure that contains
  7601.   *                the configuration information for TIM module.
  7602.   * @retval None
  7603.   */
  7604. void TIM_ResetCallback(TIM_HandleTypeDef *htim)
  7605. {
  7606.   /* Reset the TIM callback to the legacy weak callbacks */
  7607.   htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
  7608.   htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
  7609.   htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
  7610.   htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
  7611.   htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
  7612.   htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
  7613.   htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
  7614.   htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
  7615.   htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
  7616.   htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
  7617.   htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
  7618.   htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
  7619.   htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
  7620. }
  7621. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  7622.  
  7623. /**
  7624.   * @}
  7625.   */
  7626.  
  7627. #endif /* HAL_TIM_MODULE_ENABLED */
  7628. /**
  7629.   * @}
  7630.   */
  7631.  
  7632. /**
  7633.   * @}
  7634.   */
  7635. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  7636.