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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f0xx_hal_spi.c
  4.   * @author  MCD Application Team
  5.   * @brief   SPI HAL module driver.
  6.   *          This file provides firmware functions to manage the following
  7.   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
  8.   *           + Initialization and de-initialization functions
  9.   *           + IO operation functions
  10.   *           + Peripheral Control functions
  11.   *           + Peripheral State functions
  12.   *
  13.   @verbatim
  14.   ==============================================================================
  15.                         ##### How to use this driver #####
  16.   ==============================================================================
  17.     [..]
  18.       The SPI HAL driver can be used as follows:
  19.  
  20.       (#) Declare a SPI_HandleTypeDef handle structure, for example:
  21.           SPI_HandleTypeDef  hspi;
  22.  
  23.       (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
  24.           (##) Enable the SPIx interface clock
  25.           (##) SPI pins configuration
  26.               (+++) Enable the clock for the SPI GPIOs
  27.               (+++) Configure these SPI pins as alternate function push-pull
  28.           (##) NVIC configuration if you need to use interrupt process
  29.               (+++) Configure the SPIx interrupt priority
  30.               (+++) Enable the NVIC SPI IRQ handle
  31.           (##) DMA Configuration if you need to use DMA process
  32.               (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
  33.               (+++) Enable the DMAx clock
  34.               (+++) Configure the DMA handle parameters
  35.               (+++) Configure the DMA Tx or Rx Stream/Channel
  36.               (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle
  37.               (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
  38.  
  39.       (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
  40.           management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
  41.  
  42.       (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
  43.           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
  44.               by calling the customized HAL_SPI_MspInit() API.
  45.      [..]
  46.        Circular mode restriction:
  47.       (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
  48.           (##) Master 2Lines RxOnly
  49.           (##) Master 1Line Rx
  50.       (#) The CRC feature is not managed when the DMA circular mode is enabled
  51.       (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
  52.           the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
  53.      [..]
  54.        Master Receive mode restriction:
  55.       (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
  56.           bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
  57.           does not initiate a new transfer the following procedure has to be respected:
  58.           (##) HAL_SPI_DeInit()
  59.           (##) HAL_SPI_Init()
  60.      [..]
  61.        Callback registration:
  62.  
  63.       (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
  64.           allows the user to configure dynamically the driver callbacks.
  65.           Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
  66.  
  67.           Function HAL_SPI_RegisterCallback() allows to register following callbacks:
  68.             (++) TxCpltCallback        : SPI Tx Completed callback
  69.             (++) RxCpltCallback        : SPI Rx Completed callback
  70.             (++) TxRxCpltCallback      : SPI TxRx Completed callback
  71.             (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
  72.             (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
  73.             (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
  74.             (++) ErrorCallback         : SPI Error callback
  75.             (++) AbortCpltCallback     : SPI Abort callback
  76.             (++) MspInitCallback       : SPI Msp Init callback
  77.             (++) MspDeInitCallback     : SPI Msp DeInit callback
  78.           This function takes as parameters the HAL peripheral handle, the Callback ID
  79.           and a pointer to the user callback function.
  80.  
  81.  
  82.       (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
  83.           weak function.
  84.           HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
  85.           and the Callback ID.
  86.           This function allows to reset following callbacks:
  87.             (++) TxCpltCallback        : SPI Tx Completed callback
  88.             (++) RxCpltCallback        : SPI Rx Completed callback
  89.             (++) TxRxCpltCallback      : SPI TxRx Completed callback
  90.             (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
  91.             (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
  92.             (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
  93.             (++) ErrorCallback         : SPI Error callback
  94.             (++) AbortCpltCallback     : SPI Abort callback
  95.             (++) MspInitCallback       : SPI Msp Init callback
  96.             (++) MspDeInitCallback     : SPI Msp DeInit callback
  97.  
  98.        [..]
  99.        By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
  100.        all callbacks are set to the corresponding weak functions:
  101.        examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
  102.        Exception done for MspInit and MspDeInit functions that are
  103.        reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
  104.        these callbacks are null (not registered beforehand).
  105.        If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
  106.        keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
  107.  
  108.        [..]
  109.        Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
  110.        Exception done MspInit/MspDeInit functions that can be registered/unregistered
  111.        in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
  112.        thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  113.        Then, the user first registers the MspInit/MspDeInit user callbacks
  114.        using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
  115.        or HAL_SPI_Init() function.
  116.  
  117.        [..]
  118.        When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
  119.        not defined, the callback registering feature is not available
  120.        and weak (surcharged) callbacks are used.
  121.  
  122.      [..]
  123.        Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
  124.        the following table resume the max SPI frequency reached with data size 8bits/16bits,
  125.          according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
  126.  
  127.   @endverbatim
  128.  
  129.   Additional table :
  130.  
  131.        DataSize = SPI_DATASIZE_8BIT:
  132.        +----------------------------------------------------------------------------------------------+
  133.        |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
  134.        | Process | Transfer mode  |---------------------|----------------------|----------------------|
  135.        |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
  136.        |==============================================================================================|
  137.        |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
  138.        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
  139.        |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |
  140.        |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
  141.        |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
  142.        |=========|================|==========|==========|===========|==========|===========|==========|
  143.        |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |
  144.        |         |----------------|----------|----------|-----------|----------|-----------|----------|
  145.        |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |
  146.        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
  147.        |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |
  148.        |=========|================|==========|==========|===========|==========|===========|==========|
  149.        |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |
  150.        |         |----------------|----------|----------|-----------|----------|-----------|----------|
  151.        |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |
  152.        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
  153.        |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |
  154.        +----------------------------------------------------------------------------------------------+
  155.  
  156.        DataSize = SPI_DATASIZE_16BIT:
  157.        +----------------------------------------------------------------------------------------------+
  158.        |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
  159.        | Process | Transfer mode  |---------------------|----------------------|----------------------|
  160.        |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
  161.        |==============================================================================================|
  162.        |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
  163.        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
  164.        |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |
  165.        |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
  166.        |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
  167.        |=========|================|==========|==========|===========|==========|===========|==========|
  168.        |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |
  169.        |         |----------------|----------|----------|-----------|----------|-----------|----------|
  170.        |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |
  171.        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
  172.        |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |
  173.        |=========|================|==========|==========|===========|==========|===========|==========|
  174.        |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |
  175.        |         |----------------|----------|----------|-----------|----------|-----------|----------|
  176.        |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |
  177.        |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
  178.        |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |
  179.        +----------------------------------------------------------------------------------------------+
  180.        @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
  181.              SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
  182.        @note
  183.             (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
  184.             (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
  185.             (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
  186.  
  187.   ******************************************************************************
  188.   * @attention
  189.   *
  190.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  191.   * All rights reserved.</center></h2>
  192.   *
  193.   * This software component is licensed by ST under BSD 3-Clause license,
  194.   * the "License"; You may not use this file except in compliance with the
  195.   * License. You may obtain a copy of the License at:
  196.   *                        opensource.org/licenses/BSD-3-Clause
  197.   *
  198.   ******************************************************************************
  199.   */
  200.  
  201. /* Includes ------------------------------------------------------------------*/
  202. #include "stm32f0xx_hal.h"
  203.  
  204. /** @addtogroup STM32F0xx_HAL_Driver
  205.   * @{
  206.   */
  207.  
  208. /** @defgroup SPI SPI
  209.   * @brief SPI HAL module driver
  210.   * @{
  211.   */
  212. #ifdef HAL_SPI_MODULE_ENABLED
  213.  
  214. /* Private typedef -----------------------------------------------------------*/
  215. /* Private defines -----------------------------------------------------------*/
  216. /** @defgroup SPI_Private_Constants SPI Private Constants
  217.   * @{
  218.   */
  219. #define SPI_DEFAULT_TIMEOUT 100U
  220. /**
  221.   * @}
  222.   */
  223.  
  224. /* Private macros ------------------------------------------------------------*/
  225. /* Private variables ---------------------------------------------------------*/
  226. /* Private function prototypes -----------------------------------------------*/
  227. /** @defgroup SPI_Private_Functions SPI Private Functions
  228.   * @{
  229.   */
  230. static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
  231. static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
  232. static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
  233. static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
  234. static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
  235. static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
  236. static void SPI_DMAError(DMA_HandleTypeDef *hdma);
  237. static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
  238. static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
  239. static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
  240. static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
  241.                                                        uint32_t Timeout, uint32_t Tickstart);
  242. static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
  243.                                                        uint32_t Timeout, uint32_t Tickstart);
  244. static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
  245. static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
  246. static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
  247. static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
  248. static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
  249. static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
  250. static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
  251. static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
  252. #if (USE_SPI_CRC != 0U)
  253. static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
  254. static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
  255. static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
  256. static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
  257. #endif /* USE_SPI_CRC */
  258. static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
  259. static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
  260. static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
  261. static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
  262. static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
  263. static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
  264. static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
  265. /**
  266.   * @}
  267.   */
  268.  
  269. /* Exported functions --------------------------------------------------------*/
  270. /** @defgroup SPI_Exported_Functions SPI Exported Functions
  271.   * @{
  272.   */
  273.  
  274. /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
  275.   *  @brief    Initialization and Configuration functions
  276.   *
  277. @verbatim
  278.  ===============================================================================
  279.               ##### Initialization and de-initialization functions #####
  280.  ===============================================================================
  281.     [..]  This subsection provides a set of functions allowing to initialize and
  282.           de-initialize the SPIx peripheral:
  283.  
  284.       (+) User must implement HAL_SPI_MspInit() function in which he configures
  285.           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
  286.  
  287.       (+) Call the function HAL_SPI_Init() to configure the selected device with
  288.           the selected configuration:
  289.         (++) Mode
  290.         (++) Direction
  291.         (++) Data Size
  292.         (++) Clock Polarity and Phase
  293.         (++) NSS Management
  294.         (++) BaudRate Prescaler
  295.         (++) FirstBit
  296.         (++) TIMode
  297.         (++) CRC Calculation
  298.         (++) CRC Polynomial if CRC enabled
  299.         (++) CRC Length, used only with Data8 and Data16
  300.         (++) FIFO reception threshold
  301.  
  302.       (+) Call the function HAL_SPI_DeInit() to restore the default configuration
  303.           of the selected SPIx peripheral.
  304.  
  305. @endverbatim
  306.   * @{
  307.   */
  308.  
  309. /**
  310.   * @brief  Initialize the SPI according to the specified parameters
  311.   *         in the SPI_InitTypeDef and initialize the associated handle.
  312.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  313.   *               the configuration information for SPI module.
  314.   * @retval HAL status
  315.   */
  316. HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
  317. {
  318.   uint32_t frxth;
  319.  
  320.   /* Check the SPI handle allocation */
  321.   if (hspi == NULL)
  322.   {
  323.     return HAL_ERROR;
  324.   }
  325.  
  326.   /* Check the parameters */
  327.   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
  328.   assert_param(IS_SPI_MODE(hspi->Init.Mode));
  329.   assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
  330.   assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
  331.   assert_param(IS_SPI_NSS(hspi->Init.NSS));
  332.   assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
  333.   assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
  334.   assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
  335.   assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
  336.   if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
  337.   {
  338.     assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
  339.     assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
  340.  
  341.     if (hspi->Init.Mode == SPI_MODE_MASTER)
  342.     {
  343.       assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
  344.     }
  345.     else
  346.     {
  347.       /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
  348.       hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
  349.     }
  350.   }
  351.   else
  352.   {
  353.     assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
  354.  
  355.     /* Force polarity and phase to TI protocaol requirements */
  356.     hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
  357.     hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;
  358.   }
  359. #if (USE_SPI_CRC != 0U)
  360.   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
  361.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  362.   {
  363.     assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
  364.     assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
  365.   }
  366. #else
  367.   hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
  368. #endif /* USE_SPI_CRC */
  369.  
  370.   if (hspi->State == HAL_SPI_STATE_RESET)
  371.   {
  372.     /* Allocate lock resource and initialize it */
  373.     hspi->Lock = HAL_UNLOCKED;
  374.  
  375. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  376.     /* Init the SPI Callback settings */
  377.     hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */
  378.     hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */
  379.     hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */
  380.     hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */
  381.     hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */
  382.     hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
  383.     hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */
  384.     hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
  385.  
  386.     if (hspi->MspInitCallback == NULL)
  387.     {
  388.       hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */
  389.     }
  390.  
  391.     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
  392.     hspi->MspInitCallback(hspi);
  393. #else
  394.     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
  395.     HAL_SPI_MspInit(hspi);
  396. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  397.   }
  398.  
  399.   hspi->State = HAL_SPI_STATE_BUSY;
  400.  
  401.   /* Disable the selected SPI peripheral */
  402.   __HAL_SPI_DISABLE(hspi);
  403.  
  404.   /* Align by default the rs fifo threshold on the data size */
  405.   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  406.   {
  407.     frxth = SPI_RXFIFO_THRESHOLD_HF;
  408.   }
  409.   else
  410.   {
  411.     frxth = SPI_RXFIFO_THRESHOLD_QF;
  412.   }
  413.  
  414.   /* CRC calculation is valid only for 16Bit and 8 Bit */
  415.   if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
  416.   {
  417.     /* CRC must be disabled */
  418.     hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
  419.   }
  420.  
  421.   /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
  422.   /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
  423.   Communication speed, First bit and CRC calculation state */
  424.   WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
  425.                                   (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
  426.                                   (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
  427.                                   (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
  428.                                   (hspi->Init.NSS & SPI_CR1_SSM) |
  429.                                   (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
  430.                                   (hspi->Init.FirstBit  & SPI_CR1_LSBFIRST) |
  431.                                   (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
  432. #if (USE_SPI_CRC != 0U)
  433.   /*---------------------------- SPIx CRCL Configuration -------------------*/
  434.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  435.   {
  436.     /* Align the CRC Length on the data size */
  437.     if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
  438.     {
  439.       /* CRC Length aligned on the data size : value set by default */
  440.       if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  441.       {
  442.         hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
  443.       }
  444.       else
  445.       {
  446.         hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
  447.       }
  448.     }
  449.  
  450.     /* Configure : CRC Length */
  451.     if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
  452.     {
  453.       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
  454.     }
  455.   }
  456. #endif /* USE_SPI_CRC */
  457.  
  458.   /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
  459.   WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
  460.                                   (hspi->Init.TIMode & SPI_CR2_FRF) |
  461.                                   (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
  462.                                   (hspi->Init.DataSize & SPI_CR2_DS_Msk) |
  463.                                   (frxth & SPI_CR2_FRXTH)));
  464.  
  465. #if (USE_SPI_CRC != 0U)
  466.   /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
  467.   /* Configure : CRC Polynomial */
  468.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  469.   {
  470.     WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
  471.   }
  472. #endif /* USE_SPI_CRC */
  473.  
  474. #if defined(SPI_I2SCFGR_I2SMOD)
  475.   /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
  476.   CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
  477. #endif /* SPI_I2SCFGR_I2SMOD */
  478.  
  479.   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  480.   hspi->State     = HAL_SPI_STATE_READY;
  481.  
  482.   return HAL_OK;
  483. }
  484.  
  485. /**
  486.   * @brief  De-Initialize the SPI peripheral.
  487.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  488.   *               the configuration information for SPI module.
  489.   * @retval HAL status
  490.   */
  491. HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
  492. {
  493.   /* Check the SPI handle allocation */
  494.   if (hspi == NULL)
  495.   {
  496.     return HAL_ERROR;
  497.   }
  498.  
  499.   /* Check SPI Instance parameter */
  500.   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
  501.  
  502.   hspi->State = HAL_SPI_STATE_BUSY;
  503.  
  504.   /* Disable the SPI Peripheral Clock */
  505.   __HAL_SPI_DISABLE(hspi);
  506.  
  507. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  508.   if (hspi->MspDeInitCallback == NULL)
  509.   {
  510.     hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */
  511.   }
  512.  
  513.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
  514.   hspi->MspDeInitCallback(hspi);
  515. #else
  516.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
  517.   HAL_SPI_MspDeInit(hspi);
  518. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  519.  
  520.   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  521.   hspi->State = HAL_SPI_STATE_RESET;
  522.  
  523.   /* Release Lock */
  524.   __HAL_UNLOCK(hspi);
  525.  
  526.   return HAL_OK;
  527. }
  528.  
  529. /**
  530.   * @brief  Initialize the SPI MSP.
  531.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  532.   *               the configuration information for SPI module.
  533.   * @retval None
  534.   */
  535. __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
  536. {
  537.   /* Prevent unused argument(s) compilation warning */
  538.   UNUSED(hspi);
  539.  
  540.   /* NOTE : This function should not be modified, when the callback is needed,
  541.             the HAL_SPI_MspInit should be implemented in the user file
  542.    */
  543. }
  544.  
  545. /**
  546.   * @brief  De-Initialize the SPI MSP.
  547.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  548.   *               the configuration information for SPI module.
  549.   * @retval None
  550.   */
  551. __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
  552. {
  553.   /* Prevent unused argument(s) compilation warning */
  554.   UNUSED(hspi);
  555.  
  556.   /* NOTE : This function should not be modified, when the callback is needed,
  557.             the HAL_SPI_MspDeInit should be implemented in the user file
  558.    */
  559. }
  560.  
  561. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  562. /**
  563.   * @brief  Register a User SPI Callback
  564.   *         To be used instead of the weak predefined callback
  565.   * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
  566.   *                the configuration information for the specified SPI.
  567.   * @param  CallbackID ID of the callback to be registered
  568.   * @param  pCallback pointer to the Callback function
  569.   * @retval HAL status
  570.   */
  571. HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
  572.                                            pSPI_CallbackTypeDef pCallback)
  573. {
  574.   HAL_StatusTypeDef status = HAL_OK;
  575.  
  576.   if (pCallback == NULL)
  577.   {
  578.     /* Update the error code */
  579.     hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
  580.  
  581.     return HAL_ERROR;
  582.   }
  583.   /* Process locked */
  584.   __HAL_LOCK(hspi);
  585.  
  586.   if (HAL_SPI_STATE_READY == hspi->State)
  587.   {
  588.     switch (CallbackID)
  589.     {
  590.       case HAL_SPI_TX_COMPLETE_CB_ID :
  591.         hspi->TxCpltCallback = pCallback;
  592.         break;
  593.  
  594.       case HAL_SPI_RX_COMPLETE_CB_ID :
  595.         hspi->RxCpltCallback = pCallback;
  596.         break;
  597.  
  598.       case HAL_SPI_TX_RX_COMPLETE_CB_ID :
  599.         hspi->TxRxCpltCallback = pCallback;
  600.         break;
  601.  
  602.       case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
  603.         hspi->TxHalfCpltCallback = pCallback;
  604.         break;
  605.  
  606.       case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
  607.         hspi->RxHalfCpltCallback = pCallback;
  608.         break;
  609.  
  610.       case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
  611.         hspi->TxRxHalfCpltCallback = pCallback;
  612.         break;
  613.  
  614.       case HAL_SPI_ERROR_CB_ID :
  615.         hspi->ErrorCallback = pCallback;
  616.         break;
  617.  
  618.       case HAL_SPI_ABORT_CB_ID :
  619.         hspi->AbortCpltCallback = pCallback;
  620.         break;
  621.  
  622.       case HAL_SPI_MSPINIT_CB_ID :
  623.         hspi->MspInitCallback = pCallback;
  624.         break;
  625.  
  626.       case HAL_SPI_MSPDEINIT_CB_ID :
  627.         hspi->MspDeInitCallback = pCallback;
  628.         break;
  629.  
  630.       default :
  631.         /* Update the error code */
  632.         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
  633.  
  634.         /* Return error status */
  635.         status =  HAL_ERROR;
  636.         break;
  637.     }
  638.   }
  639.   else if (HAL_SPI_STATE_RESET == hspi->State)
  640.   {
  641.     switch (CallbackID)
  642.     {
  643.       case HAL_SPI_MSPINIT_CB_ID :
  644.         hspi->MspInitCallback = pCallback;
  645.         break;
  646.  
  647.       case HAL_SPI_MSPDEINIT_CB_ID :
  648.         hspi->MspDeInitCallback = pCallback;
  649.         break;
  650.  
  651.       default :
  652.         /* Update the error code */
  653.         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
  654.  
  655.         /* Return error status */
  656.         status =  HAL_ERROR;
  657.         break;
  658.     }
  659.   }
  660.   else
  661.   {
  662.     /* Update the error code */
  663.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
  664.  
  665.     /* Return error status */
  666.     status =  HAL_ERROR;
  667.   }
  668.  
  669.   /* Release Lock */
  670.   __HAL_UNLOCK(hspi);
  671.   return status;
  672. }
  673.  
  674. /**
  675.   * @brief  Unregister an SPI Callback
  676.   *         SPI callback is redirected to the weak predefined callback
  677.   * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
  678.   *                the configuration information for the specified SPI.
  679.   * @param  CallbackID ID of the callback to be unregistered
  680.   * @retval HAL status
  681.   */
  682. HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
  683. {
  684.   HAL_StatusTypeDef status = HAL_OK;
  685.  
  686.   /* Process locked */
  687.   __HAL_LOCK(hspi);
  688.  
  689.   if (HAL_SPI_STATE_READY == hspi->State)
  690.   {
  691.     switch (CallbackID)
  692.     {
  693.       case HAL_SPI_TX_COMPLETE_CB_ID :
  694.         hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */
  695.         break;
  696.  
  697.       case HAL_SPI_RX_COMPLETE_CB_ID :
  698.         hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */
  699.         break;
  700.  
  701.       case HAL_SPI_TX_RX_COMPLETE_CB_ID :
  702.         hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */
  703.         break;
  704.  
  705.       case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
  706.         hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */
  707.         break;
  708.  
  709.       case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
  710.         hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */
  711.         break;
  712.  
  713.       case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
  714.         hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
  715.         break;
  716.  
  717.       case HAL_SPI_ERROR_CB_ID :
  718.         hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */
  719.         break;
  720.  
  721.       case HAL_SPI_ABORT_CB_ID :
  722.         hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
  723.         break;
  724.  
  725.       case HAL_SPI_MSPINIT_CB_ID :
  726.         hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
  727.         break;
  728.  
  729.       case HAL_SPI_MSPDEINIT_CB_ID :
  730.         hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
  731.         break;
  732.  
  733.       default :
  734.         /* Update the error code */
  735.         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
  736.  
  737.         /* Return error status */
  738.         status =  HAL_ERROR;
  739.         break;
  740.     }
  741.   }
  742.   else if (HAL_SPI_STATE_RESET == hspi->State)
  743.   {
  744.     switch (CallbackID)
  745.     {
  746.       case HAL_SPI_MSPINIT_CB_ID :
  747.         hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
  748.         break;
  749.  
  750.       case HAL_SPI_MSPDEINIT_CB_ID :
  751.         hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
  752.         break;
  753.  
  754.       default :
  755.         /* Update the error code */
  756.         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
  757.  
  758.         /* Return error status */
  759.         status =  HAL_ERROR;
  760.         break;
  761.     }
  762.   }
  763.   else
  764.   {
  765.     /* Update the error code */
  766.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
  767.  
  768.     /* Return error status */
  769.     status =  HAL_ERROR;
  770.   }
  771.  
  772.   /* Release Lock */
  773.   __HAL_UNLOCK(hspi);
  774.   return status;
  775. }
  776. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  777. /**
  778.   * @}
  779.   */
  780.  
  781. /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
  782.   *  @brief   Data transfers functions
  783.   *
  784. @verbatim
  785.   ==============================================================================
  786.                       ##### IO operation functions #####
  787.  ===============================================================================
  788.  [..]
  789.     This subsection provides a set of functions allowing to manage the SPI
  790.     data transfers.
  791.  
  792.     [..] The SPI supports master and slave mode :
  793.  
  794.     (#) There are two modes of transfer:
  795.        (++) Blocking mode: The communication is performed in polling mode.
  796.             The HAL status of all data processing is returned by the same function
  797.             after finishing transfer.
  798.        (++) No-Blocking mode: The communication is performed using Interrupts
  799.             or DMA, These APIs return the HAL status.
  800.             The end of the data processing will be indicated through the
  801.             dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
  802.             using DMA mode.
  803.             The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
  804.             will be executed respectively at the end of the transmit or Receive process
  805.             The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
  806.  
  807.     (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
  808.         exist for 1Line (simplex) and 2Lines (full duplex) modes.
  809.  
  810. @endverbatim
  811.   * @{
  812.   */
  813.  
  814. /**
  815.   * @brief  Transmit an amount of data in blocking mode.
  816.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  817.   *               the configuration information for SPI module.
  818.   * @param  pData pointer to data buffer
  819.   * @param  Size amount of data to be sent
  820.   * @param  Timeout Timeout duration
  821.   * @retval HAL status
  822.   */
  823. HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
  824. {
  825.   uint32_t tickstart;
  826.   HAL_StatusTypeDef errorcode = HAL_OK;
  827.   uint16_t initial_TxXferCount;
  828.  
  829.   /* Check Direction parameter */
  830.   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
  831.  
  832.   /* Process Locked */
  833.   __HAL_LOCK(hspi);
  834.  
  835.   /* Init tickstart for timeout management*/
  836.   tickstart = HAL_GetTick();
  837.   initial_TxXferCount = Size;
  838.  
  839.   if (hspi->State != HAL_SPI_STATE_READY)
  840.   {
  841.     errorcode = HAL_BUSY;
  842.     goto error;
  843.   }
  844.  
  845.   if ((pData == NULL) || (Size == 0U))
  846.   {
  847.     errorcode = HAL_ERROR;
  848.     goto error;
  849.   }
  850.  
  851.   /* Set the transaction information */
  852.   hspi->State       = HAL_SPI_STATE_BUSY_TX;
  853.   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
  854.   hspi->pTxBuffPtr  = (uint8_t *)pData;
  855.   hspi->TxXferSize  = Size;
  856.   hspi->TxXferCount = Size;
  857.  
  858.   /*Init field not used in handle to zero */
  859.   hspi->pRxBuffPtr  = (uint8_t *)NULL;
  860.   hspi->RxXferSize  = 0U;
  861.   hspi->RxXferCount = 0U;
  862.   hspi->TxISR       = NULL;
  863.   hspi->RxISR       = NULL;
  864.  
  865.   /* Configure communication direction : 1Line */
  866.   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
  867.   {
  868.     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
  869.     __HAL_SPI_DISABLE(hspi);
  870.     SPI_1LINE_TX(hspi);
  871.   }
  872.  
  873. #if (USE_SPI_CRC != 0U)
  874.   /* Reset CRC Calculation */
  875.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  876.   {
  877.     SPI_RESET_CRC(hspi);
  878.   }
  879. #endif /* USE_SPI_CRC */
  880.  
  881.   /* Check if the SPI is already enabled */
  882.   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  883.   {
  884.     /* Enable SPI peripheral */
  885.     __HAL_SPI_ENABLE(hspi);
  886.   }
  887.  
  888.   /* Transmit data in 16 Bit mode */
  889.   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  890.   {
  891.     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
  892.     {
  893.       hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
  894.       hspi->pTxBuffPtr += sizeof(uint16_t);
  895.       hspi->TxXferCount--;
  896.     }
  897.     /* Transmit data in 16 Bit mode */
  898.     while (hspi->TxXferCount > 0U)
  899.     {
  900.       /* Wait until TXE flag is set to send data */
  901.       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
  902.       {
  903.         hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
  904.         hspi->pTxBuffPtr += sizeof(uint16_t);
  905.         hspi->TxXferCount--;
  906.       }
  907.       else
  908.       {
  909.         /* Timeout management */
  910.         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
  911.         {
  912.           errorcode = HAL_TIMEOUT;
  913.           goto error;
  914.         }
  915.       }
  916.     }
  917.   }
  918.   /* Transmit data in 8 Bit mode */
  919.   else
  920.   {
  921.     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
  922.     {
  923.       *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
  924.       hspi->pTxBuffPtr += sizeof(uint8_t);
  925.       hspi->TxXferCount--;
  926.     }
  927.     while (hspi->TxXferCount > 0U)
  928.     {
  929.       /* Wait until TXE flag is set to send data */
  930.       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
  931.       {
  932.         *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
  933.         hspi->pTxBuffPtr += sizeof(uint8_t);
  934.         hspi->TxXferCount--;
  935.       }
  936.       else
  937.       {
  938.         /* Timeout management */
  939.         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
  940.         {
  941.           errorcode = HAL_TIMEOUT;
  942.           goto error;
  943.         }
  944.       }
  945.     }
  946.   }
  947. #if (USE_SPI_CRC != 0U)
  948.   /* Enable CRC Transmission */
  949.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  950.   {
  951.     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  952.   }
  953. #endif /* USE_SPI_CRC */
  954.  
  955.   /* Check the end of the transaction */
  956.   if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
  957.   {
  958.     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
  959.   }
  960.  
  961.   /* Clear overrun flag in 2 Lines communication mode because received is not read */
  962.   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
  963.   {
  964.     __HAL_SPI_CLEAR_OVRFLAG(hspi);
  965.   }
  966.  
  967.   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  968.   {
  969.     errorcode = HAL_ERROR;
  970.   }
  971.  
  972. error:
  973.   hspi->State = HAL_SPI_STATE_READY;
  974.   /* Process Unlocked */
  975.   __HAL_UNLOCK(hspi);
  976.   return errorcode;
  977. }
  978.  
  979. /**
  980.   * @brief  Receive an amount of data in blocking mode.
  981.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  982.   *               the configuration information for SPI module.
  983.   * @param  pData pointer to data buffer
  984.   * @param  Size amount of data to be received
  985.   * @param  Timeout Timeout duration
  986.   * @retval HAL status
  987.   */
  988. HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
  989. {
  990. #if (USE_SPI_CRC != 0U)
  991.   __IO uint32_t tmpreg = 0U;
  992.   __IO uint8_t  * ptmpreg8;
  993.   __IO uint8_t  tmpreg8 = 0;
  994. #endif /* USE_SPI_CRC */
  995.   uint32_t tickstart;
  996.   HAL_StatusTypeDef errorcode = HAL_OK;
  997.  
  998.   if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
  999.   {
  1000.     hspi->State = HAL_SPI_STATE_BUSY_RX;
  1001.     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
  1002.     return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
  1003.   }
  1004.  
  1005.   /* Process Locked */
  1006.   __HAL_LOCK(hspi);
  1007.  
  1008.   /* Init tickstart for timeout management*/
  1009.   tickstart = HAL_GetTick();
  1010.  
  1011.   if (hspi->State != HAL_SPI_STATE_READY)
  1012.   {
  1013.     errorcode = HAL_BUSY;
  1014.     goto error;
  1015.   }
  1016.  
  1017.   if ((pData == NULL) || (Size == 0U))
  1018.   {
  1019.     errorcode = HAL_ERROR;
  1020.     goto error;
  1021.   }
  1022.  
  1023.   /* Set the transaction information */
  1024.   hspi->State       = HAL_SPI_STATE_BUSY_RX;
  1025.   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
  1026.   hspi->pRxBuffPtr  = (uint8_t *)pData;
  1027.   hspi->RxXferSize  = Size;
  1028.   hspi->RxXferCount = Size;
  1029.  
  1030.   /*Init field not used in handle to zero */
  1031.   hspi->pTxBuffPtr  = (uint8_t *)NULL;
  1032.   hspi->TxXferSize  = 0U;
  1033.   hspi->TxXferCount = 0U;
  1034.   hspi->RxISR       = NULL;
  1035.   hspi->TxISR       = NULL;
  1036.  
  1037. #if (USE_SPI_CRC != 0U)
  1038.   /* Reset CRC Calculation */
  1039.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1040.   {
  1041.     SPI_RESET_CRC(hspi);
  1042.     /* this is done to handle the CRCNEXT before the latest data */
  1043.     hspi->RxXferCount--;
  1044.   }
  1045. #endif /* USE_SPI_CRC */
  1046.  
  1047.   /* Set the Rx Fifo threshold */
  1048.   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  1049.   {
  1050.     /* Set RX Fifo threshold according the reception data length: 16bit */
  1051.     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1052.   }
  1053.   else
  1054.   {
  1055.     /* Set RX Fifo threshold according the reception data length: 8bit */
  1056.     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1057.   }
  1058.  
  1059.   /* Configure communication direction: 1Line */
  1060.   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
  1061.   {
  1062.     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
  1063.     __HAL_SPI_DISABLE(hspi);
  1064.     SPI_1LINE_RX(hspi);
  1065.   }
  1066.  
  1067.   /* Check if the SPI is already enabled */
  1068.   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  1069.   {
  1070.     /* Enable SPI peripheral */
  1071.     __HAL_SPI_ENABLE(hspi);
  1072.   }
  1073.  
  1074.   /* Receive data in 8 Bit mode */
  1075.   if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
  1076.   {
  1077.     /* Transfer loop */
  1078.     while (hspi->RxXferCount > 0U)
  1079.     {
  1080.       /* Check the RXNE flag */
  1081.       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
  1082.       {
  1083.         /* read the received data */
  1084.         (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
  1085.         hspi->pRxBuffPtr += sizeof(uint8_t);
  1086.         hspi->RxXferCount--;
  1087.       }
  1088.       else
  1089.       {
  1090.         /* Timeout management */
  1091.         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
  1092.         {
  1093.           errorcode = HAL_TIMEOUT;
  1094.           goto error;
  1095.         }
  1096.       }
  1097.     }
  1098.   }
  1099.   else
  1100.   {
  1101.     /* Transfer loop */
  1102.     while (hspi->RxXferCount > 0U)
  1103.     {
  1104.       /* Check the RXNE flag */
  1105.       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
  1106.       {
  1107.         *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
  1108.         hspi->pRxBuffPtr += sizeof(uint16_t);
  1109.         hspi->RxXferCount--;
  1110.       }
  1111.       else
  1112.       {
  1113.         /* Timeout management */
  1114.         if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
  1115.         {
  1116.           errorcode = HAL_TIMEOUT;
  1117.           goto error;
  1118.         }
  1119.       }
  1120.     }
  1121.   }
  1122.  
  1123. #if (USE_SPI_CRC != 0U)
  1124.   /* Handle the CRC Transmission */
  1125.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1126.   {
  1127.     /* freeze the CRC before the latest data */
  1128.     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  1129.  
  1130.     /* Read the latest data */
  1131.     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
  1132.     {
  1133.       /* the latest data has not been received */
  1134.       errorcode = HAL_TIMEOUT;
  1135.       goto error;
  1136.     }
  1137.  
  1138.     /* Receive last data in 16 Bit mode */
  1139.     if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  1140.     {
  1141.       *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
  1142.     }
  1143.     /* Receive last data in 8 Bit mode */
  1144.     else
  1145.     {
  1146.       (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
  1147.     }
  1148.  
  1149.     /* Wait the CRC data */
  1150.     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
  1151.     {
  1152.       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  1153.       errorcode = HAL_TIMEOUT;
  1154.       goto error;
  1155.     }
  1156.  
  1157.     /* Read CRC to Flush DR and RXNE flag */
  1158.     if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
  1159.     {
  1160.       /* Read 16bit CRC */
  1161.       tmpreg = READ_REG(hspi->Instance->DR);
  1162.       /* To avoid GCC warning */
  1163.       UNUSED(tmpreg);
  1164.     }
  1165.     else
  1166.     {
  1167.       /* Initialize the 8bit temporary pointer */
  1168.       ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
  1169.       /* Read 8bit CRC */
  1170.       tmpreg8 = *ptmpreg8;
  1171.       /* To avoid GCC warning */
  1172.       UNUSED(tmpreg8);
  1173.  
  1174.       if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
  1175.       {
  1176.         if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
  1177.         {
  1178.           /* Error on the CRC reception */
  1179.           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  1180.           errorcode = HAL_TIMEOUT;
  1181.           goto error;
  1182.         }
  1183.         /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
  1184.         tmpreg8 = *ptmpreg8;
  1185.         /* To avoid GCC warning */
  1186.         UNUSED(tmpreg8);
  1187.       }
  1188.     }
  1189.   }
  1190. #endif /* USE_SPI_CRC */
  1191.  
  1192.   /* Check the end of the transaction */
  1193.   if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
  1194.   {
  1195.     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
  1196.   }
  1197.  
  1198. #if (USE_SPI_CRC != 0U)
  1199.   /* Check if CRC error occurred */
  1200.   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
  1201.   {
  1202.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  1203.     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
  1204.   }
  1205. #endif /* USE_SPI_CRC */
  1206.  
  1207.   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  1208.   {
  1209.     errorcode = HAL_ERROR;
  1210.   }
  1211.  
  1212. error :
  1213.   hspi->State = HAL_SPI_STATE_READY;
  1214.   __HAL_UNLOCK(hspi);
  1215.   return errorcode;
  1216. }
  1217.  
  1218. /**
  1219.   * @brief  Transmit and Receive an amount of data in blocking mode.
  1220.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  1221.   *               the configuration information for SPI module.
  1222.   * @param  pTxData pointer to transmission data buffer
  1223.   * @param  pRxData pointer to reception data buffer
  1224.   * @param  Size amount of data to be sent and received
  1225.   * @param  Timeout Timeout duration
  1226.   * @retval HAL status
  1227.   */
  1228. HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
  1229.                                           uint32_t Timeout)
  1230. {
  1231.   uint16_t             initial_TxXferCount;
  1232.   uint32_t             tmp_mode;
  1233.   HAL_SPI_StateTypeDef tmp_state;
  1234.   uint32_t             tickstart;
  1235. #if (USE_SPI_CRC != 0U)
  1236.   __IO uint32_t tmpreg = 0U;
  1237.   uint32_t             spi_cr1;
  1238.   uint32_t             spi_cr2;
  1239.   __IO uint8_t  * ptmpreg8;
  1240.   __IO uint8_t  tmpreg8 = 0;
  1241. #endif /* USE_SPI_CRC */
  1242.  
  1243.   /* Variable used to alternate Rx and Tx during transfer */
  1244.   uint32_t             txallowed = 1U;
  1245.   HAL_StatusTypeDef    errorcode = HAL_OK;
  1246.  
  1247.   /* Check Direction parameter */
  1248.   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
  1249.  
  1250.   /* Process Locked */
  1251.   __HAL_LOCK(hspi);
  1252.  
  1253.   /* Init tickstart for timeout management*/
  1254.   tickstart = HAL_GetTick();
  1255.  
  1256.   /* Init temporary variables */
  1257.   tmp_state           = hspi->State;
  1258.   tmp_mode            = hspi->Init.Mode;
  1259.   initial_TxXferCount = Size;
  1260. #if (USE_SPI_CRC != 0U)
  1261.   spi_cr1             = READ_REG(hspi->Instance->CR1);
  1262.   spi_cr2             = READ_REG(hspi->Instance->CR2);
  1263. #endif /* USE_SPI_CRC */
  1264.  
  1265.   if (!((tmp_state == HAL_SPI_STATE_READY) || \
  1266.         ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
  1267.   {
  1268.     errorcode = HAL_BUSY;
  1269.     goto error;
  1270.   }
  1271.  
  1272.   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
  1273.   {
  1274.     errorcode = HAL_ERROR;
  1275.     goto error;
  1276.   }
  1277.  
  1278.   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
  1279.   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
  1280.   {
  1281.     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
  1282.   }
  1283.  
  1284.   /* Set the transaction information */
  1285.   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
  1286.   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
  1287.   hspi->RxXferCount = Size;
  1288.   hspi->RxXferSize  = Size;
  1289.   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
  1290.   hspi->TxXferCount = Size;
  1291.   hspi->TxXferSize  = Size;
  1292.  
  1293.   /*Init field not used in handle to zero */
  1294.   hspi->RxISR       = NULL;
  1295.   hspi->TxISR       = NULL;
  1296.  
  1297. #if (USE_SPI_CRC != 0U)
  1298.   /* Reset CRC Calculation */
  1299.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1300.   {
  1301.     SPI_RESET_CRC(hspi);
  1302.   }
  1303. #endif /* USE_SPI_CRC */
  1304.  
  1305.   /* Set the Rx Fifo threshold */
  1306.   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  1307.   {
  1308.     /* Set fiforxthreshold according the reception data length: 16bit */
  1309.     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1310.   }
  1311.   else
  1312.   {
  1313.     /* Set fiforxthreshold according the reception data length: 8bit */
  1314.     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1315.   }
  1316.  
  1317.   /* Check if the SPI is already enabled */
  1318.   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  1319.   {
  1320.     /* Enable SPI peripheral */
  1321.     __HAL_SPI_ENABLE(hspi);
  1322.   }
  1323.  
  1324.   /* Transmit and Receive data in 16 Bit mode */
  1325.   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  1326.   {
  1327.     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
  1328.     {
  1329.       hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
  1330.       hspi->pTxBuffPtr += sizeof(uint16_t);
  1331.       hspi->TxXferCount--;
  1332.     }
  1333.     while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
  1334.     {
  1335.       /* Check TXE flag */
  1336.       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
  1337.       {
  1338.         hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
  1339.         hspi->pTxBuffPtr += sizeof(uint16_t);
  1340.         hspi->TxXferCount--;
  1341.         /* Next Data is a reception (Rx). Tx not allowed */
  1342.         txallowed = 0U;
  1343.  
  1344. #if (USE_SPI_CRC != 0U)
  1345.         /* Enable CRC Transmission */
  1346.         if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
  1347.         {
  1348.           /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
  1349.           if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
  1350.           {
  1351.             SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
  1352.           }
  1353.           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  1354.         }
  1355. #endif /* USE_SPI_CRC */
  1356.       }
  1357.  
  1358.       /* Check RXNE flag */
  1359.       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
  1360.       {
  1361.         *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
  1362.         hspi->pRxBuffPtr += sizeof(uint16_t);
  1363.         hspi->RxXferCount--;
  1364.         /* Next Data is a Transmission (Tx). Tx is allowed */
  1365.         txallowed = 1U;
  1366.       }
  1367.       if (((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY))
  1368.       {
  1369.         errorcode = HAL_TIMEOUT;
  1370.         goto error;
  1371.       }
  1372.     }
  1373.   }
  1374.   /* Transmit and Receive data in 8 Bit mode */
  1375.   else
  1376.   {
  1377.     if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
  1378.     {
  1379.       *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
  1380.       hspi->pTxBuffPtr += sizeof(uint8_t);
  1381.       hspi->TxXferCount--;
  1382.     }
  1383.     while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
  1384.     {
  1385.       /* Check TXE flag */
  1386.       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
  1387.       {
  1388.         *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
  1389.         hspi->pTxBuffPtr++;
  1390.         hspi->TxXferCount--;
  1391.         /* Next Data is a reception (Rx). Tx not allowed */
  1392.         txallowed = 0U;
  1393.  
  1394. #if (USE_SPI_CRC != 0U)
  1395.         /* Enable CRC Transmission */
  1396.         if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
  1397.         {
  1398.           /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
  1399.           if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
  1400.           {
  1401.             SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
  1402.           }
  1403.           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  1404.         }
  1405. #endif /* USE_SPI_CRC */
  1406.       }
  1407.  
  1408.       /* Wait until RXNE flag is reset */
  1409.       if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
  1410.       {
  1411.         (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
  1412.         hspi->pRxBuffPtr++;
  1413.         hspi->RxXferCount--;
  1414.         /* Next Data is a Transmission (Tx). Tx is allowed */
  1415.         txallowed = 1U;
  1416.       }
  1417.       if ((((HAL_GetTick() - tickstart) >=  Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
  1418.       {
  1419.         errorcode = HAL_TIMEOUT;
  1420.         goto error;
  1421.       }
  1422.     }
  1423.   }
  1424.  
  1425. #if (USE_SPI_CRC != 0U)
  1426.   /* Read CRC from DR to close CRC calculation process */
  1427.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1428.   {
  1429.     /* Wait until TXE flag */
  1430.     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
  1431.     {
  1432.       /* Error on the CRC reception */
  1433.       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  1434.       errorcode = HAL_TIMEOUT;
  1435.       goto error;
  1436.     }
  1437.     /* Read CRC */
  1438.     if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
  1439.     {
  1440.       /* Read 16bit CRC */
  1441.       tmpreg = READ_REG(hspi->Instance->DR);
  1442.       /* To avoid GCC warning */
  1443.       UNUSED(tmpreg);
  1444.     }
  1445.     else
  1446.     {
  1447.       /* Initialize the 8bit temporary pointer */
  1448.       ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
  1449.       /* Read 8bit CRC */
  1450.       tmpreg8 = *ptmpreg8;
  1451.       /* To avoid GCC warning */
  1452.       UNUSED(tmpreg8);
  1453.  
  1454.       if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
  1455.       {
  1456.         if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
  1457.         {
  1458.           /* Error on the CRC reception */
  1459.           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  1460.           errorcode = HAL_TIMEOUT;
  1461.           goto error;
  1462.         }
  1463.         /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
  1464.         tmpreg8 = *ptmpreg8;
  1465.         /* To avoid GCC warning */
  1466.         UNUSED(tmpreg8);
  1467.       }
  1468.     }
  1469.   }
  1470.  
  1471.   /* Check if CRC error occurred */
  1472.   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
  1473.   {
  1474.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  1475.     /* Clear CRC Flag */
  1476.     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
  1477.  
  1478.     errorcode = HAL_ERROR;
  1479.   }
  1480. #endif /* USE_SPI_CRC */
  1481.  
  1482.   /* Check the end of the transaction */
  1483.   if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
  1484.   {
  1485.     errorcode = HAL_ERROR;
  1486.     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
  1487.   }
  1488.  
  1489. error :
  1490.   hspi->State = HAL_SPI_STATE_READY;
  1491.   __HAL_UNLOCK(hspi);
  1492.   return errorcode;
  1493. }
  1494.  
  1495. /**
  1496.   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
  1497.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  1498.   *               the configuration information for SPI module.
  1499.   * @param  pData pointer to data buffer
  1500.   * @param  Size amount of data to be sent
  1501.   * @retval HAL status
  1502.   */
  1503. HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
  1504. {
  1505.   HAL_StatusTypeDef errorcode = HAL_OK;
  1506.  
  1507.   /* Check Direction parameter */
  1508.   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
  1509.  
  1510.   /* Process Locked */
  1511.   __HAL_LOCK(hspi);
  1512.  
  1513.   if ((pData == NULL) || (Size == 0U))
  1514.   {
  1515.     errorcode = HAL_ERROR;
  1516.     goto error;
  1517.   }
  1518.  
  1519.   if (hspi->State != HAL_SPI_STATE_READY)
  1520.   {
  1521.     errorcode = HAL_BUSY;
  1522.     goto error;
  1523.   }
  1524.  
  1525.   /* Set the transaction information */
  1526.   hspi->State       = HAL_SPI_STATE_BUSY_TX;
  1527.   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
  1528.   hspi->pTxBuffPtr  = (uint8_t *)pData;
  1529.   hspi->TxXferSize  = Size;
  1530.   hspi->TxXferCount = Size;
  1531.  
  1532.   /* Init field not used in handle to zero */
  1533.   hspi->pRxBuffPtr  = (uint8_t *)NULL;
  1534.   hspi->RxXferSize  = 0U;
  1535.   hspi->RxXferCount = 0U;
  1536.   hspi->RxISR       = NULL;
  1537.  
  1538.   /* Set the function for IT treatment */
  1539.   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  1540.   {
  1541.     hspi->TxISR = SPI_TxISR_16BIT;
  1542.   }
  1543.   else
  1544.   {
  1545.     hspi->TxISR = SPI_TxISR_8BIT;
  1546.   }
  1547.  
  1548.   /* Configure communication direction : 1Line */
  1549.   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
  1550.   {
  1551.     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
  1552.     __HAL_SPI_DISABLE(hspi);
  1553.     SPI_1LINE_TX(hspi);
  1554.   }
  1555.  
  1556. #if (USE_SPI_CRC != 0U)
  1557.   /* Reset CRC Calculation */
  1558.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1559.   {
  1560.     SPI_RESET_CRC(hspi);
  1561.   }
  1562. #endif /* USE_SPI_CRC */
  1563.  
  1564.   /* Enable TXE and ERR interrupt */
  1565.   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
  1566.  
  1567.  
  1568.   /* Check if the SPI is already enabled */
  1569.   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  1570.   {
  1571.     /* Enable SPI peripheral */
  1572.     __HAL_SPI_ENABLE(hspi);
  1573.   }
  1574.  
  1575. error :
  1576.   __HAL_UNLOCK(hspi);
  1577.   return errorcode;
  1578. }
  1579.  
  1580. /**
  1581.   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
  1582.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  1583.   *               the configuration information for SPI module.
  1584.   * @param  pData pointer to data buffer
  1585.   * @param  Size amount of data to be sent
  1586.   * @retval HAL status
  1587.   */
  1588. HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
  1589. {
  1590.   HAL_StatusTypeDef errorcode = HAL_OK;
  1591.  
  1592.   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
  1593.   {
  1594.     hspi->State = HAL_SPI_STATE_BUSY_RX;
  1595.     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
  1596.     return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
  1597.   }
  1598.  
  1599.   /* Process Locked */
  1600.   __HAL_LOCK(hspi);
  1601.  
  1602.   if (hspi->State != HAL_SPI_STATE_READY)
  1603.   {
  1604.     errorcode = HAL_BUSY;
  1605.     goto error;
  1606.   }
  1607.  
  1608.   if ((pData == NULL) || (Size == 0U))
  1609.   {
  1610.     errorcode = HAL_ERROR;
  1611.     goto error;
  1612.   }
  1613.  
  1614.   /* Set the transaction information */
  1615.   hspi->State       = HAL_SPI_STATE_BUSY_RX;
  1616.   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
  1617.   hspi->pRxBuffPtr  = (uint8_t *)pData;
  1618.   hspi->RxXferSize  = Size;
  1619.   hspi->RxXferCount = Size;
  1620.  
  1621.   /* Init field not used in handle to zero */
  1622.   hspi->pTxBuffPtr  = (uint8_t *)NULL;
  1623.   hspi->TxXferSize  = 0U;
  1624.   hspi->TxXferCount = 0U;
  1625.   hspi->TxISR       = NULL;
  1626.  
  1627.   /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
  1628.   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  1629.   {
  1630.     /* Set RX Fifo threshold according the reception data length: 16 bit */
  1631.     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1632.     hspi->RxISR = SPI_RxISR_16BIT;
  1633.   }
  1634.   else
  1635.   {
  1636.     /* Set RX Fifo threshold according the reception data length: 8 bit */
  1637.     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1638.     hspi->RxISR = SPI_RxISR_8BIT;
  1639.   }
  1640.  
  1641.   /* Configure communication direction : 1Line */
  1642.   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
  1643.   {
  1644.     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
  1645.     __HAL_SPI_DISABLE(hspi);
  1646.     SPI_1LINE_RX(hspi);
  1647.   }
  1648.  
  1649. #if (USE_SPI_CRC != 0U)
  1650.   /* Reset CRC Calculation */
  1651.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1652.   {
  1653.     hspi->CRCSize = 1U;
  1654.     if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
  1655.     {
  1656.       hspi->CRCSize = 2U;
  1657.     }
  1658.     SPI_RESET_CRC(hspi);
  1659.   }
  1660.   else
  1661.   {
  1662.     hspi->CRCSize = 0U;
  1663.   }
  1664. #endif /* USE_SPI_CRC */
  1665.  
  1666.   /* Enable TXE and ERR interrupt */
  1667.   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
  1668.  
  1669.   /* Note : The SPI must be enabled after unlocking current process
  1670.             to avoid the risk of SPI interrupt handle execution before current
  1671.             process unlock */
  1672.  
  1673.   /* Check if the SPI is already enabled */
  1674.   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  1675.   {
  1676.     /* Enable SPI peripheral */
  1677.     __HAL_SPI_ENABLE(hspi);
  1678.   }
  1679.  
  1680. error :
  1681.   /* Process Unlocked */
  1682.   __HAL_UNLOCK(hspi);
  1683.   return errorcode;
  1684. }
  1685.  
  1686. /**
  1687.   * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
  1688.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  1689.   *               the configuration information for SPI module.
  1690.   * @param  pTxData pointer to transmission data buffer
  1691.   * @param  pRxData pointer to reception data buffer
  1692.   * @param  Size amount of data to be sent and received
  1693.   * @retval HAL status
  1694.   */
  1695. HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
  1696. {
  1697.   uint32_t             tmp_mode;
  1698.   HAL_SPI_StateTypeDef tmp_state;
  1699.   HAL_StatusTypeDef    errorcode = HAL_OK;
  1700.  
  1701.   /* Check Direction parameter */
  1702.   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
  1703.  
  1704.   /* Process locked */
  1705.   __HAL_LOCK(hspi);
  1706.  
  1707.   /* Init temporary variables */
  1708.   tmp_state           = hspi->State;
  1709.   tmp_mode            = hspi->Init.Mode;
  1710.  
  1711.   if (!((tmp_state == HAL_SPI_STATE_READY) || \
  1712.         ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
  1713.   {
  1714.     errorcode = HAL_BUSY;
  1715.     goto error;
  1716.   }
  1717.  
  1718.   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
  1719.   {
  1720.     errorcode = HAL_ERROR;
  1721.     goto error;
  1722.   }
  1723.  
  1724.   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
  1725.   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
  1726.   {
  1727.     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
  1728.   }
  1729.  
  1730.   /* Set the transaction information */
  1731.   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
  1732.   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
  1733.   hspi->TxXferSize  = Size;
  1734.   hspi->TxXferCount = Size;
  1735.   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
  1736.   hspi->RxXferSize  = Size;
  1737.   hspi->RxXferCount = Size;
  1738.  
  1739.   /* Set the function for IT treatment */
  1740.   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  1741.   {
  1742.     hspi->RxISR     = SPI_2linesRxISR_16BIT;
  1743.     hspi->TxISR     = SPI_2linesTxISR_16BIT;
  1744.   }
  1745.   else
  1746.   {
  1747.     hspi->RxISR     = SPI_2linesRxISR_8BIT;
  1748.     hspi->TxISR     = SPI_2linesTxISR_8BIT;
  1749.   }
  1750.  
  1751. #if (USE_SPI_CRC != 0U)
  1752.   /* Reset CRC Calculation */
  1753.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1754.   {
  1755.     hspi->CRCSize = 1U;
  1756.     if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
  1757.     {
  1758.       hspi->CRCSize = 2U;
  1759.     }
  1760.     SPI_RESET_CRC(hspi);
  1761.   }
  1762.   else
  1763.   {
  1764.     hspi->CRCSize = 0U;
  1765.   }
  1766. #endif /* USE_SPI_CRC */
  1767.  
  1768.   /* Check if packing mode is enabled and if there is more than 2 data to receive */
  1769.   if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
  1770.   {
  1771.     /* Set RX Fifo threshold according the reception data length: 16 bit */
  1772.     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1773.   }
  1774.   else
  1775.   {
  1776.     /* Set RX Fifo threshold according the reception data length: 8 bit */
  1777.     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  1778.   }
  1779.  
  1780.   /* Enable TXE, RXNE and ERR interrupt */
  1781.   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
  1782.  
  1783.   /* Check if the SPI is already enabled */
  1784.   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  1785.   {
  1786.     /* Enable SPI peripheral */
  1787.     __HAL_SPI_ENABLE(hspi);
  1788.   }
  1789.  
  1790. error :
  1791.   /* Process Unlocked */
  1792.   __HAL_UNLOCK(hspi);
  1793.   return errorcode;
  1794. }
  1795.  
  1796. /**
  1797.   * @brief  Transmit an amount of data in non-blocking mode with DMA.
  1798.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  1799.   *               the configuration information for SPI module.
  1800.   * @param  pData pointer to data buffer
  1801.   * @param  Size amount of data to be sent
  1802.   * @retval HAL status
  1803.   */
  1804. HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
  1805. {
  1806.   HAL_StatusTypeDef errorcode = HAL_OK;
  1807.  
  1808.   /* Check tx dma handle */
  1809.   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
  1810.  
  1811.   /* Check Direction parameter */
  1812.   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
  1813.  
  1814.   /* Process Locked */
  1815.   __HAL_LOCK(hspi);
  1816.  
  1817.   if (hspi->State != HAL_SPI_STATE_READY)
  1818.   {
  1819.     errorcode = HAL_BUSY;
  1820.     goto error;
  1821.   }
  1822.  
  1823.   if ((pData == NULL) || (Size == 0U))
  1824.   {
  1825.     errorcode = HAL_ERROR;
  1826.     goto error;
  1827.   }
  1828.  
  1829.   /* Set the transaction information */
  1830.   hspi->State       = HAL_SPI_STATE_BUSY_TX;
  1831.   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
  1832.   hspi->pTxBuffPtr  = (uint8_t *)pData;
  1833.   hspi->TxXferSize  = Size;
  1834.   hspi->TxXferCount = Size;
  1835.  
  1836.   /* Init field not used in handle to zero */
  1837.   hspi->pRxBuffPtr  = (uint8_t *)NULL;
  1838.   hspi->TxISR       = NULL;
  1839.   hspi->RxISR       = NULL;
  1840.   hspi->RxXferSize  = 0U;
  1841.   hspi->RxXferCount = 0U;
  1842.  
  1843.   /* Configure communication direction : 1Line */
  1844.   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
  1845.   {
  1846.     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
  1847.     __HAL_SPI_DISABLE(hspi);
  1848.     SPI_1LINE_TX(hspi);
  1849.   }
  1850.  
  1851. #if (USE_SPI_CRC != 0U)
  1852.   /* Reset CRC Calculation */
  1853.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1854.   {
  1855.     SPI_RESET_CRC(hspi);
  1856.   }
  1857. #endif /* USE_SPI_CRC */
  1858.  
  1859.   /* Set the SPI TxDMA Half transfer complete callback */
  1860.   hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
  1861.  
  1862.   /* Set the SPI TxDMA transfer complete callback */
  1863.   hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
  1864.  
  1865.   /* Set the DMA error callback */
  1866.   hspi->hdmatx->XferErrorCallback = SPI_DMAError;
  1867.  
  1868.   /* Set the DMA AbortCpltCallback */
  1869.   hspi->hdmatx->XferAbortCallback = NULL;
  1870.  
  1871.   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
  1872.   /* Packing mode is enabled only if the DMA setting is HALWORD */
  1873.   if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
  1874.   {
  1875.     /* Check the even/odd of the data size + crc if enabled */
  1876.     if ((hspi->TxXferCount & 0x1U) == 0U)
  1877.     {
  1878.       CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
  1879.       hspi->TxXferCount = (hspi->TxXferCount >> 1U);
  1880.     }
  1881.     else
  1882.     {
  1883.       SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
  1884.       hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
  1885.     }
  1886.   }
  1887.  
  1888.   /* Enable the Tx DMA Stream/Channel */
  1889.   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
  1890.                                  hspi->TxXferCount))
  1891.   {
  1892.     /* Update SPI error code */
  1893.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
  1894.     errorcode = HAL_ERROR;
  1895.  
  1896.     hspi->State = HAL_SPI_STATE_READY;
  1897.     goto error;
  1898.   }
  1899.  
  1900.   /* Check if the SPI is already enabled */
  1901.   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  1902.   {
  1903.     /* Enable SPI peripheral */
  1904.     __HAL_SPI_ENABLE(hspi);
  1905.   }
  1906.  
  1907.   /* Enable the SPI Error Interrupt Bit */
  1908.   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
  1909.  
  1910.   /* Enable Tx DMA Request */
  1911.   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
  1912.  
  1913. error :
  1914.   /* Process Unlocked */
  1915.   __HAL_UNLOCK(hspi);
  1916.   return errorcode;
  1917. }
  1918.  
  1919. /**
  1920.   * @brief  Receive an amount of data in non-blocking mode with DMA.
  1921.   * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
  1922.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  1923.   *               the configuration information for SPI module.
  1924.   * @param  pData pointer to data buffer
  1925.   * @note   When the CRC feature is enabled the pData Length must be Size + 1.
  1926.   * @param  Size amount of data to be sent
  1927.   * @retval HAL status
  1928.   */
  1929. HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
  1930. {
  1931.   HAL_StatusTypeDef errorcode = HAL_OK;
  1932.  
  1933.   /* Check rx dma handle */
  1934.   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
  1935.  
  1936.   if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
  1937.   {
  1938.     hspi->State = HAL_SPI_STATE_BUSY_RX;
  1939.  
  1940.     /* Check tx dma handle */
  1941.     assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
  1942.  
  1943.     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
  1944.     return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
  1945.   }
  1946.  
  1947.   /* Process Locked */
  1948.   __HAL_LOCK(hspi);
  1949.  
  1950.   if (hspi->State != HAL_SPI_STATE_READY)
  1951.   {
  1952.     errorcode = HAL_BUSY;
  1953.     goto error;
  1954.   }
  1955.  
  1956.   if ((pData == NULL) || (Size == 0U))
  1957.   {
  1958.     errorcode = HAL_ERROR;
  1959.     goto error;
  1960.   }
  1961.  
  1962.   /* Set the transaction information */
  1963.   hspi->State       = HAL_SPI_STATE_BUSY_RX;
  1964.   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
  1965.   hspi->pRxBuffPtr  = (uint8_t *)pData;
  1966.   hspi->RxXferSize  = Size;
  1967.   hspi->RxXferCount = Size;
  1968.  
  1969.   /*Init field not used in handle to zero */
  1970.   hspi->RxISR       = NULL;
  1971.   hspi->TxISR       = NULL;
  1972.   hspi->TxXferSize  = 0U;
  1973.   hspi->TxXferCount = 0U;
  1974.  
  1975.   /* Configure communication direction : 1Line */
  1976.   if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
  1977.   {
  1978.     /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
  1979.     __HAL_SPI_DISABLE(hspi);
  1980.     SPI_1LINE_RX(hspi);
  1981.   }
  1982.  
  1983. #if (USE_SPI_CRC != 0U)
  1984.   /* Reset CRC Calculation */
  1985.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  1986.   {
  1987.     SPI_RESET_CRC(hspi);
  1988.   }
  1989. #endif /* USE_SPI_CRC */
  1990.  
  1991. #if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6)|| defined (STM32F038xx) || defined (STM32F051x8) || defined (STM32F058xx)
  1992.   /* Packing mode management is enabled by the DMA settings */
  1993.   if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
  1994.   {
  1995.     /* Restriction the DMA data received is not allowed in this mode */
  1996.     errorcode = HAL_ERROR;
  1997.     goto error;
  1998.   }
  1999. #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F058xx */
  2000.  
  2001.   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
  2002.   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  2003.   {
  2004.     /* Set RX Fifo threshold according the reception data length: 16bit */
  2005.     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  2006.   }
  2007.   else
  2008.   {
  2009.     /* Set RX Fifo threshold according the reception data length: 8bit */
  2010.     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  2011.  
  2012.     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
  2013.     {
  2014.       /* Set RX Fifo threshold according the reception data length: 16bit */
  2015.       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  2016.  
  2017.       if ((hspi->RxXferCount & 0x1U) == 0x0U)
  2018.       {
  2019.         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
  2020.         hspi->RxXferCount = hspi->RxXferCount >> 1U;
  2021.       }
  2022.       else
  2023.       {
  2024.         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
  2025.         hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
  2026.       }
  2027.     }
  2028.   }
  2029.  
  2030.   /* Set the SPI RxDMA Half transfer complete callback */
  2031.   hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
  2032.  
  2033.   /* Set the SPI Rx DMA transfer complete callback */
  2034.   hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
  2035.  
  2036.   /* Set the DMA error callback */
  2037.   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
  2038.  
  2039.   /* Set the DMA AbortCpltCallback */
  2040.   hspi->hdmarx->XferAbortCallback = NULL;
  2041.  
  2042.   /* Enable the Rx DMA Stream/Channel  */
  2043.   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
  2044.                                  hspi->RxXferCount))
  2045.   {
  2046.     /* Update SPI error code */
  2047.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
  2048.     errorcode = HAL_ERROR;
  2049.  
  2050.     hspi->State = HAL_SPI_STATE_READY;
  2051.     goto error;
  2052.   }
  2053.  
  2054.   /* Check if the SPI is already enabled */
  2055.   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  2056.   {
  2057.     /* Enable SPI peripheral */
  2058.     __HAL_SPI_ENABLE(hspi);
  2059.   }
  2060.  
  2061.   /* Enable the SPI Error Interrupt Bit */
  2062.   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
  2063.  
  2064.   /* Enable Rx DMA Request */
  2065.   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
  2066.  
  2067. error:
  2068.   /* Process Unlocked */
  2069.   __HAL_UNLOCK(hspi);
  2070.   return errorcode;
  2071. }
  2072.  
  2073. /**
  2074.   * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
  2075.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  2076.   *               the configuration information for SPI module.
  2077.   * @param  pTxData pointer to transmission data buffer
  2078.   * @param  pRxData pointer to reception data buffer
  2079.   * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
  2080.   * @param  Size amount of data to be sent
  2081.   * @retval HAL status
  2082.   */
  2083. HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
  2084.                                               uint16_t Size)
  2085. {
  2086.   uint32_t             tmp_mode;
  2087.   HAL_SPI_StateTypeDef tmp_state;
  2088.   HAL_StatusTypeDef errorcode = HAL_OK;
  2089.  
  2090.   /* Check rx & tx dma handles */
  2091.   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
  2092.   assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
  2093.  
  2094.   /* Check Direction parameter */
  2095.   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
  2096.  
  2097.   /* Process locked */
  2098.   __HAL_LOCK(hspi);
  2099.  
  2100.   /* Init temporary variables */
  2101.   tmp_state           = hspi->State;
  2102.   tmp_mode            = hspi->Init.Mode;
  2103.  
  2104.   if (!((tmp_state == HAL_SPI_STATE_READY) ||
  2105.         ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
  2106.   {
  2107.     errorcode = HAL_BUSY;
  2108.     goto error;
  2109.   }
  2110.  
  2111.   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
  2112.   {
  2113.     errorcode = HAL_ERROR;
  2114.     goto error;
  2115.   }
  2116.  
  2117.   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
  2118.   if (hspi->State != HAL_SPI_STATE_BUSY_RX)
  2119.   {
  2120.     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
  2121.   }
  2122.  
  2123.   /* Set the transaction information */
  2124.   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
  2125.   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
  2126.   hspi->TxXferSize  = Size;
  2127.   hspi->TxXferCount = Size;
  2128.   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
  2129.   hspi->RxXferSize  = Size;
  2130.   hspi->RxXferCount = Size;
  2131.  
  2132.   /* Init field not used in handle to zero */
  2133.   hspi->RxISR       = NULL;
  2134.   hspi->TxISR       = NULL;
  2135.  
  2136. #if (USE_SPI_CRC != 0U)
  2137.   /* Reset CRC Calculation */
  2138.   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  2139.   {
  2140.     SPI_RESET_CRC(hspi);
  2141.   }
  2142. #endif /* USE_SPI_CRC */
  2143.  
  2144. #if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F051x8) || defined (STM32F058xx)
  2145.   /* Packing mode management is enabled by the DMA settings */
  2146.   if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
  2147.   {
  2148.     /* Restriction the DMA data received is not allowed in this mode */
  2149.     errorcode = HAL_ERROR;
  2150.     goto error;
  2151.   }
  2152. #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F058xx */
  2153.  
  2154.   /* Reset the threshold bit */
  2155.   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
  2156.  
  2157.   /* The packing mode management is enabled by the DMA settings according the spi data size */
  2158.   if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  2159.   {
  2160.     /* Set fiforxthreshold according the reception data length: 16bit */
  2161.     CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  2162.   }
  2163.   else
  2164.   {
  2165.     /* Set RX Fifo threshold according the reception data length: 8bit */
  2166.     SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  2167.  
  2168.     if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
  2169.     {
  2170.       if ((hspi->TxXferSize & 0x1U) == 0x0U)
  2171.       {
  2172.         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
  2173.         hspi->TxXferCount = hspi->TxXferCount >> 1U;
  2174.       }
  2175.       else
  2176.       {
  2177.         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
  2178.         hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
  2179.       }
  2180.     }
  2181.  
  2182.     if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
  2183.     {
  2184.       /* Set RX Fifo threshold according the reception data length: 16bit */
  2185.       CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  2186.  
  2187.       if ((hspi->RxXferCount & 0x1U) == 0x0U)
  2188.       {
  2189.         CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
  2190.         hspi->RxXferCount = hspi->RxXferCount >> 1U;
  2191.       }
  2192.       else
  2193.       {
  2194.         SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
  2195.         hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
  2196.       }
  2197.     }
  2198.   }
  2199.  
  2200.   /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
  2201.   if (hspi->State == HAL_SPI_STATE_BUSY_RX)
  2202.   {
  2203.     /* Set the SPI Rx DMA Half transfer complete callback */
  2204.     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
  2205.     hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
  2206.   }
  2207.   else
  2208.   {
  2209.     /* Set the SPI Tx/Rx DMA Half transfer complete callback */
  2210.     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
  2211.     hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
  2212.   }
  2213.  
  2214.   /* Set the DMA error callback */
  2215.   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
  2216.  
  2217.   /* Set the DMA AbortCpltCallback */
  2218.   hspi->hdmarx->XferAbortCallback = NULL;
  2219.  
  2220.   /* Enable the Rx DMA Stream/Channel  */
  2221.   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
  2222.                                  hspi->RxXferCount))
  2223.   {
  2224.     /* Update SPI error code */
  2225.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
  2226.     errorcode = HAL_ERROR;
  2227.  
  2228.     hspi->State = HAL_SPI_STATE_READY;
  2229.     goto error;
  2230.   }
  2231.  
  2232.   /* Enable Rx DMA Request */
  2233.   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
  2234.  
  2235.   /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
  2236.   is performed in DMA reception complete callback  */
  2237.   hspi->hdmatx->XferHalfCpltCallback = NULL;
  2238.   hspi->hdmatx->XferCpltCallback     = NULL;
  2239.   hspi->hdmatx->XferErrorCallback    = NULL;
  2240.   hspi->hdmatx->XferAbortCallback    = NULL;
  2241.  
  2242.   /* Enable the Tx DMA Stream/Channel  */
  2243.   if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
  2244.                                  hspi->TxXferCount))
  2245.   {
  2246.     /* Update SPI error code */
  2247.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
  2248.     errorcode = HAL_ERROR;
  2249.  
  2250.     hspi->State = HAL_SPI_STATE_READY;
  2251.     goto error;
  2252.   }
  2253.  
  2254.   /* Check if the SPI is already enabled */
  2255.   if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  2256.   {
  2257.     /* Enable SPI peripheral */
  2258.     __HAL_SPI_ENABLE(hspi);
  2259.   }
  2260.   /* Enable the SPI Error Interrupt Bit */
  2261.   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
  2262.  
  2263.   /* Enable Tx DMA Request */
  2264.   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
  2265.  
  2266. error :
  2267.   /* Process Unlocked */
  2268.   __HAL_UNLOCK(hspi);
  2269.   return errorcode;
  2270. }
  2271.  
  2272. /**
  2273.   * @brief  Abort ongoing transfer (blocking mode).
  2274.   * @param  hspi SPI handle.
  2275.   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
  2276.   *         started in Interrupt or DMA mode.
  2277.   *         This procedure performs following operations :
  2278.   *           - Disable SPI Interrupts (depending of transfer direction)
  2279.   *           - Disable the DMA transfer in the peripheral register (if enabled)
  2280.   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  2281.   *           - Set handle State to READY
  2282.   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
  2283.   * @retval HAL status
  2284.   */
  2285. HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
  2286. {
  2287.   HAL_StatusTypeDef errorcode;
  2288.   __IO uint32_t count;
  2289.   __IO uint32_t resetcount;
  2290.  
  2291.   /* Initialized local variable  */
  2292.   errorcode = HAL_OK;
  2293.   resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
  2294.   count = resetcount;
  2295.  
  2296.   /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
  2297.   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
  2298.  
  2299.   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
  2300.   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
  2301.   {
  2302.     hspi->TxISR = SPI_AbortTx_ISR;
  2303.     /* Wait HAL_SPI_STATE_ABORT state */
  2304.     do
  2305.     {
  2306.       if (count == 0U)
  2307.       {
  2308.         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  2309.         break;
  2310.       }
  2311.       count--;
  2312.     } while (hspi->State != HAL_SPI_STATE_ABORT);
  2313.     /* Reset Timeout Counter */
  2314.     count = resetcount;
  2315.   }
  2316.  
  2317.   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
  2318.   {
  2319.     hspi->RxISR = SPI_AbortRx_ISR;
  2320.     /* Wait HAL_SPI_STATE_ABORT state */
  2321.     do
  2322.     {
  2323.       if (count == 0U)
  2324.       {
  2325.         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  2326.         break;
  2327.       }
  2328.       count--;
  2329.     } while (hspi->State != HAL_SPI_STATE_ABORT);
  2330.     /* Reset Timeout Counter */
  2331.     count = resetcount;
  2332.   }
  2333.  
  2334.   /* Disable the SPI DMA Tx request if enabled */
  2335.   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
  2336.   {
  2337.     /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
  2338.     if (hspi->hdmatx != NULL)
  2339.     {
  2340.       /* Set the SPI DMA Abort callback :
  2341.       will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
  2342.       hspi->hdmatx->XferAbortCallback = NULL;
  2343.  
  2344.       /* Abort DMA Tx Handle linked to SPI Peripheral */
  2345.       if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
  2346.       {
  2347.         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  2348.       }
  2349.  
  2350.       /* Disable Tx DMA Request */
  2351.       CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
  2352.  
  2353.       if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  2354.       {
  2355.         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  2356.       }
  2357.  
  2358.       /* Disable SPI Peripheral */
  2359.       __HAL_SPI_DISABLE(hspi);
  2360.  
  2361.       /* Empty the FRLVL fifo */
  2362.       if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  2363.       {
  2364.         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  2365.       }
  2366.     }
  2367.   }
  2368.  
  2369.   /* Disable the SPI DMA Rx request if enabled */
  2370.   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
  2371.   {
  2372.     /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
  2373.     if (hspi->hdmarx != NULL)
  2374.     {
  2375.       /* Set the SPI DMA Abort callback :
  2376.       will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
  2377.       hspi->hdmarx->XferAbortCallback = NULL;
  2378.  
  2379.       /* Abort DMA Rx Handle linked to SPI Peripheral */
  2380.       if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
  2381.       {
  2382.         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  2383.       }
  2384.  
  2385.       /* Disable peripheral */
  2386.       __HAL_SPI_DISABLE(hspi);
  2387.  
  2388.       /* Control the BSY flag */
  2389.       if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  2390.       {
  2391.         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  2392.       }
  2393.  
  2394.       /* Empty the FRLVL fifo */
  2395.       if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  2396.       {
  2397.         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  2398.       }
  2399.  
  2400.       /* Disable Rx DMA Request */
  2401.       CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
  2402.     }
  2403.   }
  2404.   /* Reset Tx and Rx transfer counters */
  2405.   hspi->RxXferCount = 0U;
  2406.   hspi->TxXferCount = 0U;
  2407.  
  2408.   /* Check error during Abort procedure */
  2409.   if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
  2410.   {
  2411.     /* return HAL_Error in case of error during Abort procedure */
  2412.     errorcode = HAL_ERROR;
  2413.   }
  2414.   else
  2415.   {
  2416.     /* Reset errorCode */
  2417.     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  2418.   }
  2419.  
  2420.   /* Clear the Error flags in the SR register */
  2421.   __HAL_SPI_CLEAR_OVRFLAG(hspi);
  2422.   __HAL_SPI_CLEAR_FREFLAG(hspi);
  2423.  
  2424.   /* Restore hspi->state to ready */
  2425.   hspi->State = HAL_SPI_STATE_READY;
  2426.  
  2427.   return errorcode;
  2428. }
  2429.  
  2430. /**
  2431.   * @brief  Abort ongoing transfer (Interrupt mode).
  2432.   * @param  hspi SPI handle.
  2433.   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
  2434.   *         started in Interrupt or DMA mode.
  2435.   *         This procedure performs following operations :
  2436.   *           - Disable SPI Interrupts (depending of transfer direction)
  2437.   *           - Disable the DMA transfer in the peripheral register (if enabled)
  2438.   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  2439.   *           - Set handle State to READY
  2440.   *           - At abort completion, call user abort complete callback
  2441.   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
  2442.   *         considered as completed only when user abort complete callback is executed (not when exiting function).
  2443.   * @retval HAL status
  2444.   */
  2445. HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
  2446. {
  2447.   HAL_StatusTypeDef errorcode;
  2448.   uint32_t abortcplt ;
  2449.   __IO uint32_t count;
  2450.   __IO uint32_t resetcount;
  2451.  
  2452.   /* Initialized local variable  */
  2453.   errorcode = HAL_OK;
  2454.   abortcplt = 1U;
  2455.   resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
  2456.   count = resetcount;
  2457.  
  2458.   /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
  2459.   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
  2460.  
  2461.   /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
  2462.   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
  2463.   {
  2464.     hspi->TxISR = SPI_AbortTx_ISR;
  2465.     /* Wait HAL_SPI_STATE_ABORT state */
  2466.     do
  2467.     {
  2468.       if (count == 0U)
  2469.       {
  2470.         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  2471.         break;
  2472.       }
  2473.       count--;
  2474.     } while (hspi->State != HAL_SPI_STATE_ABORT);
  2475.     /* Reset Timeout Counter */
  2476.     count = resetcount;
  2477.   }
  2478.  
  2479.   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
  2480.   {
  2481.     hspi->RxISR = SPI_AbortRx_ISR;
  2482.     /* Wait HAL_SPI_STATE_ABORT state */
  2483.     do
  2484.     {
  2485.       if (count == 0U)
  2486.       {
  2487.         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  2488.         break;
  2489.       }
  2490.       count--;
  2491.     } while (hspi->State != HAL_SPI_STATE_ABORT);
  2492.     /* Reset Timeout Counter */
  2493.     count = resetcount;
  2494.   }
  2495.  
  2496.   /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
  2497.      before any call to DMA Abort functions */
  2498.   /* DMA Tx Handle is valid */
  2499.   if (hspi->hdmatx != NULL)
  2500.   {
  2501.     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
  2502.        Otherwise, set it to NULL */
  2503.     if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
  2504.     {
  2505.       hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
  2506.     }
  2507.     else
  2508.     {
  2509.       hspi->hdmatx->XferAbortCallback = NULL;
  2510.     }
  2511.   }
  2512.   /* DMA Rx Handle is valid */
  2513.   if (hspi->hdmarx != NULL)
  2514.   {
  2515.     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
  2516.        Otherwise, set it to NULL */
  2517.     if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
  2518.     {
  2519.       hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
  2520.     }
  2521.     else
  2522.     {
  2523.       hspi->hdmarx->XferAbortCallback = NULL;
  2524.     }
  2525.   }
  2526.  
  2527.   /* Disable the SPI DMA Tx request if enabled */
  2528.   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
  2529.   {
  2530.     /* Abort the SPI DMA Tx Stream/Channel */
  2531.     if (hspi->hdmatx != NULL)
  2532.     {
  2533.       /* Abort DMA Tx Handle linked to SPI Peripheral */
  2534.       if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
  2535.       {
  2536.         hspi->hdmatx->XferAbortCallback = NULL;
  2537.         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  2538.       }
  2539.       else
  2540.       {
  2541.         abortcplt = 0U;
  2542.       }
  2543.     }
  2544.   }
  2545.   /* Disable the SPI DMA Rx request if enabled */
  2546.   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
  2547.   {
  2548.     /* Abort the SPI DMA Rx Stream/Channel */
  2549.     if (hspi->hdmarx != NULL)
  2550.     {
  2551.       /* Abort DMA Rx Handle linked to SPI Peripheral */
  2552.       if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
  2553.       {
  2554.         hspi->hdmarx->XferAbortCallback = NULL;
  2555.         hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  2556.       }
  2557.       else
  2558.       {
  2559.         abortcplt = 0U;
  2560.       }
  2561.     }
  2562.   }
  2563.  
  2564.   if (abortcplt == 1U)
  2565.   {
  2566.     /* Reset Tx and Rx transfer counters */
  2567.     hspi->RxXferCount = 0U;
  2568.     hspi->TxXferCount = 0U;
  2569.  
  2570.     /* Check error during Abort procedure */
  2571.     if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
  2572.     {
  2573.       /* return HAL_Error in case of error during Abort procedure */
  2574.       errorcode = HAL_ERROR;
  2575.     }
  2576.     else
  2577.     {
  2578.       /* Reset errorCode */
  2579.       hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  2580.     }
  2581.  
  2582.     /* Clear the Error flags in the SR register */
  2583.     __HAL_SPI_CLEAR_OVRFLAG(hspi);
  2584.     __HAL_SPI_CLEAR_FREFLAG(hspi);
  2585.  
  2586.     /* Restore hspi->State to Ready */
  2587.     hspi->State = HAL_SPI_STATE_READY;
  2588.  
  2589.     /* As no DMA to be aborted, call directly user Abort complete callback */
  2590. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  2591.     hspi->AbortCpltCallback(hspi);
  2592. #else
  2593.     HAL_SPI_AbortCpltCallback(hspi);
  2594. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  2595.   }
  2596.  
  2597.   return errorcode;
  2598. }
  2599.  
  2600. /**
  2601.   * @brief  Pause the DMA Transfer.
  2602.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  2603.   *               the configuration information for the specified SPI module.
  2604.   * @retval HAL status
  2605.   */
  2606. HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
  2607. {
  2608.   /* Process Locked */
  2609.   __HAL_LOCK(hspi);
  2610.  
  2611.   /* Disable the SPI DMA Tx & Rx requests */
  2612.   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
  2613.  
  2614.   /* Process Unlocked */
  2615.   __HAL_UNLOCK(hspi);
  2616.  
  2617.   return HAL_OK;
  2618. }
  2619.  
  2620. /**
  2621.   * @brief  Resume the DMA Transfer.
  2622.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  2623.   *               the configuration information for the specified SPI module.
  2624.   * @retval HAL status
  2625.   */
  2626. HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
  2627. {
  2628.   /* Process Locked */
  2629.   __HAL_LOCK(hspi);
  2630.  
  2631.   /* Enable the SPI DMA Tx & Rx requests */
  2632.   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
  2633.  
  2634.   /* Process Unlocked */
  2635.   __HAL_UNLOCK(hspi);
  2636.  
  2637.   return HAL_OK;
  2638. }
  2639.  
  2640. /**
  2641.   * @brief  Stop the DMA Transfer.
  2642.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  2643.   *               the configuration information for the specified SPI module.
  2644.   * @retval HAL status
  2645.   */
  2646. HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
  2647. {
  2648.   HAL_StatusTypeDef errorcode = HAL_OK;
  2649.   /* The Lock is not implemented on this API to allow the user application
  2650.      to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
  2651.      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
  2652.      and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
  2653.      */
  2654.  
  2655.   /* Abort the SPI DMA tx Stream/Channel  */
  2656.   if (hspi->hdmatx != NULL)
  2657.   {
  2658.     if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
  2659.     {
  2660.       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
  2661.       errorcode = HAL_ERROR;
  2662.     }
  2663.   }
  2664.   /* Abort the SPI DMA rx Stream/Channel  */
  2665.   if (hspi->hdmarx != NULL)
  2666.   {
  2667.     if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
  2668.     {
  2669.       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
  2670.       errorcode = HAL_ERROR;
  2671.     }
  2672.   }
  2673.  
  2674.   /* Disable the SPI DMA Tx & Rx requests */
  2675.   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
  2676.   hspi->State = HAL_SPI_STATE_READY;
  2677.   return errorcode;
  2678. }
  2679.  
  2680. /**
  2681.   * @brief  Handle SPI interrupt request.
  2682.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  2683.   *               the configuration information for the specified SPI module.
  2684.   * @retval None
  2685.   */
  2686. void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
  2687. {
  2688.   uint32_t itsource = hspi->Instance->CR2;
  2689.   uint32_t itflag   = hspi->Instance->SR;
  2690.  
  2691.   /* SPI in mode Receiver ----------------------------------------------------*/
  2692.   if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
  2693.       (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
  2694.   {
  2695.     hspi->RxISR(hspi);
  2696.     return;
  2697.   }
  2698.  
  2699.   /* SPI in mode Transmitter -------------------------------------------------*/
  2700.   if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
  2701.   {
  2702.     hspi->TxISR(hspi);
  2703.     return;
  2704.   }
  2705.  
  2706.   /* SPI in Error Treatment --------------------------------------------------*/
  2707.   if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
  2708.        || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
  2709.   {
  2710.     /* SPI Overrun error interrupt occurred ----------------------------------*/
  2711.     if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
  2712.     {
  2713.       if (hspi->State != HAL_SPI_STATE_BUSY_TX)
  2714.       {
  2715.         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
  2716.         __HAL_SPI_CLEAR_OVRFLAG(hspi);
  2717.       }
  2718.       else
  2719.       {
  2720.         __HAL_SPI_CLEAR_OVRFLAG(hspi);
  2721.         return;
  2722.       }
  2723.     }
  2724.  
  2725.     /* SPI Mode Fault error interrupt occurred -------------------------------*/
  2726.     if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
  2727.     {
  2728.       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
  2729.       __HAL_SPI_CLEAR_MODFFLAG(hspi);
  2730.     }
  2731.  
  2732.     /* SPI Frame error interrupt occurred ------------------------------------*/
  2733.     if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
  2734.     {
  2735.       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
  2736.       __HAL_SPI_CLEAR_FREFLAG(hspi);
  2737.     }
  2738.  
  2739.     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  2740.     {
  2741.       /* Disable all interrupts */
  2742.       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
  2743.  
  2744.       hspi->State = HAL_SPI_STATE_READY;
  2745.       /* Disable the SPI DMA requests if enabled */
  2746.       if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
  2747.       {
  2748.         CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
  2749.  
  2750.         /* Abort the SPI DMA Rx channel */
  2751.         if (hspi->hdmarx != NULL)
  2752.         {
  2753.           /* Set the SPI DMA Abort callback :
  2754.           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
  2755.           hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
  2756.           if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
  2757.           {
  2758.             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  2759.           }
  2760.         }
  2761.         /* Abort the SPI DMA Tx channel */
  2762.         if (hspi->hdmatx != NULL)
  2763.         {
  2764.           /* Set the SPI DMA Abort callback :
  2765.           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
  2766.           hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
  2767.           if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
  2768.           {
  2769.             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  2770.           }
  2771.         }
  2772.       }
  2773.       else
  2774.       {
  2775.         /* Call user error callback */
  2776. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  2777.         hspi->ErrorCallback(hspi);
  2778. #else
  2779.         HAL_SPI_ErrorCallback(hspi);
  2780. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  2781.       }
  2782.     }
  2783.     return;
  2784.   }
  2785. }
  2786.  
  2787. /**
  2788.   * @brief  Tx Transfer completed callback.
  2789.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  2790.   *               the configuration information for SPI module.
  2791.   * @retval None
  2792.   */
  2793. __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
  2794. {
  2795.   /* Prevent unused argument(s) compilation warning */
  2796.   UNUSED(hspi);
  2797.  
  2798.   /* NOTE : This function should not be modified, when the callback is needed,
  2799.             the HAL_SPI_TxCpltCallback should be implemented in the user file
  2800.    */
  2801. }
  2802.  
  2803. /**
  2804.   * @brief  Rx Transfer completed callback.
  2805.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  2806.   *               the configuration information for SPI module.
  2807.   * @retval None
  2808.   */
  2809. __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
  2810. {
  2811.   /* Prevent unused argument(s) compilation warning */
  2812.   UNUSED(hspi);
  2813.  
  2814.   /* NOTE : This function should not be modified, when the callback is needed,
  2815.             the HAL_SPI_RxCpltCallback should be implemented in the user file
  2816.    */
  2817. }
  2818.  
  2819. /**
  2820.   * @brief  Tx and Rx Transfer completed callback.
  2821.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  2822.   *               the configuration information for SPI module.
  2823.   * @retval None
  2824.   */
  2825. __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
  2826. {
  2827.   /* Prevent unused argument(s) compilation warning */
  2828.   UNUSED(hspi);
  2829.  
  2830.   /* NOTE : This function should not be modified, when the callback is needed,
  2831.             the HAL_SPI_TxRxCpltCallback should be implemented in the user file
  2832.    */
  2833. }
  2834.  
  2835. /**
  2836.   * @brief  Tx Half Transfer completed callback.
  2837.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  2838.   *               the configuration information for SPI module.
  2839.   * @retval None
  2840.   */
  2841. __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
  2842. {
  2843.   /* Prevent unused argument(s) compilation warning */
  2844.   UNUSED(hspi);
  2845.  
  2846.   /* NOTE : This function should not be modified, when the callback is needed,
  2847.             the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
  2848.    */
  2849. }
  2850.  
  2851. /**
  2852.   * @brief  Rx Half Transfer completed callback.
  2853.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  2854.   *               the configuration information for SPI module.
  2855.   * @retval None
  2856.   */
  2857. __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
  2858. {
  2859.   /* Prevent unused argument(s) compilation warning */
  2860.   UNUSED(hspi);
  2861.  
  2862.   /* NOTE : This function should not be modified, when the callback is needed,
  2863.             the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
  2864.    */
  2865. }
  2866.  
  2867. /**
  2868.   * @brief  Tx and Rx Half Transfer callback.
  2869.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  2870.   *               the configuration information for SPI module.
  2871.   * @retval None
  2872.   */
  2873. __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
  2874. {
  2875.   /* Prevent unused argument(s) compilation warning */
  2876.   UNUSED(hspi);
  2877.  
  2878.   /* NOTE : This function should not be modified, when the callback is needed,
  2879.             the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
  2880.    */
  2881. }
  2882.  
  2883. /**
  2884.   * @brief  SPI error callback.
  2885.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  2886.   *               the configuration information for SPI module.
  2887.   * @retval None
  2888.   */
  2889. __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
  2890. {
  2891.   /* Prevent unused argument(s) compilation warning */
  2892.   UNUSED(hspi);
  2893.  
  2894.   /* NOTE : This function should not be modified, when the callback is needed,
  2895.             the HAL_SPI_ErrorCallback should be implemented in the user file
  2896.    */
  2897.   /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
  2898.             and user can use HAL_SPI_GetError() API to check the latest error occurred
  2899.    */
  2900. }
  2901.  
  2902. /**
  2903.   * @brief  SPI Abort Complete callback.
  2904.   * @param  hspi SPI handle.
  2905.   * @retval None
  2906.   */
  2907. __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
  2908. {
  2909.   /* Prevent unused argument(s) compilation warning */
  2910.   UNUSED(hspi);
  2911.  
  2912.   /* NOTE : This function should not be modified, when the callback is needed,
  2913.             the HAL_SPI_AbortCpltCallback can be implemented in the user file.
  2914.    */
  2915. }
  2916.  
  2917. /**
  2918.   * @}
  2919.   */
  2920.  
  2921. /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
  2922.   * @brief   SPI control functions
  2923.   *
  2924. @verbatim
  2925.  ===============================================================================
  2926.                       ##### Peripheral State and Errors functions #####
  2927.  ===============================================================================
  2928.     [..]
  2929.     This subsection provides a set of functions allowing to control the SPI.
  2930.      (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
  2931.      (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
  2932. @endverbatim
  2933.   * @{
  2934.   */
  2935.  
  2936. /**
  2937.   * @brief  Return the SPI handle state.
  2938.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  2939.   *               the configuration information for SPI module.
  2940.   * @retval SPI state
  2941.   */
  2942. HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
  2943. {
  2944.   /* Return SPI handle state */
  2945.   return hspi->State;
  2946. }
  2947.  
  2948. /**
  2949.   * @brief  Return the SPI error code.
  2950.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  2951.   *               the configuration information for SPI module.
  2952.   * @retval SPI error code in bitmap format
  2953.   */
  2954. uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
  2955. {
  2956.   /* Return SPI ErrorCode */
  2957.   return hspi->ErrorCode;
  2958. }
  2959.  
  2960. /**
  2961.   * @}
  2962.   */
  2963.  
  2964. /**
  2965.   * @}
  2966.   */
  2967.  
  2968. /** @addtogroup SPI_Private_Functions
  2969.   * @brief   Private functions
  2970.   * @{
  2971.   */
  2972.  
  2973. /**
  2974.   * @brief  DMA SPI transmit process complete callback.
  2975.   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
  2976.   *               the configuration information for the specified DMA module.
  2977.   * @retval None
  2978.   */
  2979. static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
  2980. {
  2981.   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
  2982.   uint32_t tickstart;
  2983.  
  2984.   /* Init tickstart for timeout management*/
  2985.   tickstart = HAL_GetTick();
  2986.  
  2987.   /* DMA Normal Mode */
  2988.   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
  2989.   {
  2990.     /* Disable ERR interrupt */
  2991.     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
  2992.  
  2993.     /* Disable Tx DMA Request */
  2994.     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
  2995.  
  2996.     /* Check the end of the transaction */
  2997.     if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  2998.     {
  2999.       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  3000.     }
  3001.  
  3002.     /* Clear overrun flag in 2 Lines communication mode because received data is not read */
  3003.     if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
  3004.     {
  3005.       __HAL_SPI_CLEAR_OVRFLAG(hspi);
  3006.     }
  3007.  
  3008.     hspi->TxXferCount = 0U;
  3009.     hspi->State = HAL_SPI_STATE_READY;
  3010.  
  3011.     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  3012.     {
  3013.       /* Call user error callback */
  3014. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  3015.       hspi->ErrorCallback(hspi);
  3016. #else
  3017.       HAL_SPI_ErrorCallback(hspi);
  3018. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  3019.       return;
  3020.     }
  3021.   }
  3022.   /* Call user Tx complete callback */
  3023. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  3024.   hspi->TxCpltCallback(hspi);
  3025. #else
  3026.   HAL_SPI_TxCpltCallback(hspi);
  3027. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  3028. }
  3029.  
  3030. /**
  3031.   * @brief  DMA SPI receive process complete callback.
  3032.   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
  3033.   *               the configuration information for the specified DMA module.
  3034.   * @retval None
  3035.   */
  3036. static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
  3037. {
  3038.   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
  3039.   uint32_t tickstart;
  3040. #if (USE_SPI_CRC != 0U)
  3041.   __IO uint32_t tmpreg = 0U;
  3042.   __IO uint8_t  * ptmpreg8;
  3043.   __IO uint8_t  tmpreg8 = 0;
  3044. #endif /* USE_SPI_CRC */
  3045.  
  3046.   /* Init tickstart for timeout management*/
  3047.   tickstart = HAL_GetTick();
  3048.  
  3049.   /* DMA Normal Mode */
  3050.   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
  3051.   {
  3052.     /* Disable ERR interrupt */
  3053.     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
  3054.  
  3055. #if (USE_SPI_CRC != 0U)
  3056.     /* CRC handling */
  3057.     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  3058.     {
  3059.       /* Wait until RXNE flag */
  3060.       if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  3061.       {
  3062.         /* Error on the CRC reception */
  3063.         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  3064.       }
  3065.       /* Read CRC */
  3066.       if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
  3067.       {
  3068.         /* Read 16bit CRC */
  3069.         tmpreg = READ_REG(hspi->Instance->DR);
  3070.         /* To avoid GCC warning */
  3071.         UNUSED(tmpreg);
  3072.       }
  3073.       else
  3074.       {
  3075.         /* Initialize the 8bit temporary pointer */
  3076.         ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
  3077.         /* Read 8bit CRC */
  3078.         tmpreg8 = *ptmpreg8;
  3079.         /* To avoid GCC warning */
  3080.         UNUSED(tmpreg8);
  3081.  
  3082.         if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
  3083.         {
  3084.           if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  3085.           {
  3086.             /* Error on the CRC reception */
  3087.             SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  3088.           }
  3089.           /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
  3090.           tmpreg8 = *ptmpreg8;
  3091.           /* To avoid GCC warning */
  3092.           UNUSED(tmpreg8);
  3093.         }
  3094.       }
  3095.     }
  3096. #endif /* USE_SPI_CRC */
  3097.  
  3098.     /* Check if we are in Master RX 2 line mode */
  3099.     if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
  3100.     {
  3101.       /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
  3102.       CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
  3103.     }
  3104.     else
  3105.     {
  3106.       /* Normal case */
  3107.       CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
  3108.     }
  3109.  
  3110.     /* Check the end of the transaction */
  3111.     if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  3112.     {
  3113.       hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
  3114.     }
  3115.  
  3116.     hspi->RxXferCount = 0U;
  3117.     hspi->State = HAL_SPI_STATE_READY;
  3118.  
  3119. #if (USE_SPI_CRC != 0U)
  3120.     /* Check if CRC error occurred */
  3121.     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
  3122.     {
  3123.       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  3124.       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
  3125.     }
  3126. #endif /* USE_SPI_CRC */
  3127.  
  3128.     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  3129.     {
  3130.       /* Call user error callback */
  3131. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  3132.       hspi->ErrorCallback(hspi);
  3133. #else
  3134.       HAL_SPI_ErrorCallback(hspi);
  3135. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  3136.       return;
  3137.     }
  3138.   }
  3139.   /* Call user Rx complete callback */
  3140. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  3141.   hspi->RxCpltCallback(hspi);
  3142. #else
  3143.   HAL_SPI_RxCpltCallback(hspi);
  3144. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  3145. }
  3146.  
  3147. /**
  3148.   * @brief  DMA SPI transmit receive process complete callback.
  3149.   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
  3150.   *               the configuration information for the specified DMA module.
  3151.   * @retval None
  3152.   */
  3153. static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
  3154. {
  3155.   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
  3156.   uint32_t tickstart;
  3157. #if (USE_SPI_CRC != 0U)
  3158.   __IO uint32_t tmpreg = 0U;
  3159.   __IO uint8_t  * ptmpreg8;
  3160.   __IO uint8_t  tmpreg8 = 0;
  3161. #endif /* USE_SPI_CRC */
  3162.  
  3163.   /* Init tickstart for timeout management*/
  3164.   tickstart = HAL_GetTick();
  3165.  
  3166.   /* DMA Normal Mode */
  3167.   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
  3168.   {
  3169.     /* Disable ERR interrupt */
  3170.     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
  3171.  
  3172. #if (USE_SPI_CRC != 0U)
  3173.     /* CRC handling */
  3174.     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  3175.     {
  3176.       if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
  3177.       {
  3178.         if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
  3179.                                           tickstart) != HAL_OK)
  3180.         {
  3181.           /* Error on the CRC reception */
  3182.           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  3183.         }
  3184.         /* Initialize the 8bit temporary pointer */
  3185.         ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
  3186.         /* Read 8bit CRC */
  3187.         tmpreg8 = *ptmpreg8;
  3188.         /* To avoid GCC warning */
  3189.         UNUSED(tmpreg8);
  3190.       }
  3191.       else
  3192.       {
  3193.         if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  3194.         {
  3195.           /* Error on the CRC reception */
  3196.           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  3197.         }
  3198.         /* Read CRC to Flush DR and RXNE flag */
  3199.         tmpreg = READ_REG(hspi->Instance->DR);
  3200.         /* To avoid GCC warning */
  3201.         UNUSED(tmpreg);
  3202.       }
  3203.     }
  3204. #endif /* USE_SPI_CRC */
  3205.  
  3206.     /* Check the end of the transaction */
  3207.     if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  3208.     {
  3209.       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  3210.     }
  3211.  
  3212.     /* Disable Rx/Tx DMA Request */
  3213.     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
  3214.  
  3215.     hspi->TxXferCount = 0U;
  3216.     hspi->RxXferCount = 0U;
  3217.     hspi->State = HAL_SPI_STATE_READY;
  3218.  
  3219. #if (USE_SPI_CRC != 0U)
  3220.     /* Check if CRC error occurred */
  3221.     if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
  3222.     {
  3223.       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  3224.       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
  3225.     }
  3226. #endif /* USE_SPI_CRC */
  3227.  
  3228.     if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  3229.     {
  3230.       /* Call user error callback */
  3231. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  3232.       hspi->ErrorCallback(hspi);
  3233. #else
  3234.       HAL_SPI_ErrorCallback(hspi);
  3235. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  3236.       return;
  3237.     }
  3238.   }
  3239.   /* Call user TxRx complete callback */
  3240. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  3241.   hspi->TxRxCpltCallback(hspi);
  3242. #else
  3243.   HAL_SPI_TxRxCpltCallback(hspi);
  3244. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  3245. }
  3246.  
  3247. /**
  3248.   * @brief  DMA SPI half transmit process complete callback.
  3249.   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
  3250.   *               the configuration information for the specified DMA module.
  3251.   * @retval None
  3252.   */
  3253. static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
  3254. {
  3255.   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
  3256.  
  3257.   /* Call user Tx half complete callback */
  3258. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  3259.   hspi->TxHalfCpltCallback(hspi);
  3260. #else
  3261.   HAL_SPI_TxHalfCpltCallback(hspi);
  3262. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  3263. }
  3264.  
  3265. /**
  3266.   * @brief  DMA SPI half receive process complete callback
  3267.   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
  3268.   *               the configuration information for the specified DMA module.
  3269.   * @retval None
  3270.   */
  3271. static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
  3272. {
  3273.   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
  3274.  
  3275.   /* Call user Rx half complete callback */
  3276. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  3277.   hspi->RxHalfCpltCallback(hspi);
  3278. #else
  3279.   HAL_SPI_RxHalfCpltCallback(hspi);
  3280. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  3281. }
  3282.  
  3283. /**
  3284.   * @brief  DMA SPI half transmit receive process complete callback.
  3285.   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
  3286.   *               the configuration information for the specified DMA module.
  3287.   * @retval None
  3288.   */
  3289. static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
  3290. {
  3291.   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
  3292.  
  3293.   /* Call user TxRx half complete callback */
  3294. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  3295.   hspi->TxRxHalfCpltCallback(hspi);
  3296. #else
  3297.   HAL_SPI_TxRxHalfCpltCallback(hspi);
  3298. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  3299. }
  3300.  
  3301. /**
  3302.   * @brief  DMA SPI communication error callback.
  3303.   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
  3304.   *               the configuration information for the specified DMA module.
  3305.   * @retval None
  3306.   */
  3307. static void SPI_DMAError(DMA_HandleTypeDef *hdma)
  3308. {
  3309.   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
  3310.  
  3311.   /* Stop the disable DMA transfer on SPI side */
  3312.   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
  3313.  
  3314.   SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
  3315.   hspi->State = HAL_SPI_STATE_READY;
  3316.   /* Call user error callback */
  3317. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  3318.   hspi->ErrorCallback(hspi);
  3319. #else
  3320.   HAL_SPI_ErrorCallback(hspi);
  3321. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  3322. }
  3323.  
  3324. /**
  3325.   * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
  3326.   *         (To be called at end of DMA Abort procedure following error occurrence).
  3327.   * @param  hdma DMA handle.
  3328.   * @retval None
  3329.   */
  3330. static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
  3331. {
  3332.   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
  3333.   hspi->RxXferCount = 0U;
  3334.   hspi->TxXferCount = 0U;
  3335.  
  3336.   /* Call user error callback */
  3337. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  3338.   hspi->ErrorCallback(hspi);
  3339. #else
  3340.   HAL_SPI_ErrorCallback(hspi);
  3341. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  3342. }
  3343.  
  3344. /**
  3345.   * @brief  DMA SPI Tx communication abort callback, when initiated by user
  3346.   *         (To be called at end of DMA Tx Abort procedure following user abort request).
  3347.   * @note   When this callback is executed, User Abort complete call back is called only if no
  3348.   *         Abort still ongoing for Rx DMA Handle.
  3349.   * @param  hdma DMA handle.
  3350.   * @retval None
  3351.   */
  3352. static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
  3353. {
  3354.   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
  3355.  
  3356.   hspi->hdmatx->XferAbortCallback = NULL;
  3357.  
  3358.   /* Disable Tx DMA Request */
  3359.   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
  3360.  
  3361.   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  3362.   {
  3363.     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  3364.   }
  3365.  
  3366.   /* Disable SPI Peripheral */
  3367.   __HAL_SPI_DISABLE(hspi);
  3368.  
  3369.   /* Empty the FRLVL fifo */
  3370.   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  3371.   {
  3372.     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  3373.   }
  3374.  
  3375.   /* Check if an Abort process is still ongoing */
  3376.   if (hspi->hdmarx != NULL)
  3377.   {
  3378.     if (hspi->hdmarx->XferAbortCallback != NULL)
  3379.     {
  3380.       return;
  3381.     }
  3382.   }
  3383.  
  3384.   /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
  3385.   hspi->RxXferCount = 0U;
  3386.   hspi->TxXferCount = 0U;
  3387.  
  3388.   /* Check no error during Abort procedure */
  3389.   if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
  3390.   {
  3391.     /* Reset errorCode */
  3392.     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  3393.   }
  3394.  
  3395.   /* Clear the Error flags in the SR register */
  3396.   __HAL_SPI_CLEAR_OVRFLAG(hspi);
  3397.   __HAL_SPI_CLEAR_FREFLAG(hspi);
  3398.  
  3399.   /* Restore hspi->State to Ready */
  3400.   hspi->State  = HAL_SPI_STATE_READY;
  3401.  
  3402.   /* Call user Abort complete callback */
  3403. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  3404.   hspi->AbortCpltCallback(hspi);
  3405. #else
  3406.   HAL_SPI_AbortCpltCallback(hspi);
  3407. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  3408. }
  3409.  
  3410. /**
  3411.   * @brief  DMA SPI Rx communication abort callback, when initiated by user
  3412.   *         (To be called at end of DMA Rx Abort procedure following user abort request).
  3413.   * @note   When this callback is executed, User Abort complete call back is called only if no
  3414.   *         Abort still ongoing for Tx DMA Handle.
  3415.   * @param  hdma DMA handle.
  3416.   * @retval None
  3417.   */
  3418. static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
  3419. {
  3420.   SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
  3421.  
  3422.   /* Disable SPI Peripheral */
  3423.   __HAL_SPI_DISABLE(hspi);
  3424.  
  3425.   hspi->hdmarx->XferAbortCallback = NULL;
  3426.  
  3427.   /* Disable Rx DMA Request */
  3428.   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
  3429.  
  3430.   /* Control the BSY flag */
  3431.   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  3432.   {
  3433.     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  3434.   }
  3435.  
  3436.   /* Empty the FRLVL fifo */
  3437.   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  3438.   {
  3439.     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  3440.   }
  3441.  
  3442.   /* Check if an Abort process is still ongoing */
  3443.   if (hspi->hdmatx != NULL)
  3444.   {
  3445.     if (hspi->hdmatx->XferAbortCallback != NULL)
  3446.     {
  3447.       return;
  3448.     }
  3449.   }
  3450.  
  3451.   /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
  3452.   hspi->RxXferCount = 0U;
  3453.   hspi->TxXferCount = 0U;
  3454.  
  3455.   /* Check no error during Abort procedure */
  3456.   if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
  3457.   {
  3458.     /* Reset errorCode */
  3459.     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  3460.   }
  3461.  
  3462.   /* Clear the Error flags in the SR register */
  3463.   __HAL_SPI_CLEAR_OVRFLAG(hspi);
  3464.   __HAL_SPI_CLEAR_FREFLAG(hspi);
  3465.  
  3466.   /* Restore hspi->State to Ready */
  3467.   hspi->State  = HAL_SPI_STATE_READY;
  3468.  
  3469.   /* Call user Abort complete callback */
  3470. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  3471.   hspi->AbortCpltCallback(hspi);
  3472. #else
  3473.   HAL_SPI_AbortCpltCallback(hspi);
  3474. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  3475. }
  3476.  
  3477. /**
  3478.   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
  3479.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  3480.   *               the configuration information for SPI module.
  3481.   * @retval None
  3482.   */
  3483. static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
  3484. {
  3485.   /* Receive data in packing mode */
  3486.   if (hspi->RxXferCount > 1U)
  3487.   {
  3488.     *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
  3489.     hspi->pRxBuffPtr += sizeof(uint16_t);
  3490.     hspi->RxXferCount -= 2U;
  3491.     if (hspi->RxXferCount == 1U)
  3492.     {
  3493.       /* Set RX Fifo threshold according the reception data length: 8bit */
  3494.       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  3495.     }
  3496.   }
  3497.   /* Receive data in 8 Bit mode */
  3498.   else
  3499.   {
  3500.     *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
  3501.     hspi->pRxBuffPtr++;
  3502.     hspi->RxXferCount--;
  3503.   }
  3504.  
  3505.   /* Check end of the reception */
  3506.   if (hspi->RxXferCount == 0U)
  3507.   {
  3508. #if (USE_SPI_CRC != 0U)
  3509.     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  3510.     {
  3511.       SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
  3512.       hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
  3513.       return;
  3514.     }
  3515. #endif /* USE_SPI_CRC */
  3516.  
  3517.     /* Disable RXNE  and ERR interrupt */
  3518.     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
  3519.  
  3520.     if (hspi->TxXferCount == 0U)
  3521.     {
  3522.       SPI_CloseRxTx_ISR(hspi);
  3523.     }
  3524.   }
  3525. }
  3526.  
  3527. #if (USE_SPI_CRC != 0U)
  3528. /**
  3529.   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
  3530.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  3531.   *               the configuration information for SPI module.
  3532.   * @retval None
  3533.   */
  3534. static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
  3535. {
  3536.   __IO uint8_t  * ptmpreg8;
  3537.   __IO uint8_t  tmpreg8 = 0;
  3538.  
  3539.   /* Initialize the 8bit temporary pointer */
  3540.   ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
  3541.   /* Read 8bit CRC to flush Data Register */
  3542.   tmpreg8 = *ptmpreg8;
  3543.   /* To avoid GCC warning */
  3544.   UNUSED(tmpreg8);
  3545.  
  3546.   hspi->CRCSize--;
  3547.  
  3548.   /* Check end of the reception */
  3549.   if (hspi->CRCSize == 0U)
  3550.   {
  3551.     /* Disable RXNE and ERR interrupt */
  3552.     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
  3553.  
  3554.     if (hspi->TxXferCount == 0U)
  3555.     {
  3556.       SPI_CloseRxTx_ISR(hspi);
  3557.     }
  3558.   }
  3559. }
  3560. #endif /* USE_SPI_CRC */
  3561.  
  3562. /**
  3563.   * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
  3564.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  3565.   *               the configuration information for SPI module.
  3566.   * @retval None
  3567.   */
  3568. static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
  3569. {
  3570.   /* Transmit data in packing Bit mode */
  3571.   if (hspi->TxXferCount >= 2U)
  3572.   {
  3573.     hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
  3574.     hspi->pTxBuffPtr += sizeof(uint16_t);
  3575.     hspi->TxXferCount -= 2U;
  3576.   }
  3577.   /* Transmit data in 8 Bit mode */
  3578.   else
  3579.   {
  3580.     *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
  3581.     hspi->pTxBuffPtr++;
  3582.     hspi->TxXferCount--;
  3583.   }
  3584.  
  3585.   /* Check the end of the transmission */
  3586.   if (hspi->TxXferCount == 0U)
  3587.   {
  3588. #if (USE_SPI_CRC != 0U)
  3589.     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  3590.     {
  3591.       /* Set CRC Next Bit to send CRC */
  3592.       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  3593.       /* Disable TXE interrupt */
  3594.       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
  3595.       return;
  3596.     }
  3597. #endif /* USE_SPI_CRC */
  3598.  
  3599.     /* Disable TXE interrupt */
  3600.     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
  3601.  
  3602.     if (hspi->RxXferCount == 0U)
  3603.     {
  3604.       SPI_CloseRxTx_ISR(hspi);
  3605.     }
  3606.   }
  3607. }
  3608.  
  3609. /**
  3610.   * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
  3611.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  3612.   *               the configuration information for SPI module.
  3613.   * @retval None
  3614.   */
  3615. static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
  3616. {
  3617.   /* Receive data in 16 Bit mode */
  3618.   *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
  3619.   hspi->pRxBuffPtr += sizeof(uint16_t);
  3620.   hspi->RxXferCount--;
  3621.  
  3622.   if (hspi->RxXferCount == 0U)
  3623.   {
  3624. #if (USE_SPI_CRC != 0U)
  3625.     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  3626.     {
  3627.       hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
  3628.       return;
  3629.     }
  3630. #endif /* USE_SPI_CRC */
  3631.  
  3632.     /* Disable RXNE interrupt */
  3633.     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
  3634.  
  3635.     if (hspi->TxXferCount == 0U)
  3636.     {
  3637.       SPI_CloseRxTx_ISR(hspi);
  3638.     }
  3639.   }
  3640. }
  3641.  
  3642. #if (USE_SPI_CRC != 0U)
  3643. /**
  3644.   * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
  3645.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  3646.   *               the configuration information for SPI module.
  3647.   * @retval None
  3648.   */
  3649. static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
  3650. {
  3651.   __IO uint32_t tmpreg = 0U;
  3652.  
  3653.   /* Read 16bit CRC to flush Data Register */
  3654.   tmpreg = READ_REG(hspi->Instance->DR);
  3655.   /* To avoid GCC warning */
  3656.   UNUSED(tmpreg);  
  3657.  
  3658.   /* Disable RXNE interrupt */
  3659.   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
  3660.  
  3661.   SPI_CloseRxTx_ISR(hspi);
  3662. }
  3663. #endif /* USE_SPI_CRC */
  3664.  
  3665. /**
  3666.   * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
  3667.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  3668.   *               the configuration information for SPI module.
  3669.   * @retval None
  3670.   */
  3671. static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
  3672. {
  3673.   /* Transmit data in 16 Bit mode */
  3674.   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
  3675.   hspi->pTxBuffPtr += sizeof(uint16_t);
  3676.   hspi->TxXferCount--;
  3677.  
  3678.   /* Enable CRC Transmission */
  3679.   if (hspi->TxXferCount == 0U)
  3680.   {
  3681. #if (USE_SPI_CRC != 0U)
  3682.     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  3683.     {
  3684.       /* Set CRC Next Bit to send CRC */
  3685.       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  3686.       /* Disable TXE interrupt */
  3687.       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
  3688.       return;
  3689.     }
  3690. #endif /* USE_SPI_CRC */
  3691.  
  3692.     /* Disable TXE interrupt */
  3693.     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
  3694.  
  3695.     if (hspi->RxXferCount == 0U)
  3696.     {
  3697.       SPI_CloseRxTx_ISR(hspi);
  3698.     }
  3699.   }
  3700. }
  3701.  
  3702. #if (USE_SPI_CRC != 0U)
  3703. /**
  3704.   * @brief  Manage the CRC 8-bit receive in Interrupt context.
  3705.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  3706.   *               the configuration information for SPI module.
  3707.   * @retval None
  3708.   */
  3709. static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
  3710. {
  3711.   __IO uint8_t  * ptmpreg8;
  3712.   __IO uint8_t  tmpreg8 = 0;
  3713.  
  3714.   /* Initialize the 8bit temporary pointer */
  3715.   ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
  3716.   /* Read 8bit CRC to flush Data Register */
  3717.   tmpreg8 = *ptmpreg8;
  3718.   /* To avoid GCC warning */
  3719.   UNUSED(tmpreg8);
  3720.  
  3721.   hspi->CRCSize--;
  3722.  
  3723.   if (hspi->CRCSize == 0U)
  3724.   {
  3725.     SPI_CloseRx_ISR(hspi);
  3726.   }
  3727. }
  3728. #endif /* USE_SPI_CRC */
  3729.  
  3730. /**
  3731.   * @brief  Manage the receive 8-bit in Interrupt context.
  3732.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  3733.   *               the configuration information for SPI module.
  3734.   * @retval None
  3735.   */
  3736. static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
  3737. {
  3738.   *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
  3739.   hspi->pRxBuffPtr++;
  3740.   hspi->RxXferCount--;
  3741.  
  3742. #if (USE_SPI_CRC != 0U)
  3743.   /* Enable CRC Transmission */
  3744.   if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
  3745.   {
  3746.     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  3747.   }
  3748. #endif /* USE_SPI_CRC */
  3749.  
  3750.   if (hspi->RxXferCount == 0U)
  3751.   {
  3752. #if (USE_SPI_CRC != 0U)
  3753.     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  3754.     {
  3755.       hspi->RxISR =  SPI_RxISR_8BITCRC;
  3756.       return;
  3757.     }
  3758. #endif /* USE_SPI_CRC */
  3759.     SPI_CloseRx_ISR(hspi);
  3760.   }
  3761. }
  3762.  
  3763. #if (USE_SPI_CRC != 0U)
  3764. /**
  3765.   * @brief  Manage the CRC 16-bit receive in Interrupt context.
  3766.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  3767.   *               the configuration information for SPI module.
  3768.   * @retval None
  3769.   */
  3770. static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
  3771. {
  3772.   __IO uint32_t tmpreg = 0U;
  3773.  
  3774.   /* Read 16bit CRC to flush Data Register */
  3775.   tmpreg = READ_REG(hspi->Instance->DR);
  3776.   /* To avoid GCC warning */
  3777.   UNUSED(tmpreg);
  3778.  
  3779.   /* Disable RXNE and ERR interrupt */
  3780.   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
  3781.  
  3782.   SPI_CloseRx_ISR(hspi);
  3783. }
  3784. #endif /* USE_SPI_CRC */
  3785.  
  3786. /**
  3787.   * @brief  Manage the 16-bit receive in Interrupt context.
  3788.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  3789.   *               the configuration information for SPI module.
  3790.   * @retval None
  3791.   */
  3792. static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
  3793. {
  3794.   *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
  3795.   hspi->pRxBuffPtr += sizeof(uint16_t);
  3796.   hspi->RxXferCount--;
  3797.  
  3798. #if (USE_SPI_CRC != 0U)
  3799.   /* Enable CRC Transmission */
  3800.   if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
  3801.   {
  3802.     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  3803.   }
  3804. #endif /* USE_SPI_CRC */
  3805.  
  3806.   if (hspi->RxXferCount == 0U)
  3807.   {
  3808. #if (USE_SPI_CRC != 0U)
  3809.     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  3810.     {
  3811.       hspi->RxISR = SPI_RxISR_16BITCRC;
  3812.       return;
  3813.     }
  3814. #endif /* USE_SPI_CRC */
  3815.     SPI_CloseRx_ISR(hspi);
  3816.   }
  3817. }
  3818.  
  3819. /**
  3820.   * @brief  Handle the data 8-bit transmit in Interrupt mode.
  3821.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  3822.   *               the configuration information for SPI module.
  3823.   * @retval None
  3824.   */
  3825. static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
  3826. {
  3827.   *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
  3828.   hspi->pTxBuffPtr++;
  3829.   hspi->TxXferCount--;
  3830.  
  3831.   if (hspi->TxXferCount == 0U)
  3832.   {
  3833. #if (USE_SPI_CRC != 0U)
  3834.     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  3835.     {
  3836.       /* Enable CRC Transmission */
  3837.       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  3838.     }
  3839. #endif /* USE_SPI_CRC */
  3840.     SPI_CloseTx_ISR(hspi);
  3841.   }
  3842. }
  3843.  
  3844. /**
  3845.   * @brief  Handle the data 16-bit transmit in Interrupt mode.
  3846.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  3847.   *               the configuration information for SPI module.
  3848.   * @retval None
  3849.   */
  3850. static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
  3851. {
  3852.   /* Transmit data in 16 Bit mode */
  3853.   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
  3854.   hspi->pTxBuffPtr += sizeof(uint16_t);
  3855.   hspi->TxXferCount--;
  3856.  
  3857.   if (hspi->TxXferCount == 0U)
  3858.   {
  3859. #if (USE_SPI_CRC != 0U)
  3860.     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  3861.     {
  3862.       /* Enable CRC Transmission */
  3863.       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  3864.     }
  3865. #endif /* USE_SPI_CRC */
  3866.     SPI_CloseTx_ISR(hspi);
  3867.   }
  3868. }
  3869.  
  3870. /**
  3871.   * @brief  Handle SPI Communication Timeout.
  3872.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  3873.   *              the configuration information for SPI module.
  3874.   * @param  Flag SPI flag to check
  3875.   * @param  State flag state to check
  3876.   * @param  Timeout Timeout duration
  3877.   * @param  Tickstart tick start value
  3878.   * @retval HAL status
  3879.   */
  3880. static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
  3881.                                                        uint32_t Timeout, uint32_t Tickstart)
  3882. {
  3883.   __IO uint32_t count;
  3884.   uint32_t tmp_timeout;
  3885.   uint32_t tmp_tickstart;
  3886.  
  3887.   /* Adjust Timeout value  in case of end of transfer */
  3888.   tmp_timeout   = Timeout - (HAL_GetTick() - Tickstart);
  3889.   tmp_tickstart = HAL_GetTick();
  3890.  
  3891.   /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
  3892.   count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
  3893.  
  3894.   while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
  3895.   {
  3896.     if (Timeout != HAL_MAX_DELAY)
  3897.     {
  3898.       if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
  3899.       {
  3900.         /* Disable the SPI and reset the CRC: the CRC value should be cleared
  3901.            on both master and slave sides in order to resynchronize the master
  3902.            and slave for their respective CRC calculation */
  3903.  
  3904.         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
  3905.         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
  3906.  
  3907.         if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
  3908.                                                      || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
  3909.         {
  3910.           /* Disable SPI peripheral */
  3911.           __HAL_SPI_DISABLE(hspi);
  3912.         }
  3913.  
  3914.         /* Reset CRC Calculation */
  3915.         if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  3916.         {
  3917.           SPI_RESET_CRC(hspi);
  3918.         }
  3919.  
  3920.         hspi->State = HAL_SPI_STATE_READY;
  3921.  
  3922.         /* Process Unlocked */
  3923.         __HAL_UNLOCK(hspi);
  3924.  
  3925.         return HAL_TIMEOUT;
  3926.       }
  3927.       /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
  3928.       if(count == 0U)
  3929.       {
  3930.         tmp_timeout = 0U;
  3931.       }
  3932.       count--;
  3933.     }
  3934.   }
  3935.  
  3936.   return HAL_OK;
  3937. }
  3938.  
  3939. /**
  3940.   * @brief  Handle SPI FIFO Communication Timeout.
  3941.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  3942.   *              the configuration information for SPI module.
  3943.   * @param  Fifo Fifo to check
  3944.   * @param  State Fifo state to check
  3945.   * @param  Timeout Timeout duration
  3946.   * @param  Tickstart tick start value
  3947.   * @retval HAL status
  3948.   */
  3949. static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
  3950.                                                        uint32_t Timeout, uint32_t Tickstart)
  3951. {
  3952.   __IO uint32_t count;
  3953.   uint32_t tmp_timeout;
  3954.   uint32_t tmp_tickstart;
  3955.   __IO uint8_t  * ptmpreg8;
  3956.   __IO uint8_t  tmpreg8 = 0;
  3957.  
  3958.   /* Adjust Timeout value  in case of end of transfer */
  3959.   tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
  3960.   tmp_tickstart = HAL_GetTick();
  3961.  
  3962.   /* Initialize the 8bit temporary pointer */
  3963.   ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
  3964.  
  3965.   /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
  3966.   count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
  3967.  
  3968.   while ((hspi->Instance->SR & Fifo) != State)
  3969.   {
  3970.     if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
  3971.     {
  3972.       /* Flush Data Register by a blank read */
  3973.       tmpreg8 = *ptmpreg8;
  3974.       /* To avoid GCC warning */
  3975.       UNUSED(tmpreg8);
  3976.     }
  3977.  
  3978.     if (Timeout != HAL_MAX_DELAY)
  3979.     {
  3980.       if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
  3981.       {
  3982.         /* Disable the SPI and reset the CRC: the CRC value should be cleared
  3983.            on both master and slave sides in order to resynchronize the master
  3984.            and slave for their respective CRC calculation */
  3985.  
  3986.         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
  3987.         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
  3988.  
  3989.         if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
  3990.                                                      || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
  3991.         {
  3992.           /* Disable SPI peripheral */
  3993.           __HAL_SPI_DISABLE(hspi);
  3994.         }
  3995.  
  3996.         /* Reset CRC Calculation */
  3997.         if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  3998.         {
  3999.           SPI_RESET_CRC(hspi);
  4000.         }
  4001.  
  4002.         hspi->State = HAL_SPI_STATE_READY;
  4003.  
  4004.         /* Process Unlocked */
  4005.         __HAL_UNLOCK(hspi);
  4006.  
  4007.         return HAL_TIMEOUT;
  4008.       }
  4009.       /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
  4010.       if(count == 0U)
  4011.       {
  4012.         tmp_timeout = 0U;
  4013.       }      
  4014.       count--;
  4015.     }
  4016.   }
  4017.  
  4018.   return HAL_OK;
  4019. }
  4020.  
  4021. /**
  4022.   * @brief  Handle the check of the RX transaction complete.
  4023.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  4024.   *               the configuration information for SPI module.
  4025.   * @param  Timeout Timeout duration
  4026.   * @param  Tickstart tick start value
  4027.   * @retval HAL status
  4028.   */
  4029. static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
  4030. {
  4031.   if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
  4032.                                                || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
  4033.   {
  4034.     /* Disable SPI peripheral */
  4035.     __HAL_SPI_DISABLE(hspi);
  4036.   }
  4037.  
  4038.   /* Control the BSY flag */
  4039.   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
  4040.   {
  4041.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  4042.     return HAL_TIMEOUT;
  4043.   }
  4044.  
  4045.   if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
  4046.                                                || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
  4047.   {
  4048.     /* Empty the FRLVL fifo */
  4049.     if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
  4050.     {
  4051.       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  4052.       return HAL_TIMEOUT;
  4053.     }
  4054.   }
  4055.   return HAL_OK;
  4056. }
  4057.  
  4058. /**
  4059.   * @brief  Handle the check of the RXTX or TX transaction complete.
  4060.   * @param  hspi SPI handle
  4061.   * @param  Timeout Timeout duration
  4062.   * @param  Tickstart tick start value
  4063.   * @retval HAL status
  4064.   */
  4065. static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
  4066. {
  4067.   /* Control if the TX fifo is empty */
  4068.   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
  4069.   {
  4070.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  4071.     return HAL_TIMEOUT;
  4072.   }
  4073.  
  4074.   /* Control the BSY flag */
  4075.   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
  4076.   {
  4077.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  4078.     return HAL_TIMEOUT;
  4079.   }
  4080.  
  4081.   /* Control if the RX fifo is empty */
  4082.   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
  4083.   {
  4084.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  4085.     return HAL_TIMEOUT;
  4086.   }
  4087.  
  4088.   return HAL_OK;
  4089. }
  4090.  
  4091. /**
  4092.   * @brief  Handle the end of the RXTX transaction.
  4093.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  4094.   *               the configuration information for SPI module.
  4095.   * @retval None
  4096.   */
  4097. static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
  4098. {
  4099.   uint32_t tickstart;
  4100.  
  4101.   /* Init tickstart for timeout management */
  4102.   tickstart = HAL_GetTick();
  4103.  
  4104.   /* Disable ERR interrupt */
  4105.   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
  4106.  
  4107.   /* Check the end of the transaction */
  4108.   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  4109.   {
  4110.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  4111.   }
  4112.  
  4113. #if (USE_SPI_CRC != 0U)
  4114.   /* Check if CRC error occurred */
  4115.   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
  4116.   {
  4117.     hspi->State = HAL_SPI_STATE_READY;
  4118.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  4119.     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
  4120.     /* Call user error callback */
  4121. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  4122.     hspi->ErrorCallback(hspi);
  4123. #else
  4124.     HAL_SPI_ErrorCallback(hspi);
  4125. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  4126.   }
  4127.   else
  4128.   {
  4129. #endif /* USE_SPI_CRC */
  4130.     if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
  4131.     {
  4132.       if (hspi->State == HAL_SPI_STATE_BUSY_RX)
  4133.       {
  4134.         hspi->State = HAL_SPI_STATE_READY;
  4135.         /* Call user Rx complete callback */
  4136. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  4137.         hspi->RxCpltCallback(hspi);
  4138. #else
  4139.         HAL_SPI_RxCpltCallback(hspi);
  4140. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  4141.       }
  4142.       else
  4143.       {
  4144.         hspi->State = HAL_SPI_STATE_READY;
  4145.         /* Call user TxRx complete callback */
  4146. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  4147.         hspi->TxRxCpltCallback(hspi);
  4148. #else
  4149.         HAL_SPI_TxRxCpltCallback(hspi);
  4150. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  4151.       }
  4152.     }
  4153.     else
  4154.     {
  4155.       hspi->State = HAL_SPI_STATE_READY;
  4156.       /* Call user error callback */
  4157. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  4158.       hspi->ErrorCallback(hspi);
  4159. #else
  4160.       HAL_SPI_ErrorCallback(hspi);
  4161. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  4162.     }
  4163. #if (USE_SPI_CRC != 0U)
  4164.   }
  4165. #endif /* USE_SPI_CRC */
  4166. }
  4167.  
  4168. /**
  4169.   * @brief  Handle the end of the RX transaction.
  4170.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  4171.   *               the configuration information for SPI module.
  4172.   * @retval None
  4173.   */
  4174. static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
  4175. {
  4176.   /* Disable RXNE and ERR interrupt */
  4177.   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
  4178.  
  4179.   /* Check the end of the transaction */
  4180.   if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  4181.   {
  4182.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  4183.   }
  4184.   hspi->State = HAL_SPI_STATE_READY;
  4185.  
  4186. #if (USE_SPI_CRC != 0U)
  4187.   /* Check if CRC error occurred */
  4188.   if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
  4189.   {
  4190.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
  4191.     __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
  4192.     /* Call user error callback */
  4193. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  4194.     hspi->ErrorCallback(hspi);
  4195. #else
  4196.     HAL_SPI_ErrorCallback(hspi);
  4197. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  4198.   }
  4199.   else
  4200.   {
  4201. #endif /* USE_SPI_CRC */
  4202.     if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
  4203.     {
  4204.       /* Call user Rx complete callback */
  4205. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  4206.       hspi->RxCpltCallback(hspi);
  4207. #else
  4208.       HAL_SPI_RxCpltCallback(hspi);
  4209. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  4210.     }
  4211.     else
  4212.     {
  4213.       /* Call user error callback */
  4214. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  4215.       hspi->ErrorCallback(hspi);
  4216. #else
  4217.       HAL_SPI_ErrorCallback(hspi);
  4218. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  4219.     }
  4220. #if (USE_SPI_CRC != 0U)
  4221.   }
  4222. #endif /* USE_SPI_CRC */
  4223. }
  4224.  
  4225. /**
  4226.   * @brief  Handle the end of the TX transaction.
  4227.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  4228.   *               the configuration information for SPI module.
  4229.   * @retval None
  4230.   */
  4231. static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
  4232. {
  4233.   uint32_t tickstart;
  4234.  
  4235.   /* Init tickstart for timeout management*/
  4236.   tickstart = HAL_GetTick();
  4237.  
  4238.   /* Disable TXE and ERR interrupt */
  4239.   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
  4240.  
  4241.   /* Check the end of the transaction */
  4242.   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
  4243.   {
  4244.     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  4245.   }
  4246.  
  4247.   /* Clear overrun flag in 2 Lines communication mode because received is not read */
  4248.   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
  4249.   {
  4250.     __HAL_SPI_CLEAR_OVRFLAG(hspi);
  4251.   }
  4252.  
  4253.   hspi->State = HAL_SPI_STATE_READY;
  4254.   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  4255.   {
  4256.     /* Call user error callback */
  4257. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  4258.     hspi->ErrorCallback(hspi);
  4259. #else
  4260.     HAL_SPI_ErrorCallback(hspi);
  4261. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  4262.   }
  4263.   else
  4264.   {
  4265.     /* Call user Rx complete callback */
  4266. #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
  4267.     hspi->TxCpltCallback(hspi);
  4268. #else
  4269.     HAL_SPI_TxCpltCallback(hspi);
  4270. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  4271.   }
  4272. }
  4273.  
  4274. /**
  4275.   * @brief  Handle abort a Rx transaction.
  4276.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  4277.   *               the configuration information for SPI module.
  4278.   * @retval None
  4279.   */
  4280. static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
  4281. {
  4282.   __IO uint32_t count;
  4283.  
  4284.   /* Disable SPI Peripheral */
  4285.   __HAL_SPI_DISABLE(hspi);
  4286.  
  4287.   count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
  4288.  
  4289.   /* Disable RXNEIE interrupt */
  4290.   CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
  4291.  
  4292.   /* Check RXNEIE is disabled */
  4293.   do
  4294.   {
  4295.     if (count == 0U)
  4296.     {
  4297.       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  4298.       break;
  4299.     }
  4300.     count--;
  4301.   } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
  4302.  
  4303.   /* Control the BSY flag */
  4304.   if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  4305.   {
  4306.     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  4307.   }
  4308.  
  4309.   /* Empty the FRLVL fifo */
  4310.   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  4311.   {
  4312.     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  4313.   }
  4314.  
  4315.   hspi->State = HAL_SPI_STATE_ABORT;
  4316. }
  4317.  
  4318. /**
  4319.   * @brief  Handle abort a Tx or Rx/Tx transaction.
  4320.   * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  4321.   *               the configuration information for SPI module.
  4322.   * @retval None
  4323.   */
  4324. static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
  4325. {
  4326.   __IO uint32_t count;
  4327.  
  4328.   count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
  4329.  
  4330.   /* Disable TXEIE interrupt */
  4331.   CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
  4332.  
  4333.   /* Check TXEIE is disabled */
  4334.   do
  4335.   {
  4336.     if (count == 0U)
  4337.     {
  4338.       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  4339.       break;
  4340.     }
  4341.     count--;
  4342.   } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
  4343.  
  4344.   if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  4345.   {
  4346.     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  4347.   }
  4348.  
  4349.   /* Disable SPI Peripheral */
  4350.   __HAL_SPI_DISABLE(hspi);
  4351.  
  4352.   /* Empty the FRLVL fifo */
  4353.   if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  4354.   {
  4355.     hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  4356.   }
  4357.  
  4358.   /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
  4359.   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
  4360.   {
  4361.     /* Disable RXNEIE interrupt */
  4362.     CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
  4363.  
  4364.     /* Check RXNEIE is disabled */
  4365.     do
  4366.     {
  4367.       if (count == 0U)
  4368.       {
  4369.         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
  4370.         break;
  4371.       }
  4372.       count--;
  4373.     } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
  4374.  
  4375.     /* Control the BSY flag */
  4376.     if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  4377.     {
  4378.       hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  4379.     }
  4380.  
  4381.     /* Empty the FRLVL fifo */
  4382.     if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
  4383.     {
  4384.       hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
  4385.     }
  4386.   }
  4387.   hspi->State = HAL_SPI_STATE_ABORT;
  4388. }
  4389.  
  4390. /**
  4391.   * @}
  4392.   */
  4393.  
  4394. #endif /* HAL_SPI_MODULE_ENABLED */
  4395.  
  4396. /**
  4397.   * @}
  4398.   */
  4399.  
  4400. /**
  4401.   * @}
  4402.   */
  4403.  
  4404. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  4405.