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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f0xx_hal_rcc.c
  4.   * @author  MCD Application Team
  5.   * @brief   RCC HAL module driver.
  6.   *          This file provides firmware functions to manage the following
  7.   *          functionalities of the Reset and Clock Control (RCC) peripheral:
  8.   *           + Initialization and de-initialization functions
  9.   *           + Peripheral Control functions
  10.   *      
  11.   @verbatim                
  12.   ==============================================================================
  13.                       ##### RCC specific features #####
  14.   ==============================================================================
  15.     [..]  
  16.       After reset the device is running from Internal High Speed oscillator
  17.       (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is disabled,
  18.       and all peripherals are off except internal SRAM, Flash and JTAG.
  19.       (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
  20.           all peripherals mapped on these buses are running at HSI speed.
  21.       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
  22.       (+) All GPIOs are in input floating state, except the JTAG pins which
  23.           are assigned to be used for debug purpose.
  24.     [..] Once the device started from reset, the user application has to:
  25.       (+) Configure the clock source to be used to drive the System clock
  26.           (if the application needs higher frequency/performance)
  27.       (+) Configure the System clock frequency and Flash settings  
  28.       (+) Configure the AHB and APB buses prescalers
  29.       (+) Enable the clock for the peripheral(s) to be used
  30.       (+) Configure the clock source(s) for peripherals whose clocks are not
  31.           derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..)
  32.  
  33.                       ##### RCC Limitations #####
  34.   ==============================================================================
  35.     [..]  
  36.       A delay between an RCC peripheral clock enable and the effective peripheral
  37.       enabling should be taken into account in order to manage the peripheral read/write
  38.       from/to registers.
  39.       (+) This delay depends on the peripheral mapping.
  40.         (++) AHB & APB peripherals, 1 dummy read is necessary
  41.  
  42.     [..]  
  43.       Workarounds:
  44.       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
  45.           inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
  46.  
  47.   @endverbatim
  48.   ******************************************************************************
  49.   * @attention
  50.   *
  51.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  52.   * All rights reserved.</center></h2>
  53.   *
  54.   * This software component is licensed by ST under BSD 3-Clause license,
  55.   * the "License"; You may not use this file except in compliance with the
  56.   * License. You may obtain a copy of the License at:
  57.   *                        opensource.org/licenses/BSD-3-Clause
  58.   *
  59.   ******************************************************************************
  60.   */
  61.  
  62. /* Includes ------------------------------------------------------------------*/
  63. #include "stm32f0xx_hal.h"
  64.  
  65. /** @addtogroup STM32F0xx_HAL_Driver
  66.   * @{
  67.   */
  68.  
  69. /** @defgroup RCC RCC
  70. * @brief RCC HAL module driver
  71.   * @{
  72.   */
  73.  
  74. #ifdef HAL_RCC_MODULE_ENABLED
  75.  
  76. /* Private typedef -----------------------------------------------------------*/
  77. /* Private define ------------------------------------------------------------*/
  78. /** @defgroup RCC_Private_Constants RCC Private Constants
  79.  * @{
  80.  */
  81. /**
  82.   * @}
  83.   */
  84. /* Private macro -------------------------------------------------------------*/
  85. /** @defgroup RCC_Private_Macros RCC Private Macros
  86.   * @{
  87.   */
  88.  
  89. #define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
  90. #define MCO1_GPIO_PORT        GPIOA
  91. #define MCO1_PIN              GPIO_PIN_8
  92.  
  93. /**
  94.   * @}
  95.   */
  96.  
  97. /* Private variables ---------------------------------------------------------*/
  98. /** @defgroup RCC_Private_Variables RCC Private Variables
  99.   * @{
  100.   */
  101. /**
  102.   * @}
  103.   */
  104.  
  105. /* Private function prototypes -----------------------------------------------*/
  106. /* Exported functions ---------------------------------------------------------*/
  107.  
  108. /** @defgroup RCC_Exported_Functions RCC Exported Functions
  109.   * @{
  110.   */
  111.  
  112. /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
  113.   *  @brief    Initialization and Configuration functions
  114.   *
  115.   @verbatim    
  116.   ===============================================================================
  117.            ##### Initialization and de-initialization functions #####
  118.   ===============================================================================
  119.     [..]
  120.       This section provides functions allowing to configure the internal/external oscillators
  121.       (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK,
  122.       AHB and APB1).
  123.  
  124.     [..] Internal/external clock and PLL configuration
  125.       (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
  126.           the PLL as System clock source.
  127.           The HSI clock can be used also to clock the USART and I2C peripherals.
  128.  
  129.       (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock
  130.           the ADC peripheral.
  131.  
  132.       (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
  133.           clock source.
  134.  
  135.       (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
  136.           through the PLL as System clock source. Can be used also as RTC clock source.
  137.  
  138.       (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.  
  139.  
  140.       (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks:
  141.        (++) The first output is used to generate the high speed system clock (up to 48 MHz)
  142.        (++) The second output is used to generate the clock for the USB FS (48 MHz)
  143.        (++) The third output may be used to generate the clock for the TIM, I2C and USART
  144.             peripherals (up to 48 MHz)
  145.  
  146.       (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
  147.           and if a HSE clock failure occurs(HSE used directly or through PLL as System
  148.           clock source), the System clocks automatically switched to HSI and an interrupt
  149.           is generated if enabled. The interrupt is linked to the Cortex-M0 NMI
  150.           (Non-Maskable Interrupt) exception vector.  
  151.  
  152.       (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
  153.           clock (divided by 2) output on pin (such as PA8 pin).
  154.  
  155.     [..] System, AHB and APB buses clocks configuration
  156.       (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
  157.           HSE and PLL.
  158.           The AHB clock (HCLK) is derived from System clock through configurable
  159.           prescaler and used to clock the CPU, memory and peripherals mapped
  160.           on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived
  161.           from AHB clock through configurable prescalers and used to clock
  162.           the peripherals mapped on these buses. You can use
  163.           "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
  164.  
  165.       (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
  166.         (++) The FLASH program/erase clock  which is always HSI 8MHz clock.
  167.         (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
  168.         (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
  169.         (++) The I2C clock which can be derived as well from HSI 8MHz clock.
  170.         (++) The ADC clock which is derived from PLL output.
  171.         (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
  172.              (HSE divided by a programmable prescaler). The System clock (SYSCLK)
  173.              frequency must be higher or equal to the RTC clock frequency.
  174.         (++) IWDG clock which is always the LSI clock.
  175.  
  176.       (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz,
  177.           Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
  178.  
  179.       (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
  180.           prefetch is disabled.
  181.   @endverbatim
  182.   * @{
  183.   */
  184.  
  185. /*
  186.   Additional consideration on the SYSCLK based on Latency settings:
  187.           +-----------------------------------------------+
  188.           | Latency       | SYSCLK clock frequency (MHz)  |
  189.           |---------------|-------------------------------|
  190.           |0WS(1CPU cycle)|       0 < SYSCLK <= 24        |
  191.           |---------------|-------------------------------|
  192.           |1WS(2CPU cycle)|      24 < SYSCLK <= 48        |
  193.           +-----------------------------------------------+
  194.   */
  195.  
  196. /**
  197.   * @brief  Resets the RCC clock configuration to the default reset state.
  198.   * @note   The default reset state of the clock configuration is given below:
  199.   *            - HSI ON and used as system clock source
  200.   *            - HSE and PLL OFF
  201.   *            - AHB, APB1 prescaler set to 1.
  202.   *            - CSS and MCO1 OFF
  203.   *            - All interrupts disabled
  204.   *            - All interrupt and reset flags cleared
  205.   * @note   This function does not modify the configuration of the
  206.   *            - Peripheral clocks
  207.   *            - LSI, LSE and RTC clocks
  208.   * @retval HAL status
  209.   */
  210. HAL_StatusTypeDef HAL_RCC_DeInit(void)
  211. {
  212.   uint32_t tickstart;
  213.  
  214.   /* Get Start Tick*/
  215.   tickstart = HAL_GetTick();
  216.  
  217.   /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/
  218.   SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
  219.  
  220.   /* Wait till HSI is ready */
  221.   while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
  222.   {
  223.     if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
  224.     {
  225.       return HAL_TIMEOUT;
  226.     }
  227.   }
  228.  
  229.   /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
  230.   CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO);
  231.  
  232.   /* Wait till HSI as SYSCLK status is enabled */
  233.   while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
  234.   {
  235.     if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
  236.     {
  237.       return HAL_TIMEOUT;
  238.     }
  239.   }
  240.  
  241.   /* Update the SystemCoreClock global variable for HSI as system clock source */
  242.   SystemCoreClock = HSI_VALUE;
  243.  
  244.   /* Adapt Systick interrupt period */
  245.   if (HAL_InitTick(uwTickPrio) != HAL_OK)
  246.   {
  247.     return HAL_ERROR;
  248.   }
  249.  
  250.   /* Reset HSEON, CSSON, PLLON bits */
  251.   CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
  252.  
  253.   /* Reset HSEBYP bit */
  254.   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
  255.  
  256.   /* Get start tick */
  257.   tickstart = HAL_GetTick();
  258.  
  259.   /* Wait till PLLRDY is cleared */
  260.   while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
  261.   {
  262.     if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
  263.     {
  264.       return HAL_TIMEOUT;
  265.     }
  266.   }
  267.  
  268.   /* Reset CFGR register */
  269.   CLEAR_REG(RCC->CFGR);
  270.  
  271.   /* Reset CFGR2 register */
  272.   CLEAR_REG(RCC->CFGR2);
  273.  
  274.   /* Reset CFGR3 register */
  275.   CLEAR_REG(RCC->CFGR3);
  276.  
  277.   /* Disable all interrupts */
  278.   CLEAR_REG(RCC->CIR);
  279.  
  280.   /* Clear all reset flags */
  281.   __HAL_RCC_CLEAR_RESET_FLAGS();
  282.  
  283.   return HAL_OK;
  284. }
  285.  
  286. /**
  287.   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
  288.   *         RCC_OscInitTypeDef.
  289.   * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
  290.   *         contains the configuration information for the RCC Oscillators.
  291.   * @note   The PLL is not disabled when used as system clock.
  292.   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
  293.   *         supported by this macro. User should request a transition to LSE Off
  294.   *         first and then LSE On or LSE Bypass.
  295.   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
  296.   *         supported by this macro. User should request a transition to HSE Off
  297.   *         first and then HSE On or HSE Bypass.
  298.   * @retval HAL status
  299.   */
  300. HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
  301. {
  302.   uint32_t tickstart;
  303.   uint32_t pll_config;
  304.   uint32_t pll_config2;
  305.  
  306.   /* Check Null pointer */
  307.   if(RCC_OscInitStruct == NULL)
  308.   {
  309.     return HAL_ERROR;
  310.   }
  311.  
  312.   /* Check the parameters */
  313.   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  314.  
  315.   /*------------------------------- HSE Configuration ------------------------*/
  316.   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
  317.   {
  318.     /* Check the parameters */
  319.     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
  320.  
  321.     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
  322.     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
  323.        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
  324.     {
  325.       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
  326.       {
  327.         return HAL_ERROR;
  328.       }
  329.     }
  330.     else
  331.     {
  332.       /* Set the new HSE configuration ---------------------------------------*/
  333.       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
  334.      
  335.  
  336.        /* Check the HSE State */
  337.       if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
  338.       {
  339.         /* Get Start Tick */
  340.         tickstart = HAL_GetTick();
  341.        
  342.         /* Wait till HSE is ready */
  343.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
  344.         {
  345.           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
  346.           {
  347.             return HAL_TIMEOUT;
  348.           }
  349.         }
  350.       }
  351.       else
  352.       {
  353.         /* Get Start Tick */
  354.         tickstart = HAL_GetTick();
  355.        
  356.         /* Wait till HSE is disabled */
  357.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
  358.         {
  359.            if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
  360.           {
  361.             return HAL_TIMEOUT;
  362.           }
  363.         }
  364.       }
  365.     }
  366.   }
  367.   /*----------------------------- HSI Configuration --------------------------*/
  368.   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
  369.   {
  370.     /* Check the parameters */
  371.     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
  372.     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
  373.    
  374.     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
  375.     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
  376.        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
  377.     {
  378.       /* When HSI is used as system clock it will not disabled */
  379.       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
  380.       {
  381.         return HAL_ERROR;
  382.       }
  383.       /* Otherwise, just the calibration is allowed */
  384.       else
  385.       {
  386.         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
  387.         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
  388.       }
  389.     }
  390.     else
  391.     {
  392.       /* Check the HSI State */
  393.       if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
  394.       {
  395.        /* Enable the Internal High Speed oscillator (HSI). */
  396.         __HAL_RCC_HSI_ENABLE();
  397.        
  398.         /* Get Start Tick */
  399.         tickstart = HAL_GetTick();
  400.        
  401.         /* Wait till HSI is ready */
  402.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
  403.         {
  404.           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
  405.           {
  406.             return HAL_TIMEOUT;
  407.           }
  408.         }
  409.                
  410.         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
  411.         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
  412.       }
  413.       else
  414.       {
  415.         /* Disable the Internal High Speed oscillator (HSI). */
  416.         __HAL_RCC_HSI_DISABLE();
  417.        
  418.         /* Get Start Tick */
  419.         tickstart = HAL_GetTick();
  420.        
  421.         /* Wait till HSI is disabled */
  422.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
  423.         {
  424.           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
  425.           {
  426.             return HAL_TIMEOUT;
  427.           }
  428.         }
  429.       }
  430.     }
  431.   }
  432.   /*------------------------------ LSI Configuration -------------------------*/
  433.   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
  434.   {
  435.     /* Check the parameters */
  436.     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
  437.    
  438.     /* Check the LSI State */
  439.     if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
  440.     {
  441.       /* Enable the Internal Low Speed oscillator (LSI). */
  442.       __HAL_RCC_LSI_ENABLE();
  443.      
  444.       /* Get Start Tick */
  445.       tickstart = HAL_GetTick();
  446.      
  447.       /* Wait till LSI is ready */  
  448.       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
  449.       {
  450.         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
  451.         {
  452.           return HAL_TIMEOUT;
  453.         }
  454.       }
  455.     }
  456.     else
  457.     {
  458.       /* Disable the Internal Low Speed oscillator (LSI). */
  459.       __HAL_RCC_LSI_DISABLE();
  460.      
  461.       /* Get Start Tick */
  462.       tickstart = HAL_GetTick();
  463.      
  464.       /* Wait till LSI is disabled */  
  465.       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
  466.       {
  467.         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
  468.         {
  469.           return HAL_TIMEOUT;
  470.         }
  471.       }
  472.     }
  473.   }
  474.   /*------------------------------ LSE Configuration -------------------------*/
  475.   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
  476.   {
  477.     FlagStatus       pwrclkchanged = RESET;
  478.    
  479.     /* Check the parameters */
  480.     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
  481.  
  482.     /* Update LSE configuration in Backup Domain control register    */
  483.     /* Requires to enable write access to Backup Domain of necessary */
  484.     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
  485.     {
  486.       __HAL_RCC_PWR_CLK_ENABLE();
  487.       pwrclkchanged = SET;
  488.     }
  489.    
  490.     if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
  491.     {
  492.       /* Enable write access to Backup domain */
  493.       SET_BIT(PWR->CR, PWR_CR_DBP);
  494.      
  495.       /* Wait for Backup domain Write protection disable */
  496.       tickstart = HAL_GetTick();
  497.  
  498.       while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
  499.       {
  500.         if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
  501.         {
  502.           return HAL_TIMEOUT;
  503.         }
  504.       }
  505.     }
  506.  
  507.     /* Set the new LSE configuration -----------------------------------------*/
  508.     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
  509.     /* Check the LSE State */
  510.     if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
  511.     {
  512.       /* Get Start Tick */
  513.       tickstart = HAL_GetTick();
  514.      
  515.       /* Wait till LSE is ready */  
  516.       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
  517.       {
  518.         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  519.         {
  520.           return HAL_TIMEOUT;
  521.         }
  522.       }
  523.     }
  524.     else
  525.     {
  526.       /* Get Start Tick */
  527.       tickstart = HAL_GetTick();
  528.      
  529.       /* Wait till LSE is disabled */  
  530.       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
  531.       {
  532.         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  533.         {
  534.           return HAL_TIMEOUT;
  535.         }
  536.       }
  537.     }
  538.  
  539.     /* Require to disable power clock if necessary */
  540.     if(pwrclkchanged == SET)
  541.     {
  542.       __HAL_RCC_PWR_CLK_DISABLE();
  543.     }
  544.   }
  545.  
  546.   /*----------------------------- HSI14 Configuration --------------------------*/
  547.   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
  548.   {
  549.     /* Check the parameters */
  550.     assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
  551.     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
  552.  
  553.     /* Check the HSI14 State */
  554.     if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
  555.     {
  556.       /* Disable ADC control of the Internal High Speed oscillator HSI14 */
  557.       __HAL_RCC_HSI14ADC_DISABLE();
  558.  
  559.       /* Enable the Internal High Speed oscillator (HSI). */
  560.       __HAL_RCC_HSI14_ENABLE();
  561.  
  562.       /* Get Start Tick */
  563.       tickstart = HAL_GetTick();
  564.      
  565.       /* Wait till HSI is ready */  
  566.       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
  567.       {
  568.         if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
  569.         {
  570.           return HAL_TIMEOUT;
  571.         }      
  572.       }
  573.  
  574.       /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
  575.       __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
  576.     }
  577.     else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
  578.     {
  579.       /* Enable ADC control of the Internal High Speed oscillator HSI14 */
  580.       __HAL_RCC_HSI14ADC_ENABLE();
  581.  
  582.       /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
  583.       __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
  584.     }
  585.     else
  586.     {
  587.       /* Disable ADC control of the Internal High Speed oscillator HSI14 */
  588.       __HAL_RCC_HSI14ADC_DISABLE();
  589.  
  590.       /* Disable the Internal High Speed oscillator (HSI). */
  591.       __HAL_RCC_HSI14_DISABLE();
  592.  
  593.       /* Get Start Tick */
  594.       tickstart = HAL_GetTick();
  595.      
  596.       /* Wait till HSI is ready */  
  597.       while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
  598.       {
  599.         if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
  600.         {
  601.           return HAL_TIMEOUT;
  602.         }
  603.       }
  604.     }
  605.   }
  606.  
  607. #if defined(RCC_HSI48_SUPPORT)
  608.   /*----------------------------- HSI48 Configuration --------------------------*/
  609.   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
  610.   {
  611.     /* Check the parameters */
  612.     assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
  613.  
  614.     /* When the HSI48 is used as system clock it is not allowed to be disabled */
  615.     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) ||
  616.        ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48)))
  617.     {
  618.       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON))
  619.       {
  620.         return HAL_ERROR;
  621.       }
  622.     }
  623.     else
  624.     {
  625.       /* Check the HSI48 State */
  626.       if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
  627.       {
  628.         /* Enable the Internal High Speed oscillator (HSI48). */
  629.         __HAL_RCC_HSI48_ENABLE();
  630.  
  631.         /* Get Start Tick */
  632.         tickstart = HAL_GetTick();
  633.      
  634.         /* Wait till HSI48 is ready */  
  635.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
  636.         {
  637.           if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
  638.           {
  639.             return HAL_TIMEOUT;
  640.           }
  641.         }
  642.       }
  643.       else
  644.       {
  645.         /* Disable the Internal High Speed oscillator (HSI48). */
  646.         __HAL_RCC_HSI48_DISABLE();
  647.  
  648.         /* Get Start Tick */
  649.         tickstart = HAL_GetTick();
  650.      
  651.         /* Wait till HSI48 is ready */  
  652.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
  653.         {
  654.           if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
  655.           {
  656.             return HAL_TIMEOUT;
  657.           }
  658.         }
  659.       }
  660.     }
  661.   }
  662. #endif /* RCC_HSI48_SUPPORT */
  663.        
  664.   /*-------------------------------- PLL Configuration -----------------------*/
  665.   /* Check the parameters */
  666.   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  667.   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
  668.   {
  669.     /* Check if the PLL is used as system clock or not */
  670.     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
  671.     {
  672.       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
  673.       {
  674.         /* Check the parameters */
  675.         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
  676.         assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
  677.         assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
  678.  
  679.         /* Disable the main PLL. */
  680.         __HAL_RCC_PLL_DISABLE();
  681.        
  682.         /* Get Start Tick */
  683.         tickstart = HAL_GetTick();
  684.        
  685.         /* Wait till PLL is disabled */
  686.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
  687.         {
  688.           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  689.           {
  690.             return HAL_TIMEOUT;
  691.           }
  692.         }
  693.  
  694.         /* Configure the main PLL clock source, predivider and multiplication factor. */
  695.         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
  696.                              RCC_OscInitStruct->PLL.PREDIV,
  697.                              RCC_OscInitStruct->PLL.PLLMUL);
  698.         /* Enable the main PLL. */
  699.         __HAL_RCC_PLL_ENABLE();
  700.        
  701.         /* Get Start Tick */
  702.         tickstart = HAL_GetTick();
  703.        
  704.         /* Wait till PLL is ready */
  705.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
  706.         {
  707.           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  708.           {
  709.             return HAL_TIMEOUT;
  710.           }
  711.         }
  712.       }
  713.       else
  714.       {
  715.         /* Disable the main PLL. */
  716.         __HAL_RCC_PLL_DISABLE();
  717.  
  718.         /* Get Start Tick */
  719.         tickstart = HAL_GetTick();
  720.        
  721.         /* Wait till PLL is disabled */  
  722.         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
  723.         {
  724.           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  725.           {
  726.             return HAL_TIMEOUT;
  727.           }
  728.         }
  729.       }
  730.     }
  731.     else
  732.     {
  733.       /* Check if there is a request to disable the PLL used as System clock source */
  734.       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
  735.       {
  736.         return HAL_ERROR;
  737.       }
  738.       else
  739.       {
  740.         /* Do not return HAL_ERROR if request repeats the current configuration */
  741.         pll_config  = RCC->CFGR;
  742.         pll_config2 = RCC->CFGR2;
  743.         if((READ_BIT(pll_config,  RCC_CFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
  744.            (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)    ||
  745.            (READ_BIT(pll_config,  RCC_CFGR_PLLMUL)  != RCC_OscInitStruct->PLL.PLLMUL))
  746.         {
  747.           return HAL_ERROR;
  748.         }
  749.       }
  750.     }
  751.   }
  752.  
  753.   return HAL_OK;
  754. }
  755.  
  756. /**
  757.   * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
  758.   *         parameters in the RCC_ClkInitStruct.
  759.   * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
  760.   *         contains the configuration information for the RCC peripheral.
  761.   * @param  FLatency FLASH Latency                  
  762.   *          The value of this parameter depend on device used within the same series
  763.   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
  764.   *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
  765.   *
  766.   * @note   The HSI is used (enabled by hardware) as system clock source after
  767.   *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
  768.   *         of failure of the HSE used directly or indirectly as system clock
  769.   *         (if the Clock Security System CSS is enabled).
  770.   *          
  771.   * @note   A switch from one clock source to another occurs only if the target
  772.   *         clock source is ready (clock stable after start-up delay or PLL locked).
  773.   *         If a clock source which is not yet ready is selected, the switch will
  774.   *         occur when the clock source will be ready.
  775.   *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
  776.   *         currently used as system clock source.
  777.   * @retval HAL status
  778.   */
  779. HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
  780. {
  781.   uint32_t tickstart;
  782.  
  783.   /* Check Null pointer */
  784.   if(RCC_ClkInitStruct == NULL)
  785.   {
  786.     return HAL_ERROR;
  787.   }
  788.  
  789.   /* Check the parameters */
  790.   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
  791.   assert_param(IS_FLASH_LATENCY(FLatency));
  792.  
  793.   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
  794.   must be correctly programmed according to the frequency of the CPU clock
  795.     (HCLK) of the device. */
  796.  
  797.   /* Increasing the number of wait states because of higher CPU frequency */
  798.   if(FLatency > __HAL_FLASH_GET_LATENCY())
  799.   {    
  800.     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
  801.     __HAL_FLASH_SET_LATENCY(FLatency);
  802.    
  803.     /* Check that the new number of wait states is taken into account to access the Flash
  804.     memory by reading the FLASH_ACR register */
  805.     if(__HAL_FLASH_GET_LATENCY() != FLatency)
  806.     {
  807.       return HAL_ERROR;
  808.     }
  809.   }
  810.  
  811.   /*-------------------------- HCLK Configuration --------------------------*/
  812.   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
  813.   {
  814.     /* Set the highest APB divider in order to ensure that we do not go through
  815.        a non-spec phase whatever we decrease or increase HCLK. */
  816.     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
  817.     {
  818.       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
  819.     }
  820.  
  821.     /* Set the new HCLK clock divider */
  822.     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
  823.     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
  824.   }
  825.  
  826.   /*------------------------- SYSCLK Configuration ---------------------------*/
  827.   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
  828.   {
  829.     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
  830.    
  831.     /* HSE is selected as System Clock Source */
  832.     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  833.     {
  834.       /* Check the HSE ready flag */  
  835.       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
  836.       {
  837.         return HAL_ERROR;
  838.       }
  839.     }
  840.     /* PLL is selected as System Clock Source */
  841.     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
  842.     {
  843.       /* Check the PLL ready flag */  
  844.       if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
  845.       {
  846.         return HAL_ERROR;
  847.       }
  848.     }
  849. #if defined(RCC_CFGR_SWS_HSI48)
  850.     /* HSI48 is selected as System Clock Source */
  851.     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
  852.     {
  853.       /* Check the HSI48 ready flag */
  854.       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
  855.       {
  856.         return HAL_ERROR;
  857.       }
  858.     }
  859. #endif /* RCC_CFGR_SWS_HSI48 */
  860.     /* HSI is selected as System Clock Source */
  861.     else
  862.     {
  863.       /* Check the HSI ready flag */  
  864.       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
  865.       {
  866.         return HAL_ERROR;
  867.       }
  868.     }
  869.     __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
  870.  
  871.     /* Get Start Tick */
  872.     tickstart = HAL_GetTick();
  873.    
  874.     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
  875.     {
  876.       if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  877.       {
  878.         return HAL_TIMEOUT;
  879.       }
  880.     }
  881.   }
  882.  
  883.   /* Decreasing the number of wait states because of lower CPU frequency */
  884.   if(FLatency < __HAL_FLASH_GET_LATENCY())
  885.   {    
  886.     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
  887.     __HAL_FLASH_SET_LATENCY(FLatency);
  888.    
  889.     /* Check that the new number of wait states is taken into account to access the Flash
  890.     memory by reading the FLASH_ACR register */
  891.     if(__HAL_FLASH_GET_LATENCY() != FLatency)
  892.     {
  893.       return HAL_ERROR;
  894.     }
  895.   }    
  896.  
  897.   /*-------------------------- PCLK1 Configuration ---------------------------*/
  898.   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
  899.   {
  900.     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
  901.     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
  902.   }
  903.  
  904.   /* Update the SystemCoreClock global variable */
  905.   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
  906.  
  907.   /* Configure the source of time base considering new system clocks settings*/
  908.   HAL_InitTick (TICK_INT_PRIORITY);
  909.  
  910.   return HAL_OK;
  911. }
  912.  
  913. /**
  914.   * @}
  915.   */
  916.  
  917. /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
  918.   *  @brief   RCC clocks control functions
  919.   *
  920.   @verbatim  
  921.   ===============================================================================
  922.                   ##### Peripheral Control functions #####
  923.   ===============================================================================  
  924.     [..]
  925.     This subsection provides a set of functions allowing to control the RCC Clocks
  926.     frequencies.
  927.  
  928.   @endverbatim
  929.   * @{
  930.   */
  931.  
  932. #if defined(RCC_CFGR_MCOPRE)
  933. /**
  934.   * @brief  Selects the clock source to output on MCO pin.
  935.   * @note   MCO pin should be configured in alternate function mode.
  936.   * @param  RCC_MCOx specifies the output direction for the clock source.
  937.   *          This parameter can be one of the following values:
  938.   *            @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
  939.   * @param  RCC_MCOSource specifies the clock source to output.
  940.   *          This parameter can be one of the following values:
  941.   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK     No clock selected
  942.   *            @arg @ref RCC_MCO1SOURCE_SYSCLK      System Clock selected as MCO clock
  943.   *            @arg @ref RCC_MCO1SOURCE_HSI         HSI selected as MCO clock
  944.   *            @arg @ref RCC_MCO1SOURCE_HSE         HSE selected as MCO clock
  945.   *            @arg @ref RCC_MCO1SOURCE_LSI         LSI selected as MCO clock
  946.   *            @arg @ref RCC_MCO1SOURCE_LSE         LSE selected as MCO clock
  947.   *            @arg @ref RCC_MCO1SOURCE_HSI14       HSI14 selected as MCO clock
  948.   @if STM32F042x6
  949.   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 selected as MCO clock
  950.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
  951.   @elseif STM32F048xx
  952.   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 selected as MCO clock
  953.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
  954.   @elseif STM32F071xB
  955.   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 selected as MCO clock
  956.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
  957.   @elseif STM32F072xB
  958.   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 selected as MCO clock
  959.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
  960.   @elseif STM32F078xx
  961.   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 selected as MCO clock
  962.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
  963.   @elseif STM32F091xC
  964.   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 selected as MCO clock
  965.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
  966.   @elseif STM32F098xx
  967.   *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 selected as MCO clock
  968.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
  969.   @elif STM32F030x6
  970.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
  971.   @elif STM32F030xC
  972.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
  973.   @elif STM32F031x6
  974.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
  975.   @elif STM32F038xx
  976.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
  977.   @elif STM32F070x6
  978.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
  979.   @elif STM32F070xB
  980.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
  981.   @endif
  982.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
  983.   * @param  RCC_MCODiv specifies the MCO DIV.
  984.   *          This parameter can be one of the following values:
  985.   *            @arg @ref RCC_MCODIV_1   no division applied to MCO clock
  986.   *            @arg @ref RCC_MCODIV_2   division by 2 applied to MCO clock
  987.   *            @arg @ref RCC_MCODIV_4   division by 4 applied to MCO clock
  988.   *            @arg @ref RCC_MCODIV_8   division by 8 applied to MCO clock
  989.   *            @arg @ref RCC_MCODIV_16  division by 16 applied to MCO clock
  990.   *            @arg @ref RCC_MCODIV_32  division by 32 applied to MCO clock
  991.   *            @arg @ref RCC_MCODIV_64  division by 64 applied to MCO clock
  992.   *            @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock
  993.   * @retval None
  994.   */
  995. #else
  996. /**
  997.   * @brief  Selects the clock source to output on MCO pin.
  998.   * @note   MCO pin should be configured in alternate function mode.
  999.   * @param  RCC_MCOx specifies the output direction for the clock source.
  1000.   *          This parameter can be one of the following values:
  1001.   *            @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
  1002.   * @param  RCC_MCOSource specifies the clock source to output.
  1003.   *          This parameter can be one of the following values:
  1004.   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK     No clock selected as MCO clock
  1005.   *            @arg @ref RCC_MCO1SOURCE_SYSCLK      System clock selected as MCO clock
  1006.   *            @arg @ref RCC_MCO1SOURCE_HSI         HSI selected as MCO clock
  1007.   *            @arg @ref RCC_MCO1SOURCE_HSE         HSE selected as MCO clock
  1008.   *            @arg @ref RCC_MCO1SOURCE_LSI         LSI selected as MCO clock
  1009.   *            @arg @ref RCC_MCO1SOURCE_LSE         LSE selected as MCO clock
  1010.   *            @arg @ref RCC_MCO1SOURCE_HSI14       HSI14 selected as MCO clock
  1011.   *            @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
  1012.   * @param  RCC_MCODiv specifies the MCO DIV.
  1013.   *          This parameter can be one of the following values:
  1014.   *            @arg @ref RCC_MCODIV_1 no division applied to MCO clock
  1015.   * @retval None
  1016.   */
  1017. #endif
  1018. void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
  1019. {
  1020.   GPIO_InitTypeDef gpio;
  1021.  
  1022.   /* Check the parameters */
  1023.   assert_param(IS_RCC_MCO(RCC_MCOx));
  1024.   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
  1025.   assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
  1026.  
  1027.   /* Configure the MCO1 pin in alternate function mode */
  1028.   gpio.Mode      = GPIO_MODE_AF_PP;
  1029.   gpio.Speed     = GPIO_SPEED_FREQ_HIGH;
  1030.   gpio.Pull      = GPIO_NOPULL;
  1031.   gpio.Pin       = MCO1_PIN;
  1032.   gpio.Alternate = GPIO_AF0_MCO;
  1033.  
  1034.   /* MCO1 Clock Enable */
  1035.   MCO1_CLK_ENABLE();
  1036.  
  1037.   HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
  1038.  
  1039.   /* Configure the MCO clock source */
  1040.   __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
  1041. }
  1042.  
  1043. /**
  1044.   * @brief  Enables the Clock Security System.
  1045.   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
  1046.   *         is automatically disabled and an interrupt is generated to inform the
  1047.   *         software about the failure (Clock Security System Interrupt, CSSI),
  1048.   *         allowing the MCU to perform rescue operations. The CSSI is linked to
  1049.   *         the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.  
  1050.   * @retval None
  1051.   */
  1052. void HAL_RCC_EnableCSS(void)
  1053. {
  1054.   SET_BIT(RCC->CR, RCC_CR_CSSON) ;
  1055. }
  1056.  
  1057. /**
  1058.   * @brief  Disables the Clock Security System.
  1059.   * @retval None
  1060.   */
  1061. void HAL_RCC_DisableCSS(void)
  1062. {
  1063.   CLEAR_BIT(RCC->CR, RCC_CR_CSSON) ;
  1064. }
  1065.  
  1066. /**
  1067.   * @brief  Returns the SYSCLK frequency    
  1068.   * @note   The system frequency computed by this function is not the real
  1069.   *         frequency in the chip. It is calculated based on the predefined
  1070.   *         constant and the selected clock source:
  1071.   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
  1072.   * @note     If SYSCLK source is HSE, function returns a value based on HSE_VALUE
  1073.   *           divided by PREDIV factor(**)
  1074.   * @note     If SYSCLK source is PLL, function returns a value based on HSE_VALUE
  1075.   *           divided by PREDIV factor(**) or depending on STM32F0xxxx devices either a value based
  1076.   *           on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the
  1077.   *           PLL factor.
  1078.   * @note     (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
  1079.   *               8 MHz) but the real value may vary depending on the variations
  1080.   *               in voltage and temperature.
  1081.   * @note     (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
  1082.   *                8 MHz), user has to ensure that HSE_VALUE is same as the real
  1083.   *                frequency of the crystal used. Otherwise, this function may
  1084.   *                have wrong result.
  1085.   *                  
  1086.   * @note   The result of this function could be not correct when using fractional
  1087.   *         value for HSE crystal.
  1088.   *          
  1089.   * @note   This function can be used by the user application to compute the
  1090.   *         baud-rate for the communication peripherals or configure other parameters.
  1091.   *          
  1092.   * @note   Each time SYSCLK changes, this function must be called to update the
  1093.   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
  1094.   *        
  1095.   * @retval SYSCLK frequency
  1096.   */
  1097. uint32_t HAL_RCC_GetSysClockFreq(void)
  1098. {
  1099.   const uint8_t aPLLMULFactorTable[16] = { 2U,  3U,  4U,  5U,  6U,  7U,  8U,  9U,
  1100.                                          10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
  1101.   const uint8_t aPredivFactorTable[16] = { 1U, 2U,  3U,  4U,  5U,  6U,  7U,  8U,
  1102.                                            9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
  1103.  
  1104.   uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
  1105.   uint32_t sysclockfreq = 0U;
  1106.  
  1107.   tmpreg = RCC->CFGR;
  1108.  
  1109.   /* Get SYSCLK source -------------------------------------------------------*/
  1110.   switch (tmpreg & RCC_CFGR_SWS)
  1111.   {
  1112.     case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
  1113.     {
  1114.       sysclockfreq = HSE_VALUE;
  1115.       break;
  1116.     }
  1117.     case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
  1118.     {
  1119.       pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
  1120.       prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
  1121.       if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
  1122.       {
  1123.         /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
  1124.         pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
  1125.       }
  1126. #if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV)
  1127.       else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48)
  1128.       {
  1129.         /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */
  1130.         pllclk = (uint32_t)((uint64_t) HSI48_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
  1131.       }
  1132. #endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */
  1133.       else
  1134.       {
  1135. #if  (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
  1136.         /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
  1137.         pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
  1138. #else
  1139.         /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
  1140.         pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
  1141. #endif
  1142.       }
  1143.       sysclockfreq = pllclk;
  1144.       break;
  1145.     }
  1146. #if defined(RCC_CFGR_SWS_HSI48)
  1147.     case RCC_SYSCLKSOURCE_STATUS_HSI48:    /* HSI48 used as system clock source */
  1148.     {
  1149.       sysclockfreq = HSI48_VALUE;
  1150.       break;
  1151.     }
  1152. #endif /* RCC_CFGR_SWS_HSI48 */
  1153.     case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
  1154.     default: /* HSI used as system clock */
  1155.     {
  1156.       sysclockfreq = HSI_VALUE;
  1157.       break;
  1158.     }
  1159.   }
  1160.   return sysclockfreq;
  1161. }
  1162.  
  1163. /**
  1164.   * @brief  Returns the HCLK frequency    
  1165.   * @note   Each time HCLK changes, this function must be called to update the
  1166.   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
  1167.   *
  1168.   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
  1169.   *         and updated within this function
  1170.   * @retval HCLK frequency
  1171.   */
  1172. uint32_t HAL_RCC_GetHCLKFreq(void)
  1173. {
  1174.   return SystemCoreClock;
  1175. }
  1176.  
  1177. /**
  1178.   * @brief  Returns the PCLK1 frequency    
  1179.   * @note   Each time PCLK1 changes, this function must be called to update the
  1180.   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  1181.   * @retval PCLK1 frequency
  1182.   */
  1183. uint32_t HAL_RCC_GetPCLK1Freq(void)
  1184. {
  1185.   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  1186.   return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_BITNUMBER]);
  1187. }    
  1188.  
  1189. /**
  1190.   * @brief  Configures the RCC_OscInitStruct according to the internal
  1191.   * RCC configuration registers.
  1192.   * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
  1193.   * will be configured.
  1194.   * @retval None
  1195.   */
  1196. void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
  1197. {
  1198.   /* Check the parameters */
  1199.   assert_param(RCC_OscInitStruct != NULL);
  1200.  
  1201.   /* Set all possible values for the Oscillator type parameter ---------------*/
  1202.   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI  \
  1203.                   | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI14;
  1204. #if defined(RCC_HSI48_SUPPORT)
  1205.   RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
  1206. #endif /* RCC_HSI48_SUPPORT */
  1207.  
  1208.  
  1209.   /* Get the HSE configuration -----------------------------------------------*/
  1210.   if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
  1211.   {
  1212.     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
  1213.   }
  1214.   else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
  1215.   {
  1216.     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
  1217.   }
  1218.   else
  1219.   {
  1220.     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
  1221.   }
  1222.  
  1223.   /* Get the HSI configuration -----------------------------------------------*/
  1224.   if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
  1225.   {
  1226.     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
  1227.   }
  1228.   else
  1229.   {
  1230.     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
  1231.   }
  1232.  
  1233.   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber);
  1234.  
  1235.   /* Get the LSE configuration -----------------------------------------------*/
  1236.   if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
  1237.   {
  1238.     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
  1239.   }
  1240.   else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
  1241.   {
  1242.     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
  1243.   }
  1244.   else
  1245.   {
  1246.     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
  1247.   }
  1248.  
  1249.   /* Get the LSI configuration -----------------------------------------------*/
  1250.   if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
  1251.   {
  1252.     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
  1253.   }
  1254.   else
  1255.   {
  1256.     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
  1257.   }
  1258.  
  1259.   /* Get the HSI14 configuration -----------------------------------------------*/
  1260.   if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON)
  1261.   {
  1262.     RCC_OscInitStruct->HSI14State = RCC_HSI_ON;
  1263.   }
  1264.   else
  1265.   {
  1266.     RCC_OscInitStruct->HSI14State = RCC_HSI_OFF;
  1267.   }
  1268.  
  1269.   RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_HSI14TRIM_BIT_NUMBER);
  1270.  
  1271. #if defined(RCC_HSI48_SUPPORT)
  1272.   /* Get the HSI48 configuration if any-----------------------------------------*/
  1273.   RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE();
  1274. #endif /* RCC_HSI48_SUPPORT */
  1275.  
  1276.   /* Get the PLL configuration -----------------------------------------------*/
  1277.   if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
  1278.   {
  1279.     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
  1280.   }
  1281.   else
  1282.   {
  1283.     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
  1284.   }
  1285.   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
  1286.   RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
  1287.   RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
  1288. }
  1289.  
  1290. /**
  1291.   * @brief  Get the RCC_ClkInitStruct according to the internal
  1292.   * RCC configuration registers.
  1293.   * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
  1294.   * contains the current clock configuration.
  1295.   * @param  pFLatency Pointer on the Flash Latency.
  1296.   * @retval None
  1297.   */
  1298. void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
  1299. {
  1300.   /* Check the parameters */
  1301.   assert_param(RCC_ClkInitStruct != NULL);
  1302.   assert_param(pFLatency != NULL);
  1303.  
  1304.   /* Set all possible values for the Clock type parameter --------------------*/
  1305.   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1;
  1306.  
  1307.   /* Get the SYSCLK configuration --------------------------------------------*/
  1308.   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
  1309.  
  1310.   /* Get the HCLK configuration ----------------------------------------------*/
  1311.   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
  1312.  
  1313.   /* Get the APB1 configuration ----------------------------------------------*/
  1314.   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE);  
  1315.   /* Get the Flash Wait State (Latency) configuration ------------------------*/  
  1316.   *pFLatency = __HAL_FLASH_GET_LATENCY();
  1317. }
  1318.  
  1319. /**
  1320.   * @brief This function handles the RCC CSS interrupt request.
  1321.   * @note This API should be called under the NMI_Handler().
  1322.   * @retval None
  1323.   */
  1324. void HAL_RCC_NMI_IRQHandler(void)
  1325. {
  1326.   /* Check RCC CSSF flag  */
  1327.   if(__HAL_RCC_GET_IT(RCC_IT_CSS))
  1328.   {
  1329.     /* RCC Clock Security System interrupt user callback */
  1330.     HAL_RCC_CSSCallback();
  1331.    
  1332.     /* Clear RCC CSS pending bit */
  1333.     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
  1334.   }
  1335. }
  1336.  
  1337. /**
  1338.   * @brief  RCC Clock Security System interrupt callback
  1339.   * @retval none
  1340.   */
  1341. __weak void HAL_RCC_CSSCallback(void)
  1342. {
  1343.   /* NOTE : This function Should not be modified, when the callback is needed,
  1344.     the HAL_RCC_CSSCallback could be implemented in the user file
  1345.     */
  1346. }
  1347.  
  1348. /**
  1349.   * @}
  1350.   */
  1351.  
  1352. /**
  1353.   * @}
  1354.   */
  1355.  
  1356. #endif /* HAL_RCC_MODULE_ENABLED */
  1357. /**
  1358.   * @}
  1359.   */
  1360.  
  1361. /**
  1362.   * @}
  1363.   */
  1364.  
  1365. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1366.